Equipment address allocation method and device based on controller area network bus communication, machine equipment and program product

Abstract

The invention relates to an equipment address allocation method and device based on controller area network bus communication, machine equipment and a program product, relates to the field of communication, and solves the technical problems that in the prior art, an additional hardware circuit is needed and is not flexible enough. The method comprises the following steps: sending an address allocation signal to a corresponding slave device through a pulse width modulation signal line; and in response to the received response signal of the address allocation signal sent by the corresponding slave device through the controller area network bus, sending the set address information to the corresponding slave device through the controller area network bus. According to the scheme, the problem that the device address needs to be set manually is solved, no hardware circuit is added, and the communication logic is simpler.

Description

Technical Field

[0001] This invention relates to the field of communications, and more particularly to a device address allocation method, apparatus, machine equipment, and program product based on controller local area network bus communication. Background Technology

[0002] In automatic control systems, there is typically a main controller module and multiple I / O controller modules connected sequentially. Different addresses need to be assigned to each I / O controller module on the same communication bus. In existing technologies, this is usually done manually using DIP switches. This address allocation method is simple to implement and reliable, but it wastes hardware resources. Furthermore, the DIP switches increase the space required for hardware board layout and require manual control, making it inflexible. Summary of the Invention

[0003] Based on the above analysis, the embodiments of the present invention aim to provide a device address allocation method, apparatus, machine equipment and program product based on controller area network bus communication, so as to solve the technical problem that the prior art requires additional hardware circuits and is not flexible enough.

[0004] In a first aspect, embodiments of the present invention provide a device address allocation method based on controller area network (CLAN) bus communication. A master device and multiple slave devices are electrically interconnected via a CLAN bus and a pulse width modulation (PWM) signal harness. Motion control of each slave device is controlled by the master device via a corresponding PWM signal line in the PWM signal harness. The device address allocation method includes the following steps:

[0005] Sending an address allocation signal to the corresponding slave device via the pulse width modulation signal line; and

[0006] In response to receiving the address allocation signal sent by the corresponding slave device via the controller area network bus, the configured address information is sent to the corresponding slave device via the controller area network bus.

[0007] Based on a further improvement to the above device address allocation method, the pulse width modulation signal line is the i-th pulse width modulation signal line in the pulse width modulation signal line bundle, where i takes the value [1, N], and N is the number of pulse width modulation signal lines in the pulse width modulation signal line bundle. The device address allocation method further includes the following steps:

[0008] Step S10: In response to receiving the address allocation completion signal sent by the corresponding slave device through the controller local area network bus, send an address allocation signal to the corresponding slave device through the (i+1)th pulse width modulation signal line;

[0009] Step S20: In response to receiving the address allocation signal sent by the corresponding slave device through the controller local area network bus, send the set address information to the corresponding slave device through the controller local area network bus.

[0010] Based on a further improvement to the above device address allocation method, the pulse width modulation signal line is the i-th pulse width modulation signal line in the pulse width modulation signal line bundle, and the device address allocation method further includes the following steps:

[0011] Step S100: In response to the failure to receive the address allocation signal sent by the corresponding slave device within a preset time, send the address allocation signal to the corresponding slave device through the (i+1)th pulse width modulation signal line;

[0012] Step S200: In response to receiving the address allocation signal sent by the corresponding slave device through the controller local area network bus, send the set address information to the corresponding slave device through the controller local area network bus.

[0013] Based on a further improvement to the above device address allocation method, before sending the address allocation signal to the corresponding slave device through the (i+1)th pulse width modulation signal line, the device address allocation method further includes the following steps:

[0014] Determine whether the i-th pulse width modulation signal line is the last pulse width modulation signal line in the pulse width modulation signal line bundle;

[0015] If yes, the process ends; otherwise, proceed to step S10.

[0016] Based on a further improvement to the above device address allocation method, before sending the address allocation signal to the corresponding slave device through the (i+1)th pulse width modulation signal line, the device address allocation method further includes the following steps:

[0017] Determine whether the i-th pulse width modulation signal line is the last pulse width modulation signal line in the pulse width modulation signal line bundle;

[0018] If yes, the process ends; otherwise, proceed to step S100.

[0019] Based on a further improvement of the above-mentioned device address allocation method, the address allocation signal is a pulse width modulation signal with a preset pulse width length.

[0020] Based on a further improvement of the above-mentioned device address allocation method, the pulse width modulation signal with the preset pulse width length is a pulse width modulation signal with a duty cycle of 1% to 9%.

[0021] Secondly, embodiments of the present invention provide a device address allocation apparatus based on controller area network (CLAN) bus communication, wherein a master device and multiple slave devices are electrically interconnected via a CLAN bus and a pulse width modulation (PWM) signal harness, and the motion control of each slave device is controlled by the master device via a corresponding PWM signal line in the PWM signal harness. The device address allocation apparatus includes:

[0022] The first transmitting module is configured to transmit an address allocation signal to the corresponding slave device via the pulse width modulation signal line; and

[0023] The second sending module is configured to send the set address information to the corresponding slave device via the controller local area network bus in response to receiving the address allocation signal sent by the corresponding slave device via the controller local area network bus.

[0024] Thirdly, embodiments of the present invention provide a machine device including a master device and a plurality of slave devices, wherein the master device and the plurality of slave devices are electrically interconnected via a controller area network bus and a pulse width modulation signal harness, and the motion control of each slave device is controlled by the master device via a corresponding pulse width modulation signal harness, and the machine device is used to execute the device address allocation method based on controller area network bus communication according to any one of the first aspects of the present invention.

[0025] Fourthly, embodiments of the present invention provide a program product, including a computer program, which, when executed by a processor, implements the steps of the device address allocation method based on controller local area network bus communication according to any one of the first aspects of the present invention.

[0026] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0027] 1. The present invention does not add hardware circuitry for allocating device addresses. Address allocation is performed on the basis of the original hardware circuitry, which solves the problem of needing to manually set device addresses. It does not add hardware circuitry and the communication logic is simpler.

[0028] 2. Unlike the traditional solution that uses high and low levels of I / O interfaces to allocate addresses, the present invention uses pulse width modulation signals to replace these I / O interfaces. The present invention allocates addresses based on the existing hardware circuitry and does not require additional I / O port hardware resources.

[0029] 3. The logic of the present invention is simple. Address allocation can be achieved in a question-and-answer manner without the need for complex software logic, thus saving software code.

[0030] 4. In the present invention, since the slave devices are all the same hardware devices, but they are responsible for different functions under different communication addresses, it is not necessary to install them one by one during the maintenance or assembly process. It is only necessary to install them in the location and execute the communication address allocation function. The slave device can then perform the function corresponding to the installation location, thereby reducing the complexity of the maintenance or installation process, achieving the effect of allocating communication addresses by utilizing the original hardware conditions, reducing hardware circuits, and optimizing the address allocation logic.

[0031] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0032] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0033] Figure 1 A flowchart illustrating a device address allocation method based on controller area network bus communication according to an embodiment of the present invention is shown.

[0034] Figure 2 A schematic diagram of the system framework of the master device and slave device according to an embodiment of the present invention is shown.

[0035] Figure 3 A flowchart illustrating a device address allocation method based on controller area network bus communication according to another embodiment of the present invention.

[0036] Figure 4 An exemplary block diagram of a device address allocation apparatus based on controller area network bus communication according to an embodiment of the present invention is shown. Detailed Implementation

[0037] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0038] Figure 1 A flowchart illustrating a device address allocation method based on controller area network bus communication according to an embodiment of the present invention is shown. Figure 1 As shown, the device address allocation method based on controller area network bus communication includes the following steps:

[0039] Step S101: Send an address allocation signal to the corresponding slave device via a pulse width modulation signal line.

[0040] Figure 2 A schematic diagram of a system framework for a master device and a slave device according to an embodiment of the present invention is shown. Figure 2 As shown, the system includes a master device and multiple slave devices. The master device includes a master control module, an isolation module, a multi-channel PWM generator module, and a CAN transceiver module. Each slave device includes a master control module, an isolation module, a PWM receiver module, and a CAN transceiver module. The master control module of the master device refers to its main control module. The master control module of the slave device refers to its main control module. The multi-channel PWM generator module generates multiple Pulse Width Modulation (PWM) signals. The PWM receiver module receives PWM signals. The CAN transceiver module of the slave device converts the digital signals output by the master control module into the physical signals required by the CAN (Controller Area Network) bus, and simultaneously converts the physical signals received on the CAN bus into digital signals, which are then transmitted to the master control module for processing. The isolation module is a signal isolation chip used to establish an electrical isolation barrier between the input and output terminals to protect the safety and stability of signal transmission.

[0041] like Figure 2 As shown, in this embodiment, the master device is physically connected to multiple slave devices via a CAN bus, PWM connection lines, and a PWM signal line. The PWM connection line (also known as the "PWM signal line") is the motion control signal line from the master device to the slave devices. In this embodiment, the PWM connection line also serves as the signal line for address allocation during the master device's allocation of communication addresses to the slave devices. The process of the master device allocating addresses to slave devices using the PWM connection line will be described below.

[0042] First, the master device sends an address allocation signal to the corresponding slave device via the PWM connection cable. For example, in Figure 2 In this embodiment, the master device sends an address allocation signal to the first slave device via a PWM connection line. The PWM connections between the master and slave devices are one-to-one.

[0043] In this embodiment, the master device can use the pulse width modulation (PWM) signal to initiate address allocation by adjusting the pulse width length of the PWM signal. In this embodiment, the address allocation signal can be a pulse width modulation (PWM) signal with a preset pulse width length. For example, the master device can use a PWM signal with a duty cycle of 1% to 9% as the address allocation signal. Specifically, the master device can set the PWM duty cycle of the PWM connection line connected to the slave device to 1% to 9%. Since the master device can only set the duty cycle of one PWM connection line to 1% to 9% at a time, this embodiment ensures that the address allocation process is one-to-one. It should be noted that the duty cycle of the PWM signal currently used for motor control is in the range of 10%-90%. Therefore, using a PWM signal with a duty cycle of 1% to 9% as the address allocation signal is not only feasible but also solves the problem of manually setting the device address, saves hardware resources, and simplifies the communication interaction logic. For example, a PWM signal with a duty cycle of 5% can be used as the address allocation signal. It should be noted that using a PWM signal with a duty cycle of 5% as the address allocation signal has the following advantages:

[0044] Considering hardware differences, a 5% duty cycle PWM signal sent by the master device might be detected by the slave device as a 4.8% or 5.2% duty cycle PWM signal. Therefore, the PWM signal detected by the slave device will have an error value. Typically, the error value of the PWM signal detected by the slave device is 1%. Thus, if a 5% duty cycle PWM signal is used as the address allocation signal, for the slave device, PWM signals with duty cycles of 4% to 6% are all acceptable for address allocation. If a PWM signal with a different duty cycle (e.g., 9%) is used as the address allocation signal, considering the impact of the error, there is a risk of conflict between the slave device's address allocation signal and control signal, thereby affecting system stability.

[0045] Step S102: In response to receiving the address allocation signal sent by the corresponding slave device through the controller area network bus, send the set address information to the corresponding slave device through the controller area network bus.

[0046] In this embodiment, after the slave device reads the address allocation signal from the master device through the PWM receiving module and the isolation module, it can initiate a handshake communication with the master device. In this embodiment, the selected slave device will generate a response signal to the address allocation signal, while other slave devices will not respond to the master device. Specifically, the slave device can identify whether the PWM duty cycle on the PWM line connected to the master device is 5%. If so, the slave device determines that it has been selected; otherwise, it has not been selected. The data information in the response signal in this embodiment may include the current slave device's communication address, device status, and acknowledgment flag.

[0047] In this embodiment, after receiving the response signal of the address allocation signal sent by the slave device, the master device can set the address information for the slave device and send the set address information to the slave device through the CAN bus.

[0048] In some embodiments, Figure 1 The pulse width modulation (PWM) signal line in the signal bundle is the i-th PWM signal line, where i takes the value [1, N], and N is the number of PWM signal lines in the PWM signal bundle. Figure 1 The device address allocation method in the document also includes the following steps:

[0049] Step S10: In response to receiving the address allocation completion signal sent by the corresponding slave device through the controller LAN bus, send the address allocation signal to the corresponding slave device through the (i+1)th pulse width modulation signal line.

[0050] In this embodiment, after the slave device obtains the address information set for it by the master device, it can initiate a handshake communication with the master device. In this embodiment, the slave device selected by the i-th PWM connection line will generate an address allocation completion signal in response to the communication; other slave devices will not respond to the master device. Specifically, the master device can send data information on the CAN bus, including the communication address expected to be set by the slave device, the master device status, etc.

[0051] In this embodiment, after receiving the address allocation completion signal from the slave device connected to the i-th PWM connection line, the master device can send an address allocation signal to the slave device selected by the (i+1)-th PWM connection line via the (i+1)-th PWM connection line. The process of the master device sending the address allocation signal to the slave device selected by the (i+1)-th PWM connection line is similar to the process of sending the address allocation signal to the slave device selected by the i-th PWM connection line, and will not be described again here.

[0052] Step S20: In response to receiving the address allocation signal sent by the corresponding slave device through the controller area network bus, send the set address information to the corresponding slave device through the controller area network bus.

[0053] In this embodiment, the slave device selected by the (i+1)th PWM connection line reads the address allocation signal of the master device through the PWM receiving module and the isolation module, and can then perform a handshake communication with the master device. In this embodiment, the slave device selected by the (i+1)th PWM connection line will generate a response signal to generate the address allocation signal, while other slave devices will not respond to the master device.

[0054] In this embodiment, after receiving the response signal of the address allocation signal sent by the slave device selected by the (i+1)th PWM connection line, the master device can set the address information for the slave device and send the set address information to the slave device through the CAN bus.

[0055] In some embodiments, before the master device sends the address allocation signal to the corresponding slave device through the (i+1)th pulse width modulation signal line, steps S10 to S20 above further include the following steps:

[0056] Determine whether the i-th pulse width modulation (PWM) signal line is the last PWM signal line in the PWM signal line bundle; if yes, end the process; otherwise, proceed to step S10. The number of PWM connection lines connected to the master device is known. During address allocation, the master device can determine whether the i-th PWM connection line is the last one based on the number of slave devices that have already been allocated.

[0057] In some embodiments, Figure 1 The pulse width modulation signal line in the diagram is the i-th pulse width modulation signal line in the pulse width modulation signal line bundle. Figure 1 The device address allocation method in the document also includes the following steps:

[0058] Step S100: In response to the failure to receive the corresponding address allocation signal from the slave device within a preset time, send the address allocation signal to the corresponding slave device through the (i+1)th pulse width modulation signal line.

[0059] In this embodiment, after the slave device obtains the address information set for it by the master device, it should perform a handshake communication with the master device. In this embodiment, the slave device selected by the i-th PWM connection line should respond with a communication response to generate an address allocation completion signal.

[0060] In this embodiment, if the master device does not receive a response signal from the slave device selected by the i-th PWM connection line within a preset time, it indicates a response timeout. In this case, the master device can send an address allocation signal to the slave device selected by the (i+1)-th PWM connection line. The process of the master device sending the address allocation signal to the slave device selected by the (i+1)-th PWM connection line is similar to the process of sending the address allocation signal to the slave device selected by the i-th PWM connection line, and will not be described again here.

[0061] Step S200: In response to receiving the address allocation signal sent by the corresponding slave device through the controller area network bus, send the set address information to the corresponding slave device through the controller area network bus.

[0062] In this embodiment, the slave device selected by the (i+1)th PWM connection line reads the address allocation signal of the master device through the PWM receiving module and the isolation module, and can then perform a handshake communication with the master device. In this embodiment, the slave device selected by the (i+1)th PWM connection line will generate a response signal to generate the address allocation signal, while other slave devices will not respond to the master device.

[0063] In this embodiment, after receiving the response signal of the address allocation signal sent by the slave device selected by the (i+1)th PWM connection line, the master device can set the address information for the slave device and send the set address information to the slave device through the CAN bus.

[0064] In some embodiments, before sending the address allocation signal to the corresponding slave device through the (i+1)th pulse width modulation signal line, the above steps S100 to S200 further include the following steps:

[0065] Determine whether the i-th pulse width modulation signal line is the last pulse width modulation signal line in the pulse width modulation signal line bundle;

[0066] If yes, the process ends; otherwise, proceed to step S100.

[0067] Figure 3 A flowchart illustrating a device address allocation method based on controller area network bus communication according to another embodiment of the present invention.

[0068] like Figure 3 As shown, the device address allocation method for communication on the controller area network bus includes the following steps:

[0069] First, the master device sets up multiple PWM signals. Then, the master device can send an address allocation signal to one of the slave devices via CAN communication. The master device can then determine whether it receives a response signal from the slave device within a preset time. If the slave device's response time expires, the master device changes its communication address. It can then determine if the changed slave device is the last slave device in the specified position. If so, the process ends, and the allocation fails; otherwise, the master device can send an address allocation signal to the changed slave device via CAN communication.

[0070] If the slave device's response time does not time out, the master device can set the slave device's communication address (i.e., "address information" in this document). Afterward, the master device can determine whether the address setting is complete by receiving an address allocation completion signal from the slave device within a preset time. If so, it determines whether the slave device is the last slave device; otherwise, it disables the current channel's PWM output and sets the PWM output for the next channel. If the slave device is determined to be the last slave device, the process ends, and the allocation is complete.

[0071] Figure 4 An exemplary block diagram of a device address allocation apparatus based on controller area network bus communication according to an embodiment of the present invention is shown. Figure 4 As shown, the device address allocation device 400 based on controller area network bus communication includes: a first transmitting module 401, configured to transmit an address allocation signal to the corresponding slave device via a pulse width modulation signal line; and a second transmitting module 402, configured to transmit set address information to the corresponding slave device via the controller area network bus in response to a response signal received from the corresponding slave device transmitting the address allocation signal via the controller area network bus.

[0072] It should be understood that Figure 4 The various modules of the device 400 shown can be connected to the reference. Figure 1 The steps in the described method correspond accordingly. Therefore, the operations, features, and advantages described above for the method also apply to apparatus 400 and its included modules. For the sake of brevity, some operations, features, and advantages will not be repeated here.

[0073] This invention provides a machine device including a master device and multiple slave devices. The master device and the multiple slave devices are electrically interconnected via a controller area network bus and a pulse width modulation signal harness. The motion control of each slave device is controlled by the master device through a corresponding pulse width modulation signal line in the pulse width modulation signal harness. The machine device is used to execute the device address allocation method based on controller area network bus communication as described in any one of the embodiments of this invention.

[0074] This invention also provides a program product, including a computer program, which, when executed by a processor, implements the steps in the device address allocation method based on controller area network bus communication as described in any one of the embodiments of this invention.

[0075] Compared with the prior art, the embodiments of the present invention can achieve at least one of the following beneficial effects:

[0076] 1. The present invention does not add hardware circuitry for allocating device addresses. Address allocation is performed on the basis of the original hardware circuitry, which solves the problem of needing to manually set device addresses. It does not add hardware circuitry and the communication logic is simpler.

[0077] 2. In the present invention, since the slave devices are all the same hardware devices, but they are responsible for different functions under different communication addresses, it is not necessary to install them one by one during the maintenance or assembly process. It is only necessary to install them in the location and execute the communication address allocation function. The slave device can then perform the function corresponding to the installation location, thereby reducing the complexity of the maintenance or installation process, achieving the effect of allocating communication addresses by utilizing the original hardware conditions, reducing hardware circuits, and optimizing the address allocation logic.

[0078] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A device address allocation method based on controller area network bus communication, characterized in that, The master device and multiple slave devices are electrically interconnected via a controller area network bus and a pulse width modulation signal harness. The motion control of each slave device is controlled by the master device through a corresponding pulse width modulation signal line in the pulse width modulation signal harness. The device address allocation method includes the following steps: An address allocation signal is sent to the corresponding slave device via the pulse width modulation signal line; as well as In response to receiving the address allocation signal sent by the corresponding slave device via the controller area network bus, the configured address information is sent to the corresponding slave device via the controller area network bus.

2. The device address allocation method according to claim 1, characterized in that, The pulse width modulation signal line is the i-th pulse width modulation signal line in the pulse width modulation signal line bundle, where i takes the value [1, N], and N is the number of pulse width modulation signal lines in the pulse width modulation signal line bundle. The device address allocation method further includes the following steps: Step S10: In response to receiving the address allocation completion signal sent by the corresponding slave device through the controller local area network bus, send an address allocation signal to the corresponding slave device through the (i+1)th pulse width modulation signal line; Step S20: In response to receiving the address allocation signal sent by the corresponding slave device through the controller local area network bus, send the set address information to the corresponding slave device through the controller local area network bus.

3. The device address allocation method according to claim 1, characterized in that, The pulse width modulation signal line is the i-th pulse width modulation signal line in the pulse width modulation signal line bundle, and the device address allocation method further includes the following steps: Step S100: In response to the failure to receive the address allocation signal sent by the corresponding slave device within a preset time, send the address allocation signal to the corresponding slave device through the (i+1)th pulse width modulation signal line; Step S200: In response to receiving the address allocation signal sent by the corresponding slave device through the controller local area network bus, send the set address information to the corresponding slave device through the controller local area network bus.

4. The device address allocation method according to claim 2, characterized in that, Before sending the address allocation signal to the corresponding slave device via the (i+1)th pulse width modulation signal line, the device address allocation method further includes the following steps: Determine whether the i-th pulse width modulation signal line is the last pulse width modulation signal line in the pulse width modulation signal line bundle; If yes, the process ends; otherwise, proceed to step S10.

5. The device address allocation method according to claim 3, characterized in that, Before sending the address allocation signal to the corresponding slave device via the (i+1)th pulse width modulation signal line, the device address allocation method further includes the following steps: Determine whether the i-th pulse width modulation signal line is the last pulse width modulation signal line in the pulse width modulation signal line bundle; If yes, the process ends; otherwise, proceed to step S100.

6. The device address allocation method according to claim 1, characterized in that, The address allocation signal is a pulse width modulation signal with a preset pulse width length.

7. The device address allocation method according to claim 6, characterized in that, The pulse width modulation signal with the preset pulse width length is a pulse width modulation signal with a duty cycle of 1% to 9%.

8. A device address allocation device based on controller local area network bus communication, characterized in that, The master device and multiple slave devices are electrically interconnected via a controller area network bus and a pulse width modulation signal harness. The motion control of each slave device is controlled by the master device through a corresponding pulse width modulation signal line in the pulse width modulation signal harness. The device address allocation device includes: The first transmitting module is configured to transmit an address allocation signal to the corresponding slave device via a pulse width modulation signal line; and The second sending module is configured to send the set address information to the corresponding slave device via the controller local area network bus in response to a response signal received from the corresponding slave device of the address allocation signal sent via the controller local area network bus.

9. A machine device comprising a master device and a plurality of slave devices, wherein the master device and the plurality of slave devices are electrically interconnected via a controller area network bus and a pulse width modulation signal harness, wherein the motion control of each slave device is controlled by the master device via a corresponding pulse width modulation signal line in the pulse width modulation signal harness, and the machine device is used to execute the device address allocation method based on controller area network bus communication as described in any one of claims 1-7.

10. A program product comprising a computer program, which, when executed by a processor, implements the steps of the device address allocation method based on controller area network bus communication according to any one of claims 1-7.

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