Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device includes a substrate, a stack structure on the substrate, an interconnect structure between the substrate and the stack structure, and a pillar element penetrating the stack structure. The pillar element includes a channel layer, a memory layer surrounding the channel layer, and a dielectric layer surrounding the channel layer. The dielectric layer and the storage layer contain different materials.

Description

TECHNICAL FIELD

[0001] The present application relates to semiconductor devices and methods of fabricating the same, and more particularly to three-dimensional semiconductor devices and methods of fabricating the same. BACKGROUND

[0002] In the semiconductor field, improvement in feature size, speed, performance, density, and cost per integrated circuit are important goals. However, as the size of semiconductor devices is reduced, the distance between elements and elements decreases, which can cause undesirable interference problems, resulting in reduced electrical performance of the semiconductor devices. SUMMARY

[0003] The present application relates to semiconductor devices and methods of fabricating the same, and more particularly to three-dimensional semiconductor devices and methods of fabricating the same.

[0004] According to some embodiments of the present application, a semiconductor device is provided. The semiconductor device includes a substrate, a stack structure on the substrate, an interconnect structure between the substrate and the stack structure, and a pillar element through the stack structure. The pillar element includes a channel layer, a storage layer surrounding the channel layer, and a dielectric layer surrounding the channel layer. The dielectric layer and the storage layer include different materials.

[0005] For a better understanding of the above and other aspects of the present application, one exemplary embodiment is hereinafter described in detail, with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a cross-sectional schematic diagram illustrating a semiconductor device according to some embodiments;

[0007] Figure 2 is a cross-sectional schematic diagram illustrating a semiconductor device according to some embodiments;

[0008] Figures 3 to 22 is a cross-sectional schematic diagram illustrating a semiconductor device according to some embodiments; and

[0009] Figures 23 to 36 is a cross-sectional schematic diagram illustrating a semiconductor device according to some embodiments.

[0010] BRIEF DESCRIPTION OF DRAWINGS

[0011] 10, 20: semiconductor device

[0012] 10M, 10P, 20M, 20P: semiconductor structure

[0013] 100, 300: substrate

[0014] 100S, 101U, 113BU, 113U, 115U, 121U, 300U, 302U, ST1U: upper surface

[0015] 101, 302: insulating layer

[0016] 102: conductive layer

[0017] 110: pillar element

[0018] 111, 111A, 111B, 111C: storage layer

[0019] 111BU, 111CU, 111E, 112BU, 112E, 112U, 240E, 241E: end surface

[0020] 112, 112A, 112B: passage layer

[0021] 112S: sidewall

[0022] 113, 113A, 113B: insulating film

[0023] 113E1, 113E2: end portion

[0024] 114: air gap

[0025] 115: contact pad

[0026] 116, 116A: dielectric layer

[0027] 116S: outer sidewall

[0028] 120, 120A: conductive film

[0029] 120-1: first portion

[0030] 120-2: second portion

[0031] 121, 123, 125, 161, 181: insulating material layer

[0032] 122: conductive structure

[0033] 124, 1651, 1851, 2651, 2851: via element

[0034] 126, 1652, 1852, 2652, 2852: conductive element

[0035] 140, 240, 240A: isolation layer

[0036] 160, 180, 260, 280: interconnect structure

[0037] 165, 185: conductive interconnect

[0038] 195,295: semiconductor element

[0039] 241: conductive strip

[0040] 401, 901, 2001, 2301: hole

[0041] 701: recessed chamber

[0042] 810: column structure

[0043] 1001R, 2401R: space

[0044] 1121: first passage portion

[0045] 1122: second passage portion

[0046] 1123: third passage portion

[0047] 2201, 3601: opening

[0048] 2202, 3602: recess

[0049] D1: first direction

[0050] D2: second direction

[0051] D3: third direction

[0052] ST: stacked structure

[0053] ST1: insulating stacked structure

[0054] ST-1, ST-2: surface DETAILED DESCRIPTION

[0055] The drawings are not necessarily drawn to scale of the actual product for the purpose of clarity in illustrating the embodiments. In the following manufacturing methods, one or more additional operations can be present between the operations, and the order of the operations can be changed. Therefore, the specification and drawings are merely illustrative of the embodiments and are not intended to limit the scope of the present application. The same reference numerals are used to designate the same elements throughout the specification.

[0056] The ordinal numbers used to modify elements in the specification and claims, such as "first," "second," etc., do not imply or represent a specific position, arrangement, or manufacturing order in the structure; these ordinal numbers are merely used to clearly distinguish multiple elements with the same name. Spatial terms used in the specification and claims, such as "above," "over," "above," "higher than," "top," "below," "below," "below," "lower than," "bottom," etc., describe the relative spatial or positional relationship between one element and another in the drawings, and these spatial or positional relationships can be direct or indirect (with other elements disposed between the two elements), unless otherwise specified. Spatial terms may cover structures shown in other orientations, not limited to those shown in the drawings. Structures can be flipped or rotated at various angles, and the spatial terms used herein can be interpreted accordingly. The singular forms "a" and "the" used in the specification and claims are also intended to include the plural forms, unless the context clearly indicates otherwise. The use of "and / or" in the specification and claims includes any and all combinations of one or more of the listed items.

[0057] Furthermore, the term "electrical connection" used in the specification and appended claims can mean that multiple elements form an ohmic contact, that current flows between multiple elements, or that multiple elements have an operational relationship. An operational relationship can be, for example, one element driving another element, but the current may not flow directly between the two elements. The term "deposition" used in the specification and appended claims includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and epitaxial growth. Depending on the type of material to be formed, those skilled in the art can select a suitable technique for forming the material. The terms "etching" and "etching back" used in the specification and appended claims include, but are not limited to, dry etching and wet etching. The term "polishing" used in the specification and appended claims includes, but is not limited to, chemical-mechanical planarization (CMP) and ion milling. The terms "etching," "etching back," and "polishing" used in the specification and appended claims are interchangeable, and those skilled in the art can select appropriate removal techniques based on the structure and materials.

[0058] Embodiments of the present disclosure can be applied to a variety of different types of three-dimensional semiconductor devices. For example, embodiments of the present disclosure can be applied to, but are not limited to, semiconductor devices including a memory array, which can be a volatile memory array or a non-volatile memory array. In some embodiments, the present disclosure can be applied to semiconductor devices including a vertical channel and NAND flash memory.

[0059] Figure 1 FIG. 1 is a schematic diagram illustrating a cross-sectional view of a semiconductor device 10 according to some embodiments of the present disclosure. The semiconductor device 10 includes a semiconductor structure 10P and a semiconductor structure 10M. The semiconductor structure 10P is bonded to the semiconductor structure 10M.

[0060] The semiconductor structure 10P includes a substrate 100, one or more semiconductor elements 195 in the substrate 100, and an interconnect structure 180 on the substrate 100. The interconnect structure 180 can include one or more insulating material layers 181 and one or more conductive interconnects 185 in the one or more insulating material layers 181. The conductive interconnects 185 can electrically connect the semiconductor elements 195. In some embodiments, the insulating material layers 181 can separate the conductive interconnects 185 from each other. In this embodiment, the insulating material layers 181 can be stacked along a first direction Dl. The first direction Dl can be parallel or substantially parallel to a normal direction of an upper surface 100S of the substrate 100. The conductive interconnects 185 can include one or more via elements 1851 and one or more conductive elements 1852. Figure 1 The conductive interconnects 185 are illustrated as including 3 via elements 1851 and 3 conductive elements 1852, but the present disclosure is not limited thereto, and the conductive interconnects 185 can include more or less via elements 1851 and more or less conductive elements 1852. The via elements 1851 electrically connect the conductive elements 1852. The semiconductor elements 195 can be peripheral devices. The peripheral devices can be used to control signals transmitted to or from the semiconductor structure 10M. The peripheral devices can include digital peripheral circuits, analog peripheral circuits, and / or mixed-signal peripheral circuits, etc. For example, the peripheral devices can include page buffers, row decoders, column decoders, sense amplifiers, drivers, transistors, diodes, resistors, or capacitors, etc. Figure 1The semiconductor elements 195 are illustrated as being in the substrate 100, but the application is not limited thereto, and the semiconductor elements 195 can be formed on the upper surface 100S of the substrate 100, or partially in the substrate 100 (i.e., a portion of the semiconductor elements 195 is on the upper surface 100S of the substrate 100 and another portion is below the upper surface 100S of the substrate 100), or completely in the substrate 100 (i.e., the semiconductor elements 195 are completely below the upper surface 100S of the substrate 100). In some embodiments, the semiconductor structure 10P can include one or more isolation regions between the plurality of semiconductor elements 195 to separate the plurality of semiconductor elements 195 from each other. In some embodiments, complementary metal-oxide-semiconductor (CMOS) technology can be used to form the semiconductor elements 195 in or on the substrate 100.

[0061] The semiconductor structure 10M includes the interconnect structure 160, the stack structure ST, the pillar elements 110, the isolation layers 140, the conductive films 120, the conductive structures 122, the via elements 124, the conductive elements 126, the insulating material layers 121, the insulating material layers 123, and the insulating material layers 125. The interconnect structure 160 is on and bonded to the interconnect structure 180. The interconnect structure 160 can include one or more insulating material layers 161 and one or more conductive interconnects 165 in the one or more insulating material layers 161. In some embodiments, the insulating material layers 161 can separate the plurality of conductive interconnects 165 from each other. In this embodiment, the plurality of insulating material layers 161 can be stacked along the first direction D1. The conductive interconnects 165 can include one or more via elements 1651 and one or more conductive elements 1652. Figure 1 The conductive interconnects 165 are illustrated as including 3 via elements 1651 and 3 conductive elements 1652, but the application is not limited thereto, and the conductive interconnects 165 can include more or fewer via elements 1651 and more or fewer conductive elements 1652. The via elements 1651 electrically connect the conductive elements 1652. The insulating material layers 161 of the interconnect structure 160 can be bonded to the insulating material layers 181 of the interconnect structure 180. The conductive elements 1652 of the interconnect structure 160 can be bonded to the conductive elements 1852 of the interconnect structure 180. The conductive interconnects 165 can electrically connect the conductive interconnects 185.

[0062] The stack structure ST is on the substrate 100. The interconnect structure 160 is between the substrate 100 and the stack structure ST. The stack structure ST includes a plurality of insulating layers 101 and a plurality of conductive layers 102 stacked alternately along the first direction D1. The plurality of insulating layers 101 separate the plurality of conductive layers 102 from each other. In this embodiment, the uppermost layer and the lowermost layer of the stack structure ST are both insulating layers 101. The lowermost insulating layer 101 in the stack structure ST can directly contact the insulating material layer 161 of the interconnect structure 160. Figure 1 Seven insulating layers 101 and six conductive layers 102 are shown, but the present disclosure is not limited thereto, and the stack structure ST can include more or fewer insulating layers 101 and conductive layers 102.

[0063] The semiconductor structure 10M may include one or more pillar elements 110. Multiple pillar elements 110 may be distributed. Pillar elements 110 may extend along a first direction D1 and through the stacked structure ST. Pillar element 110 includes a storage layer 111, a channel layer 112, an insulating film 113, an air gap 114, a pad 115, and a dielectric layer 116. Multiple conductive layers 102 of the stacked structure ST may surround the storage layer 111. The channel layer 112 and the insulating film 113 may extend beyond the stacked structure ST. The storage layer 111 and the pad 115 are in the stacked structure ST. The dielectric layer 116 is on the stacked structure ST. The channel layer 112 may include a first channel portion 1121, a second channel portion 1122, and a third channel portion 1123. The second channel portion 1122 connects the first channel portion 1121 and the third channel portion 1123. The first channel portion 1121 is located between the insulating film 113 and the storage layer 111. Storage layer 111 is on the outer wall of the first channel portion 1121 of channel layer 112. Storage layer 111 may cover the outer wall of the first channel portion 1121. Storage layer 111 may surround the first channel portion 1121. Storage layer 111 may be tubular. First channel portion 1121 is on the sidewall of insulating film 113. First channel portion 1121 may surround a portion of the sidewall of insulating film 113. Second channel portion 1122 is located between insulating film 113 and dielectric layer 116. Dielectric layer 116 is on the outer wall of the second channel portion 1122 of channel layer 112. Dielectric layer 116 may cover the outer wall of the second channel portion 1122. Dielectric layer 116 may be tubular. Second channel portion 1122 is on the sidewall of insulating film 113. Second channel portion 1122 may surround a portion of the sidewall of insulating film 113. A third channel portion 1123 is located between the insulating film 113 and the conductive structure 122. The third channel portion 1123 may be on the end portion 113E1 of the insulating film 113. The third channel portion 1123 may cover the end portion 113E1 of the insulating film 113. The insulating film 113 may extend along the first direction D1 and penetrate the stacked structure ST. An air gap 114 is in the insulating film 113. A pad 115 is on the end portion 113E2 of the insulating film 113. The ends portion 113E1 and 113E2 of the insulating film 113 are on opposite sides of the insulating film 113. The pad 115 is located between the insulating film 113 and the interconnect structure 160. A storage layer 111 is connected between the dielectric layer 116 and the pad 115. The dielectric layer 116 and the pad 115 may be located on opposite sides of the storage layer 111. The ends of channel layer 112, storage layer 111, and insulating film 113 are accessible to pad 115. Pad 115 is electrically connected to channel layer 112. Conductive interconnects 165 of interconnect structure 160 are electrically connected to pad 115 of pillar element 110 and channel layer 112.

[0064] The semiconductor structure 10M may include one or more isolation layers 140. The isolation layer 140 may extend along a first direction D1 and penetrate the stacked structure ST. The ends of the isolation layer 140 may extend beyond the stacked structure ST. The isolation layer 140 may be located between two pillar elements 110. A conductive film 120 is on the stacked structure ST. The conductive film 120 is on the sidewall of the dielectric layer 116. The conductive film 120 may surround the dielectric layer 116. The conductive film 120 may contact the dielectric layer 116. An insulating material layer 121 is on the conductive film 120. In this embodiment, a portion of the insulating material layer 121 may penetrate the conductive film 120 and divide the conductive film 120 into a first portion 120-1 and a second portion 120-2, and the insulating material layer 121 may electrically isolate the first portion 120-1 from the second portion 120-2. The insulating material layer 121 may surround the dielectric layer 116. The insulating material layer 121 may contact the dielectric layer 116. Conductive structure 122 is located within insulating material layer 123. Conductive structure 122 and insulating material layer 123 are located on insulating material layer 121. Conductive structure 122 is located on the third channel portion 1123 of channel layer 112. Conductive structure 122 can contact dielectric layer 116 and the third channel portion 1123 of channel layer 112. Conductive structure 122 can electrically connect multiple pillar elements 110. Dielectric layer 116 can be connected between storage layer 111 and conductive structure 122. Through-hole element 124 is located within insulating material layer 125. Through-hole element 124 and insulating material layer 125 are located on conductive structure 122 and insulating material layer 123. Insulating material layer 123 is located between insulating material layer 121 and insulating layer 125. Conductive element 126 is located on insulating material layer 125. Conductive element 126, through-hole element 124, and conductive structure 122 can be electrically connected to each other. The channel layer 112 is electrically connected between the conductive structure 122 and the conductive interconnect 165 of the interconnect structure 160.

[0065] The semiconductor structure 10M of the semiconductor device 10 includes multiple memory cells. These memory cells are configured in a stacked structure ST. A memory cell can be defined in a memory layer 111 at the intersection of a channel layer 112 and a conductive layer 102 of the stacked structure ST. The memory cells are electrically connected to semiconductor elements 195 via conductive interconnects 165 of interconnect structure 160 and conductive interconnects 185 of interconnect structure 180. The memory cells are electrically connected to conductive structures 122, via elements 124, and conductive elements 126. Multiple memory cells arranged along a first direction D1 can form a memory cell array, and multiple memory cell arrays can form a memory array. The conductive structure 122 can serve as a common source line for the memory cells (or control memory cells). The lowest conductive layer 102 in the stacked structure ST can serve as a string select line (SSL) for the memory cells (or control memory cells), and other conductive layers 102 can serve as multiple word lines (WL) for the memory cells (or control memory cells). The conductive film 120 can serve as a ground select line (GSL) for the memory cell (or control memory cell). The conductive film 120, dielectric layer 116, and second channel portion 1122 can form a transistor switch. The transistor switch formed by the conductive film 120, dielectric layer 116, and second channel portion 1122 can function as a ground select switch. The semiconductor element 195 of the semiconductor structure 10P can be used to control the operation of the memory cell of the semiconductor structure 10M, such as read operations, write operations, erase operations, etc.

[0066] Figure 2 This is a schematic cross-sectional view of a semiconductor device 20 according to some embodiments of the present invention. The semiconductor device 20 includes a semiconductor structure 20P and a semiconductor structure 20M. The semiconductor structure 20P is bonded to the semiconductor structure 20M. Figure 1 and Figure 2 In this context, identical component symbols represent the same component and have the same properties; this will not be repeated below. Semiconductor structure 20P and... Figure 1 The difference between the semiconductor structure 10P and the semiconductor structure 20P is that the semiconductor structure 20P also includes a semiconductor element 295 in the substrate 100 and a conductive interconnect 285 electrically connecting the semiconductor element 295.

[0067] Semiconductor structure 20P includes a substrate 100, one or more semiconductor elements 195 and one or more semiconductor elements 295 in the substrate 100, and an interconnect structure 280 on the substrate 100. The interconnect structure 280 may include one or more insulating material layers 181, and one or more conductive interconnects 185 and one or more conductive interconnects 285 in the one or more insulating material layers 181. In some embodiments, the insulating material layers 181 may separate the conductive interconnects 185 and conductive interconnects 285 from each other. The conductive interconnects 285 may include one or more through-hole elements 2851 and one or more conductive elements 2852. Figure 2 The conductive interconnect 285 is illustrated as including three through-hole elements 2851 and three conductive elements 2852, but the invention is not limited thereto; the conductive interconnect 285 may include more or fewer through-hole elements 2851 and more or fewer conductive elements 2852. The through-hole elements 2851 are electrically connected to the conductive elements 2852. Semiconductor elements 195 and 295 may be peripheral devices. Peripheral devices can be used to control signals transmitted to or from the semiconductor structure 20M. Figure 2 The semiconductor element 295 is illustrated as being in the substrate 100, but the invention is not limited thereto. The semiconductor element 295 may be formed on the upper surface 100S of the substrate 100, or partially formed in the substrate 100 (i.e., a portion of the semiconductor element 295 is on the upper surface 100S of the substrate 100 and another portion is below the upper surface 100S of the substrate 100), or completely formed in the substrate 100 (i.e., the semiconductor element 295 is completely below the upper surface 100S of the substrate 100). In some embodiments, complementary metal-oxide-semiconductor (CMOS) technology may be used to form the semiconductor element 295 in or on the substrate 100.

[0068] Semiconductor structure 20M and Figure 1 The difference between the semiconductor structure 10M and the semiconductor structure 20M is that the semiconductor structure 20M also includes conductive interconnects 265 and conductive strips 241 in the stacked structure ST.

[0069] Semiconductor structure 20M includes interconnect structure 260, stacked structure ST, pillar element 110, isolation layer 240, conductive strip 241, conductive film 120, conductive structure 122, through-hole element 124, conductive element 126, insulating material layer 121, insulating material layer 123, and insulating material layer 125. Interconnect structure 260 is on and bonded to interconnect structure 280. Interconnect structure 260 may include one or more insulating material layers 161, and one or more conductive interconnects 165 and one or more conductive interconnects 265 within one or more insulating material layers 161. In some embodiments, insulating material layer 161 may separate conductive interconnects 165 and conductive interconnects 265 from each other. Conductive interconnect 265 may include one or more through-hole elements 2651 and one or more conductive elements 2652. Figure 2 The conductive interconnect 265 is illustrated as comprising three through-hole elements 2651 and three conductive elements 2652, but the invention is not limited thereto; the conductive interconnect 265 may comprise more or fewer through-hole elements 2651 and more or fewer conductive elements 2652. The through-hole elements 2651 are electrically connected to the conductive elements 2652. The insulating material layer 161 of the interconnect structure 260 may be bonded to the insulating material layer 181 of the interconnect structure 280. The conductive elements 1652 of the interconnect structure 260 may be bonded to the conductive elements 1852 of the interconnect structure 280. The conductive elements 2652 of the interconnect structure 260 may be bonded to the conductive elements 2852 of the interconnect structure 280. The conductive interconnect 265 may be electrically connected to the conductive interconnect 285. The conductive strip 241 extends along a first direction D1 and penetrates the stacked structure ST. An isolation layer 240 is on the sidewall of the conductive strip 241. The isolation layer 240 may cover the sidewall of the conductive strip 241. The isolation layer 240 separates the conductive strip 241 from the stacked structure ST. The conductive strip 241 is electrically isolated from the multiple conductive layers 102 of the stacked structure ST. The conductive strip 241 is electrically connected between the conductive structure 122 and the conductive interconnect 265 of the interconnect structure 260. In this embodiment, the isolation layer 240 and the conductive strip 241 divide the conductive film 120 into a first portion 120-1 and a second portion 120-2, and the isolation layer 240 electrically isolates the first portion 120-1 from the second portion 120-2. The conductive strip 241 can serve as a source line (SL) for a memory cell (or control memory cell) in the semiconductor structure 20M. The semiconductor elements 195 and 295 of the semiconductor structure 20P can be used to control operations on the memory cells of the semiconductor structure 20M, such as read operations, write operations, erase operations, etc.

[0070] Figures 3 to 22 This illustrates a method of manufacturing a semiconductor device according to some embodiments.

[0071] Figure 3This is a schematic diagram illustrating a stage of the manufacturing process. A substrate 300 is provided. The substrate 300 may be a semiconductor substrate. The substrate 300 may contain semiconductor materials, such as doped or undoped single-crystal silicon, doped or undoped polycrystalline silicon, germanium, etc. In some embodiments, the substrate 300 may be a carrier wafer, such as a low-cost wafer or a regenerated wafer. An insulating stack structure ST1 is formed on the substrate 300. The insulating stack structure ST1 includes a plurality of insulating layers 101 and a plurality of insulating layers 302 staggered along a first direction D1 on the upper surface 300U of the substrate 300. The plurality of insulating layers 101 separate the plurality of insulating layers 302 from each other. The insulating layers 101 and insulating layers 302 may extend along a second direction D2 and / or a third direction D3. The first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other. In this embodiment, the uppermost and lowermost layers of the insulating stack structure ST1 are both insulating layers 101. The uppermost insulating layer 101 in the insulating stack structure ST1 can serve as a hard mask. The lowermost insulating layer 101 in the insulating stack structure ST1 can contact the substrate 300. The lowermost insulating layer 101 in the insulating stack structure ST1 can electrically isolate the insulating layer 302 from the substrate 300. Figure 3 The invention shows seven insulating layers 101 and six insulating layers 302, but is not limited thereto. The insulating stack structure ST1 may contain more or fewer insulating layers 101 and insulating layers 302.

[0072] The thickness of insulating layer 101 in the first direction D1 may be between 50 Å (Angstroms) and 600 Å, for example, between 150 Å and 300 Å. The thickness of insulating layer 302 in the first direction D1 may be between 50 Å and 600 Å, for example, between 150 Å and 350 Å. Insulating layer 101 and insulating layer 302 may contain different materials. Insulating layer 101 may contain an insulating material, which may contain an oxide. In some embodiments, insulating layer 101 may contain silicon oxide. Insulating layer 302 may contain an insulating material, which may contain a nitride. In some embodiments, insulating layer 302 may contain silicon nitride. In some embodiments, insulating layer 101 is a silicon oxide layer and insulating layer 302 is a silicon nitride layer. In some embodiments, insulating layers 101 and 302 may be interleaved on the upper surface 300U of substrate 300 by deposition to form an insulating stack structure ST1.

[0073] Figure 4This is a schematic diagram illustrating a stage of the manufacturing process. A plurality of holes 401 are formed in the insulating stack structure ST1. The plurality of holes 401 are separated from each other. The holes 401 extend along a first direction D1 and penetrate the plurality of insulating layers 101 and 302 of the insulating stack structure ST1, ending at the substrate 300. The bottom of the holes 401 may be lower than the upper surface 300U of the substrate 300 in the first direction D1. The holes 401 expose the sidewalls of the insulating stack structure ST1 and the substrate 300. The holes 401 may have any shape, such as cylindrical, elliptical, or square. In some embodiments, the holes 401 may be formed by etching to remove portions of the insulating layers 101, 302, and 300.

[0074] Figure 5 This is a schematic diagram illustrating a stage of the manufacturing process. A storage layer 111A, a channel layer 112A, an insulating film 113A, and an air gap 114 are formed. The storage layer 111A, channel layer 112A, and insulating film 113A can fill the hole 401 and are formed on the upper surface ST1U of the insulating stack structure ST1. A portion of the storage layer 111A may be located between the channel layer 112A and the insulating stack structure ST1. A portion of the storage layer 111A may be located between the channel layer 112A and the substrate 300. The channel layer 112A may be located between the storage layer 111A and the insulating film 113A. The air gap 114 may be located within the insulating film 113A. Storage layer 111A may comprise a multilayer structure known in the field of memory technology, such as ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride-oxide), ONONONO (oxide-nitride-oxide-nitride-oxide-oxide), SONOS (silicon-silicon oxide-silicon nitride-silicon oxide-silicon), BE-SONOS (bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon), TANOS (tantalum nitride-alumina-silicon nitride-silicon oxide-silicon), MA BE-SONOS (metal-high dielectric constant material bandgap silicon-silicon oxide-silicon nitride-silicon oxide-silicon), MONOS (metal-oxide-nitride-oxide-silicon), and combinations thereof. Channel layer 112A may comprise a semiconductor material, such as doped or undoped single-crystal silicon, polycrystalline silicon, germanium, etc. In some embodiments, channel layer 112A comprises undoped polycrystalline silicon. The insulating film 113A may comprise an insulating material, which may comprise an oxide. In some embodiments, the insulating film 113A comprises silicon oxide.

[0075] In some embodiments, a storage layer 111A can be formed by deposition on the upper surface ST1U of the insulating stack structure ST1, the sidewalls of the insulating layer 101 exposed by the aperture 401, the sidewalls of the insulating layer 302 exposed by the aperture 401, and the surface of the substrate 300 exposed by the aperture 401. A channel layer 112A can be formed on the storage layer 111A by deposition, a portion of the channel layer 112A being formed in the aperture 401 and a portion of the channel layer 112A being formed on the insulating stack structure ST1. An insulating film 113A can be formed in the remaining space of the aperture 401 by deposition, a portion of the insulating film 113A being formed on the insulating stack structure ST1. During the formation of the insulating film 113A, an air gap 114 can be formed within the insulating film 113A. In some embodiments, the air gap 114 may not be present within the insulating film 113A.

[0076] Figure 6 This is a schematic diagram illustrating a stage of the manufacturing process. A storage layer 111B, a channel layer 112B, and an insulating film 113B are formed in an insulating stack structure ST1. An air gap 114 is located within the insulating film 113B. The storage layer 111B, channel layer 112B, and insulating film 113B can extend along a first direction D1 and penetrate the insulating stack structure ST1. The upper surface 113BU of the insulating film 113B, the end face 112BU of the channel layer 112B, the end face 111BU of the storage layer 111B, and the upper surface ST1U of the insulating stack structure ST1 can be coplanar. In some embodiments, the portions of the storage layer 111A, channel layer 112A, and insulating film 113A above the insulating stack structure ST1 can be removed by polishing, while retaining the portions of the storage layer 111A, channel layer 112A, and insulating film 113A within the aperture 401, to form a structure as shown in the diagram. Figure 6 The structure shown is as follows: The portion of storage layer 111A within the aperture 401 is storage layer 111B. The portion of channel layer 112A within the aperture 401 is channel layer 112B. The portion of insulating film 113A within the aperture 401 is insulating film 113B.

[0077] Figure 7This is a schematic diagram illustrating a stage of the manufacturing process. A storage layer 111C, a channel layer 112, and an insulating film 113 are formed in an insulating stack structure ST1. An air gap 114 is located within the insulating film 113. The storage layer 111C, channel layer 112, and insulating film 113 can extend along a first direction D1 and penetrate the insulating stack structure ST1. The storage layer 111C can surround the channel layer 112. The upper surface 113U of the insulating film 113, the end face 112U of the channel layer 112, and the end face 111CU of the storage layer 111C can be coplanar. The upper surface 113U of the insulating film 113, the end face 112U of the channel layer 112, and the end face 111CU of the storage layer 111C can be higher than the upper surface 302U of the uppermost insulating layer 302 among the plurality of insulating layers 302 in the first direction D1. The upper surface 113U of the insulating film 113, the end face 112U of the channel layer 112, and the end face 111CU of the storage layer 111C may be lower than the upper surface ST1U of the insulating stack structure ST1 in the first direction D1. The channel layer 112 may include a first channel portion 1121, a second channel portion 1122, and a third channel portion 1123. The third channel portion 1123 is in the substrate 300. At least a portion of the second channel portion 1122 is in the substrate 300. In some embodiments, a portion of the storage layer 111B, a portion of the channel layer 112B, and a portion of the insulating film 113B may be removed by an etching back process to form a recess 701. The portion of the storage layer 111B that is retained is the storage layer 111C. The portion of the channel layer 112B that is retained is the channel layer 112. The portion of the insulating film 113B that is retained is the insulating film 113. In some embodiments, the etching process used in this stage can be wet etching using hydrofluoric acid (HF), or dry etching using hydrofluoric acid / ammonia (HF / NH3) or nitrogen trifluoride / ammonia (NF3 / NH3).

[0078] Figure 8This is a schematic diagram illustrating a stage of the manufacturing process. A pad 115 is formed. The upper surface 115U of the pad 115 may be coplanar with the upper surface ST1U of the insulating stack structure ST1. In some embodiments, a pad material may be formed in the recess 701 and on the upper surface ST1U of the insulating stack structure ST1 by a deposition process; then, a polishing process may be used to remove the portion of the pad material above the upper surface ST1U of the insulating stack structure ST1, leaving the portion of the pad material in the recess 701, thereby forming a pillar structure 810. The pillar structure 810 includes a storage layer 111C, a channel layer 112, an insulating film 113, an air gap 114, and a pad 115. The portion of the pad material in the recess 701 is the pad 115. The pad material and the pad 115 may contain semiconductor materials, such as doped or undoped monocrystalline silicon, polycrystalline silicon, germanium, etc. In some embodiments, the pad material and the pad 115 contain N-type doped polycrystalline silicon. In some embodiments, the pad material and the pad 115 comprise N+ polycrystalline silicon with high N-type doping.

[0079] Figure 9 This is a schematic diagram illustrating a stage of the manufacturing process. An insulating material layer 161 is formed on an insulating stack structure ST1. A hole 901 is formed in the insulating stack structure ST1. The hole 901 may extend along a first direction D1 and penetrate the insulating stack structure ST1 and the insulating material layer 161, and terminate at an insulating layer 101 of the insulating stack structure ST1. In this embodiment, the hole 901 terminates at the lowermost insulating layer 101 among the plurality of insulating layers 101. The bottom of the hole 901 may be higher than the upper surface 300U of the substrate 300 in the first direction D1. The bottom of the hole 901 may be lower than the upper surface 101U of the lowermost insulating layer 101 among the plurality of insulating layers 101 in the first direction D1. The hole 901 may be located between a plurality of pillar structures 810. The hole 901 exposes the sidewalls of the insulating material layer 161 and the sidewalls of the insulating stack structure ST1. The insulating material layer 161 may contain an insulating material, which may contain an oxide. In some embodiments, the insulating material layer 161 contains silicon oxide. In some embodiments, an insulating material layer 161 may be formed on the upper surface ST1U of the insulating stack structure ST1 by a deposition process; and a portion of the insulating material layer 161, a portion of the insulating layer 101 and a portion of the insulating layer 302 may be removed by an etching process to form a hole 901.

[0080] Figure 10This is a schematic diagram illustrating a stage of the manufacturing process. Multiple spaces 1001R are formed. The multiple spaces 1001R are situated between multiple insulating layers 101. The spaces 1001R can connect to vias 901. The spaces 1001R expose the upper and lower surfaces of the insulating layers 101, and a portion of the outer sidewall of the storage layer 111C of the pillar structure 810. In some embodiments, multiple spaces 1001R can be formed by selectively etching away multiple insulating layers 302 between the multiple insulating layers 101, while retaining the multiple insulating layers 101, the insulating material layer 161, the pillar structure 810, and the substrate 300. The selective etching can be performed via the vias 901. In some embodiments, phosphoric acid (H3PO4) can be used to remove the insulating layers 302. In this stage, the pillar structure 810 can serve as a structural support.

[0081] Figure 11 This is a schematic diagram illustrating a stage of the manufacturing process. A stacked structure ST comprising multiple conductive layers 102 and multiple insulating layers 101 is formed, and an isolation layer 140 is formed in the stacked structure ST. The multiple conductive layers 102 are interposed between the multiple insulating layers 101. The conductive layers 102 may extend along a second direction D2 and / or a third direction D3. The isolation layer 140 may extend along a first direction D1 and penetrate the stacked structure ST and the insulating material layer 161. The isolation layer 140 may be interposed between multiple pillar structures 810. The isolation layer 140 may contain an insulating material, which may contain an oxide. In some embodiments, the isolation layer 140 contains silicon oxide. The conductive layers 102 may contain a conductive material, which may include, but is not limited to, doped or undoped polysilicon, metals, or combinations thereof. The conductive layer 102 may contain a combination of metals and high-dielectric-constant dielectric materials. The conductive layer 102 may contain a multilayer structure, such as a multilayer structure formed by multiple metal layers, or a multilayer structure formed by one or more metal layers and one or more high-dielectric-constant dielectric layers. High dielectric constant materials are those with a dielectric constant greater than 3.9. High dielectric constant materials include, but are not limited to, Si3N4 and AlO. x , La2O3, Ta2O5, Y2O3, TiO2, HfO x ZrO x And so on, where x is greater than 0. In some embodiments, the conductive layer 102 comprises AlO x / TiN / W multilayer structure. In some embodiments, the conductive layer 102 can be deposited to fill the space 1001R to form a stacked structure ST; the insulating layer 140 can be deposited to fill the hole 901.

[0082] Figure 12This is a schematic diagram illustrating a stage of the manufacturing process. An interconnect structure 160 is formed on surface ST-1 of the stacked structure ST. The interconnect structure 160 includes a plurality of insulating material layers 161 and a plurality of conductive interconnects 165 in the plurality of insulating material layers 161. In this embodiment, two conductive interconnects 165 correspond to different pillar structures 810. The two conductive interconnects 165 are electrically connected to the different pillar structures 810. The conductive interconnects 165 include through-hole elements 1651 and conductive elements 1652. Through-hole elements 1651 and conductive elements 1652 may contain the same or different materials. Through-hole elements 1651 and conductive elements 1652 may contain conductive materials, including but not limited to metals. For example, through-hole elements 1651 and conductive elements 1652 may contain TiN, TaN, Ti, Ta, Cu, Al, Ag, W, Ir, Ru, Pt or any combination thereof. In some embodiments, through-hole elements 1651 and conductive elements 1652 contain Cu. In some embodiments, an insulating material layer 161 may be formed by deposition, and one or more grooves may be formed in the insulating material layer 161 by patterning, the grooves being located where via elements 1651 and / or conductive elements 1652 will be formed. The material of the via elements 1651 and / or the material of the conductive elements 1652 is then filled into the grooves to form the via elements 1651 and / or conductive elements 1652 in the insulating material layer 161. The above steps may be repeated until the configuration of the conductive interconnects 165 meets the requirements. In some embodiments, the interconnect structure 160 may be understood as a memory array interconnect structure. The conductive element 1652 located in the insulating material layer 161 furthest from the pillar structure 810 in the first direction D1 may be understood as a bonding layer, which can be used to bond other structures. In some embodiments, the insulating material layer 161 may be understood as an inter-metal dielectric (IMD) layer.

[0083] Figure 13This is a schematic diagram illustrating a stage of the manufacturing process. A semiconductor structure 10P is provided. The semiconductor structure 10P is bonded to an interconnect structure 160. The semiconductor structure 10P includes a substrate 100, a plurality of semiconductor elements 195 in the substrate 100, and an interconnect structure 180 on the substrate 100 and the semiconductor elements 195. The interconnect structure 180 may include a plurality of insulating material layers 181 and a plurality of conductive interconnects 185 in the plurality of insulating material layers 181. The plurality of conductive interconnects 185 may electrically connect different semiconductor elements 195 respectively. The conductive interconnects 185 include through-hole elements 1851 and conductive elements 1852. Through-hole elements 1851 and conductive elements 1852 may contain the same or different materials. Through-hole elements 1851 and conductive elements 1852 may contain conductive materials, including but not limited to metals. For example, via element 1851 and conductive element 1852 may comprise TiN, TaN, Ti, Ta, Cu, Al, Ag, W, Ir, Ru, Pt, or any combination thereof. In some embodiments, via element 1851 and conductive element 1852 comprise Cu. The conductive element 1852 located in the insulating material layer 181 furthest from the substrate 100 in the first direction D1 can be understood as a bonding layer, which can be used to bond other structures (e.g., to bond interconnect structure 160). The manufacturing method of interconnect structure 180 may be similar to the manufacturing method of interconnect structure 160. In some embodiments, the bonding layer (conductive element 1852) of interconnect structure 180 of semiconductor structure 10P may be bonded to the bonding layer (conductive element 1652) of interconnect structure 160 by solid-state bonding technology, such as diffusion bonding technology. The bonding of semiconductor structure 10P and interconnect structure 160 may be a copper-copper hybrid bonding (Cu-Cu hybrid bonding).

[0084] After the semiconductor structure 10P is bonded to the interconnect structure 160, the multiple conductive interconnects 185 of the semiconductor structure 10P can be electrically connected to different conductive interconnects 165 in the interconnect structure 160, so that the semiconductor element 195 can be electrically connected to the pillar structure 810 through the corresponding conductive interconnect 185 and the corresponding conductive interconnect 165.

[0085] In some embodiments, the interconnect structure 180 may be a middle-end-of-line (MEOL) interconnect structure or a back-end-of-line (BEOL) interconnect structure.

[0086] Figure 14 This is a structural diagram illustrating one stage of the manufacturing process. (Rotation) Figure 13 The structure is shown. After rotation, the substrate 300 is positioned above the substrate 100. In some embodiments, the rotation step may be omitted from the manufacturing process.

[0087] Figure 15 This is a schematic diagram illustrating a stage in the manufacturing process. A portion of the pillar structure 810 is exposed. In some embodiments, the portion of the pillar structure 810 originally within the substrate 300 can be exposed by etching to remove the substrate 300, and surface ST-2 of the stacked structure ST is exposed. Surface ST-2 of the stacked structure ST is relative to surface ST-1.

[0088] Figure 16 This is a schematic diagram illustrating a stage of the manufacturing process. A storage layer 111 is formed. A portion of the channel layer 112 is exposed. In some embodiments, a portion of the storage layer 111C can be removed by etching to expose the second channel portion 1122 and the third channel portion 1123 of the channel layer 112. The portion of the storage layer 111C in the stacked structure ST is retained during the etching process. The portion of the storage layer 111C in the stacked structure ST constitutes the storage layer 111. Removing a portion of the storage layer 111C exposes a portion of the sidewall 112S and end face 112E of the channel layer 112. In the first direction D1, the end face 111E of the storage layer 111 is lower than the end face 112E of the channel layer 112.

[0089] Figure 17 This is a schematic diagram illustrating a stage of the manufacturing process. A dielectric layer 116A is formed on the stacked structure ST and the channel layer 112. In some embodiments, the dielectric layer 116A can be formed by deposition on the surface ST-2 of the stacked structure ST, on the sidewalls 112S of the exposed channel layer 112, and on the end face 112E of the exposed channel layer 112.

[0090] Figure 18 This is a schematic diagram illustrating a stage of the manufacturing process. A dielectric layer 116 is formed. The dielectric layer 116 is formed on the sidewall 112S of the channel layer 112. The width of the dielectric layer 116 in the second direction D2 may be smaller than the width of the storage layer 111 in the second direction D2. The dielectric layer 116 and the storage layer 111 contain different materials. The dielectric layer 116 may contain a dielectric material, which includes, but is not limited to, SiO2. x SiON, SiN, AlO x HfO x ZrO x HfZr x O yOr any combination thereof, where x and y are greater than 0. In some embodiments, dielectric layer 116 may comprise a thin silicon nitride layer with a thickness between 5 Å and 30 Å. For example, the thickness of the thin silicon nitride layer is 20 Å. In some embodiments, dielectric layer 116 may comprise a multilayer structure, such as an ONO (oxide-nitride-oxide) structure formed of thin silicon nitride. In some embodiments, dielectric layer 116 may comprise doped HfZr. x O y Furthermore, the dielectric layer 116 operates not based on the ferroelectric effect. In some embodiments, the dielectric layer 116 may comprise a high dielectric constant dielectric material, which can improve the electrical performance of the semiconductor device. In some embodiments, portions of the dielectric layer 116A on the surface ST-2 of the stacked structure ST and on the end face 112E of the channel layer 112 can be removed by etching, thereby exposing the surface ST-2 of the stacked structure ST and the end face 112E of the channel layer 112. The portion of the dielectric layer 116A on the sidewall 112S of the channel layer 112 is retained during the etching process. The retained portion of the dielectric layer 116A is the dielectric layer 116. Thus, a pillar element 110 comprising a storage layer 111, a channel layer 112, an insulating film 113, an air gap 114, a pad 115, and the dielectric layer 116 can be formed.

[0091] In other embodiments, the dielectric layer 116 can be formed by oxidation. For example, it can be formed by oxidation. Figure 16 The channel layer 112 of the structure shown is subjected to an oxidation treatment so that the exposed portions of the channel layer 112 (e.g., the second channel portion 1122 and the third channel portion 1123) are oxidized and transformed into oxide portions. Then, the portion of the oxide portion on the end face 112E of the channel layer 112 can be removed by an etching process, while the portion of the oxide portion on the sidewall 112S of the channel layer 112 is retained. The retained portion of the oxide portion is the dielectric layer 116. The aforementioned oxidation treatment does not oxidize all the exposed portions of the channel layer 112, but only oxidizes the portion of the channel layer 112 near the outer surface; the portion of the channel layer 112 near the insulating film 113 is not oxidized. Therefore, after the etching process, the insulating film 113 remains covered by the channel layer 112 and is not exposed.

[0092] Figure 19This is a schematic diagram illustrating a stage of the manufacturing process. A conductive film 120A is formed. In some embodiments, a conductive material can be formed on the surface ST-2 of the stacked structure ST, the outer sidewall 116S of the dielectric layer 116, and the end face 112E of the channel layer 112 by a deposition process; a back-etching process can be used to remove portions of the conductive material on the outer sidewall 116S of the dielectric layer 116 and on the end face 112E of the channel layer 112, while retaining the portion of the conductive material on the surface ST-2 of the stacked structure ST. The retained portion of the conductive material on the surface ST-2 of the stacked structure ST constitutes the conductive film 120A.

[0093] Figure 20 This is a schematic diagram illustrating a stage of the manufacturing process. A conductive film 120 and holes 2001 in the conductive film 120 are formed. The holes 2001 may extend along a first direction D1 and penetrate the conductive film 120, ending at the surface ST-2 of the stacked structure ST. The holes 2001 expose a portion of the surface ST-2 of the stacked structure ST. The holes 2001 expose the sidewalls of the conductive film 120. The location of the holes 2001 may correspond to the location of the insulating layer 140. In the first direction D1, the holes 2001 may at least partially overlap the insulating layer 140. In some embodiments, the holes 2001 may be formed by etching to remove a portion of the conductive film 120A. The portion of the conductive film 120A that is retained is the conductive film 120.

[0094] The conductive film 120 and the conductive layer 102 may contain the same or different materials. The conductive film 120 may contain a conductive material, which includes, but is not limited to, doped or undoped polysilicon, metals, silicides, or combinations thereof. The conductive film 120 may contain a multilayer structure, such as a multilayer structure formed by multiple metal layers, a multilayer structure formed by metal and polysilicon, a multilayer structure formed by polysilicon and silicides, etc. In some embodiments, the conductive film 120 may contain TiN / W, TaN / W, TiN, TaN, TaAlN, TiAlN, N-type doped polysilicon, P-type doped polysilicon, polysilicon / silicide, TaN / Cu, TaN / Co, TaN / Ru, or a group of materials selected from the above.

[0095] Figure 21This is a schematic diagram illustrating a stage of the manufacturing process. An insulating material layer 121 is formed on the conductive film 120. The insulating material layer 121 may cover the conductive film 120 and fill the holes 2001. The insulating material layer 121 may not cover the end face 112E of the channel layer 112. The upper surface of the insulating material layer 121 may be coplanar with the end face 112E of the channel layer 112. The insulating material layer 121 may contain an insulating material, which may contain an oxide. In some embodiments, the insulating material layer 121 contains silicon oxide. In some embodiments, the insulating material layer 121 may be formed on the conductive film 120 and in the holes 2001 by deposition and polishing processes, exposing the end face 112E of the channel layer 112.

[0096] Figure 22 This is a schematic diagram illustrating a stage of the manufacturing process. An insulating material layer 123, a conductive structure 122 in the insulating material layer 123, an insulating material layer 125, a through-hole element 124 in the insulating material layer 125, and a conductive element 126 on the insulating material layer 125 are formed. The conductive structure 122 is contactable with the end face 112E of the channel layer 112. The insulating material layers 121, 123, and 125 may contain the same or different materials. The insulating material layers 123 and 125 may contain an insulating material, which may include an oxide. In some embodiments, the insulating material layers 123 and 125 contain silicon oxide. The conductive structure 122 may contain a conductive material, which may include, but is not limited to, doped or undoped polysilicon, a metal, or a combination thereof. In some embodiments, the conductive structure 122 contains N-type doped polysilicon. The through-hole element 124 and the conductive element 126 may contain the same or different materials. The through-hole element 124 and the conductive element 126 may comprise a conductive material, which includes, but is not limited to, doped or undoped polysilicon, metals, or combinations thereof. In some embodiments, the through-hole element 124 and the conductive element 126 comprise TiN, TaN, Ti, Ta, Cu, Al, Ag, W, Ir, Ru, Pt, or any combination thereof. In some embodiments, the through-hole element 124 comprises N-type doped polysilicon.

[0097] In some embodiments, an insulating material layer 123 can be formed on the insulating material layer 121 and the conductive film 120 by deposition, an opening 2201 can be formed in the insulating material layer 123 by etching, and then a conductive structure 122 can be formed in the opening 2201 by deposition. In some embodiments, an insulating material layer 125 can be formed on the insulating material layer 123 and the conductive structure 122 by deposition, a groove 2202 can be formed in the insulating material layer 125 by etching, and then a through-hole element 124 can be formed in the groove 2202 by deposition. In some embodiments, a conductive element 126 can be formed on the insulating material layer 125 and the through-hole element 124 by patterning.

[0098] In some embodiments, by implementing exemplary illustrations Figures 3 to 22 The method can yield results such as Figure 1 The semiconductor device 10 shown.

[0099] Figures 23 to 36 This illustrates a method of manufacturing a semiconductor device according to other embodiments. In some embodiments, reference may be made to... Figures 3 to 8 After the manufacturing steps described above, refer to Figures 23 to 36 The manufacturing steps described above.

[0100] Figure 23 This is a schematic diagram illustrating a stage of the manufacturing process. An insulating material layer 161 is formed on an insulating stack structure ST1. A hole 2301 is formed in the insulating stack structure ST1. The hole 2301 may extend along a first direction D1 and penetrate the insulating stack structure ST1 and the insulating material layer 161, and stop at the substrate 300. The bottom of the hole 2301 may be lower than the upper surface 300U of the substrate 300 in the first direction D1. The hole 2301 may be located between a plurality of pillar structures 810. The hole 2301 exposes the sidewalls of the insulating material layer 161, the sidewalls of the insulating stack structure ST1, and the substrate 300. In some embodiments, the insulating material layer 161 may be formed on the upper surface ST1U of the insulating stack structure ST1 by a deposition process; the hole 2301 may be formed by an etching process to remove a portion of the insulating material layer 161, a portion of the insulating layer 101, a portion of the insulating layer 302, and a portion of the substrate 300.

[0101] Figure 24This is a schematic diagram illustrating a stage of the manufacturing process. Multiple spaces 2401R are formed. The multiple spaces 2401R are situated between multiple insulating layers 101. The spaces 2401R can connect to holes 2301. The spaces 2401R expose the upper and lower surfaces of the insulating layers 101, and a portion of the outer sidewall of the storage layer 111C of the pillar structure 810. In some embodiments, multiple spaces 2401R can be formed by selectively etching away multiple insulating layers 302 between the multiple insulating layers 101, while retaining the multiple insulating layers 101, the insulating material layer 161, the pillar structure 810, and the substrate 300. The selective etching can be performed via the holes 2301. In this stage, the pillar structure 810 can serve as a structural support.

[0102] Figure 25 This is a schematic diagram illustrating a stage of the manufacturing process. A stacked structure ST comprising multiple conductive layers 102 and multiple insulating layers 101 is formed, along with an isolation layer 240A within the stacked structure ST. The isolation layer 240A extends along a first direction D1 and penetrates the stacked structure ST, the insulating material layer 161, and the substrate 300. The isolation layer 240A may be located between multiple pillar structures 810. The isolation layer 240A may comprise an insulating material comprising an oxide. In some embodiments, the isolation layer 240A may comprise silicon oxide. In some embodiments, the conductive layers 102 may be deposited to fill spaces 2401R to form the stacked structure ST; then, the isolation layer 240A may be deposited to fill holes 2301.

[0103] Figure 26 This is a schematic diagram illustrating a stage of the manufacturing process. A conductive strip 241 and an isolation layer 240 are formed. The conductive strip 241 and the isolation layer 240 are located within a hole 2301. The conductive strip 241 may contain a conductive material, including, but not limited to, doped or undoped polysilicon, metals, or combinations thereof. In some embodiments, the conductive strip 241 contains TiN, TaN, Ti, Ta, Cu, Al, Ag, W, Ir, Ru, Pt, or any combination thereof. In some embodiments, a portion of the isolation layer 240A can be removed by etching to form a channel, while a portion of the isolation layer 240A is retained; the retained portion of the isolation layer 240A constitutes the isolation layer 240. Subsequently, a deposition process can be used to form the conductive strip 241 within the channel.

[0104] Figure 27This is a schematic diagram illustrating a stage of the manufacturing process. An interconnect structure 260 is formed on surface ST-1 of the stacked structure ST. The interconnect structure 260 includes multiple insulating material layers 161, multiple conductive interconnects 165 within the multiple insulating material layers 161, and conductive interconnects 265 within the multiple insulating material layers 161. Two conductive interconnects 165 may correspond to different pillar structures 810. The two conductive interconnects 165 are electrically connected to the different pillar structures 810. The conductive interconnect 265 corresponds to a conductive strip 241. The conductive interconnect 265 is electrically connected to the conductive strip 241. The conductive interconnect 265 may include through-hole elements 2651 and conductive elements 2652. Through-hole elements 2651 and conductive elements 2652 may contain the same or different materials. Through-hole elements 2651 and conductive elements 2652 may contain conductive materials, including but not limited to metals. For example, the through-hole element 2651 and the conductive element 2652 may comprise TiN, TaN, Ti, Ta, Cu, Al, Ag, W, Ir, Ru, Pt, or any combination thereof. In some embodiments, the through-hole element 2651 and the conductive element 2652 comprise Cu. In some embodiments, an insulating material layer 161 may be formed by deposition. A plurality of grooves may be formed in the insulating material layer 161 by a patterning process. The locations of the grooves are where via elements 1651 and / or conductive elements 1652 and / or via elements 2651 and / or conductive elements 2652 will be formed. Then, the materials of via elements 1651 and / or conductive elements 1652 and / or via elements 2651 and / or conductive elements 2652 are filled into the grooves to form via elements 1651 and / or conductive elements 1652 and / or via elements 2651 and / or conductive elements 2652 in the insulating material layer 161. The above steps may be repeated until the configuration of conductive interconnects 165 and 265 meets the requirements. In some embodiments, the interconnect structure 260 may be understood as a memory array interconnect structure. The conductive elements 1652 and 2652 located in the insulating material layer 161 furthest from the column structure 810 in the first direction D1 can be understood as bonding layers, which can be used to bond other structures.

[0105] Figure 28This is a schematic diagram illustrating a stage of the manufacturing process. A semiconductor structure 20P is provided. The semiconductor structure 20P is bonded to an interconnect structure 260. The semiconductor structure 20P includes a substrate 100, a plurality of semiconductor elements 195 in the substrate 100, semiconductor elements 295 in the substrate 100, and an interconnect structure 280 on the substrate 100, the semiconductor elements 195, and the semiconductor elements 295. The interconnect structure 280 may include a plurality of insulating material layers 181, a plurality of conductive interconnects 185 in the plurality of insulating material layers 181, and conductive interconnects 285 in the plurality of insulating material layers 181. The plurality of conductive interconnects 185 may electrically connect to different semiconductor elements 195 respectively. The conductive interconnects 285 may electrically connect to semiconductor elements 295. The conductive interconnects 285 may include through-hole elements 2851 and conductive elements 2852. The through-hole elements 2851 and conductive elements 2852 may contain the same or different materials. The via element 2851 and conductive element 2852 may contain conductive materials, including but not limited to metals. For example, the via element 2851 and conductive element 2852 may contain TiN, TaN, Ti, Ta, Cu, Al, Ag, W, Ir, Ru, Pt, or any combination thereof. In some embodiments, the via element 2851 and conductive element 2852 contain Cu. The conductive elements 1852 and 2852 located in the insulating material layer 181 furthest from the substrate 100 in the first direction D1 can be understood as bonding layers, which can be used to bond other structures (e.g., to bond interconnect structure 260). The manufacturing method of interconnect structure 280 may be similar to the manufacturing method of interconnect structure 260 or interconnect structure 180. In some embodiments, the bonding layers (conductive elements 1852 and 2852) of interconnect structure 280 of semiconductor structure 20P can be bonded to the bonding layers (conductive elements 1652 and 2652) of interconnect structure 260 by solid-state bonding technology, such as diffusion bonding technology. The junction of semiconductor structure 20P and interconnect structure 260 can be a copper-copper hybrid bonding.

[0106] After the semiconductor structure 20P is bonded to the interconnect structure 260, the multiple conductive interconnects 185 of the semiconductor structure 20P can be electrically connected to different conductive interconnects 165 in the interconnect structure 260, and the conductive interconnects 285 of the semiconductor structure 20P can be electrically connected to the conductive interconnects 265 in the interconnect structure 260. Thus, the semiconductor element 195 can be electrically connected to the pillar structure 810 through the corresponding conductive interconnects 185 and the corresponding conductive interconnects 165, and the semiconductor element 295 can be electrically connected to the conductive strip 241 through the conductive interconnects 285 and the conductive interconnects 265.

[0107] In some embodiments, the interconnect structure 280 may be a middle-end-of-line (MEOL) interconnect structure or a back-end-of-line (BEOL) interconnect structure.

[0108] Figure 29 This is a structural diagram illustrating one stage of the manufacturing process. (Rotation) Figure 28 The structure is shown. After rotation, the substrate 300 is positioned above the substrate 100. In some embodiments, the rotation step may be omitted from the manufacturing process.

[0109] Figure 30 This is a schematic diagram illustrating a stage of the manufacturing process. A portion of the pillar structure 810, a portion of the conductive strip 241, and a portion of the insulating layer 240 are exposed. In some embodiments, the substrate 300 may be removed by etching, exposing the portions of the pillar structure 810 originally within the substrate 300, as well as the portions of the conductive strip 241 and the insulating layer 240 originally within the substrate 300, and exposing surface ST-2 of the stacked structure ST. Surface ST-2 of the stacked structure ST is relative to surface ST-1.

[0110] Figure 31 This is a schematic diagram illustrating a stage of the manufacturing process. A storage layer 111 is formed. A portion of the channel layer 112 is exposed. In some embodiments, a portion of the storage layer 111C can be removed by etching to expose the second channel portion 1122 and the third channel portion 1123 of the channel layer 112, while retaining the portion of the storage layer 111C in the stacked structure ST. The portion of the storage layer 111C in the stacked structure ST constitutes the storage layer 111. Removing a portion of the storage layer 111C exposes a portion of the sidewall 112S and the end face 112E of the channel layer 112.

[0111] Figure 32 This is a schematic diagram illustrating a stage of the manufacturing process. A dielectric layer 116A is formed on the stacked structure ST and the channel layer 112. In some embodiments, the dielectric layer 116A can be formed by deposition on the surface ST-2 of the stacked structure ST, on the exposed sidewalls 112S of the channel layer 112, on the exposed end faces 112E of the channel layer 112, on the exposed conductive strips 241 and the isolation layer 240.

[0112] Figure 33This is a schematic diagram illustrating a stage of the manufacturing process. A dielectric layer 116 is formed. The dielectric layer 116 is formed on the sidewall 112S of the channel layer 112. The width of the dielectric layer 116 in the second direction D2 may be smaller than the width of the storage layer 111 in the second direction D2. In some embodiments, portions of the dielectric layer 116A on the surface ST-2 of the stacked structure ST, portions of the dielectric layer 116A on the end face 112E of the channel layer 112, and portions of the dielectric layer 116A on the conductive strip 241 and the isolation layer 240 can be removed by etching, thereby exposing the surface ST-2 of the stacked structure ST, the end face 112E of the channel layer 112, the conductive strip 241, and the isolation layer 240, while retaining the portion of the dielectric layer 116A on the sidewall 112S of the channel layer 112. The retained portion of the dielectric layer 116A is the dielectric layer 116. Therefore, a pillar element 110 comprising a storage layer 111, a channel layer 112, an insulating film 113, an air gap 114, a pad 115, and a dielectric layer 116 can be formed. In other embodiments, the dielectric layer 116 can be formed by an oxidation process. The oxidation process is described in the preceding reference. Figure 16 Related explanations.

[0113] Figure 34 This is a schematic diagram illustrating a stage in the manufacturing process. A conductive film 120 is formed. In some embodiments, the conductive film 120 can be formed on the surface ST-2 of the stacked structure ST by deposition and etching processes.

[0114] Figure 35 This is a schematic diagram illustrating a stage of the manufacturing process. An insulating material layer 121 is formed on the conductive film 120. The insulating material layer 121 may cover the conductive film 120. The insulating material layer 121 may not cover the end face 112E of the channel layer 112, the end face 241E of the conductive strip 241, and the end face 240E of the isolation layer 240. The upper surface 121E of the insulating material layer 121, the end face 112E of the channel layer 112, the end face 241E of the conductive strip 241, and the end face 240E of the isolation layer 240 may be coplanar. In some embodiments, the insulating material layer 121 may be formed on the conductive film 120 by deposition and polishing processes, exposing the end face 112E of the channel layer 112, the end face 241E of the conductive strip 241, and the end face 240E of the isolation layer 240.

[0115] Figure 36This is a schematic diagram illustrating a stage of the manufacturing process. An insulating material layer 123, a conductive structure 122 within the insulating material layer 123, an insulating material layer 125, a through-hole element 124 within the insulating material layer 125, and a conductive element 126 on the insulating material layer 125 are formed. The conductive structure 122 is contactable with the end face 112E of the channel layer 112, the end face 241E of the conductive strip 241, and the end face 240E of the insulating layer 240. In some embodiments, the insulating material layer 123 can be formed on the insulating material layer 121 and the conductive film 120 by deposition, an opening 3601 can be formed in the insulating material layer 123 by etching, and then the conductive structure 122 can be formed in the opening 3601 by deposition. In some embodiments, an insulating material layer 125 may be formed on the insulating material layer 123 and the conductive structure 122 by deposition, a groove 3602 may be formed in the insulating material layer 125 by etching, and a through-hole element 124 may be formed in the groove 3602 by deposition. In some embodiments, a conductive element 126 may be formed on the insulating material layer 125 and the through-hole element 124 by patterning.

[0116] In some embodiments, by implementing exemplary illustrations Figures 23 to 36 The method can yield results such as Figure 2 The semiconductor device 20 shown.

[0117] According to several embodiments, the semiconductor device and its manufacturing method of the present invention use a dielectric layer (e.g., dielectric layer 116) as the gate dielectric layer of a ground selection switch, wherein the dielectric layer and the memory layer comprise different materials. With this configuration, the voltage Vt of the ground selection line differs from the voltage of the memory cell, thereby reducing or avoiding operational interference (e.g., read interference, write interference, erase interference, etc.) and improving the electrical performance of the semiconductor device. In a comparative example, the gate dielectric layer and the memory layer of the ground selection switch of the semiconductor device comprise the same material. This comparative example is easily interfered with during write and / or erase operations because the voltage Vt of the ground selection line will be changed to be the same as the voltage of the memory cell.

[0118] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor device comprising: One substrate; A stacked structure on the substrate; An interconnect structure is provided between the substrate and the stacked structure; and A pillar element, extending through the stacked structure, comprising: One channel layer; A storage layer surrounding the channel layer; and A dielectric layer surrounds the channel layer, and the dielectric layer and the storage layer contain different materials.

2. The semiconductor device of claim 1, wherein the pillar element further comprises an insulating film and a pad, the channel layer surrounds the insulating film, the pad is disposed between the insulating film and the interconnect structure, and the storage layer is connected between the dielectric layer and the pad.

3. The semiconductor device of claim 2, wherein the channel layer and the insulating film extend beyond the stacked structure, the storage layer and the pad are in the stacked structure, and the dielectric layer is on the stacked structure.

4. The semiconductor device of claim 1, further comprising a conductive structure on the stacked structure, the channel layer being electrically connected between the conductive structure and the interconnect structure.

5. The semiconductor device of claim 4, wherein the pillar element further comprises an insulating film. The channel layer includes a first channel portion, a second channel portion and a third channel portion. The second channel portion is connected between the first channel portion and the third channel portion. The first channel portion is located between the insulating film and the storage layer. The second channel portion is located between the insulating film and the dielectric layer. The third channel portion covers one end of the insulating film and is located between the insulating film and the conductive structure.

6. The semiconductor device of claim 4, wherein the semiconductor device includes a plurality of the pillar elements, and the conductive structure is electrically connected to the pillar elements.

7. The semiconductor device of claim 4, further comprising a conductive strip that extends through the stacked structure and is electrically connected between the conductive structure and the interconnect structure.

8. The semiconductor device of claim 1, further comprising a conductive film on the stacked structure, the conductive film surrounding the dielectric layer.

9. The semiconductor device of claim 8, wherein the semiconductor device comprises a plurality of memory cells defined in the memory layer. The conductive film serves as a ground select line (GSL) for these memory cells.

10. The semiconductor device of claim 9, wherein the stacked structure includes a plurality of conductive layers surrounding the memory layer, the conductive layers serving as a plurality of word lines for the plurality of memory cells, and the conductive film and the conductive layers comprising different materials.

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