Semiconductor structure preparation method and semiconductor structure

Abstract

The present disclosure relates to a semiconductor structure preparation method and a semiconductor structure, and relates to the technical field of semiconductors, and comprises the following steps: providing a substrate, the top surface of the substrate comprising a gate dielectric layer; forming an interlayer dielectric layer on the top surface of the gate dielectric layer, the interlayer dielectric layer comprising a groove exposing part of the top surface of the gate dielectric layer, the bottom surface of the groove comprising a bottom barrier layer, and the sidewall of the groove and the top surface of the bottom barrier layer comprising a diffusion barrier layer; forming an initial titanium film covering the diffusion barrier layer, etching and removing the initial titanium film on the bottom surface of the groove based on plasma generated by an inert gas; forming a target density of hydroxyl and amino groups on the surface of the remaining target titanium film; treating the surface of the remaining target titanium film with a phosphorus-containing solution to form a molecular protective film comprising titanium, phosphorus and oxygen; in the groove, after forming a work function layer covering the bottom barrier layer, forming an adhesion layer covering the work function layer and the molecular protective film; and forming a gate conductive layer filling the groove. At least the situation of missing gate structure filling can be effectively avoided.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Technology

[0002] The gate is the core structure of a field-effect transistor (FET), and its fabrication process directly determines the device's performance and reliability.

[0003] In related technologies, threshold voltage regulation of NMOS and PMOS devices is achieved through a metal gate using a work function metal stack. After the gate is fabricated, other devices are typically fabricated after the metal gate is polished.

[0004] However, after the gate metal layers are filled normally and other devices are fabricated, a lack of gate structure filler occurs, which seriously reduces the yield and performance of the fabricated semiconductor devices. Summary of the Invention

[0005] According to various embodiments of this disclosure, a method for fabricating a semiconductor structure and a semiconductor structure are provided, which can at least effectively avoid the occurrence of missing gate structure filler, thereby improving the yield, performance and reliability of the semiconductor products.

[0006] According to some embodiments, a first aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0007] A substrate is provided, the top surface of which includes a gate dielectric layer;

[0008] An interlayer dielectric layer is formed on the top surface of the gate dielectric layer. The interlayer dielectric layer includes a groove that exposes a portion of the top surface of the gate dielectric layer. The bottom surface of the groove includes a bottom barrier layer. The sidewalls of the groove and the top surface of the bottom barrier layer include a diffusion barrier layer.

[0009] An initial titanium film covering the diffusion barrier layer is formed, and the initial titanium film located at the bottom of the groove is removed by plasma etching based on inert gas generation;

[0010] The remaining target titanium film is treated with a target gas containing oxygen, nitrogen, and hydrogen to form hydroxyl and amino groups of the target density on the surface of the remaining target titanium film; the hydroxyl and amino groups are used to provide chemical anchoring sites and reactive sites.

[0011] The surface of the remaining target titanium film is treated with a phosphorus-containing solution to form a molecular protective film containing titanium, phosphorus, and oxygen.

[0012] After forming a work function layer covering the bottom barrier layer within the groove, an adhesion layer covering the work function layer and the molecular protective film is formed; a gate conductive layer filling the groove is then formed.

[0013] In the semiconductor structure fabrication method described above, a groove is formed in the interlayer dielectric layer on the top surface of the gate dielectric layer, a bottom barrier layer is provided on the bottom surface of the groove, and a diffusion barrier layer is provided on the sidewall of the groove and the top surface of the bottom barrier layer to prevent the filler from diffusing into the substrate or the interlayer dielectric layer during the subsequent filling of the gate structure into the groove. After forming the initial titanium film covering the diffusion barrier layer, plasma etching based on inert gas is used to remove the initial titanium film located at the bottom of the groove. Then, the remaining target titanium film is treated with a target gas containing oxygen, nitrogen, and hydrogen, forming hydroxyl and amino groups of a target density on the surface of the remaining target titanium film. The hydroxyl and amino groups provide chemical anchoring sites and reactive sites. After treating the surface of the remaining target titanium film with a phosphorus-containing solution, a molecular protective film containing titanium, phosphorus, and oxygen is formed. This molecular protective film inhibits the adhesion of the work function layer to the groove sidewalls during the subsequent formation of the work function layer covering the bottom barrier layer at the bottom of the groove, preventing the formation of the work function layer on the groove sidewalls and avoiding a reduction in the groove opening size during the formation of the work function layer. This facilitates the formation of a gate conductive layer filling the groove after the adhesion layer covering the work function layer and the molecular protective film is formed. Since the sidewalls of the gate conductive layer do not contain the work function layer, the subsequent wet etching solution avoids the loss of gate structure filler due to etching of the work function layer in the sidewalls, improving the yield, performance, and reliability of the fabricated semiconductor products.

[0014] According to some embodiments, removing the initial titanium film located at the bottom of the groove includes: bombarding the initial titanium film located at the bottom of the groove with accelerated post-plasma generated by inert gas to remove the initial titanium film located at the bottom of the groove, and retaining the initial titanium film on the sidewall of the groove to form an initial protective film.

[0015] According to some embodiments, the target gas includes oxygen, nitrogen, and hydrogen; the surface oxidation treatment produces an initial protective film, generating hydroxyl-rich titanium oxide on the titanium surface; the surface amination treatment produces amino groups on the target titanium film surface.

[0016] According to some embodiments, surface amination treatment of titanium oxide includes: treating titanium oxide with a nitrogen and hydrogen mixed plasma for a preset time under a power of 50W-150W to generate amino groups on the surface of the target titanium film.

[0017] According to some embodiments, forming a molecular protective film includes: reacting a target phosphate with hydroxyl and amino groups to form a molecular protective film for enhancing corrosion resistance.

[0018] According to some embodiments, the target phosphoric acid includes octadecylphosphonic acid, ethanol, and sodium hydroxide.

[0019] According to some embodiments, after forming a gate conductive layer that fills the groove, the method further includes: planarizing the top surface of the gate conductive layer until the top surface of the remaining gate conductive layer is flush with the top surface of the interlayer dielectric layer; forming a stack covering the gate conductive layer and the interlayer dielectric layer; and patterning the stack to form a device with a target resistance value.

[0020] According to some embodiments, the stack includes an oxide layer, a conductive layer, and a nitride layer sequentially stacked along a direction away from the substrate; the patterned stack includes: forming a patterned mask layer on the top surface of the nitride layer, the patterned mask layer including a pattern for defining a target resistance device; based on the patterned mask layer, using the oxide layer as an etch stop layer, etching the nitride layer and the conductive layer to expose a portion of the oxide layer.

[0021] According to some embodiments, the semiconductor structure fabrication method includes at least one of the following features: the thickness of the titanium film is 1nm-2nm; the thickness of the molecular protective film is 1nm-2nm; and the inert gas includes nitrogen, argon, helium, or a combination thereof.

[0022] According to some embodiments, a second aspect of this disclosure provides a semiconductor structure prepared using the semiconductor structure preparation method described in any of the foregoing embodiments.

[0023] The semiconductor structure fabrication method and semiconductor structure in the above embodiments have at least the following unexpected technical effects:

[0024] A groove is formed within the interlayer dielectric layer on the top surface of the gate dielectric layer. A bottom barrier layer is formed on the bottom surface of the groove, and a diffusion barrier layer is formed on the sidewalls of the groove and the top surface of the bottom barrier layer to prevent the filler from diffusing into the substrate or interlayer dielectric layer during the subsequent filling of the gate structure into the groove. After forming an initial titanium film covering the diffusion barrier layer, the initial titanium film located at the bottom surface of the groove is etched and removed by plasma generated based on an inert gas. Then, the remaining target titanium film is treated with a target gas containing oxygen, nitrogen, and hydrogen to form hydroxyl and amino groups of a target density on the surface of the remaining target titanium film. The hydroxyl and amino groups are used to provide chemical anchoring sites and reactive sites. Thus, after treating the surface of the remaining target titanium film with a phosphorus-containing solution, a molecular protective film containing titanium, phosphorus, and oxygen is formed. During the subsequent formation of the work function layer covering the bottom barrier layer on the bottom surface of the groove, this molecular protective film is used to inhibit the adhesion of the work function layer to the sidewalls of the groove, avoid the formation of the work function layer on the sidewalls of the groove, and avoid reducing the groove opening size during the formation of the work function layer. This facilitates the formation of a gate conductive layer that fills the groove after the formation of the adhesion layer covering the work function layer and the molecular protective film. Since the sidewalls of the gate conductive layer do not contain a work function layer, the subsequent wet etching solution avoids the loss of gate structure filler due to etching of the work function layer in the sidewalls, thereby improving the yield, performance and reliability of the semiconductor products. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic cross-sectional view of a grid structure including sidewall gaps and bottom gaps provided in one embodiment;

[0027] Figure 2 This is a schematic flowchart of a semiconductor structure fabrication method in one embodiment;

[0028] Figure 3 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a diffusion barrier layer in step S220 of the semiconductor structure fabrication method in one embodiment.

[0029] Figure 4 This is a schematic cross-sectional view of the semiconductor structure obtained after forming an initial titanium film in step S220 of the semiconductor structure fabrication method in one embodiment.

[0030] Figure 5 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the target titanium film in step S230 of the semiconductor structure fabrication method in one embodiment.

[0031] Figure 6 This is a schematic cross-sectional view of the semiconductor structure obtained after the formation of hydroxyl and amino groups in step S240 of the semiconductor structure preparation method in one embodiment.

[0032] Figure 7 This is a schematic cross-sectional view of the semiconductor structure obtained after forming a molecular protective film in step S250 of the semiconductor structure preparation method in one embodiment.

[0033] Figure 8 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the functional layer in step S260 of the semiconductor structure fabrication method in one embodiment.

[0034] Figure 9 This is a schematic cross-sectional view of the semiconductor structure obtained after forming the gate conductive layer in step S260 of the semiconductor structure fabrication method in one embodiment.

[0035] Explanation of reference numerals in the attached figures:

[0036] 10. Substrate; 11. Groove; 12. Gate dielectric layer; 13. Bottom barrier layer; 100. Interlayer dielectric layer; 14. Diffusion barrier layer; 151. Initial titanium film; 15. Target titanium film; 16. Hydroxyl and amino groups; 17. Molecular protective film; 19. Adhesion layer; 110. Gate conductive layer; 20. Plasma; 30. Sidewall gap; 40. Bottom gap; 400. Stacked layers; 401. Oxide layer; 402. Conductive layer; 403. Nitride layer. Detailed Implementation

[0037] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0039] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0040] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0041] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0042] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for the anticipation of variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0043] Please see Figure 1The applicant discovered that some gate structures have sidewall gaps (30 mm) and bottom gaps (40 mm). The resistivity of these gaps directly affects the resistance of the metal interconnects, thus impacting RC delay. The capacitive characteristics of these gaps amplify electromagnetic interference (EMI). The charging and discharging of the gate capacitance is controlled by the gate resistance (RG). An excessively small RG value leads to an excessively high rate of current rise (di / dt), generating voltage spikes that may damage the device. The applicant further discovered that the sidewall gaps (30 mm) and bottom gaps (40 mm) primarily originate from missing TiAl layers. The TiAl layer is easily etched away during wet etching. However, after gate filling, a wet etching process is required to form the patterned resistor, inevitably resulting in missing TiAl layers and thus missing gate filler.

[0044] For the reasons mentioned above, this disclosure aims to provide a method for preparing a semiconductor structure and a semiconductor structure that can at least effectively avoid the occurrence of missing gate structure filler, thereby improving the yield, performance and reliability of the prepared semiconductor products.

[0045] Please see Figure 2 This disclosure provides a method for fabricating a semiconductor structure, which includes the following steps:

[0046] Step S210: Provide a substrate, the top surface of which includes a gate dielectric layer;

[0047] Step S220: An interlayer dielectric layer is formed on the top surface of the gate dielectric layer. The interlayer dielectric layer includes a groove that exposes part of the top surface of the gate dielectric layer. The bottom surface of the groove includes a bottom barrier layer. The sidewalls of the groove and the top surface of the bottom barrier layer include a diffusion barrier layer.

[0048] Step S230: Form an initial titanium film covering the diffusion barrier layer, and etch and remove the initial titanium film located at the bottom of the groove based on plasma generated by inert gas;

[0049] Step S240: Treat the remaining target titanium film with a target gas containing oxygen, nitrogen, and hydrogen to form hydroxyl and amino groups of the target density on the surface of the remaining target titanium film; the hydroxyl and amino groups are used to provide chemical anchoring sites and reactive sites.

[0050] Step S250: Treat the surface of the remaining target titanium film with a phosphorus-containing solution to form a molecular protective film containing titanium, phosphorus, and oxygen;

[0051] Step S260: After forming a work function layer covering the bottom barrier layer in the groove, an adhesion layer covering the work function layer and the molecular protective film is formed; a gate conductive layer filling the groove is formed.

[0052] As an example, please continue reading Figure 2A groove is formed within the interlayer dielectric layer on the top surface of the gate dielectric layer. A bottom barrier layer is formed on the bottom surface of the groove, and a diffusion barrier layer is formed on the sidewalls of the groove and the top surface of the bottom barrier layer to prevent the filler from diffusing into the substrate or interlayer dielectric layer during the subsequent filling of the gate structure into the groove. After forming an initial titanium film covering the diffusion barrier layer, the initial titanium film located at the bottom surface of the groove is etched and removed by plasma generated based on an inert gas. Then, the remaining target titanium film is treated with a target gas containing oxygen, nitrogen, and hydrogen to form hydroxyl and amino groups of a target density on the surface of the remaining target titanium film. The hydroxyl and amino groups are used to provide chemical anchoring sites and reactive sites. Thus, after treating the surface of the remaining target titanium film with a phosphorus-containing solution, a molecular protective film containing titanium, phosphorus, and oxygen is formed. During the subsequent formation of the work function layer covering the bottom barrier layer on the bottom surface of the groove, this molecular protective film is used to inhibit the adhesion of the work function layer on the sidewalls of the groove, avoid the formation of the work function layer on the sidewalls of the groove, and avoid reducing the groove opening size during the formation of the work function layer. This facilitates the formation of a gate conductive layer that fills the groove after the formation of the adhesion layer covering the work function layer and the molecular protective film. Since the sidewalls of the gate conductive layer do not contain a work function layer, the subsequent wet etching solution avoids the loss of gate structure filler due to etching of the work function layer in the sidewalls, thereby improving the yield, performance and reliability of the semiconductor products.

[0053] Please see Figure 3 In some embodiments, in step S210, a first type of doped well region (not shown) may be formed within the substrate 10. The substrate 10 may be constructed of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 may be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 10 should not limit the scope of protection of this disclosure. P-type ions can be implanted into the substrate 10 using an ion implantation process to form a first type of doped well region (not shown). The P-type ions can be any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride ions, and indium (In) ions.

[0054] As an example, please continue reading Figure 3In step S210, any one or more of the following processes can be used to form a gate dielectric layer 12 on the top surface of the substrate 10: In-situ Steam Generation (ISSG), atomic layer deposition, plasma vapor deposition, and rapid thermal oxidation (RTO).

[0055] As an example, please continue reading Figure 3 A bottom barrier layer 13 is formed on the top surface of the gate dielectric layer 12. The bottom barrier layer 13 can be formed using a material with a high k dielectric constant (e.g., a dielectric constant greater than or equal to 3.9). For example, the material of the bottom barrier layer 13 can include, but is not limited to, alumina, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanium oxide, or combinations thereof. The interlayer dielectric layer 100 can include silicon oxide. The gate dielectric layer 12 can include silicon oxide.

[0056] As an example, please continue reading Figure 3 In step S220, an interlayer dielectric layer 100 is deposited on the top surface of the substrate 10, the interlayer dielectric layer 100 at least covering the exposed top surface of the substrate 10 and the top surface of the bottom barrier layer 13. A groove 11 can be formed in the interlayer dielectric layer 100 using a dry etching process. The groove 11 exposes the top surface of the bottom barrier layer 13, avoiding etching damage to the gate dielectric layer 12 during the formation of the groove 11.

[0057] As an example, please continue reading Figure 3 In step S220, a diffusion barrier layer 14 can be formed on the inner surface of the groove 11, the top surface of the bottom barrier layer 13, and the top surface of the interlayer dielectric layer 100 using a deposition process. The diffusion barrier layer 14 may include, but is not limited to, tantalum nitride. The diffusion barrier layer 14 can prevent ions from diffusing into the interlayer dielectric layer 100 during subsequent deposition processes.

[0058] Please see Figures 4-5 In some embodiments, in step S230, a plasma deposition process can be used to form an initial titanium film 151 covering the diffusion barrier layer 14. The thickness of the initial titanium film 151 can be 1 nm to 2 nm, for example, the thickness of the initial titanium film 151 can be 1 nm, 1.5 nm, or 2 nm, etc. The thickness of the initial titanium film 151 cannot be too thin to avoid the subsequent failure to fully cover the molecular protective film on the sidewalls of the groove 11; the thickness of the initial titanium film 151 cannot be too thick to avoid reducing the size of the groove opening used to fill the gate structure.

[0059] Please see Figures 4-5In some embodiments, in step S230, plasma 20 generated based on inert gas etches and removes the initial titanium film 151 located at the bottom surface of the groove 11, and the initial titanium film 151 retained on the sidewall of the groove 11 is used to form the target titanium film 15. The target titanium film 15 is used to subsequently form a molecular protective film on its surface, which can inhibit TiAl film formation on its surface.

[0060] For example, please continue reading Figure 5 The inert gas includes nitrogen, argon, helium, or combinations thereof. For example, the initial titanium film 151 on the bottom surface of the groove 11 can be bombarded with accelerated argon (Ar) ions, allowing titanium atoms to be partially transferred to the sidewalls of the groove 11 by the argon (Ar) ions, thereby removing the initial titanium film 151 located on the bottom surface of the groove 11. With a predetermined bias power, the dry etching time can be controlled to completely remove the initial titanium film 151 on the bottom surface of the groove 11 while avoiding damage to the surface of the diffusion barrier layer 14.

[0061] Please see Figure 6 In some embodiments, in step S240, the remaining target titanium film 15 is treated with a target gas containing oxygen, nitrogen, and hydrogen to form hydroxyl and amino groups 16 of a target density on the surface of the remaining target titanium film 15; the hydroxyl and amino groups 16 are used to provide chemical anchoring sites and reactive sites.

[0062] For example, please continue reading Figure 6 The target gas can be set to include oxygen, nitrogen, and hydrogen. The content of oxygen, nitrogen, and hydrogen can be set according to actual needs, and there are no specific limitations here.

[0063] For example, please continue reading Figure 6 The target gases include oxygen, nitrogen, and hydrogen. Surface oxidation treatment creates an initial protective film, generating hydroxyl-rich titanium oxide on the titanium surface. Surface amination treatment of titanium oxide generates amino groups on the target titanium film surface. The plasma of oxygen and hydrogen can generate water molecules, and oxygen can oxidize the target titanium film to form titanium oxide. The adsorption and dissociation of water molecules on the titanium oxide surface generates hydroxyl groups. The plasma of nitrogen and hydrogen can generate ammonia. Ammonia plasma treatment of the titanium or titanium oxide surface allows the active nitrogen and hydrogen species generated by the plasma to react directly with the surface, generating amino groups.

[0064] For example, please continue reading Figure 6 Surface amination treatment of titanium dioxide includes: treating titanium dioxide with a nitrogen-hydrogen mixed plasma for a preset time at a power of 50W-150W to generate amino groups on the target titanium film surface. For example, the power for surface amination treatment of titanium dioxide can be 50W, 70W, 90W, 100W, 120W, or 150W. The adsorption and dissociation of water molecules on the titanium dioxide surface will generate hydroxyl groups.

[0065] For example, please continue reading Figure 6 The target gas can be set to include oxygen, nitrogen, and ammonia. Oxygen can oxidize the target titanium film 15 to generate titanium oxide. When ammonia plasma is used to treat the titanium or titanium oxide surface, the active nitrogen and hydrogen species generated by the plasma can directly react with the surface to generate amino groups; the adsorption and dissociation of water molecules on the titanium oxide surface will generate hydroxyl groups.

[0066] Please see Figure 7 In some embodiments, forming a molecular protective film 17 includes: reacting a target phosphoric acid with hydroxyl and amino groups 16 to form a molecular protective film 17 comprising titanium, phosphorus, and oxygen, thereby forming a molecular protective film 17 for enhancing corrosion resistance.

[0067] For example, the target phosphoric acid includes octadecylphosphonic acid, ethanol, and sodium hydroxide.

[0068] For example, please continue reading Figure 7 In step S250, the surface of the remaining target titanium film 15 is treated with a phosphoric acid solution. The phosphoric acid solution reacts with the hydroxyl and amino groups 16 on the surface of the target titanium film 15 to generate a molecular protective film 17 containing titanium, phosphorus, and oxygen. Phosphate has a strong coordination ability, and multiple hydroxyl groups of phosphoric acid can react simultaneously with multiple Ti-OH sites on the titanium surface to form a molecular protective film 17 containing titanium, phosphorus, and oxygen. This layer is firmly attached to the titanium surface through covalent bonds (Ti-OP), coordination bonds, ionic bonds (adsorbed phosphate groups), and hydrogen bonds, resulting in cross-linking and densification of the surface layer. The thickness of the molecular protective film 17 is 1 nm-2 nm. For example, the thickness of the molecular protective film 17 can be 1 nm, 1.5 nm, or 2 nm, etc.

[0069] Please see Figure 8 In some embodiments, in step S260, after forming a work function layer 18 covering the bottom barrier layer 13 within the groove 11, the work function layer 18 may include TiAl, and the work function value of TiAl can be continuously adjusted within the range of 3.9 eV-4.3 eV by adjusting the Al content. By increasing the Al content in TiAl, the work function decreases, which can reduce the nMOS threshold voltage (V... tn The work function decreases by reducing the Al content in TiAl, and the pMOS threshold voltage (V) decreases. tp )optimization.

[0070] Please see Figure 9In some embodiments, in step S260, an adhesion layer 19 covering the work function layer 18 and the molecular protective film 17 is formed; a gate conductive layer 110 filling the groove 11 is also formed. The adhesion layer 19 may include Ti, TiN, Ta, TaN, or a combination thereof. The adhesion layer 19 can simultaneously form strong chemical bonds with the work function layer 18 and the gate conductive layer, thereby bridging the two materials and significantly improving the interfacial bonding strength. The gate conductive layer 110 may include, but is not limited to, aluminum, tungsten, tantalum, molybdenum, cobalt, platinum, or a combination thereof to meet the practical needs of various application scenarios and reduce the cost and complexity of preparation.

[0071] Please see Figure 9 In some embodiments, after forming a gate conductive layer 110 that fills the groove 11 using a deposition process, the method further includes: planarizing the top surface of the gate conductive layer 110 until the top surface of the remaining gate conductive layer 110 is flush with the top surface of the interlayer dielectric layer 100; forming a stack covering the gate conductive layer 110 and the interlayer dielectric layer 100; and patterning the stack 400 to form a target resistance device.

[0072] For example, the stack 400 includes an oxide layer 401, a conductive layer 402, and a nitride layer 403 sequentially stacked along the direction away from the substrate. The patterned stack 400 includes: forming a patterned mask layer (not shown) on the top surface of the nitride layer 403, the patterned mask layer including a pattern for defining a target resistance device; based on the patterned mask layer, using the oxide layer 401 as an etch stop layer, etching the nitride layer 403 and the conductive layer 402 to expose a portion of the oxide layer 401. Wet cleaning removes etching residue. Since the gate structure sidewalls do not contain a TiAl layer that is easily corroded by acid solutions during wet etching, the lack of gate structure filler can be effectively avoided, improving the yield, performance, and reliability of the fabricated semiconductor products.

[0073] The deposition process may include, but is not limited to, one or more of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD).

[0074] In some embodiments, a semiconductor structure is provided, which is prepared using the semiconductor structure preparation method of any of the foregoing embodiments.

[0075] Please refer to Figures 2-9 The semiconductor structure fabrication method and semiconductor structure in the above embodiments have at least the following unexpected technical effects:

[0076] A groove 11 is formed in the interlayer dielectric layer 100 on the top surface of the gate dielectric layer 12. A bottom barrier layer 13 is provided on the bottom surface of the groove 11. A diffusion barrier layer 14 is provided on the sidewall of the groove 11 and the top surface of the bottom barrier layer 13 to prevent the filler from diffusing into the substrate 10 or the interlayer dielectric layer 100 during the subsequent filling of the gate structure into the groove 11. After forming the initial titanium film 151 covering the diffusion barrier layer 14, the initial titanium film 151 located at the bottom surface of the groove 11 is etched and removed by plasma 20 generated based on inert gas. Then, the remaining target titanium film 15 is treated with a target gas containing oxygen, nitrogen, and hydrogen, forming hydroxyl and amino groups 16 of a target density on the surface of the remaining target titanium film 15. The hydroxyl and amino groups 16 are used to provide chemical anchoring sites and reactive sites. Thus, after treating the surface of the remaining target titanium film 15 with a phosphorus-containing solution, a molecular protective film 17 containing titanium, phosphorus, and oxygen is formed. During the subsequent formation of the work function layer 18 covering the bottom barrier layer 13 at the bottom surface of the groove 11, the molecular protective film 17 is used to suppress the adhesion of the work function layer 18 to the sidewall of the groove 11, avoid the formation of the work function layer 18 on the sidewall of the groove 11, and avoid reducing the opening size of the groove 11 during the formation of the work function layer 18. This facilitates the formation of a gate conductive layer 110 that fills the groove 11 after the formation of the adhesion layer 19 covering the work function layer 18 and the molecular protective film 17. Since the sidewalls of the gate conductive layer 110 do not include the work function layer 18, the subsequent wet etching solution avoids the absence of gate structure filler due to etching of the work function layer 18 in the sidewalls, thereby improving the yield, performance and reliability of the semiconductor products.

[0077] Although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the exact order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are executed, and they can be executed in other sequences. Moreover, although Figure 2 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution of these sub-steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method of fabricating a semiconductor structure, comprising: The method comprises: providing a substrate, a top surface of the substrate comprising a gate dielectric layer; forming an interlayer dielectric layer on a top surface of the gate dielectric layer, the interlayer dielectric layer comprising a recess exposing a portion of a top surface of the gate dielectric layer, a bottom surface of the recess comprising a bottom barrier layer, sidewalls of the recess and a top surface of the bottom barrier layer comprising a diffusion barrier layer; forming an initial titanium film covering the diffusion barrier layer, etching and removing the initial titanium film on the bottom surface of the recess based on a plasma generated by an inert gas; treating a remaining target titanium film with a target gas containing oxygen, nitrogen and hydrogen, forming a target density of hydroxyl and amino groups on a surface of the remaining target titanium film; the hydroxyl and amino groups being used to provide chemical anchoring sites and reactive sites; treating the surface of the remaining target titanium film with a phosphorus-containing solution, forming a molecular protective film containing titanium, phosphorus and oxygen; after forming a work function layer covering the bottom barrier layer in the recess, forming an adhesion layer covering the work function layer and the molecular protective film; forming a gate conductive layer filling the recess.

2. The method of claim 1, wherein The removing the initial titanium film on the bottom surface of the recess comprises: bombarding the initial titanium film on the bottom surface of the recess with an accelerated plasma generated by an inert gas to remove the initial titanium film on the bottom surface of the recess, and the initial titanium film remaining on the sidewalls of the recess being used to form an initial protective film.

3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The target gas comprises oxygen, nitrogen and hydrogen; surface oxidation treatment of the initial protective film generates titanium oxide rich in hydroxyl on a titanium surface; surface amine treatment of the titanium oxide generates amino groups on the surface of the target titanium film.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: The surface amine treatment of the titanium oxide comprises: treating the titanium oxide with a nitrogen-hydrogen mixed plasma under a power of 50-150 W for a preset time to generate amino groups on the surface of the target titanium film.

5. The method of claim 1-4, wherein The forming the molecular protective film comprises: reacting a target phosphoric acid with the hydroxyl and amino groups to form the molecular protective film for enhancing corrosion resistance.

6. The method of claim 5, wherein the step of forming the semiconductor structure is performed by a method selected from the group consisting of: epitaxial growth, ion implantation, and a combination thereof. The target phosphoric acid comprises octadecyl phosphonic acid, ethanol and sodium hydroxide.

7. The method of claim 1-4, wherein After forming the gate conductive layer filling the recess, the method further comprises: planarizing a top surface of the gate conductive layer until a remaining top surface of the gate conductive layer is flush with a top surface of the interlayer dielectric layer; forming a stack layer covering the gate conductive layer and the interlayer dielectric layer; patterning the stack layer to form a target resistance device.

8. The method of claim 7, wherein the step of forming the semiconductor structure is performed by a method selected from the group consisting of: epitaxial growth, ion implantation, and photolithography. The stack layer comprises, in a direction away from the substrate, an oxide layer, a conductive layer and a nitride layer stacked in sequence; The patterning the stack layer comprises: forming a patterned mask layer on a top surface of the nitride layer, the patterned mask layer comprising a pattern for defining the target resistance device; based on the patterned mask layer, etching the nitride layer and the conductive layer with the oxide layer as an etching stop layer to expose a portion of the oxide layer.

9. The method of claim 1-4, wherein, At least one of the following features is included: a thickness of the initial titanium film is 1-2 nm; a thickness of the molecular protective film is 1-2 nm; the inert gas comprises nitrogen, argon, helium or a combination thereof.

10. A semiconductor structure, characterized by The semiconductor structure is prepared by the method of any one of claims 1-9.

Images