Conductive pads on through silicon vias

Abstract

A semiconductor device is provided. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A via extends completely through the substrate. The via includes a protruding portion that extends beyond the backside of the substrate. A silicon nitride carbon layer is disposed at the backside of the substrate and along sidewalls of the protruding portions of the vias. An oxide layer is disposed at the backside of the substrate and at least partially surrounds the protruding portion of the via. A conductive pad is disposed at a coupling surface of the via and extends at least partially through the oxide layer. Therefore, a reliable and cost-effective semiconductor device can be assembled.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor device assemblies, and more specifically to conductive pads on through-silicon vias (TSVs). Background Technology

[0002] Microelectronic devices typically have dies (e.g., chips) containing integrated circuits with a high density of extremely small components. Typically, a die contains an array of bonding pads electrically coupled to the integrated circuit. These bonding pads are external electrical contacts through which power supply voltages, signals, etc., are transmitted to and from the integrated circuit. After the die is formed, the electrical contacts are “encapsulated” to couple the bonding pads to a larger array of electrical terminals that can be more easily coupled to various power lines, signal lines, and ground lines. Conventional processes for encapsulating dies involve electrically coupling the bonding pads on the die to lead, ball pads, or other types of electrical terminal arrays, and encapsulating the die to protect it from environmental factors such as moisture, particles, static electricity, and physical shock. Attached Figure Description

[0003] Figure 1 A simplified schematic cross-sectional view illustrating a semiconductor device assembly.

[0004] Figure 2 A simplified schematic cross-sectional view illustrating a semiconductor device assembly according to an embodiment of the present technology.

[0005] Figures 3 to 6 A simplified schematic cross-sectional view illustrating a series of steps for manufacturing a semiconductor device assembly according to an embodiment of the present technology.

[0006] Figure 7 This diagram illustrates a system comprising a semiconductor device assembly configured according to an embodiment of the present technology.

[0007] Figure 8 A method for manufacturing a semiconductor device assembly according to embodiments of the present technology is described. Detailed Implementation

[0008] Semiconductor devices are integrated into numerous devices to implement memory cells, processor circuitry, imaging devices, and other functional features. As more applications for semiconductor devices are discovered, the designer's task is to create improved devices that can perform more operations per second, store larger amounts of data, or operate with higher levels of security. To accomplish this, designers are constantly developing new technologies to increase the number of circuit elements on semiconductor devices without simultaneously increasing the device's size. However, this development may not be sustainable due to the various challenges arising from designing semiconductor devices with high circuit density. Therefore, additional technologies may be needed to continue the growth of semiconductor device capabilities.

[0009] One such technique implements multiple circuit components within a single package. For example, stacked semiconductor devices can stack multiple semiconductor dies on top of each other to increase the number of circuit elements within the package without increasing its footprint. In some cases, individual semiconductor dies can be stacked on top of each other to create a vertical stack of semiconductor dies. A semiconductor die may include a through-silicon via (TSV) extending between a front side (e.g., the active side where circuitry is located) and a back side opposite the front side. Contact pads may be disposed on the back side of the semiconductor die to contact the exposed portion of the TSV, allowing additional semiconductor dies to be electrically coupled there. Various techniques exist for placing contact pads at the TSV; however, some of these techniques may be too time-consuming or result in semiconductor devices with reliability or cost issues. Figure 1 The example semiconductor device is shown in the image.

[0010] Figure 1 This describes a semiconductor device assembly 100 including a semiconductor die 102. The semiconductor die 102 can be assembled onto a carrier wafer to enable the semiconductor die 102 to withstand processing. The semiconductor die 102 includes a substrate 104 (e.g., a silicon substrate, an organic substrate, a printed circuit board (PCB) core, etc.), the substrate 104 having a metallization layer 106 (e.g., having interconnect circuitry, such as traces, lines, and vias) on the front side. A TSV 108 extends completely through the substrate 104 from the front side to the back side opposite the front side. Contact pads 110 can be disposed on the coupling surface 112 of the TSV 108 exposed on the back side of the substrate 104. Contact pads 110 can be disposed within an oxide layer 114 (e.g., high-temperature silicon oxide deposited at temperatures above 300, 400, 500, or 700 degrees Celsius).

[0011] Various techniques can be used to mount the contact pad 110 of the TSV 108. For example, initially, the TSV 108 may protrude beyond the back side of the substrate 104 (e.g., by more than 3 micrometers). A silicon nitride layer 116 (e.g., low-temperature silicon nitride deposited at temperatures below 200, 300, or 400 degrees Celsius) may be mounted on the back side of the substrate, along the sidewalls of the TSV 108, and above the top of the TSV 108. In some cases, the silicon nitride layer is mounted with a thickness greater than 1 micrometer. Next, an oxide layer (not shown) (e.g., a low-temperature oxide) may be deposited on the back side of the semiconductor die 102 above the silicon nitride layer 116. The oxide layer may be mounted with a thickness of about 0.5 micrometers (e.g., within 0.1 micrometers, within 0.2 micrometers, etc.). The TSV 108 may then be exposed by removing material from the back side of the semiconductor die 102 through chemical mechanical planarization (CMP). For example, the oxide layer can be completely removed, and the silicon nitride layer 116 can be thinned to about 1 micrometer (e.g., within 0.1 micrometer, within 0.2 micrometer, within 0.5 micrometer, etc.). In this way, the back side of the semiconductor die 102 can correspond to the planarized silicon nitride layer 116, wherein the coupling surface 112 of the TSV 108 is exposed.

[0012] Next, a silicon nitride carbon layer 118 (e.g., high-temperature silicon nitride carbon) can be disposed over the silicon nitride layer 116 and the coupling surface 112 of the TSV 108. An oxide layer 114 can be disposed on the back side of the semiconductor die 102 over the silicon nitride carbon layer 118. Next, an additional silicon nitride carbon layer 120 (e.g., high-temperature silicon nitride carbon) can be disposed over the oxide layer 114. The silicon nitride carbon layer 118, oxide layer 114, and silicon nitride carbon layer 120 can be etched (e.g., dry etched) to expose the coupling surface 112 of the TSV 108. Next, a contact pad 110 can be disposed in the opening at the coupling surface 112, such that the contact pad 110 is exposed on the back side of the semiconductor die 102. In this way, additional semiconductor dies can be stacked onto the semiconductor die 102 and electrically coupled at the contact pad 110.

[0013] For many reasons, using these techniques to place contact pads on TSVs can be suboptimal. As discussed above, the process can involve multiple deposition steps to place individual layers on the back side of semiconductor die 102 (e.g., silicon nitride layer 116 or oxide layers that are later removed). Therefore, implementations of the design process can require significant time and have high material costs. Furthermore, the coupling surface 112 of TSV 108 can be exposed by CMP, which may result in smearing of conductive material within TSV 108 across the back side of semiconductor die 102 or breakage of semiconductor die 102. In this way, the use of CMP can reduce the reliability or yield of semiconductor die 102. On the other hand, using CMP in regions containing and not containing TSV 108 can create morphologies (e.g., height differences up to 200 nm) on the back surface of semiconductor die 102. These morphologies may arise because regions containing TSV 108 are more resistant to CMP than regions not containing TSV 108. In some cases, this topography can introduce weaknesses in semiconductor die 102 or make it difficult to stack additional semiconductor dies on top of semiconductor die 102. In one aspect, the topography can reduce the reliability of the metal-metal junction at TSV 108 (e.g., due to DC resistance yield). Therefore, designing semiconductor devices using these techniques may result in semiconductor devices with reliability issues or require excessive cost or manufacturing time.

[0014] To address these and other drawbacks, various embodiments of this technology provide semiconductor device assemblies including contact pads disposed at TSVs. The semiconductor device includes a substrate having a front side and a back side opposite the front side. A via extends completely through the substrate. The via includes a protrusion extending beyond the back side of the substrate. A silicon nitride carbon layer is disposed on the back side of the substrate and along the sidewall of the protrusion of the via. An oxide layer is disposed on the back side of the substrate and at least partially surrounds the protrusion of the via. A conductive pad is disposed at the coupling surface of the via and at least partially extends through the oxide layer. Therefore, a reliable and cost-effective semiconductor device can be assembled, examples of which are shown in […]. Figure 2 It is displayed in the middle.

[0015] Figure 2This describes a semiconductor device assembly 200 including a semiconductor die 202. The semiconductor die 202 can be assembled onto a carrier wafer to enable the semiconductor die 202 to withstand processing. The semiconductor die 202 includes a substrate 204 having a metallization layer 206 (e.g., having interconnect circuitry, such as traces, lines, and vias) on its front side. A TSV 208 extends completely through the substrate 204 from the front side to the back side opposite the front side. A contact pad 210 may be disposed on a coupling surface 212 of the TSV 208. The contact pad 210 may be disposed within an oxide layer 214 (e.g., high-temperature silicon oxide) and exposed on the back side of the semiconductor die 202. A silicon nitride carbon layer 216 (e.g., high-temperature silicon nitride carbon) may be disposed on the back side of the substrate 204, and a silicon nitride carbon layer 218 may be disposed opposite to the silicon nitride carbon layer 218 on the oxide layer 214.

[0016] and Figure 1 In contrast to the semiconductor device assembly 100 described herein, the TSV 208 may have a protrusion 220 extending beyond the back side of the substrate 204. For example, the protrusion 220 may extend beyond the back side of the substrate 204 by more than 1 micrometer, more than 2 micrometers, more than 3 micrometers, more than 4 micrometers, or more than 5 micrometers. A silicon nitride carbon layer 216 may be disposed on the back side of the substrate 204, extending along the sidewall 222 of the protrusion 220 of the TSV 208, and extending above a portion of the coupling surface 212. In this way, the silicon nitride carbon layer 216 may conform to the shape of the protrusion 220 of the TSV 208. In this aspect, the silicon nitride carbon layer 216 may be about 0.15 micrometers thick (e.g., within 0.01 micrometers, within 0.05 micrometers, within 0.1 micrometers, etc.). As illustrated, the silicon nitride carbon layer 216 may be in direct contact with the substrate 204 (e.g., on the back side). For example, the silicon nitride carbon layer 216 and the substrate 204 may not be made of another material (e.g., Figure 1 The silicon nitride layer 116 is used as a separator.

[0017] Contact pad 210 may be disposed on the back side of semiconductor die 202 on coupling surface 212 of TSV 208. In one aspect, contact pad 210 may be smaller than coupling surface 212 of TSV 208, such that contact pad 210 contacts only a portion of coupling surface 212. For example, the cross-sectional area of ​​contact pad 210 in a plane coplanar with coupling surface 212 is smaller than the area of ​​coupling surface 212. The surface of contact pad 210 may be disposed on the back side of semiconductor die 202 to allow additional semiconductor dies to be stacked on semiconductor die 202 and electrically coupled to semiconductor die 202 at contact pad 210.

[0018] Although described and illustrated as a semiconductor die, semiconductor die 202 can be replaced by a wafer (e.g., a semiconductor wafer) on which multiple semiconductor dies are implemented. For example, substrate 204 can be replaced by a wafer-level or panel-level substrate for implementing multiple semiconductor dies. Furthermore, although described as a TSV, TSV 208 can generally refer to a substrate via. Thus, TSV 208 can be implemented through a non-silicon substrate (e.g., an organic substrate or other semiconductor substrate). In another aspect, although described with reference to a particular material, other materials can be used to form the various layers of semiconductor die 202. In this way, oxide layer 214, silicon carbon nitride layer 216, or silicon carbon nitride layer 218 can alternatively comprise any other material, such as different dielectric materials (e.g., silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, or the like).

[0019] This disclosure now turns to a series of steps for manufacturing a semiconductor device assembly according to embodiments of the present technology. Specifically, Figures 3 to 6 A simplified schematic cross-sectional view illustrating a series of steps for manufacturing a semiconductor device assembly according to embodiments of the present technology is provided. For ease of description, the steps are illustrated with respect to specific embodiments. However, these steps may be performed according to other embodiments to manufacture the semiconductor device assembly.

[0020] from Figure 3 Beginning at stage 300, a simplified schematic cross-sectional view of the semiconductor device assembly is shown. The semiconductor device assembly includes a semiconductor die 202 assembled onto a carrier substrate. The semiconductor die 202 may be disposed face down and adhered (e.g., by adhesive or dielectric material) to the carrier substrate such that the front side of the semiconductor die 202 faces the carrier substrate. The semiconductor die 202 may be implemented at a substrate 204. A metallization layer 206, including traces, lines, vias, and other interconnect structures, may be disposed on the front side of the semiconductor die 202. A TSV 208 extends completely through the substrate 204 from the metallization layer 206. A protrusion 220 of the TSV 208 extends beyond the back side of the substrate 204. For example, the protrusion 220 of the TSV 208 may extend beyond the back side of the substrate 204 by an amount greater than 1 micrometer, greater than 2 micrometers, greater than 3 micrometers, greater than 4 micrometers, greater than 5 micrometers, etc.

[0021] Figure 4A simplified schematic cross-sectional view of stage 400 illustrates a passivation material disposed around the protrusion 220 of the TSV 208 on the back side of the substrate 204. The coupling surface 212 of the TSV 208 may be exposed at a remote portion of the protrusion 220 of the TSV 208. In this aspect, the protrusion 220 is not planarized downwards to be substantially coplanar with the back side of the substrate 204 (e.g., within 0.5 μm, within 1 μm, within 2 μm, within 5 μm, etc.). Therefore, the back side of the substrate 204 may have a morphology less than 200 nm, less than 100 nm, less than 50 nm. Instead of planarizing downwards to the back side of the substrate 204, a silicon carbon nitride layer 216 may be deposited on the back side of the substrate 204 (e.g., in direct contact with the back side of the substrate 204) and around the protrusion 220 of the TSV 208. For example, a silicon nitride carbon layer 216 may be disposed on the back side of substrate 204, along the sidewall 222 of protrusion 220, and above coupling surface 212. The silicon nitride carbon layer 216 may comprise high-temperature silicon nitride carbon deposited at temperatures above 300, 400, 500, or 700 degrees Celsius. The silicon nitride carbon layer 216 may be disposed with a thickness of approximately 0.15 micrometers (e.g., within 0.01 micrometers, within 0.05 micrometers, within 1 micrometer, etc.).

[0022] An oxide layer 214 (e.g., high-temperature silicon oxide) may be disposed at least partially around the protrusion 220. For example, the oxide layer 214 may be deposited such that it extends more than 1 micrometer above the protrusion 220. The oxide layer 214 may be disposed over a silicon nitride carbon layer 216 such that the silicon nitride carbon layer 216 separates the substrate 204 and the TSV 208 from the oxide layer 214. Subsequently, an additional silicon nitride carbon layer 218 may be disposed over the oxide layer 214 opposite to the silicon nitride carbon layer 216 (e.g., opposite to the substrate 204).

[0023] Figure 5 A simplified schematic cross-sectional view of stage 500 illustrates that contact pad 210 is disposed at the coupling surface 212 of TSV 208 such that contact pad 210 is electrically coupled to TSV 208. Portions of oxide layer 214, silicon carbon nitride layer 216, and silicon carbon nitride layer 218 can be removed to expose coupling surface 212 of TSV 208. This can be achieved, for example, by etching. A conductive material can then be disposed in the opening to implement contact pad 210. Contact pad 210 may be smaller than coupling surface 212 of TSV 208. In this manner, silicon carbon nitride layer 216 may still cover a portion of coupling surface 212 of TSV 208. In this aspect, CMP is not used to expose coupling surface 212 of TSV 208. Therefore, the risk of contamination from TSV 208 or breakage of semiconductor die 202 can be eliminated. In the other hand, without planarizing TSV 208 down to the substrate, passivation material can be removed from substrate 204 (e.g., regarding...). Figure 1 The described steps involve removing a low-temperature oxide layer (using CMP) or planarizing TSV208 during the fabrication of the semiconductor device assembly, thereby simplifying the manufacturing process and reducing the overall cost of producing the semiconductor device assembly. Subsequently, additional semiconductor dies can be stacked onto semiconductor die 202, and the stacked semiconductor dies can be packaged into a packaged semiconductor device, an example of which is... Figure 6 It is displayed in the middle.

[0024] Figure 6 A simplified schematic cross-sectional view of the semiconductor device assembly at stage 600 is shown. The semiconductor device assembly 600 includes stacked semiconductor dies 602. One or more of the stacked semiconductor dies 602 may include TSVs with contact pads disposed thereon. Thus, interconnects (e.g., metal-to-metal interconnects) electrically coupling the semiconductor dies 602 may be formed between corresponding contact pads on the respective dies of the stacked semiconductor dies 602. The stacked semiconductor dies 602 may be assembled onto a package-grade substrate 604 via conductive structures 606 (e.g., conductive pillars, solder joints, etc.). For example, contact pads at the base die of the stacked semiconductor dies 602 may be electrically coupled to contact pads (not shown) on the upper surface of the package-grade substrate 604 via conductive structures 606. The package-grade substrate 604 may include internal circuitry (traces, lines, vias, and other connection structures) connecting contact pads on the upper surface to contact pads (not shown) on the lower surface. Conductive structures 608 may be disposed at contact pads on the lower surface to provide external connectivity (e.g., power, ground, input / output (I / O) signaling, or the like) to the stacked semiconductor die 602. A base filler material 610 (e.g., capillary base filler) may be disposed around the conductive structures 606 to electrically insulate these structures and mechanically support the semiconductor device assembly 600. An encapsulant 612 (e.g., molding resin) may be disposed at least partially around the stacked semiconductor die 602 and the package-grade substrate 604 to protect the semiconductor device assembly 600 and prevent electrical contact therewith.

[0025] Although the semiconductor device assembly has been described and depicted in the foregoing example embodiments as having a specific configuration including semiconductor dies, in other embodiments, the assembly may have different configurations of semiconductor dies. For example, with appropriate modifications, the semiconductor device assembly described in any of the foregoing examples may be implemented as a vertical stack of semiconductor dies (e.g., according to the High Bandwidth Memory (HBM) protocol), a stack of multiple semiconductor dies, multiple semiconductor dies, or a single semiconductor die.

[0026] According to one aspect of this disclosure, Figures 1 to 6The semiconductor device described in the assembly may include memory dies, such as dynamic random access memory (DRAM) dies, not-AND (NAND) memory dies, not-OR (NOR) memory dies, magnetic random access memory (MRAM) dies, phase-change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, or the like. In embodiments where multiple dies are provided in a single assembly, the semiconductor device may include memory dies of the same type (e.g., two NAND, two DRAM, etc.) or memory dies of different types (e.g., one DRAM and one NAND, etc.). According to another aspect of this disclosure, the semiconductor dies of the assemblies described above may be logic dies (e.g., controller dies, processor dies, etc.), or a mixture of logic and memory dies (e.g., memory controller dies and memory dies controlled by them).

[0027] The above text is about Figures 1 to 6 Any of the described semiconductor devices and semiconductor device assemblies can be incorporated into any of a multitude of larger and / or more complex systems, a representative example of which is... Figure 7 The system 700 is schematically shown in the diagram. System 700 may include a semiconductor device assembly 702 (e.g., a discrete semiconductor device), a power supply 704, a driver 706, a processor 708, and / or other subsystems or components 710. The semiconductor device assembly 702 may include components related to those described above. Figures 1 to 6 The described semiconductor device assemblies are characterized by generally similar features. The resulting system 700 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 700 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, home appliances, and other products. Components of system 700 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 700 may also include remote devices and any of a variety of computer-readable media.

[0028] Figure 8 An example method 800 for manufacturing a semiconductor device assembly according to embodiments of the present technology is described. Although described with a specific configuration, one or more operations of method 800 may be omitted, repeated, or rearranged. Additionally, method 800 may include... Figure 8 Other operations not described herein, such as those detailed in one or more other methods described herein.

[0029] At 802, a substrate is provided. The substrate may include a front side, a back side opposite the front side, and a via that extends completely through the substrate and has a protrusion extending beyond the back side of the substrate. At 804, a silicon carbon nitride layer is disposed on the back side of the substrate and surrounds the protrusion of the via. At 806, an oxide layer is disposed on the back side of the substrate and at least partially surrounds the protrusion of the via. At 808, the oxide layer and the silicon carbon nitride layer are etched to expose the coupling surface of the via. At 810, a conductive pad is disposed at the coupling surface of the via and at least partially extends through the oxide layer.

[0030] The foregoing describes specific details of several embodiments of semiconductor devices and associated systems and methods. Depending on the context in which it is used, the term "substrate" may refer to a wafer-level substrate or a monolithically derived die-level substrate. Furthermore, unless the context otherwise indicates, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. Materials may be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials may be removed, for example, using plasma etching, wet etching, CMP, or other suitable techniques.

[0031] The technologies disclosed herein relate to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term "semiconductor device" generally refers to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include, in particular, logic devices, memory devices, and diodes. Furthermore, the term "semiconductor device" may refer to a finished device or an assembly or other structure at various processing stages prior to becoming a finished device. Depending on the context in which it is used, the term "substrate" may refer to a structure supporting electronic components (e.g., a die), such as a PCB or wafer-level substrate, a die-level substrate, or another die for die stacking or three-dimensional integration (3DI) applications.

[0032] The devices discussed herein (including memory devices) can be formed on a semiconductor substrate or die (e.g., silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0033] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality may also be physically located in various locations, including portions distributed such that the functionality is implemented at different physical locations.

[0034] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a closed set of conditions. For example, an instance step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0035] As used herein, the terms “vertical,” “lateral,” “up,” “down,” “above,” and “below” may refer to a feature in a semiconductor device in relation to the relative orientation or position shown in the figures. For example, “up” or “top” may refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices with other orientations (e.g., inverted or tilted orientations), where top / bottom, above / below, above / below, up / down, and left / right may be interchanged depending on the orientation.

[0036] As will be understood from the foregoing, specific embodiments of this disclosure have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of this disclosure. Specifically, numerous specific details are set forth in the foregoing description to provide a thorough and exhaustive description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of these specific details. In other instances, well-known structures or operations typically associated with memory systems and apparatuses have not been shown or described in detail to avoid obscuring other aspects of the present technology. In general, it should be understood that various other apparatuses, systems, and methods, in addition to the specific embodiments disclosed herein, may also be within the scope of this technology.

Claims

1. A semiconductor device comprising: A substrate having a front side and a back side opposite to the front side; A through-hole that extends completely through the substrate and has a protrusion that extends beyond the back side of the substrate; A silicon nitride carbon layer disposed on the back side of the substrate and extending along the sidewall of the protruding portion of the via; An oxide layer disposed on the back side of the substrate and at least partially surrounding the protruding portion of the via; and A conductive pad is disposed at the coupling surface of the via and extends at least partially through the oxide layer.

2. The semiconductor device of claim 1, wherein the silicon nitride carbon layer directly contacts the back side of the substrate.

3. The semiconductor device of claim 1, wherein the silicon nitride carbon layer extends over a portion of the coupling surface of the via.

4. The semiconductor device of claim 1, further comprising an additional silicon carbon nitride layer disposed on the oxide layer opposite to the silicon carbon nitride layer.

5. The semiconductor device of claim 1, wherein the surface area of ​​the conductive pad in a plane coplanar with the coupling surface of the via is smaller than the surface area of ​​the coupling surface of the via.

6. The semiconductor device of claim 1, wherein the back side of the substrate has a morphology of less than 200 nanometers.

7. The semiconductor device of claim 1, wherein the oxide layer comprises tetraethyl orthosilicate, spin-coated dielectric, or spin-coated glass.

8. A method for manufacturing a semiconductor device, comprising: A substrate is provided, the substrate including a front side, a back side opposite to the front side, and a through-hole extending completely through the substrate and having a protrusion extending beyond the back side of the substrate; A silicon nitride carbon layer is disposed on the back side of the substrate and surrounds the protruding portion of the via; An oxide layer is disposed on the back side of the substrate and at least partially surrounds the protruding portion of the via; Etch the oxide layer and the silicon carbon nitride layer to expose the coupling surface of the via; and A conductive pad is placed at the coupling surface of the via and extends at least partially through the oxide layer.

9. The method of claim 8, further comprising positioning the silicon nitride carbon layer in direct contact with the back side of the substrate.

10. The method of claim 8, further comprising placing the silicon nitride carbon layer at a temperature above 700 degrees Celsius.

11. The method of claim 8, further comprising etching the oxide layer and the silicon carbon nitride layer to expose the coupling surface of the via, such that a portion of the silicon carbon nitride layer extends over a portion of the coupling surface where the conductive pad is not disposed.

12. The method of claim 8, further comprising disposing an additional silicon carbon nitride layer opposite to the silicon carbon nitride layer at the oxide layer.

13. The method of claim 8, further comprising placing the oxide layer by flowable chemical vapor deposition, fluid vapor deposition, or spin coating.

14. A semiconductor device comprising: A substrate having a front side and a back side opposite to the front side; A through-hole that extends completely through the substrate and has a protrusion that extends beyond the back side of the substrate; A silicon nitride carbon layer that is in direct contact with the back side of the substrate; An oxide layer is disposed on the back side of the substrate and above the protruding portion of the via; and A conductive pad is disposed at the coupling surface of the via and extends at least partially through the oxide layer.

15. The semiconductor device of claim 14, wherein the silicon nitride carbon layer extends along the sidewall of the protruding portion of the via.

16. The semiconductor device of claim 14, wherein the silicon nitride carbon layer extends over a portion of the coupling surface of the via.

17. The semiconductor device of claim 14, further comprising an additional silicon carbon nitride layer disposed on the oxide layer opposite to the silicon carbon nitride layer.

18. The semiconductor device of claim 14, wherein the cross-sectional area of ​​the conductive pad in a plane coplanar with the coupling surface of the via is smaller than the area of ​​the coupling surface of the via.

19. The semiconductor device of claim 14, further comprising: A semiconductor die comprising the substrate and the contact pad; and Additional semiconductor dies, which include additional contact pads, The semiconductor die and the additional semiconductor die are coupled at the contact pad and the additional contact pad to implement semiconductor die stacking according to a high-bandwidth memory protocol.

20. The semiconductor device of claim 14, further comprising: Logic dies; A semiconductor die comprising the substrate and the contact pad, and coupled to the logic die at a first lateral position; Additional semiconductor dies, which include additional contact pads, The semiconductor die and the additional semiconductor die are coupled at the contact pad and the additional contact pad to implement a first semiconductor die stack; and A second semiconductor die stack is coupled to the logic die at a second lateral location.

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