Semiconductor device and method of manufacturing the same

Abstract

This semiconductor device is provided with: a first substrate (100) on which a first semiconductor element (10) is mounted, the first substrate (100) having a plurality of first front-surface-side pads disposed around the front surface; a second substrate (200) on which the first semiconductor element (20) is mounted, the second substrate (200) having a plurality of second front-surface-side pads disposed around the front surface; a third substrate (300) disposed between the first substrate (100) and the second substrate (200) so as to face the front surface of the first substrate (100) and the front surface of the second substrate (200), the third substrate (300) having a plurality of third rear-surface-side pads on the periphery of the rear surface, and a plurality of third front-surface-side pads on the periphery of the front surface; a plurality of first connection members (50) that electrically connect the corresponding first front-surface-side pads of the first substrate (100) and the corresponding third back-surface-side pads of the third substrate (300), respectively; a plurality of second connection members (70) that electrically connect the corresponding second front-surface-side pads of the second substrate (200) and the corresponding third front-surface-side pads of the third substrate (300); a first resin layer (400) that is in contact with the periphery of the front surface of the first substrate (100) and the periphery of the rear surface of the third substrate (300), and that has a hollow section; and a second resin layer (500) which is in contact with the periphery of the front surface of the second substrate (200) and the periphery of the back surface of the third substrate (300), and which has a hollow portion.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device mounted with a semiconductor element and a manufacturing method thereof. BACKGROUND

[0002] In the field of high-frequency devices such as communication, an amplifier with high efficiency and wide band is required, and Non-Patent Literature 1 proposes a semiconductor device with good heat dissipation and implementation and small size mounted with an amplifier, i.e., a semiconductor element, which switches between Doherty mode and out-of-phase mode for each frequency.

[0003] The semiconductor device shown in Non-Patent Literature 1 is a stacked package configured to have: a lower thick copper substrate composed of a double-input amplifier, an output combining circuit, an input circuit, and the like mounted in a dug portion; an upper thick copper substrate composed of a power supply, a driver amplifier, an input-output circuit, and the like mounted in a dug portion; and a multilayer interposer substrate disposed between the lower thick copper substrate and the upper thick copper substrate, each of the substrates being connected by solder balls containing copper core balls.

[0004] Prior Art Documents

[0005] Non-Patent Literature

[0006] Non-Patent Literature 1: Nishimura et al., "Research Results of Stacked Amplifier Package Using Thick Copper Substrate", 2022 Society Conference, Electronic Information Communication Society, September 2022 (Japanese: Nishimura et al., "Research Results of Stacked Amplifier Package Using Thick Copper Substrate", 2022 Society Conference, Electronic Information Communication Society, September 2022) SUMMARY

[0007] Problems to be Solved by the Invention

[0008] The semiconductor device shown in Non-Patent Literature 1 has the advantage of obtaining good characteristics on the basis of miniaturization.

[0009] On the other hand, in such a semiconductor device, improvement in environmental resistance and impact resistance is also desired.

[0010] The present disclosure was completed in view of the above problems, and aims to obtain a semiconductor device that exhibits good characteristics even for widebanding, is small, and has improved environmental resistance and impact resistance.

[0011] Means for Solving the Problems

[0012] The semiconductor device of the present disclosure includes a first substrate that mounts a first semiconductor element, has a plurality of first front-side pads arranged around a front surface on a side on which the first semiconductor element is mounted; a second substrate that mounts a second semiconductor element, has a plurality of second front-side pads arranged around a front surface on a side on which the second semiconductor element is mounted, and is arranged so that the front surfaces face each other with respect to the first substrate; a third substrate that is arranged between the first substrate and the second substrate so as to face the front surface of the first substrate and the front surface of the second substrate, has a plurality of third back-side pads arranged around a back surface so as to face the plurality of first front-side pads of the first substrate, respectively, and has a plurality of third front-side pads arranged around the front surface so as to face the plurality of second front-side pads of the second substrate, respectively; a plurality of first connection members that electrically connect corresponding ones of the plurality of first front-side pads of the first substrate and corresponding ones of the plurality of third back-side pads of the third substrate, respectively; a plurality of second connection members that electrically connect corresponding ones of the plurality of second front-side pads of the second substrate and corresponding ones of the plurality of third front-side pads of the third substrate, respectively; a first resin layer that is in contact with the front surface of the first substrate and the back surface of the third substrate, and has a hollow portion; and a second resin layer that is in contact with the front surface of the second substrate and the back surface of the third substrate, and has a hollow portion.

[0013] Effects of the Invention

[0014] According to the present disclosure, since the first resin layer having the hollow portion around the periphery where the first dielectric substrate and the interposer substrate face each other and the second resin layer having the hollow portion around the periphery where the second dielectric substrate and the interposer substrate face each other are provided, environmental resistance and impact resistance are improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 FIG. 1 is a cross-sectional view showing a semiconductor device of Embodiment 1.

[0016] Figure 2 FIG. 2 is a schematic view as viewed from the front surface of the first substrate of the semiconductor device of Embodiment 1.

[0017] Figure 3 FIG. 3 is a schematic view showing the connection relationship between the first semiconductor element and the wiring layer of the front surface of the first substrate of the semiconductor device of Embodiment 1.

[0018] Figure 4 FIG. 4 is a view showing a resist of the front surface layer of the first substrate of the semiconductor device of Embodiment 1.

[0019] Figure 5 FIG. 5 is a back surface view projected from the front surface of the first substrate of the semiconductor device of Embodiment 1.

[0020] Figure 6 This is a schematic view of the second substrate of the semiconductor device according to Embodiment 1 from the front.

[0021] Figure 7 This is a schematic diagram showing the connection relationship between the second and third semiconductor elements of the semiconductor device in Embodiment 1 and the wiring layer on the front side of the second substrate.

[0022] Figure 8 This is a diagram showing the photoresist on the front side layer of the second substrate of the semiconductor device in Embodiment 1.

[0023] Figure 9 This is a rear view of the second substrate of the semiconductor device according to Embodiment 1, projected from the front side.

[0024] Figure 10 This is a diagram showing the conductor pattern on the front side of the first layer of the third substrate of the semiconductor device according to Embodiment 1.

[0025] Figure 11 This is a diagram showing the photoresist on the front side of the first layer of the third substrate of the semiconductor device in Embodiment 1.

[0026] Figure 12 This is a diagram showing the conductor pattern on the front side of the second layer of the third substrate of the semiconductor device according to Embodiment 1.

[0027] Figure 13 This is a diagram showing the conductor pattern on the front side of the third layer of the third substrate of the semiconductor device according to Embodiment 1.

[0028] Figure 14 This is a diagram showing the conductor pattern on the front side of the fourth layer of the third substrate of the semiconductor device according to Embodiment 1.

[0029] Figure 15 This is a diagram showing the conductor pattern on the front side of the fifth layer of the third substrate of the semiconductor device according to Embodiment 1.

[0030] Figure 16 This is a diagram showing the conductor pattern on the back side of the sixth layer of the third substrate of the semiconductor device according to Embodiment 1.

[0031] Figure 17 This is a diagram showing the resist on the back side of the sixth layer of the third substrate of the semiconductor device in Embodiment 1.

[0032] Figure 18 This is a cross-sectional view showing the semiconductor device of Embodiment 2.

[0033] Figure 19 This is a cross-sectional view showing the semiconductor device of Embodiment 3.

[0034] Figure 20 This is a cross-sectional view showing the semiconductor device of Embodiment 4.

[0035] Figure 21 This is a schematic view of the first substrate of the semiconductor device according to Embodiment 4 from the front.

[0036] Figure 22 This is a schematic diagram showing the connection relationship between the first semiconductor element of the semiconductor device in Embodiment 4 and the wiring layer on the front side of the first substrate.

[0037] Figure 23 This is a diagram showing the photoresist on the front side layer of the first substrate of the semiconductor device in Embodiment 4.

[0038] Figure 24 This is a rear view of the front projection of the first substrate of the semiconductor device in Embodiment 4.

[0039] Figure 25 This is a schematic view of the second substrate of the semiconductor device in Embodiment 4 as seen from the front.

[0040] Figure 26 This is a schematic diagram showing the connection relationship between the second semiconductor element of the semiconductor device in Embodiment 4 and the wiring layer on the front side of the second substrate.

[0041] Figure 27 This is a diagram showing the photoresist on the front side layer of the second substrate of the semiconductor device in Embodiment 4.

[0042] Figure 28 This is a rear view of the second substrate of the semiconductor device in Embodiment 4, projected from the front side.

[0043] Figure 29 This is a diagram showing the conductor pattern of the front surface layer of the third substrate of the semiconductor device according to Embodiment 4.

[0044] Figure 30 This is a diagram showing the photoresist on the front side of the front side layer of the third substrate of the semiconductor device in Embodiment 4.

[0045] Figure 31 This is a diagram showing the conductor pattern of the back layer projected from the front side of the third substrate of the semiconductor device in Embodiment 4.

[0046] Figure 32 This is a diagram showing the photoresist on the back side of the back side layer of the third substrate of the semiconductor device in Embodiment 4. Detailed Implementation

[0047] Implementation method 1.

[0048] based on Figures 1 to 17The semiconductor device of Embodiment 1 will be described.

[0049] The semiconductor device of Embodiment 1 is a semiconductor device used in high-frequency equipment such as communication devices, and is composed of a stacked package containing a semiconductor element with high output amplification function, a semiconductor element with power control function, and a semiconductor element with drive amplification function.

[0050] The semiconductor device in Implementation 1 is a broadband GaN amplifier that switches between Doherty mode and out-of-phase mode at each frequency.

[0051] The semiconductor device of Embodiment 1 is particularly a semiconductor device that achieves ultra-wideband performance capable of covering the entire region of the Sub-6 frequency band (a frequency band above 0.8 GHz and less than 5 GHz), and is small in size and has good environmental resistance and shock resistance.

[0052] like Figure 1 As shown, the semiconductor device of Embodiment 1 includes: a first substrate 100 on which a first semiconductor element 10 is mounted; a second substrate 200 on which a second semiconductor element 20 and a third semiconductor element 30 are mounted; a third substrate 300 serving as an interposer substrate; a first connecting member 50; a second connecting member 70; a first resin layer 400; and a second resin layer 500.

[0053] Furthermore, regarding the first substrate 100, the second substrate 200, and the third substrate 300, since... Figure 2 It uses a square to represent the shape when viewed from the front, but depending on the purpose, it can also be vertical or horizontal, and is not limited to a square; it can also be a rectangle.

[0054] The first semiconductor element 10 is a semiconductor element with high output amplification function. The first semiconductor element 10 has two amplification circuits. The first semiconductor element 10 is a semiconductor element that is prone to heat generation. The characteristic impedance of the first semiconductor element 10 is, for example, 100Ω.

[0055] like Figure 3 As shown, the first semiconductor element 10 is a semiconductor element having two input terminals 11, 12, two output terminals 13, 14 and two bias terminals 15, 16 on the front side of the semiconductor substrate and the back side of the semiconductor substrate being a ground layer.

[0056] Terminals 11 to 16 are pads formed on the front side of the semiconductor substrate.

[0057] The first substrate 100 is on which a first semiconductor element 10 is mounted, and has a plurality of first front-side pads arranged around the front side of the side on which the first semiconductor element 10 is mounted.

[0058] The first substrate 100 has a first dielectric substrate 101 made of a single layer of insulating substrate, a first wiring pattern layer formed on the front side of the first dielectric substrate 101, a plurality of first front side pads formed around the front side of the first dielectric substrate 101, a first ground conductor 130 formed of thick copper on the back side of the first dielectric substrate 101, and a plurality of first back side pads.

[0059] The first substrate 100 has a first opening 102 formed on the first dielectric substrate 101, which extends from the front side to the front side of the first ground conductor 130. In the first opening 102, a first semiconductor element 10 electrically connected to the lines constituting the first wiring pattern layer is mounted and fixed on the front side of the first ground conductor 130.

[0060] The first semiconductor element 10 is mounted on the first opening 102 via the first heat sink 10A.

[0061] The ground layer on the back side of the first semiconductor element 10 is grounded through the first grounding conductor 130, and the heat generated by the first semiconductor element 10 is dissipated through the first heat sink 10A and the first grounding conductor 130.

[0062] The thickness of the first dielectric substrate 101 is set to reach the manufacturing limit for forming the first opening 102, so that the lines formed in the first wiring pattern layer on the front side of the first dielectric substrate 101 can achieve high impedance lines.

[0063] The first wiring pattern layer is formed of copper foil, i.e., conductor, with a thickness of, for example, 18um or 35um, and consists of transmission lines for transmitting signals, power supply lines for supplying power (current) from the power source, bias lines for supplying bias potential, and grounding conductors set to ground potential.

[0064] The first wiring pattern layer, through the first semiconductor element 10 and chip components 40 such as chip capacitors (only a portion is shown in the figure) that are electrically connected to the lines constituting the first wiring pattern, constitutes part of a high-frequency package or high-frequency module with built-in high-frequency circuitry.

[0065] like Figure 2 and Figure 3 As shown, the first wiring pattern layer consists of two input lines 103 and 104, a first transmission line 106 to a third transmission line 108 constituting the output synthesis circuit 105, a bias line 109, an output line 110, two bias lines 111 and 112, and a plurality of grounding conductors 113.

[0066] like Figure 3 As shown, an input line 103 is connected to an input terminal 11 of the first semiconductor element 10 via lead wires W such as gold wires.

[0067] The number of leads W is in Figure 3 The Chinese character is represented by a unit of 2, but it can also be 1 or more than 3.

[0068] The number of leads W used for wire bonding as described below can also be 2, 1, 3 or more.

[0069] An input line 103 is a general term for a line from a location connected to an input terminal 11 of the first semiconductor element 10 to an input pad 103a. If chip components such as chip capacitors (not shown) are connected along the way, an input circuit is formed. This type of input circuit is a generally known input circuit.

[0070] Furthermore, although this embodiment 1 is described using leads, connections using other connecting components such as gold strips can also be used as long as the pad size is suitable for installation.

[0071] like Figure 3 As shown, another input line 104 is connected to another input terminal 12 of the first semiconductor element 10 by means of a gold wire or other lead W through lead bonding.

[0072] The other input line 104 is a general term for the line from the location connected to the other input terminal 12 of the first semiconductor element 10 to the other input pad 104a. If a chip component (not shown) such as a chip capacitor is connected in the middle, it constitutes another input circuit. This other input circuit is a generally known input circuit.

[0073] The first transmission line 106 to the third transmission line 108 are high impedance lines with characteristic impedance of, for example, 100Ω and electrical length of 50 to 90 degrees.

[0074] Furthermore, in this disclosure, 100Ω does not strictly mean only 100Ω, but includes values ​​within the range that are permissible in the design relative to 100Ω.

[0075] Furthermore, in this disclosure, 50 degrees to 90 degrees does not strictly refer to only 50 degrees to 90 degrees, but includes values ​​within the range that are permissible in the design relative to 50 degrees to 90 degrees.

[0076] like Figure 3 As shown, one end of the first transmission line 106 is connected to an output terminal 13 of the first semiconductor element 10 by means of a gold wire or other lead W through lead bonding.

[0077] One end of the second transmission line 107 is connected to the other end of the first transmission line 106, and the other end of the second transmission line 107 is connected to the output branch 105a of the output synthesis circuit 105.

[0078] The first transmission line 106 and the second transmission line 107 are lines that transmit a high-frequency amplified signal output from an output terminal 13 of the first semiconductor element 10 to the output branch 105a.

[0079] like Figure 3 As shown, one end of the third transmission line 108 is connected to another output terminal 14 of the first semiconductor element 10 by means of gold wire or other leads W through lead bonding, and the other end of the third transmission line 108 is connected to the output branch 105a of the output synthesis circuit 105.

[0080] The third transmission line 108 is a line that transmits the high-frequency amplified signal output from another output terminal 14 of the first semiconductor element 10 to the output branch 105a.

[0081] One end of the bias line 109 is connected to the output branch 105a of the output combining circuit 105, and the other end of the bias line 109 is connected to the bias pad 109a.

[0082] The bias line 109 is a general term for the line from the output branch 105a of the output combining circuit 105 to the bias pad 109a. It connects to a chip component (not shown) in the middle to form an output-side bias circuit. The bias circuit is a generally known circuit.

[0083] The output line 110 is the line connecting the output branch 105a of the output combining circuit 105 and the output pad 110a.

[0084] If the output synthesis circuit 105 is constructed using a first transmission line 106 to a third transmission line 108 with a characteristic impedance of around 100Ω, and the characteristic impedance of the first semiconductor element 10 is set to 100Ω, then it is not necessary to use other matching circuits between the first transmission line 106 and the third transmission line 108 and the output pad 110a connected to the 50Ω line system.

[0085] In addition, the output synthesis circuit 105 is constructed using the first transmission line 106 to the third transmission line 108 with an electrical length of about 50 to 90 degrees, so that the amplification mode of the first semiconductor element 10 can be switched efficiently by using the phase difference of each frequency.

[0086] Therefore, it is possible to achieve ultra-wideband performance as an amplifier while maintaining miniaturization as a semiconductor device.

[0087] likeFigure 3 As shown, a bias line 111 is connected to a bias terminal 15 of the first semiconductor element 10 via a lead W through a lead bonding.

[0088] A bias line 111 is a general term for a line from a location connected to a bias terminal 15 of the first semiconductor element 10 to a bias pad 111a. If a chip component (not shown) such as a chip capacitor is connected along the way, it constitutes an input-side bias circuit. In this case, the bias circuit is a generally known bias circuit.

[0089] like Figure 3 As shown, another bias line 112 is connected to another bias terminal 16 of the first semiconductor element 10 via lead W through lead bonding.

[0090] Another bias line 112 is a general term for the line from the location connected to another bias terminal 16 of the first semiconductor element 10 to another bias pad 112a. If a chip component (not shown) such as a chip capacitor is connected in the middle, it constitutes another input-side bias circuit. This other bias circuit is a generally known bias circuit.

[0091] like Figure 2 and Figure 3 As shown, multiple grounding conductors 113 are respectively arranged between adjacent transmission lines to prevent interference between signals between adjacent transmission lines.

[0092] exist Figure 2 In the figure, a plurality of grounding conductors 113 are electrically connected to the first grounding conductor 130 formed on the back side of the first dielectric substrate 101 through through holes (VIA) marked by ○ in the grounding conductors 113.

[0093] Furthermore, among the plurality of grounding conductors 113, the grounding conductor 113 that extends to the edge of the first dielectric substrate 101 and has a line width wider than the diameter of the pad also serves as a grounding pad 113a whose end is connected to the through-hole VIA.

[0094] In this embodiment 1, a plurality of first front-side pads formed on the front side of the first dielectric substrate 101 are formed along the four sides of the first dielectric substrate 101 by conductors that are copper foil, and there are 11 pads on each side.

[0095] However, the number of front-side pads can be changed according to the size of the first dielectric substrate 101 and the substrate manufacturing rules and required specifications, and is therefore not limited to 11.

[0096] In addition to having an input pad 103a, another input pad 104a, a bias pad 109a, an output pad 110a, a bias pad 111a, a bias pad 112a, and a ground pad 113a, the plurality of first front-side pads also have an input pad 121a, an output pad 122a, bias pads 123aa to 123iaa, bias pads 124aa to 124ca, and a ground pad 125a, which are electrically connected to the third substrate 300 and the second substrate 200 respectively via corresponding pads.

[0097] Each front-side pad is selected from multiple first front-side pads based on the lines of the first wiring pattern layer.

[0098] Multiple front-side pads are electrically connected to multiple first back-side pads formed on the first back side of the opposing first dielectric substrate 101 via vias VIA.

[0099] like Figure 1 As shown in part, multiple first front-side pads are electrically and physically connected to multiple third back-side pads of the corresponding third substrate 300 via first connecting members 50 that are conductive, such as solder balls.

[0100] The first connecting component 50 can also use solder balls with copper cores, provided that flatness can be ensured. Alternatively, it can be a conventional conductive adhesive component such as a solder ball, copper pillar, or gold bump that does not contain a copper core, provided it meets the specified specifications.

[0101] Hereinafter, the first connecting component 50 will be described as the solder ball 50.

[0102] Solder ball 50 is a first conductive connection component that electrically connects a corresponding first front side pad among a plurality of first front side pads of the first substrate 100 to a corresponding third back side pad among a plurality of third back side pads of the third substrate 300.

[0103] A resist film 60 is formed on the front side of the first dielectric substrate 101, such as... Figure 4 As shown, it has a circular opening 60a for mounting solder balls 50, which exposes the front side of each of the input pad 121a, output pad 122a, bias pads 123aa to 123iaa, bias pads 124aa to 124caa, and ground pad 125a corresponding to the second substrate 200, and a rectangular opening 60b for mounting chip components (not shown).

[0104] The resist film 60 covers the front sides of one input pad 103a, another input pad 104a, a bias pad 109a, an output pad 110a, a bias pad 111a, and a bias pad 112a, preventing solder flow when mounting the solder balls 50, and enabling protection of these front side pads and uniform adhesion of the solder balls 50.

[0105] like Figure 5 As shown, the first grounding conductor 130 formed on the back side of the first dielectric substrate 101 is formed by patterning a thick copper foil, i.e., a conductor, with a thickness of 100 μm or more (200 μm in this embodiment 1) in the central part excluding the surrounding area.

[0106] The first grounding conductor 130 is electrically connected to a plurality of grounding conductors 113 formed on the front side of the first dielectric substrate 101 through a through-hole VIA indicated by the ○ mark in the figure.

[0107] In the first grounding conductor 130, a first semiconductor element 10 is mounted and fixed on the exposed surface of the first opening 102 located on the first dielectric substrate 101 via a first heat sink 10A.

[0108] The first grounding conductor 130 is a conductor of thick copper foil, so it has good heat diffusion, excellent heat dissipation for the heat generated by the first semiconductor element 10, and excellent rigidity, thus reducing the warping of the first dielectric substrate 101.

[0109] The first grounding conductor 130 is fixed to a grounding layer formed on the front side of a mounting substrate (not shown) by means of solder or the like, and is grounded through the grounding layer of the mounting substrate.

[0110] The plurality of first back side pads formed on the back side of the first dielectric substrate 101 are formed by patterning the conductor, which is a thick copper foil, along the four sides of the first dielectric substrate 101 and the first ground conductor 130.

[0111] Multiple first back side pads are respectively disposed opposite to multiple first front side pads formed on the front side, and are electrically connected to the multiple first front side pads respectively via through-holes VIA through the first dielectric substrate 101.

[0112] In addition to having an input pad 103b, another input pad 104b, an output bias pad 109b, an output pad 110b, an input bias pad 111b, another input bias pad 112b, and a ground pad 113b, the plurality of first back side pads also have an input pad 121b, an output pad 122b, bias pads 123ab to 123ib, and bias pads 124ab to 124cb corresponding to the second substrate 200, and a ground pad 125a.

[0113] Each back-side pad is electrically connected to the corresponding wiring layer formed on the front side of the mounting substrate (not shown) via solder or the like.

[0114] Because the wiring pattern layer is surrounded by multiple grounding pads 125a on the front side, multiple grounding pads 125b on the back side, and vias VIA connecting the grounding pads 125a and 125b, it becomes a structure resistant to external noise intrusion.

[0115] In addition, Figure 1 In this document, multiple first back side pads are not individually labeled. For ease of explanation, 131 is used as a general label to represent them.

[0116] The second semiconductor element 20 is a semiconductor element that generates less heat during operation than the first semiconductor element 10 during operation.

[0117] The second semiconductor element 20 is a semiconductor element with power control function.

[0118] like Figure 7 As shown, the second semiconductor element 20 is a semiconductor element having two input terminals 21, 22, an output terminal 23, and three bias terminals 24a to 24c on the front side of a semiconductor substrate.

[0119] Terminals 21-23 and 24a-24c are pads formed on the front side of the semiconductor substrate.

[0120] The third semiconductor element 30 is a semiconductor element that generates less heat during operation than the first semiconductor element 10 during operation.

[0121] The third semiconductor element 30 is a semiconductor element with driving and amplification functions.

[0122] like Figure 7 As shown, the third semiconductor element 30 is a semiconductor element having an input terminal 31, two output terminals 32 and 33 and nine bias terminals 34a to 34i on the front side of a semiconductor substrate.

[0123] Terminals 31-33 and 34a-34i are pads formed on the front side of the semiconductor substrate.

[0124] The two output terminals 32 and 33 of the third semiconductor element 30 are respectively connected to the two corresponding input terminals 21 and 22 of the second semiconductor element 20 by means of gold wire or other leads W.

[0125] like Figure 1 As shown, the second substrate 200 is equipped with a second semiconductor element 20 and a third semiconductor element 30, and has a plurality of second front-side pads arranged around the front side of the side on which the second semiconductor element 20 and the third semiconductor element 30 are mounted, and is arranged in a manner that faces each other on the front side relative to the first substrate 100.

[0126] The second substrate 200 has a second dielectric substrate 201 made of a single layer of insulating substrate, a second wiring pattern layer formed on the front side of the second dielectric substrate 201, a plurality of second front side pads formed around the front side of the second dielectric substrate 201, and a second ground conductor 230 formed of thick copper on the back side of the second dielectric substrate 201.

[0127] The second substrate 200 has a second opening 202 formed on the second dielectric substrate 201, which extends from the front side to the front side of the second ground conductor 230. In the second opening 202, a second semiconductor element 20 and a third semiconductor element 30, which are electrically connected to the lines constituting the second wiring pattern layer, are mounted and fixed on the front side of the second ground conductor 230.

[0128] The second semiconductor element 20 is mounted on the second opening 202 via the second heat sink 20A.

[0129] The back side of the second semiconductor element 20 is mounted and fixed to the second grounding conductor 230 via the second heat sink 20A, and the heat generated by the second semiconductor element 20 is dissipated via the second heat sink 20A and the second grounding conductor 230.

[0130] Similar to the second semiconductor element 20, the third semiconductor element 30 is mounted on the second opening 202 via the second heat sink 20A.

[0131] The back side of the third semiconductor element 30 is mounted and fixed to the second grounding conductor 230 via the second heat sink 20A, and the heat generated by the third semiconductor element 30 is dissipated via the second heat sink 20A and the second grounding conductor 230.

[0132] In this embodiment 1, the second dielectric substrate 201 is the same insulating substrate as the first dielectric substrate 101.

[0133] The thickness of the second dielectric substrate 201 is the same as the thickness of the first dielectric substrate 101, and is set to the thickness that reaches the manufacturing limit for forming the second opening 202.

[0134] Therefore, even in a semiconductor device in which the first substrate 100 and the second substrate 200 are stacked without the third substrate 300 shown in Embodiment 1, the thermal stress applied to the first substrate 100 and the second substrate 200 is the same when mounting using solder balls 50, thus achieving high-precision mounting and prevention of failure.

[0135] In a semiconductor device of the type in which a second substrate 200 is directly stacked on a first substrate 100, solder balls 50 respectively become connection components that electrically connect corresponding first front-side pads among a plurality of first front-side pads of the first substrate 100 and corresponding second front-side pads among a plurality of second front-side pads of the second substrate 200.

[0136] The second wiring pattern layer is made of the same material and has the same thickness as the first wiring pattern layer.

[0137] The second wiring pattern layer is formed of copper foil, i.e., conductor, with a thickness of, for example, 18um or 35um, and consists of transmission lines for transmitting signals, power supply lines for supplying power (current) from the power source, bias lines for supplying bias potential, and grounding conductors set to ground potential.

[0138] The second wiring pattern layer, through the second semiconductor element 20, the third semiconductor element 30, and chip components 40 such as chip capacitors (only a portion is shown in the figure) that are electrically connected to the lines constituting the second wiring pattern, constitutes part of a high-frequency package or high-frequency module with built-in high-frequency circuitry.

[0139] like Figure 6 and Figure 7 As shown, the second wiring pattern layer consists of input lines 203, output lines 204, nine input-side bias lines 205a to 205i, three output-side bias lines 206a to 206c, and multiple grounding conductors 207.

[0140] The input line 203 is connected to the input terminal 31 of the third semiconductor element 30 by means of a gold wire or other lead W.

[0141] The number of leads W is in Figure 7 The unit is represented by 2 wires, but the selection can be made from the perspective of input and output power and power resistance, so it can also be 1 wire or more than 3 wires.

[0142] Furthermore, while this explanation uses leads, connections utilizing other connecting components such as gold strips can also be used, provided the pad size is suitable for installation.

[0143] Input line 203 is a general term for the line from the location connected to the input terminal 31 of the third semiconductor element 30 to the input pad 203a.

[0144] The output line 204 is connected to the output terminal 23 of the second semiconductor element 20 by means of gold wire or other leads W through lead bonding.

[0145] Output line 204 is a general term for the line from the location connected to the output terminal 23 of the second semiconductor element 20 to the output pad 204a.

[0146] The input bias lines 205a to 205i are connected to the bias terminals 34a to 34i of the corresponding third semiconductor element 30 by means of lead wire W.

[0147] The bias lines 205a to 205i are collective names for the lines from the location connected to the bias terminals 34a to 34i of the corresponding third semiconductor element 30 to the bias pads 205aa to 205ia.

[0148] Furthermore, as an example, the input bias lines 205a to 205i are configured to be nine in number, matching the bias terminals 34a to 34i of the third semiconductor element 30. However, if the number of bias terminals of the third semiconductor element 30 is reduced, the number of input bias lines is reduced; if the number of bias terminals of the third semiconductor element 30 is increased, the number of input bias lines is increased.

[0149] The output bias lines 206a to 206c are connected to the bias terminals 24a to 24c of the corresponding second semiconductor element 20 by means of lead W.

[0150] Each bias line 206a to 206c is a general name for the lines from the location connected to the bias terminals 24a to 24c of the corresponding second semiconductor element 20 to the bias pads 206aa to 206ca.

[0151] Furthermore, as an example, the output bias lines 206a to 206c are configured to be three in number, matching the bias terminals 24a to 24c of the second semiconductor element 20. However, if the number of bias terminals of the second semiconductor element 20 is reduced, the number of output bias lines is reduced; if the number of bias terminals of the second semiconductor element 20 is increased, the number of output bias lines is increased.

[0152] The input line 203, the output line 204, the input side bias lines 205a to 205i, and the output side bias lines 206a to 206c are formed to a degree of non-coupling and are set to patterns that meet the required size, such as a bent shape.

[0153] like Figure 6 and Figure 7 As shown, multiple grounding conductors 207 are respectively arranged between adjacent transmission lines to prevent interference between signals between adjacent transmission lines.

[0154] exist Figure 6 In this process, multiple grounding conductors 207 are electrically connected to the second grounding conductor 230 formed on the back side of the second dielectric substrate 201 through through holes VIA marked with ○ in the grounding conductor 207.

[0155] Furthermore, among the multiple grounding conductors 207, the grounding conductor 207 that extends to the edge of the second dielectric substrate 201 and has a line width wider than the diameter of the pad is connected to the through hole VIA located on the edge of the second dielectric substrate 201. The position of the grounding conductor 207 also serves as the grounding pad 207A.

[0156] In this embodiment 1, the plurality of front-side pads formed on the front side of the second dielectric substrate 201 have 11 pads on each side formed by conductors as copper foil along the four sides of the second dielectric substrate 201 and the wiring pattern layer, output pads 204a, and bias pads 205fa to 205ia. However, the number of pads on each side is not limited to 11.

[0157] The plurality of second front-side pads disposed on the four sides of the second dielectric substrate 201 include an input pad 203a, input-side bias pads 205aa to 205eaa, output-side bias pads 206aa to 206ac, and a grounding pad 207a.

[0158] Each second front-side pad is selected from multiple front-side pads based on the lines of the second wiring pattern layer.

[0159] The grounding pads 207a are electrically connected to the second grounding conductor 230 formed on the back side of the second dielectric substrate 201 via through holes VIA penetrating the second dielectric substrate 201.

[0160] like Figure 1 As shown in part, multiple second front-side pads are electrically and physically connected to multiple third front-side pads of the corresponding third substrate 300 via conductive second connection members 70 such as solder balls.

[0161] The second connecting component 70 can also use solder balls with copper cores, provided that flatness can be ensured. Alternatively, it can be a conventional conductive adhesive component such as a solder ball, copper pillar, or gold bump that does not contain a copper core, provided it meets the specified specifications.

[0162] The second connecting component 70 will be described below as a solder ball 70.

[0163] Solder balls 70 are multiple second conductive connection components that electrically connect corresponding second front-side pads of multiple second front-side pads of the second substrate 200 to corresponding third front-side pads of multiple third front-side pads of the third substrate 300.

[0164] A resist film 80 is formed on the front side of the second dielectric substrate 201, such as... Figure 8 As shown, it has a circular opening 80a for mounting solder balls 70, which exposes all the front side pads of the plurality of front side pads formed on the front side of the second dielectric substrate 201, and a rectangular opening 80b for mounting chip components (not shown).

[0165] The second grounding conductor 230 formed on the back side of the second dielectric substrate 201 is made of the same material and has the same thickness as the first grounding conductor 130 formed on the back side of the first dielectric substrate 101.

[0166] like Figure 9 As shown, the second grounding conductor 230 is formed on the entire back side of the second dielectric substrate 201 by a thick copper foil, i.e., a conductor, with a thickness of 100 μm or more, or 200 μm in this embodiment 1.

[0167] The second grounding conductor 230 is electrically connected to a plurality of grounding conductors 207 and grounding pads 207A formed on the front side of the second dielectric substrate 201 through a through-hole VIA indicated by the ○ mark in the figure.

[0168] Similar to the first substrate 100, in the second grounding conductor 230, on the exposed surface of the second opening 202 located on the second dielectric substrate 201, a second semiconductor element 20 and a third semiconductor element 30 are mounted and fixed via a second heat sink 20A.

[0169] The second grounding conductor 230 is a conductor made of thick copper foil, so it has good heat diffusion and excellent heat dissipation for the heat generated by the second semiconductor element 20 and the third semiconductor element 30.

[0170] In addition, the second grounding conductor 230 is formed of copper foil that is thicker than that of a typical resin substrate, which has excellent rigidity and thus can reduce the warping of the second dielectric substrate 201.

[0171] The first semiconductor element 10, the first wiring pattern layer formed on the front side of the first dielectric substrate 101, the chip component 40 (only a portion is shown) which is electrically connected to the lines constituting the first wiring pattern and mounted thereon, the second semiconductor element 20, the third semiconductor element 30, the second wiring pattern layer formed on the front side of the second dielectric substrate 201, and the chip component 40 (only a portion is shown) which is electrically connected to the lines constituting the second wiring pattern and mounted thereon, constitute a part of a high-frequency package or high-frequency module with built-in high-frequency circuitry.

[0172] The first substrate 100 and the second substrate 200 have the same overall thickness, and the thickness and material of their respective constituent elements are also the same.

[0173] That is, the first dielectric substrate 101 and the second dielectric substrate 201 are made of the same material and have the same thickness, the first wiring pattern layer and the second wiring pattern layer are made of the same material and have the same thickness, and the first grounding conductor 130 and the second grounding conductor 230 are made of the same material and have the same thickness.

[0174] In addition, such as Figure 1 As shown, when the first substrate 100 and the second substrate 200 are stacked, the front side of the first substrate 100 and the front side of the second substrate 200 are arranged opposite each other, that is, the first wiring pattern layer and the second wiring pattern layer are arranged opposite each other.

[0175] like Figure 1 As shown, the third substrate 300 is disposed opposite to the front side of the first substrate 100 and the front side of the second substrate 200 between the first substrate 100 and the second substrate 200. Multiple third back-side pads are provided around the back side, and multiple third front-side pads are provided around the front side. These multiple third back-side pads are respectively disposed opposite to multiple first front-side pads formed around the front side of the first dielectric substrate 101 of the first substrate 100, and are respectively connected to the corresponding first front-side pads via solder balls 50. These multiple third front-side pads are respectively disposed opposite to multiple second front-side pads formed around the front side of the second dielectric substrate 201 of the second substrate 200, and are respectively connected to the corresponding second front-side pads via solder balls 70.

[0176] In this embodiment 1, the third substrate 300 is an interlayer substrate with a multilayer structure that relays the electrical connection between the first substrate 100 and the second substrate 200.

[0177] In this embodiment 1, the third substrate 300 is a 6-layer interposer substrate.

[0178] The front side, i.e., the top layer, of the third substrate 300 is defined as layer 1, and the back side, i.e., the bottom layer, is defined as layer 6. Layers 2 to 5 are intermediate layers, especially intermediate layers where circuits are formed and intermediate layers that serve as ground layers.

[0179] To avoid unnecessary complexity, the pattern on the front side of layer 1 of the third substrate 300, i.e., the pattern of the first layer (top layer), will be simply referred to as the layer 1 pattern. The second to sixth layers (bottom layers) will also be described using abbreviations.

[0180] The 1-layer to 6-layer patterns are formed from copper foil, i.e., conductors, with a thickness of, for example, 18um or 35um.

[0181] In addition, the insulating layer is located between adjacent patterns.

[0182] The third substrate 300 is a relay substrate that has pads in a 1-layer pattern that are respectively disposed opposite to the pads disposed in the center of the front side of the second substrate 200, namely output pads 204a and bias pads 205fa to 205ia in this embodiment 1; and has pads in a 6-layer pattern that are respectively disposed opposite to the input pads 121a, output pads 122a, bias pads 123aa to 123ia, bias pads 124aa to 124ca and ground pads 125a disposed along the edge of the front side of the first substrate 100. The corresponding pads in the 1-layer pattern and the 6-layer pattern are connected to each other.

[0183] In addition, in the third substrate 300, the first pattern is a first pad layer connected to the output pad 204a and bias pads 205fa to 205ia on the front side of the second substrate 200, the second and fifth patterns are the first wiring layer and the second wiring layer, the third and fourth patterns are the first ground layer and the second ground layer, and the sixth pattern is a second pad layer connected to the input pad 121a, output pad 122a, bias pads 123aa to 123ia and bias pads 124aa to 124ca on the front side of the first substrate 100.

[0184] use Figures 10 to 17 The patterns of each layer in the third substrate 300 are described.

[0185] like Figure 10 As shown, the first layer pattern 310 is the pattern on the front side of the third substrate 300, and is a pad layer connected to the second front side pad of the second substrate 200 through solder balls 70.

[0186] The first layer pattern 310 has input pads 311, output pads 312, bias pads 313a to 313i and bias pads 314a to 314c at positions opposite to the input pads 203a, output pads 204a, bias pads 205aa to 205ia and bias pads 206aa to 206ca formed on the front side of the second substrate 200, respectively.

[0187] Additionally, the 1st layer pattern 310 has a ground layer 315, which is a solid pattern electrically insulated from these pads, in the area excluding the input pads 311, output pads 312, bias pads 313a to 313i, and bias pads 314a to 314c.

[0188] exist Figure 10 In the middle, the grounding layer 315 is electrically connected to the grounding layer located below through a through hole VIA indicated by the ○ mark in the figure.

[0189] In addition, in the grounding layer 315, the portion connected to the through-hole VIA positioned along the four sides also serves as a grounding pad 315a.

[0190] Input pad 311 is connected via a through-hole VIA that runs from layer 1 pattern to layer 6 pattern.

[0191] Output pad 312 is connected via a through-hole VIA that runs from the 1st layer pattern to the 2nd layer pattern.

[0192] The bias pads 313a to 313e are connected in the same way as the input pads 311 via vias VIA that extend from the 1st layer pattern to the 6th layer pattern.

[0193] The bias pads 313g and 313i are similar to the output pad 312, and are connected by a through-hole VIA that runs from the first layer pattern to the second layer pattern.

[0194] The bias pads 313f and 313h are connected via vias VIA that extend from the 1st layer pattern to the 5th layer pattern.

[0195] The bias pads 314a to 314c are connected via vias VIA that extend from the 5th layer pattern to the 6th layer pattern.

[0196] The resist film 370 is formed on the front side of a single-layer pattern 310, such as... Figure 11 As shown, it has a circular opening 370a that exposes the front sides of the input pad 311, output pad 312, bias pads 313a to 313i, bias pads 314a to 314c and ground pad 315a and is used to mount the solder ball 70.

[0197] In addition, Figure 11In the diagram, there is no through-hole VIA at the location indicated by the ○ mark 316, and the ground layer 315 is not electrically connected to the 2-layer pattern at the location indicated by the ○ mark 316.

[0198] like Figure 12 As shown, the two-layer pattern 320 has a first line 321, a second line 322 and a third line 323.

[0199] In addition, the two-layer pattern 320 has a ground layer 324 that is a solid pattern electrically insulated from these through holes VIA, except for the vias VIA that are connected to the input pads 311, the bias pads 313a to 313e, 313f, 313h and the bias pads 314a to 314c respectively.

[0200] exist Figure 12 In the middle, the ground layer 324 is electrically connected to the ground layers located on the upper and lower layers through the through hole VIA indicated by the ○ mark in the figure.

[0201] In the first line 321, one end 321a is connected to the through-hole VIA of the output pad 312 connected to the 1st layer pattern 310, and the other end 321b is connected to the through-hole VIA of the output pad 362 connected to the 6th layer pattern.

[0202] In the second line 322, one end 322a is connected to the via VIA of the bias pad 313g connected to the 1st layer pattern 310, and the other end 322b is connected to the via VIA of the bias pad 363g connected to the 6th layer pattern.

[0203] In the third line 323, one end 323a is connected to the via VIA of the bias pad 313i connected to the 1st layer pattern 310, and the other end 323b is connected to the via VIA of the bias pad 363i connected to the 6th layer pattern.

[0204] like Figure 13 As shown, the 3-layer pattern 330 is a layer in which the area other than the via VIA, which is set to ground potential, is used as the ground layer 331.

[0205] exist Figure 13 In the middle, the grounding layer 331 is electrically connected to the grounding layers located on the upper and lower layers through the through hole VIA indicated by the ○ mark in the figure.

[0206] The 3-layer pattern 330 is a solid pattern electrically insulated from the following via VIA, which is a via VIA that electrically connects the input pads 311, bias pads 313a-313e, and bias pads 314a-314c in the 1-layer pattern 310 to the corresponding input pads 361, bias pads 363a-363e, and bias pads 364a-364c in the 6-layer pattern 360, respectively. The first line in the 2-layer pattern 320... The other end 321b of line 321, the other end 322b of second line 322, and the other end 323b of third line 323 are respectively electrically connected to the corresponding output pads 362 and bias pads 313g and 313i in the 6-layer pattern 360 via VIA, and the bias pads 313f and 313h in the 1-layer pattern 310 are electrically connected to one end of the corresponding fourth line and one end of the corresponding fifth line in the 5-layer pattern 350 via VIA.

[0207] like Figure 14 As shown, the 4-layer pattern 340 is a layer in which the area other than the via VIA, which is set to ground potential, is used as the ground layer 341.

[0208] exist Figure 14 In the middle, the grounding layer 341 is electrically connected to the grounding layers located on the upper and lower layers through the through hole VIA indicated by the ○ mark in the figure.

[0209] The 4-layer pattern 340 is a solid pattern with the same shape as the 3-layer pattern 330.

[0210] like Figure 15 As shown, the 5-layer pattern 350 has a fourth line 351 and a fifth line 352.

[0211] In addition, the 5-layer pattern 350, apart from the vias VIA that are connected to the input pads 361, output pads 362, bias pads 363a-363e, 363g, 363i and bias pads 364a-364c in the 6-layer pattern 360, has a ground layer 353 that is electrically insulated from these vias VIA.

[0212] exist Figure 15 In the middle, the ground layer 353 is electrically connected to the ground layers located on the upper and lower layers through the through hole VIA indicated by the ○ mark in the figure.

[0213] In the fourth line 351, one end 351a is connected to the via VIA of the bias pad 313f connected to the 1st layer pattern 310, and the other end 351b is connected to the via VIA of the bias pad 363f connected to the 6th layer pattern.

[0214] In the fifth line 352, one end 352a is connected to the via VIA of the bias pad 313h connected to the 1st layer pattern 310, and the other end 352b is connected to the via VIA of the bias pad 363h connected to the 6th layer pattern.

[0215] like Figure 16 As shown, the 6-layer pattern 360 is the pattern on the back side of the third substrate 300, and is a pad layer connected to the front side pad of the first substrate 100 through solder balls 50.

[0216] The six-layer pattern 360 has input pads 361, output pads 362, bias pads 363a to 363i, bias pads 364a to 364c, and ground pads 365 at positions opposite to the input pads 121a, output pads 122a, bias pads 123aa to 123ia, bias pads 124aa to 124ca, and ground pads 125a formed on the front side of the first substrate 100, respectively.

[0217] In addition, the 6-layer pattern 360 has a ground layer 366, which is a solid pattern electrically insulated from these pads, in the area other than the input pads 361, output pads 362, bias pads 363a to 363i, and bias pads 364a to 364c.

[0218] exist Figure 16 In the middle, the ground layer 366 is electrically connected to the upper ground layer through a through hole VIA marked with ○ in the figure.

[0219] Furthermore, in the ground layer 366, the portion connected to the via VIA positioned along the four sides also serves as a grounding pad 365. However, in positions opposite to the plurality of front-side pads of the first substrate 100, the via VIA does not serve as a grounding pad 365.

[0220] Input pad 361 is connected to via VIA of input pad 311 connected to layer 1 pattern 310.

[0221] The output pad 362 is connected to the through-hole VIA at the other end 321b of the first line 321 connected to the 2-layer pattern 320.

[0222] The bias pads 363a to 363e are connected to the vias VIA of the bias pads 313a to 313e connected to the pattern 310 in layer 1.

[0223] The bias pad 363f is connected to the via VIA at the other end 351b of the fourth line 351 connected to the 5th layer pattern 350.

[0224] The bias pad 363g is connected to the via VIA at the other end 322b of the second line 322 connected to the 2-layer pattern 320.

[0225] The bias pad 363h is connected to the via VIA at the other end 352b of the fifth line 352 connected to the 5th layer pattern 350.

[0226] The bias pad 363i is connected to the via VIA at the other end 323b of the third line 323 connected to the 2-layer pattern 320.

[0227] The bias pads 364a to 364c are connected to the vias VIA of the bias pads 314a to 314c connected to the pattern 310 of layer 1.

[0228] The resist film 380 is formed on the front side of the 6-layer pattern 360, such as Figure 17 As shown, it has a circular opening 380a that exposes the front sides of the input pad 361, output pad 362, bias pads 363a to 363i, bias pads 364a to 364c and ground pad 365 and is used to mount solder balls 50.

[0229] In addition, resist film 380 in Figure 17 The front side of the substrate 100 is covered by the ○ mark indicated by reference numeral 366, which is the position opposite to one input pad 103a, another input pad 104a, bias pad 109a, output pad 110a, bias pad 111a, and bias pad 112a.

[0230] The first lines 321 to the third lines 323 in the 2-layer pattern 320 and the fourth lines 351 and the fifth lines 352 in the 5-layer pattern 350 are respectively as follows: Figure 12 and Figure 15 As shown, the circuit is configured not as a straight line but has at least one bend, so that the first line 321 to the third line 323 and the fourth line 351 and the fifth line 352 do not interfere with each other structurally or electrically.

[0231] In the third substrate 300, as described above, the areas other than the grounding pads of the 1st layer pattern 310 and the 6th layer pattern 360, which will become the pad layers, are used as ground layers 315 and 366.

[0232] In the third substrate 300, the area of ​​the two-layer pattern 320 and the five-layer pattern 350 that will become the wiring layer, except for the vias VIA that are connected to pads other than the lines and grounding pads, will be used as the ground layer.

[0233] In the third substrate 300, the areas of the 3-layer and 4-layer patterns other than the vias VIAs connected to the pads other than the grounding pads are used as ground layers 331 and 341.

[0234] In the third substrate 300, one layer of pattern 310 to six layers of pattern 360 are formed as described above. Therefore, unnecessary coupling between the first semiconductor element 10 mounted on the first substrate 100 and the second semiconductor element 20 and the third semiconductor element 30 mounted on the second substrate 200, as well as unnecessary coupling between the first line 321 to the third line 323 in the two-layer pattern 320 and the fourth line 351 and the fifth line 352 in the five-layer pattern 350, can be achieved by wiring with the required lines without increasing the size of the third substrate 300 in the surface direction, thereby miniaturizing the semiconductor device itself.

[0235] like Figure 1 As shown, the first resin layer 400 is a resin sealing material that has a hollow portion 400C and contacts the periphery of the front side of the first substrate 100 and the periphery of the back side of the third substrate 300 to airtightly seal the hollow portion 400C.

[0236] Resin sealing materials only need to have insulating properties, such as silicone-based resin materials or epoxy-based resin materials. The resin material can be selected according to the needs.

[0237] like Figure 2 As shown, the first resin layer 400 is bonded to the resin bonding surface 400A around the front side of the first substrate 100.

[0238] The resin bonding surface 400A in the first substrate 100 is equivalent to Figure 4 The area shown is around the four sides of the resist film 60 coated on the front side of the first dielectric substrate 101 of the first substrate 100.

[0239] Therefore, according to Figure 2 It is understood that the first resin layer 400 does not cover the first semiconductor element 10 and the first wiring pattern layer constituting transmission lines, etc., formed on the front side of the first dielectric substrate 101.

[0240] The fact that the first resin layer 400 does not cover the first wiring pattern layer does not mean that it does not cover the first wiring pattern layer at all. As long as the impedance of the circuit constituting the first wiring pattern layer is within the design margin, it is included in the range that can be slightly covered.

[0241] The first resin layer 400 is formed to at least not cover the first semiconductor element 10 and the first transmission line 106 to the third transmission line 108.

[0242] like Figure 16As shown, the first resin layer 400 is bonded to the resin bonding surface 400B around the back side of the third substrate 300.

[0243] The resin bonding surface 400B in the third substrate 300 becomes the region opposite to the resin bonding surface 400A in the first substrate 100.

[0244] The first resin layer 400 is a rectangular frame structure having a rectangular hollow portion 400C as a space to be hermetically sealed between the front side of the first substrate 100 and the back side of the third substrate 300.

[0245] Therefore, the first semiconductor element 10 is installed in a hermetically sealed hollow portion 400°C, thus isolating it from external gases and improving the environmental resistance of the first semiconductor element 10. That is, it can mitigate the effects of high humidity and high temperature air, which are causes of amplifier degradation when used as an amplifier.

[0246] Furthermore, although a first resin layer 400 with a relatively large relative permittivity of 1 relative to air, such as 3, is used, since the first resin layer 400 does not cover the first semiconductor element 10 and the first wiring pattern layer formed on the front side of the first dielectric substrate 101, there is no concern about the change in characteristic impedance caused by the effect of wavelength shortening or the decrease in gain and efficiency of the amplifier caused by the increase in dielectric loss due to the dielectric loss tangent, and the ultra-wideband capability of the amplifier can be maintained.

[0247] Furthermore, since the first resin layer 400 functions as an adhesive between the first substrate 100 and the third substrate 300, the bonding area between the first substrate 100 and the third substrate 300 is increased, and it is strengthened even under external vibration and impact, thus improving its impact resistance.

[0248] like Figure 1 As shown, the second resin layer 500 is a resin sealing material that has a hollow portion 500C and contacts the periphery of the front side of the second substrate 200 and the periphery of the front side of the third substrate 300 to airtightly seal the hollow portion 500C.

[0249] Resin sealing materials only need to have insulating properties, such as silicone-based resin materials or epoxy-based resin materials. The resin material can be selected according to the needs.

[0250] like Figure 6 As shown, the second resin layer 500 is bonded to the resin bonding surface 500A around the front side of the second substrate 200.

[0251] The resin bonding surface 500A around the front side of the second substrate 200 is equivalent to Figure 8The area shown is around the four sides of the resist film 80 coated on the front side of the second dielectric substrate 201 of the second substrate 200.

[0252] Therefore, according to Figure 6 It is understood that the second resin layer 500 does not cover the second semiconductor element 20 and the third semiconductor element 30, nor the second wiring pattern layer forming the circuit on the front side of the second dielectric substrate 201.

[0253] The fact that the second resin layer 500 does not cover the second wiring pattern layer does not mean that it does not cover the second wiring pattern layer at all. As long as the impedance of the circuit constituting the second wiring pattern layer is within the design margin, it is included in the range that can be slightly covered.

[0254] like Figure 10 As shown, the second resin layer 500 is bonded to the resin bonding surface 500B around the front side of the third substrate 300.

[0255] The resin bonding surface 500B in the third substrate 300 becomes the region opposite to the resin bonding surface 500A in the second substrate 200.

[0256] The second resin layer 500 is a rectangular frame structure having a rectangular hollow portion 500C as a space to be hermetically sealed between the front side of the second substrate 200 and the front side of the third substrate 300.

[0257] Therefore, the second semiconductor element 20 and the third semiconductor element 30 are installed in a hermetically sealed hollow section 500°C, thus isolating them from external gases and improving their environmental resistance. That is, the effects of high humidity and high temperature air, which are causes of amplifier degradation when used as an amplifier, can be mitigated.

[0258] Furthermore, although a second resin layer 500 with a relatively large relative permittivity of 1 relative to air, such as 3, is used, since the second resin layer 500 does not cover the second semiconductor element 20 and the third semiconductor element 30 and the second wiring pattern layer formed on the front side of the second dielectric substrate 201, there is no concern about the change in characteristic impedance caused by the effect of wavelength shortening or the decrease in gain and efficiency of the amplifier caused by the increase in dielectric loss due to the dielectric loss tangent, and the ultra-wideband capability of the amplifier can be maintained.

[0259] Furthermore, since the second resin layer 500 functions as an adhesive between the second substrate 200 and the third substrate 300, the bonding area between the second substrate 200 and the third substrate 300 is increased, and it is strengthened even under external vibration and impact, thus improving its impact resistance.

[0260] Furthermore, in a semiconductor device of the type in which a second substrate 200 is directly stacked on a first substrate 100, a resin layer is formed in direct and close contact with the resin bonding surface 400A around the front side of the first substrate 100 and the resin bonding surface 500A around the front side of the second substrate 200.

[0261] As a result, a hollow part is formed by an airtight seal of the resin layer. The first semiconductor element 10, the second semiconductor element 20 and the third semiconductor element 30 installed in the hollow part are isolated from the external gas, exhibiting excellent environmental resistance and excellent impact resistance as a semiconductor device.

[0262] Next, the assembly of the semiconductor device according to Embodiment 1, i.e., the manufacturing method of the semiconductor device, will be described.

[0263] First, a first substrate 100 on which a first semiconductor element 10 is mounted, a second substrate 200 on which a second semiconductor element 20 and a third semiconductor element 30 are mounted, and a third substrate 300 as an intermediary layer substrate is disposed opposite to the first dielectric substrate and the second dielectric substrate.

[0264] This process involves preparing the first substrate 100, the second substrate 200, and the third substrate 300.

[0265] The first substrate 100 is a substrate that has a first semiconductor element 10 mounted on a first opening 102 of a first dielectric substrate 101, a first wiring pattern layer and a first front side pad formed on the front side of the first dielectric substrate 101, necessary chip components mounted on the front side of the first dielectric substrate 101, the lead bonding between the first semiconductor element 10 and the first wiring pattern layer is terminated, and a first ground conductor 130 is formed on the back side of the first dielectric substrate 101.

[0266] The second substrate 200 is a substrate that has a second semiconductor element 20 and a third semiconductor element 30 mounted on the second opening 202 of the second dielectric substrate 201, a second wiring pattern layer and a second front side pad formed on the front side of the second dielectric substrate 201, necessary chip components mounted on the front side of the second dielectric substrate 201, the lead bonding between the second semiconductor element 20 and the third semiconductor element 30 and the second wiring pattern layer is completed, and a second ground conductor 230 is formed on the back side of the second dielectric substrate 201.

[0267] The third substrate 300 is a substrate with a multilayer structure consisting of an interposer substrate having a third back-side pad formed around the back side and a third front-side pad formed around the front side, serving as an interposer substrate for relaying the electrical connection between the first substrate 100 and the second substrate 200.

[0268] The first substrate 100, with its multiple first front-side pads exposed through the opening 60a of the resist film 60, and the third substrate 300, with its multiple third back-side pads exposed through the opening 380a of the resist film 380, are respectively positioned so that the pads are opposite each other.

[0269] Solder balls 50 are disposed between the first substrate 100 and the third substrate 300.

[0270] In this way, the back side of the third substrate 300 is facing the front side of the first substrate 100, and then the third substrate 300 is placed on the first substrate 100.

[0271] This process involves placing the third substrate 300 onto the first substrate 100 via solder balls 50.

[0272] Next, the plurality of third front-side pads of the third substrate 300 exposed through the opening 370a of the resist film 370 and the plurality of second front-side pads of the second substrate 200 exposed through the opening 80a of the resist film 80 are respectively arranged in a state where the corresponding pads are facing each other.

[0273] Solder balls 70 are disposed between the third substrate 300 and the second substrate 200.

[0274] In this way, the front side of the second substrate 200 and the front side of the third substrate 300 are facing each other, and then the second substrate 200 is placed on the third substrate 300.

[0275] This process involves placing the second substrate 200 onto the third substrate 300 via solder balls 70.

[0276] With the third substrate 300 and the second substrate 200 stacked on the front side of the first substrate 100, the solder balls 50 and 70 are melted by heating, for example, through reflow soldering. Additionally, pressure bonding is performed from the second substrate 200 side according to manufacturing precision requirements.

[0277] When solder balls 50 and 70 melt, the corresponding pads adhere to each other, the corresponding pads are electrically connected, and the third substrate 300 is placed and fixed on the first substrate 100, and the second substrate 200 is placed and fixed on the third substrate 300.

[0278] This process involves manufacturing a laminate on a first substrate 100, on which a third substrate 300 is stacked and on which a second substrate 200 is stacked.

[0279] Next, in the stacked body, such as Figure 1 As shown, resin sealing material is partially injected around the entire circumference between the first substrate 100 and the third substrate 300 from the side of the laminate to form a first resin layer 400.

[0280] This process is the process of forming the first resin layer 400.

[0281] The periphery of the front side of the first substrate 100 and the periphery of the back side of the third substrate 300 are also bonded together by the first resin layer 400.

[0282] The injection depth when the first resin layer 400 is formed is Figure 4 The area shown is around the four sides of the resist film 60 coated on the front side of the first dielectric substrate 101 of the first substrate 100.

[0283] The first resin layer 400 is configured not to cover the first semiconductor element 10 and the first wiring pattern layer forming transmission lines and the like formed on the front side of the first dielectric substrate 101.

[0284] Therefore, the first resin layer 400 is formed only around the four sides of the first dielectric substrate 101 of the first substrate 100, so most of the space between the first substrate 100 and the third substrate 300 becomes hollow.

[0285] That is, a rectangular hollow portion 400C, which is airtight and sealed by a first resin layer 400, is formed between the first substrate 100 and the third substrate 300.

[0286] Similarly, as Figure 1 As shown, a resin sealing material is partially injected around the entire circumference between the second substrate 200 and the third substrate 300 from the side of the laminate to form a second resin layer 500.

[0287] This process is the process of forming the second resin layer 500.

[0288] The periphery of the front side of the second substrate 200 and the periphery of the front side of the third substrate 300 are also bonded together by the second resin layer 500.

[0289] The injection depth when the second resin layer 500 is formed is Figure 8 The area shown is around the four sides of the resist film 80 coated on the front side of the second dielectric substrate 201 of the second substrate 200.

[0290] The second resin layer 500 is configured not to cover the second semiconductor element 20 and the third semiconductor element 30, nor the second wiring pattern layer formed on the front side of the second dielectric substrate 201.

[0291] Therefore, the second resin layer 500 is formed only around the four sides of the second dielectric substrate 201 of the second substrate 200, so that most of the space between the second substrate 200 and the third substrate 300 becomes hollow.

[0292] That is, a rectangular hollow portion 500C, which is airtight and sealed by a second resin layer 500, is formed between the second substrate 200 and the third substrate 300.

[0293] As described above, the assembly of a semiconductor device having a third substrate 300 stacked on a first substrate 100 and a second substrate 200 stacked on the third substrate 300, i.e., the manufacturing of the semiconductor device, is completed.

[0294] Furthermore, in a semiconductor device of the type in which a second substrate 200 is directly stacked on a first substrate 100, assembly and manufacturing are performed as follows.

[0295] The first substrate 100, with its plurality of first front-side pads exposed through the opening 60a of the resist film 60, and the second substrate 200, with its plurality of second front-side pads exposed through the opening 80a of the resist film 80, are respectively positioned so that the corresponding pads are facing each other.

[0296] Solder balls are disposed between the first substrate 100 and the second substrate 200, and the second substrate 200 is placed on the first substrate 100.

[0297] Next, the solder balls are melted, causing the solder pads to adhere to each other.

[0298] In this state, resin sealing material is injected circumferentially over the entire area between the first substrate 100 and the second substrate 200 to form a resin layer, thereby completing the assembly and manufacturing of the semiconductor device.

[0299] In the assembly and manufacturing of the semiconductor device according to Embodiment 1, if heating is performed when melting solder balls 50 and 70, the first substrate 100, the second substrate 200 and the third substrate 300 will each expand due to heat.

[0300] However, since the first substrate 100 and the second substrate 200 are arranged on the top and bottom, the warping of the first substrate 100, the second substrate 200 and the third substrate 300 during assembly can be reduced, thereby improving the yield and stability of the compensation performance of the semiconductor device and increasing the reliability of the semiconductor device.

[0301] Furthermore, a resin sealing material is injected from the side of the laminate between the front side of the first substrate 100 and the back side of the third substrate 300 to form a first resin layer 400 and provide a hermetically sealed hollow portion 400C. A resin sealing material is also injected from the side of the laminate between the front side of the second substrate 200 and the front side of the third substrate 300 to form a second resin layer 500 and provide a hermetically sealed hollow portion 500C. This isolates the first semiconductor element 10, the second semiconductor element 20, and the third semiconductor element 30 from external gases, thereby mitigating the effects of high humidity and high temperature air, which are causes of degradation of the amplifier constituting the semiconductor device of Embodiment 1.

[0302] Furthermore, although a first resin layer 400 and a second resin layer 500 with a relatively large relative permittivity 1 relative to air are used, the hollow portions 400C and 500C are formed. Therefore, in the amplifier constituting the semiconductor device of Embodiment 1, the first resin layer 400 and the second resin layer 500 do not cause any concern about the decrease in amplifier gain and efficiency due to the change in characteristic impedance caused by the effect of wavelength shortening or the increase in dielectric loss caused by the dielectric loss tangent. The ultra-wideband capability of the amplifier can also be maintained.

[0303] Furthermore, since the first resin layer 400 fills the area around the solder balls 50, the bonding area between the front side of the first substrate 100 and the front side of the third substrate 300 is increased. Since the second resin layer 500 fills the area around the solder balls 70, the bonding area between the front side of the second substrate 200 and the front side of the third substrate 300 is increased. Even under external vibration and impact, it is strengthened, thus improving impact resistance.

[0304] Here, each signal path will be explained. Here, the case where the semiconductor device of this embodiment 1 is mounted on a mounting substrate, such as a resin substrate, will be described.

[0305] The high-frequency input signals for each input terminal 11, 12 of the first semiconductor element 10 are supplied from the mounting substrate via the input pads 103b, 104b, via the vias VIA, input pads 103a, 104a, and input lines 103, 104 in the first substrate 100 to the input terminals 11, 12.

[0306] The high-frequency amplified signal output from the output terminals 13 and 14 of the first semiconductor element 10 is transmitted in the first transmission line 106, the second transmission line 107 and the third transmission line 108 of the first substrate 100, and is output to the mounting substrate from the output branch 105a of the output synthesis circuit 105 via the output line 110-output pad 110a-through hole VIA-output pad 110b.

[0307] The bias current for each bias terminal 15, 16 of the first semiconductor element 10 is supplied from the mounting substrate via bias pads 111b, 112b, via vias VIA, bias pads 111a, 112a, and bias lines 111, 112 in the first substrate 100 to the bias terminals 15, 16.

[0308] The bias current for the output branch 105a of the output synthesis circuit 105 is supplied from the mounting substrate through the bias pad 109b-via VIA-bias pad 109a-bias line 109 in the first substrate 100 to the output branch 105a.

[0309] Input signals for each input terminal 31 of the third semiconductor element 30 are supplied from the mounting substrate via the input pad 121b-via VIA-input pad 121-solder ball 50 in the first substrate 100, via the input pad 361-via VIA-input pad 311-solder ball 70 in the third substrate 300, and via the input pad 203a-input line 203 in the second substrate 200 to the input terminal 31.

[0310] The output signals from the output terminals 32 and 33 of the second semiconductor element 20 are output to the mounting substrate via the output line 204-output pad 204a-solder ball 70 in the second substrate 200, via the output pad 312-through hole VIA-first line 321-through hole VIA-output pad 362-solder ball 50 in the third substrate 300, and via the output pad 122a-through hole VIA-output pad in the first substrate 100.

[0311] The bias current for each bias terminal 24a to 24c of the second semiconductor element 20 is supplied to the bias terminals 24a to 24c from the mounting substrate via bias pads 124ab to 124cb in the first substrate 100, via via VIA, via bias pads 124aa to 124ca, via solder balls 50 in the third substrate 300, via bias pads 364a to 364c, via via VIA, via bias pads 314a to 314c, via solder balls 70 in the second substrate 200, via bias pads 206aa to 206ac, via bias lines 206a to 206c in the second substrate 200.

[0312] The bias current for each bias terminal 34a to 34e of the third semiconductor element 30 is supplied from the mounting substrate via bias pads 123ab to 123eb in the first substrate 100, via via VIA, bias pads 123aa to 123ea in the second substrate 200, via bias pads 363a to 363e in the third substrate 300, via via VIA, bias pads 313a to 313e in the second substrate 200, via bias pads 205aa to 205ea in the second substrate 200, and via bias lines 205a to 205e in the third substrate 300.

[0313] The bias current for the bias terminal 34f of the third semiconductor element 30 is supplied to the bias terminal 34f from the mounting substrate via the bias pad 123fb-via VIA-bias pad 123fa-solder ball 50 in the first substrate 100, via the bias pad 363f-via VIA-fourth line 351-via VIA-bias pad 313f-solder ball 70 in the third substrate 300, and via the bias pad 205fa-bias line 205f in the second substrate 200.

[0314] The bias current for the bias terminal 34g of the third semiconductor element 30 is supplied to the bias terminal 34g from the mounting substrate via the bias pad 123gb-via VIA-bias pad 123ga-solder ball 50 in the first substrate 100, via the bias pad 363g-via VIA-second line 322-via VIA-bias pad 313g-solder ball 70 in the third substrate 300, and via the bias pad 205ga-bias line 205g in the second substrate 200.

[0315] The bias current for the bias terminal 34h of the third semiconductor element 30 is supplied to the bias terminal 34g from the mounting substrate via the bias pad 123hb-via VIA-bias pad 123ha-solder ball 50 in the first substrate 100, via the bias pad 363h-via VIA-fifth line 352-via VIA-bias pad 313g-solder ball 70 in the third substrate 300, and via the bias pad 205ga-bias line 205g in the second substrate 200.

[0316] The bias current for the bias terminal 34i of the third semiconductor element 30 is supplied to the bias terminal 34g from the mounting substrate via the bias pad 123ib-via VIA-bias pad 123ia-solder ball 50 in the first substrate 100, via the bias pad 363i-via VIA-third line 323-via VIA-bias pad 313i-solder ball 70 in the third substrate 300, and via the bias pad 205ia-bias line 205i in the second substrate 200.

[0317] As described above, the semiconductor device of Embodiment 1 has the following structure.

[0318] That is, the first substrate 100 and the second substrate 200 are stacked in such a way that the third substrate 300 is sandwiched between them. A first ground conductor 130 and a second ground conductor 230 made of thick copper are formed on the back sides of the first substrate 100 and the second substrate 200, respectively. A first semiconductor element 10 is mounted and fixed to the front side of the first ground conductor 130 via a first heat sink 10A at a first opening 102 reaching the front side of the first ground conductor 130. Similarly, a second semiconductor element 20 is mounted and fixed to the front side of the second ground conductor 230 via a second heat sink 20A at a second opening 202 reaching the front side of the second ground conductor 230.

[0319] Therefore, the first grounding conductor 130 and the second grounding conductor 230 have good heat diffusion properties for the first semiconductor element 10 and the second semiconductor element 20, thus improving the heat dissipation performance of the semiconductor device.

[0320] In addition, the semiconductor device of Embodiment 1 uses solder balls 50 and solder balls 70, which are conductive materials, when assembling the first substrate 100, the second substrate 200 and the third substrate 300, and therefore heats them.

[0321] Therefore, the first substrate 100, the second substrate 200 and the third substrate 300 respectively undergo thermal expansion.

[0322] However, in Embodiment 1, the semiconductor device is formed by the same material to create a first substrate 100 and a second substrate 200, which are arranged vertically to form a stack.

[0323] Therefore, since the coefficients of thermal expansion of the first substrate 100, the second substrate 200 and the third substrate 300 are the same, the yield and stability of the compensation performance of the semiconductor device can be improved, and the reliability of the semiconductor device can be improved.

[0324] Furthermore, the semiconductor device of Embodiment 1 includes an output combining circuit 105 in the first wiring pattern layer of the first substrate 100. The output combining circuit 105 has a first transmission line 106 and a second transmission line 107 connected in series between the output branch 105a and one output terminal 13 of the first semiconductor element 10, and a third transmission line 108 connected between the output branch 105a and another output terminal 14 of the first semiconductor element 10. Therefore, without using redundant matching circuits, the ultra-wideband characteristics of the semiconductor device can be realized.

[0325] The semiconductor device of Embodiment 1 can form the output synthesis circuit 105 as a wiring pattern on the front side of the first substrate 100, thereby reducing the influence of unnecessary parasitic components and making it easier to achieve ultra-wideband characteristics.

[0326] In addition, in the semiconductor device of Embodiment 1, the third substrate 300 has a ground layer 315 and a ground layer 366 as solid patterns on the front and back sides, respectively. Therefore, these ground layers 315 and 366 function as conductive shielding parts, thereby suppressing unnecessary coupling between the first semiconductor element 10 and the second semiconductor element 20 and the third semiconductor element 30.

[0327] Furthermore, in the semiconductor device of Embodiment 1, the various wirings of the third substrate 300 are constructed using the inner layer wirings of the third substrate 300, namely, two-layer patterns 320 to five-layer patterns 350, thereby suppressing the coupling of these various wirings with the various wirings formed on the first substrate 100 and the second substrate 200.

[0328] Therefore, the semiconductor device of Embodiment 1 can be formed into a stacked package by stacking the first substrate 100 and the second substrate 200 in a manner that sandwiches the third substrate 300, thereby improving the reliability of the circuit.

[0329] Furthermore, by utilizing the inner layer wiring of the third substrate 300, the semiconductor device of Embodiment 1 can arrange a portion of the wiring that needs to be formed on the first substrate 100 and the second substrate 200 in the inner layer of the third substrate 300. Therefore, the necessary wiring can be performed without increasing the size of the semiconductor device in the surface direction, and the miniaturization of the semiconductor device itself can be achieved.

[0330] In addition, the semiconductor device of Embodiment 1 has a first resin layer 400 disposed between the front side of the first substrate 100 and the back side of the third substrate 300, thus having a hollow portion 400C that is hermetically sealed by the four sides of the front side of the first substrate 100 and the back side of the third substrate 300, thereby improving the environmental resistance of the first semiconductor element 10.

[0331] Moreover, even under external vibration and impact, it becomes a structure reinforced by the first resin layer 400, thus improving its impact resistance.

[0332] In addition, the semiconductor device of Embodiment 1 has a second resin layer 500 disposed between the front periphery of the second substrate 200 and the front periphery of the third substrate 300, thus having a hollow portion 500C that is hermetically sealed by the four sides of the front periphery of the second substrate 200 and the front periphery of the third substrate 300, thereby improving the environmental resistance of the second semiconductor element 20 and the third semiconductor element 30.

[0333] Moreover, even under external vibration and impact, it becomes a structure reinforced by the second resin layer 500, thus improving its impact resistance.

[0334] In addition, after the semiconductor device of Embodiment 1 is assembled into a laminate by stacking the first substrate 100, the second substrate 200 and the third substrate 300 using solder balls 50 and solder balls 70, in a subsequent process, resin sealing material is injected only near the mounting portion of the solder balls 50 and solder balls 70 to form the first resin layer 400 and the second resin layer 500.

[0335] As a result, the first wiring pattern layer and the second wiring pattern layer, which are composed of various lines required to achieve the ultra-wideband capability of the amplifier, such as the first semiconductor element 10, the second semiconductor element 20, and the third semiconductor element 30 and the transmission line 106 with high impedance and long electrical length, are not coated with the resin sealing material used to form the first resin layer 400 and the second resin layer 500. Hollow portions 400C and 500C can be formed inside the first resin layer 400 and the second resin layer 500, which are rectangular frame structures.

[0336] Therefore, in the amplifier constituting the semiconductor device of Embodiment 1, the effects of wavelength shortening caused by the relative permittivity of the resin sealing material, which serves as the first resin layer 400 and the second resin layer 500, and the effects of increased dielectric loss can be mitigated, thus maintaining the characteristics of the amplifier and enabling stable operation of the amplifier even in high humidity and high temperature environments.

[0337] Furthermore, in Embodiment 1, after the semiconductor device is assembled into a laminate, in a subsequent process, resin sealing material is injected only near the mounting portions of solder balls 50 and 70 to form a first resin layer 400 and a second resin layer 500. Therefore, compared to a laminate assembled using only solder balls 50 and 70, the bonding area between the first substrate 100 and the third substrate 300, as well as the bonding area between the second substrate 200 and the third substrate 300, are increased. As a result, the device is strengthened against external vibrations and other impacts, and its impact resistance is improved.

[0338] Furthermore, in the semiconductor device of Embodiment 1, a first semiconductor element 10 is mounted on the first substrate 100, but other semiconductor elements may also be mounted according to the required function.

[0339] In addition, a second semiconductor element 20 and a third semiconductor element 30 are mounted on the second substrate 200, but other semiconductor elements may also be mounted according to the required functions.

[0340] Alternatively, in the semiconductor device of Embodiment 1, a portion of the first transmission lines 106 to the third transmission lines 108 may be formed on the third substrate 300, and the first transmission lines 106 to the third transmission lines 108 constitute the output synthesis circuit 105 formed on the front side of the first dielectric substrate 101 of the first substrate 100.

[0341] In addition, in the semiconductor device of Embodiment 1, the line-based wiring in the third substrate 300 is line-based wiring for both the second semiconductor element 20 and the third semiconductor element 30, but it can also be line-based wiring for either the second semiconductor element 20 or the third semiconductor element 30.

[0342] Furthermore, in the semiconductor device of Embodiment 1, the insulating materials constituting the first dielectric substrate 101 in the first substrate 100, the second dielectric substrate 201 in the second substrate 200, and the third substrate 300 can be selected from materials such as resin or ceramic depending on the application.

[0343] By selecting resin as the insulating material, relatively inexpensive semiconductor devices can be obtained.

[0344] By selecting ceramics as the insulating material, high-precision patterns can be formed, and effects such as improved heat dissipation can be achieved.

[0345] If the same material is used as the insulating material for the first dielectric substrate 101 in the first substrate 100, the second dielectric substrate 201 in the second substrate 200, and the third substrate 300, the reliability is improved.

[0346] Implementation method 2.

[0347] based on Figure 18 The semiconductor device of Embodiment 2 will be described.

[0348] The semiconductor device of Embodiment 1 is configured such that a first substrate 100 is mounted and fixed on a mounting substrate, and a third substrate 300 and a second substrate 200 are stacked in sequence. In contrast, the semiconductor device of Embodiment 2 is configured such that a second substrate 200 is mounted and fixed on a mounting substrate, and a third substrate 300 and a first substrate 100 are stacked in sequence.

[0349] The first substrate 100, the second substrate 200, and the third substrate 300 in the semiconductor device of Embodiment 2 have the same basic structure as the first substrate 100, the second substrate 200, and the third substrate 300 in the semiconductor device of Embodiment 1, so the description will focus on the differences.

[0350] In addition, Figure 18 In, withFigure 1 The same labels in the same way indicate the same or equivalent parts.

[0351] The first substrate 100 does not have the plurality of first back side pads 131 as in Embodiment 1, and has a first ground conductor 130 formed by patterning a thick copper foil, i.e. a conductor, with a thickness of 100 μm or more, or 200 μm in Embodiment 2, on the entire back side of the first dielectric substrate 101.

[0352] The first grounding conductor 130 is connected to the grounding pad 125a formed on the front side of the first dielectric substrate 101 via a through-hole VIA.

[0353] By forming the first grounding conductor 130 on the entire back side of the first dielectric substrate 101, the heat dissipation area of ​​the first semiconductor element 10, which generates a lot of heat, can be increased.

[0354] The first substrate 100 does not have the through-hole VIA shown in Embodiment 1 on the first front side pads other than the grounding pad 125a.

[0355] The structure of the first substrate 100 is otherwise the same as that of the first substrate 100 in Embodiment 1.

[0356] The second substrate 200 has a plurality of second back side pads 231 formed by patterning a conductor, which is a thick copper foil, along the four sides of the back side of the second dielectric substrate 201 and the second ground conductor 230.

[0357] The plurality of second back side pads 231 are pads corresponding to the plurality of first back side pads 131 of the first substrate 100 in Embodiment 1.

[0358] That is, as a plurality of first back side pads 131 in the first substrate 100, an input pad 103b, another input pad 104b, an output side bias pad 109b, an output pad 110b, an input side bias pad 111b, another input side bias pad 112b, a ground pad 113b, an input pad 121b, an output pad 122b, bias pads 123ab to 123ib and bias pads 124ab to 124cb, and a ground pad 125a, and the pads corresponding to them are formed along the four sides of the back side of the second dielectric substrate 201 in the same configuration.

[0359] In addition, along the four sides of the front side of the second dielectric substrate 201, the second substrate 200 has a plurality of second front side pads corresponding to the plurality of second back side pads 231, and the corresponding pads of the plurality of second back side pads 231 and the plurality of second front side pads are electrically connected to each other through vias VIA.

[0360] In the second substrate 200, the front surfaces of the input pad 203a, the input bias pads 205aa to 205eaa, and the output bias pads 206aa to 206ac formed on the front surface of the second dielectric substrate 201 are covered by a resist film 80. The front surfaces of the other plurality of second front surface pads are exposed through the circular openings 80a of the resist film 80 and solder balls 70 are mounted thereon.

[0361] The structure of the second substrate 200 is otherwise the same as that of the second substrate 200 in Embodiment 1.

[0362] like Figure 18 As shown, the third substrate 300 is a multilayer interposer substrate, which is disposed opposite to the first substrate 100 and the second substrate 200 between the second substrate 200 and the first substrate 100. On the front side, it has a plurality of third front side pads that are respectively connected to a plurality of second front side pads of the second substrate 200 by solder balls 70, and on the back side, it has a plurality of third back side pads that are respectively connected to a plurality of first front side pads of the first substrate 100 by solder balls 50.

[0363] The third substrate 300 is a substrate that relays the electrical connection between the front-side pads disposed in the center of the second substrate 200 (output pads 204a and bias pads 205fa to 205ia in this embodiment 2) and the second front-side pads disposed on the edge of the second substrate 200 (output pads 122b and bias pads 123fb to 123ib in this embodiment 2) and the front-side pads (hereinafter referred to as output pads 222 and bias pads 223f to 223i) corresponding to the output pads 122b and bias pads 123fb to 123ib in the first substrate 100, respectively.

[0364] In this embodiment 2, the third substrate 300 is a 6-layer interlayer substrate.

[0365] The third substrate 300 will be described with the front side (bottom layer) set as layer 1 and the back side (top layer) set as layer 6.

[0366] In the following description, since the layer patterns are the same as those in Embodiment 1, the description will be provided without the use of accompanying drawings. Furthermore, reference numerals are used for distinction.

[0367] The first layer pattern 310 is the pattern on the front side of the third substrate 300, and is a pad layer connected to the front side pad of the second substrate 200 through solder balls 70.

[0368] The 1st layer pattern 310 is similar to the 1st layer pattern 310 in Embodiment 1, having pads corresponding to the front side pads formed on the front side of the second substrate 200, and a ground layer 315 as a solid pattern.

[0369] The two-layer pattern 320 is similar to the two-layer pattern 320 in Embodiment 1, having a first line 321, a second line 322, a third line 323, and a ground layer 324 as a solid pattern.

[0370] In the first line 321, one end is connected to a through-hole VIA of an output pad 312 disposed in the center of the 1st layer pattern 310, and the other end is connected to a through-hole VIA of an output pad 362 disposed at the edge of the 6th layer pattern.

[0371] In the second line 322, one end is connected to a via VIA of a bias pad 313g disposed in the center of the 1st layer pattern 310, and the other end is connected to a via VIA of a bias pad 363g disposed at the edge of the 6th layer pattern.

[0372] In the third line 323, one end is connected to a via VIA of a bias pad 313i disposed in the center of the 1st layer pattern 310, and the other end is connected to a via VIA of a bias pad 363i disposed in the edge of the 6th layer pattern.

[0373] The 3-layer pattern 330 and the 4-layer pattern 340 are the same as the 3-layer pattern 330 and the 4-layer pattern 340 in Embodiment 1, respectively serving as ground layer 331 and ground layer 341 as solid patterns.

[0374] The 5-layer pattern 350 is similar to the 5-layer pattern 350 in Embodiment 1, having a fourth line 351 and a fifth line 352, and a ground layer 353 as a solid pattern.

[0375] In the fourth line 351, one end is connected to a via VIA of a bias pad 313f disposed in the center of the 1st layer pattern 310, and the other end is connected to a via VIA of a bias pad 363f disposed at the edge of the 6th layer pattern.

[0376] In the fifth line 352, one end is connected to a via VIA of a bias pad 313h disposed in the center of the 1st layer pattern 310, and the other end is connected to a via VIA of a bias pad 363h disposed at the edge of the 6th layer pattern.

[0377] The 6-layer pattern 360 is the pattern on the back side of the third substrate 300, which is a pad layer connected to the first front side pad of the first substrate 100 through solder balls 50.

[0378] The 6-layer pattern 360 is similar to the 6-layer pattern 360 in Embodiment 1, having pads corresponding to the first front-side pads formed on the front side of the first substrate 100, and a ground layer 366 as a solid pattern.

[0379] like Figure 18 As shown, the first resin layer 400 is a resin sealing material that is in contact with the periphery of the front side of the first substrate 100 and the periphery of the back side of the third substrate 300 in such a way that it has a rectangular hollow portion 400C as an airtight sealing space, and is the same as the first resin layer 400 in Embodiment 1.

[0380] That is, the first resin layer 400 is bonded to the resin bonding surface 400A around the front side of the first substrate 100, and to the resin bonding surface 400B around the back side of the third substrate 300.

[0381] The first resin layer 400 does not cover the first semiconductor element 10 and the first wiring pattern layer constituting transmission lines, etc., formed on the front side of the first dielectric substrate 101.

[0382] like Figure 18 As shown, the second resin layer 500 is a resin sealing material that is in contact with the periphery of the front side of the second substrate 200 and the periphery of the front side of the third substrate 300 in such a way that it has a rectangular hollow portion 500C as an airtight sealing space, and is the same as the second resin layer 500 in Embodiment 1.

[0383] That is, the second resin layer 500 is bonded to the resin bonding surface 500A around the front side of the second substrate 200, and to the resin bonding surface 500B around the front side of the third substrate 300.

[0384] The second resin layer 500 does not cover the second semiconductor element 20 and the third semiconductor element 30, nor the second wiring pattern layer forming the circuit on the front side of the second dielectric substrate 201.

[0385] The semiconductor device in Embodiment 2 is configured as described above. Therefore, the input terminals 11 and 12, output terminals 13 and 14, and bias terminals 15 and 16 of the first semiconductor element 10 are connected to the first wiring pattern layer formed on the front side of the first substrate 100 via leads W. They are connected to the mounting substrate via the pads-solder balls 50 formed on the front side of the first substrate 100, via the pads-vias VIA of the 6-layer pattern 360 and the pads-solder balls 70 of the 1-layer pattern 310 in the third substrate 300, and via the front side pads-vias VIA and the back side pads in the second substrate 200.

[0386] The bias terminals 24a to 24c of the second semiconductor element 20 and the input terminals 31 and bias terminals 34a to 34 of the third semiconductor element 30 are respectively connected to the second wiring pattern layer formed on the front side of the second substrate 200 via leads W, and are connected to the mounting substrate via the front side pad-via VIA-back side pad formed on the edge of the front side of the second substrate 200.

[0387] The output terminal 23 of the second semiconductor element 20 and the bias terminals 34g and 34i of the third semiconductor element 30 are respectively connected to the second wiring pattern layer formed on the front side of the second substrate 200 via leads W. They are connected to the mounting substrate via the front side pad-solder ball 70 formed in the center of the front side of the second substrate 200, via the pad-via-first line 321, second line 322, third line 323-via-padding-solder ball 70 formed in the center of the single-layer pattern of the third substrate 300, and via the back side pad formed on the edge of the single-layer pattern.

[0388] The bias terminals 34f and 34h of the third semiconductor element 30 are connected to the second wiring pattern layer formed on the front side of the second substrate 200 via leads W. They are connected to the mounting substrate via the front side pad-solder ball 70 formed in the center of the front side of the second substrate 200, via the pad-via VIA-fourth line 351 and fifth line 352-via VIA-pad-solder ball 70 formed in the center of the single-layer pattern of the third substrate 300, and via the back side pad formed on the edge of the single-layer pattern.

[0389] The assembly of the semiconductor device in Embodiment 2, i.e. the manufacturing method of the semiconductor device, is similar to the manufacturing method in Embodiment 1. First, a first substrate 100, a second substrate 200, and a third substrate 300 are prepared.

[0390] Next, similar to the manufacturing method in Embodiment 1, with the third substrate 300 and the first substrate 100 stacked on the front side of the second substrate 200, the solder balls 50 and 70 are melted to manufacture a laminate in which the third substrate 300 is stacked on the second substrate 200 and the first substrate 100 is stacked on the third substrate 300.

[0391] Then, similarly to the manufacturing method in Embodiment 1, as... Figure 18 As shown, a second resin layer 500 is formed by partially injecting resin sealant material around the entire circumference between the second substrate 200 and the third substrate 300 from the side of the laminate, and a first resin layer 400 is formed by partially injecting resin sealant material around the entire circumference between the first substrate 100 and the third substrate 300 from the side of the laminate.

[0392] Therefore, the second resin layer 500 is formed only around the four sides of the second dielectric substrate 201 of the second substrate 200, so that most of the space between the second substrate 200 and the third substrate 300 becomes hollow.

[0393] Similarly, since the first resin layer 400 is formed only around the four sides of the first dielectric substrate 101 of the first substrate 100, most of the space between the first substrate 100 and the third substrate 300 becomes hollow.

[0394] That is, a hermetically sealed rectangular hollow portion 500C surrounded by a second resin layer 500 is formed between the second substrate 200 and the third substrate 300, and a hermetically sealed rectangular hollow portion 400C surrounded by a first resin layer 400 is formed between the first substrate 100 and the third substrate 300.

[0395] As described above, the assembly of a semiconductor device having a third substrate 300 stacked on a second substrate 200 and a first substrate 100 stacked on a third substrate 300, i.e., the manufacturing of the semiconductor device, is completed.

[0396] Therefore, similar to the semiconductor device of Embodiment 1, the first semiconductor element 10, the second semiconductor element 20 and the third semiconductor element 30 can be isolated from the external gas, thereby reducing the influence of the external gas, resulting in excellent shock resistance of the semiconductor device and suppressing the performance degradation of the semiconductor device caused by the first resin layer 400 and the second resin layer 500.

[0397] As described above, in addition to having the same effects as the semiconductor device of Embodiment 1, the semiconductor device of Embodiment 2 has good heat dissipation performance due to the large heat dissipation area on the front side of the first ground conductor 130 in the first substrate 100, thus improving the heat dissipation performance of the semiconductor device.

[0398] In addition, the first grounding conductor 130 in the first substrate 100 is solid grounded, which can increase the wiring area of ​​the first substrate 100, thus enabling further miniaturization as a semiconductor device.

[0399] Implementation method 3.

[0400] based on Figure 19 The semiconductor device of Embodiment 3 will be described.

[0401] The semiconductor device of Embodiment 3 differs from the semiconductor device of Embodiment 2 in that it has a heat sink 600 mounted on the back side of the first ground conductor 130 of the first substrate 100, but is otherwise the same.

[0402] likeFigure 19 As shown, the semiconductor device of Embodiment 3 includes a heat sink 600 with heat dissipation fins fixed to the entire back side of the first grounding conductor 130 by solder or the like.

[0403] In addition, the size of the plane of the heat sink 600 can also be larger than the plane of the back side of the first ground conductor 130.

[0404] In addition, Figure 19 In, with Figure 1 , Figure 18 The same labels in the same way indicate the same or equivalent parts.

[0405] In addition to having the same effects as the semiconductor device of Embodiment 2, the semiconductor device of Embodiment 3 can dissipate heat generated by the first semiconductor element 10 more efficiently, thus improving the heat dissipation performance of the semiconductor device.

[0406] Furthermore, the idea of ​​having a heat sink 600 on the entire back side of the first ground conductor 130 in Embodiment 3 can also be applied to the semiconductor device of Embodiment 1. In the semiconductor device of Embodiment 1, when the heat generated by the second semiconductor element 20 and the third semiconductor element 30 mounted on the second substrate 200 is large, the heat sink 600, which is fixed by solder or the like, is bonded to the entire back side of the second substrate 200.

[0407] Implementation method 4.

[0408] based on Figures 20 to 32 The semiconductor device of Embodiment 4 will be described.

[0409] In Embodiment 1, the semiconductor device has a second semiconductor element 20 and a third semiconductor element 30 mounted on the second substrate 200. In contrast, the semiconductor device in Embodiment 4 is different in that it only has a semiconductor element with power control function, namely the second semiconductor element 20. In addition, the third substrate 300 uses an interlayer substrate as a single-layer substrate, and other aspects are the same.

[0410] In addition, Figures 20 to 32 In, with Figures 1 to 17 The same labels in the text indicate the same or equivalent parts.

[0411] The semiconductor device of Embodiment 4 is a stacked semiconductor device used in high-frequency equipment such as communication devices, which is equipped with a semiconductor element 10 with high output amplification function and a semiconductor element 20 with power control function.

[0412] The semiconductor device of embodiment 4 is in particular a semiconductor device that achieves ultra-wideband performance, high reliability, and good manufacturability, capable of covering approximately the entire region of the Sub-6 frequency band.

[0413] like Figure 20 As shown, the semiconductor device of Embodiment 4 includes a first semiconductor element 10, a second semiconductor element 20, a first substrate 100, a second substrate 200, and a third substrate 300.

[0414] The first semiconductor element 10 and the second semiconductor element 20 are the same as those in Embodiment 1.

[0415] like Figures 21 to 24 As shown, the basic structure of the first substrate 100 is the same as that of the first substrate 100 in Embodiment 1.

[0416] That is, since the third semiconductor element 30 is not mounted on the second substrate 200, in the first substrate 100, the first front side pads, namely input pads 121a and bias pads 123aa to 123ia, and the first back side pads, namely input pads 121b and bias pads 123ab to 123ib, in the first substrate 100 for the third semiconductor element in Embodiment 1 are set as ground pads 125a and 125b. The first front side pads and the second back side pads, namely one input pad 141a and 141b and another input pad 142a and 142b, are used for one input terminal 21 and another input terminal 22 of the second semiconductor element 20.

[0417] The structure of the first substrate 100, except as described above, is the same as that of the first substrate 100 in Embodiment 1.

[0418] Since it does not have pads for the third semiconductor element, the first wiring pattern formed in the first wiring pattern layer on the front side of the first dielectric substrate 101 is slightly different from the first wiring pattern formed in the first wiring pattern layer on the front side of the first substrate 100 in Embodiment 1, but the functions are exactly the same.

[0419] like Figure 20 As shown, the second substrate 200 has a second dielectric substrate 201 made of a single layer of insulating substrate, a second wiring pattern layer formed on the front side of the second dielectric substrate 201 and a plurality of second front side pads, and a second ground conductor 230 made of thick copper formed on the back side of the second dielectric substrate 201. A second opening 202 is formed on the second dielectric substrate 201 that extends from the front side to the front side of the second ground conductor 230.

[0420] The second dielectric substrate 201 is the same insulating substrate as the first dielectric substrate 101.

[0421] The thickness of the second dielectric substrate 201 is the same as the thickness of the first dielectric substrate 101, and is set to the thickness that reaches the manufacturing limit for forming the second opening 202.

[0422] The second wiring pattern layer is made of the same material and has the same thickness as the first wiring pattern layer.

[0423] The second substrate 200 has a second semiconductor element 20 mounted in the second opening 202 via a second heat sink 20A.

[0424] like Figure 25 and Figure 26 As shown, the second wiring pattern layer formed on the front side of the second dielectric substrate 201 of the second substrate 200 consists of two input lines 211 and 212, an output line 204, three bias lines 206a to 206c, and a plurality of grounding conductors 207.

[0425] An input line 211 is connected to an input terminal 21 of a second semiconductor element 20 via lead wires W, such as gold wires, through lead bonding.

[0426] Another input line 212 is connected to another input terminal 22 of the second semiconductor element 20 by means of a gold wire or other lead W through lead bonding.

[0427] The number of leads W is in Figure 26 The Chinese character is represented by a unit of 2, but it can also be 1 or more than 3.

[0428] Input lines 211 and 212 are collective names for the lines from the locations connected to the respective input terminals 21 and 22 of the second semiconductor element 20 to the respective input pads 211a and 212a.

[0429] Furthermore, although this embodiment 4 is described using leads, connections using other connecting components such as gold strips can also be used as long as the pad size is suitable for installation.

[0430] The output line 204 is connected to the output terminal 23 of the second semiconductor element 20 by means of gold wire or other leads W through lead bonding.

[0431] Output line 204 is a general term for the line from the location connected to the output terminal 23 of the second semiconductor element 20 to the output pad 204a.

[0432] The bias lines 206a to 206c are connected to the bias terminals 24a to 24c of the corresponding second semiconductor element 20 by means of lead W.

[0433] Each bias line 206a to 206c is a general name for the lines from the location connected to the bias terminals 24a to 24c of the corresponding second semiconductor element 20 to the bias pads 206aa to 206ca.

[0434] The input lines 211 and 212, the output line 204, and the bias lines 206a to 206c are patterned to a degree of non-coupling and are set to patterns that meet the required size, such as bent line patterns.

[0435] like Figure 25 and Figure 26 As shown, multiple grounding conductors 207 are respectively arranged between adjacent transmission lines to prevent interference between signals between adjacent transmission lines.

[0436] exist Figure 25 In this process, multiple grounding conductors 207 are electrically connected to the second grounding conductor 230 formed on the back side of the second dielectric substrate 201 through through holes VIA marked with ○ in the grounding conductor 207.

[0437] Multiple grounding conductors 207 can each form an electric wall, thus suppressing unnecessary interference between transmission lines.

[0438] Furthermore, among the multiple grounding conductors 207, the grounding conductor 207 that extends to the edge of the second dielectric substrate 201 and has a line width wider than the diameter of the pad is connected to the through hole VIA located on the edge of the second dielectric substrate 201, and the position of the grounding conductor 207 also serves as the grounding pad 207a.

[0439] In this embodiment 4, the plurality of second front-side pads formed on the front side of the second dielectric substrate 201 have 11 pads on each side formed by patterning a conductor, which is a copper foil, along the four sides of the second dielectric substrate 201 at the same time as the wiring pattern layer. However, the number of pads on each side is not limited to 11.

[0440] The plurality of second front-side pads disposed on the four sides of the second dielectric substrate 201 include input pads 211a and 212a, output pads 204a, bias pads 206aa to 206ac, and grounding pads 207a.

[0441] Each second front-side pad is selected from multiple second front-side pads according to the lines of the second wiring pattern.

[0442] The grounding pads 207a are electrically connected to the second grounding conductor 230 formed on the back side of the second dielectric substrate 201 via through holes VIA penetrating the second dielectric substrate 201.

[0443] like Figure 20 As shown in the diagram, multiple second front-side pads are electrically and physically connected to multiple third front-side pads of the corresponding third substrate 300 via conductive second connection members 70 such as solder balls. Hereinafter, the second connection member 70 will be described as a solder ball 70.

[0444] A resist film 80 is formed on the front side of the second dielectric substrate 201, such as... Figure 27 As shown, it has a circular opening 80a for mounting solder balls 70, which exposes all the front sides of a plurality of second front-side pads formed on the front side of the second dielectric substrate 201, and a rectangular opening 80b for mounting chip components (not shown).

[0445] like Figure 28 As shown, the second grounding conductor 230 formed on the back side of the second dielectric substrate 201 is electrically connected to a plurality of grounding conductors 207 and grounding pads 207a formed on the front side of the second dielectric substrate 201 through a through-hole VIA indicated by the ○ mark in the figure.

[0446] The first substrate 100 and the second substrate 200 have the same overall thickness, and the thickness and material of their respective constituent elements are also the same. That is, the first dielectric substrate 101 and the second dielectric substrate 201 are made of the same material and have the same thickness, the first wiring pattern layer and the second wiring pattern layer are made of the same material and have the same thickness, and the first grounding conductor 130 and the second grounding conductor 230 are made of the same material and have the same thickness.

[0447] The front side of the first substrate 100, i.e. the first wiring pattern layer, and the front side of the second substrate 200, i.e. the second wiring pattern layer, are arranged opposite each other.

[0448] like Figure 20 As shown, the third substrate 300 is a single-layer interposer substrate, which is disposed opposite to the first substrate 100 and the second substrate 200 between the first substrate 100 and the second substrate 200. It has a plurality of third back side pads on the back side that are connected to a plurality of first front side pads of the first substrate 100 by solder balls 50, and a plurality of third front side pads on the front side that are connected to a plurality of second front side pads of the second substrate 200 by solder balls 70, thereby relaying the electrical connection between the first substrate 100 and the second substrate 200.

[0449] The third substrate 300 has a single-layer insulating substrate 301, a plurality of third front-side pads 317, 318, 312, 313a to 313c and a ground layer 315 formed on the front side of the insulating substrate 301, and a plurality of third back-side pads 367, 368, 362, 363a to 363c and a ground layer 365 formed on the back side of the insulating substrate 301.

[0450] like Figure 29 As shown, multiple third front-side pads 317, 318, 312, 313a to 313c are respectively disposed on the edge of the insulating substrate 301 at positions opposite to the input pads 211a and 212a, the output pad 204a, and the bias pads 206aa to 206ca of the second substrate 200, and are connected by solder balls 70.

[0451] like Figure 31 As shown, multiple third back side pads 367, 368, 362, 363a to 363c are respectively disposed on the edge of the insulating substrate 301 at positions opposite to the multiple third front side pads 317, 318, 312, 313a to 313c.

[0452] Multiple third front-side pads 317, 318, 312, 313a to 313c are each connected to the opposing pads of multiple third back-side pads 367, 368, 362, 363a to 363c via vias VIA.

[0453] Multiple third backside pads 367, 368, 362, 363a to 363c are respectively connected to one input pad 141a, another input pad 142a, an output pad 122a, and bias pads 124aa to 124ca of the opposing first substrate 100 via solder balls 50.

[0454] like Figure 29 As shown, the ground layer 315 formed on the front side of the insulating substrate 301 is a solid pattern that is electrically insulated from these pads in the area excluding the third front side pads 317, 318, 312, 313a to 313c.

[0455] exist Figure 29 In the figure, the ground layer 315 is electrically connected to the ground layer 325 formed on the front side of the insulating substrate 301 through a through hole VIA marked with ○ in the ground layer 315.

[0456] In addition, in the ground layer 315, the portion connected to the through-holes VIA positioned along the four sides of the insulating substrate 301 also serves as a grounding pad 315a.

[0457] like Figure 31As shown, the ground layer 365 formed on the back side of the insulating substrate 301 is a solid pattern that is electrically insulated from these pads in the area excluding the third back side pads 367, 368, 362, 363a to 363c.

[0458] In addition, in the ground layer 365, the portion connected to the through-holes VIA positioned along the four sides of the insulating substrate 301 also serves as a grounding pad 365a.

[0459] A resist film 370 is formed on the front side of the insulating substrate 301, such as... Figure 30 As shown, it has a circular opening 370a that exposes the front sides of the input pads 317 and 318, the output pads 312, the bias pads 313a to 313c, and the ground pad 315a and is used to mount the solder ball 70.

[0460] A resist film 380 is formed on the back side of the insulating substrate 301, such as... Figure 32 As shown, it has a circular opening 380a that exposes the front sides of the input pads 367, 368, the output pads 362, the bias pads 363a to 364c, and the ground pad 365a and is used to mount the solder ball 50.

[0461] In addition, resist film 380 in Figure 32 The front side of the substrate 100 is covered by the ○ mark indicated by reference numeral 366, which is the position opposite to one input pad 103a, another input pad 104a, bias pad 109a, output pad 110a, bias pad 111a, and bias pad 112a.

[0462] As described above, the third substrate 300 has areas other than the grounding pads on both the front and back sides of the insulating substrate 301 as grounding layers 315 and 365, thus suppressing unnecessary coupling between the first semiconductor element 10 mounted on the first substrate 100 and the second semiconductor element 20 mounted on the second substrate 200.

[0463] As a result, the semiconductor device itself can be miniaturized by stacking independent first substrate 100, third substrate 300 and second substrate 200 in the vertical direction.

[0464] like Figure 20 As shown, the first resin layer 400 is a resin sealing material that is in contact with the periphery of the front side of the first substrate 100 and the periphery of the back side of the third substrate 300 in such a way that it has a rectangular hollow portion 400C as an airtight sealing space, and is the same as the first resin layer 400 in Embodiment 1.

[0465] First resin layer 400 Figure 21The resin bonding surface 400A is shown to be bonded to the periphery of the front side of the first substrate 100, and as shown... Figure 31 The resin bonding surface 400B is shown to be bonded to the back side of the third substrate 300.

[0466] The first resin layer 400 does not cover the first semiconductor element 10 and the first wiring pattern layer constituting transmission lines, etc., formed on the front side of the first dielectric substrate 101.

[0467] like Figure 20 As shown, the second resin layer 500 is a resin sealing material that is in contact with the periphery of the front side of the second substrate 200 and the periphery of the front side of the third substrate 300 in such a way that it has a rectangular hollow portion 500C as an airtight sealing space, and is the same as the second resin layer 500 in Embodiment 1.

[0468] Second resin layer 500 Figure 25 The resin bonding surface 500A is bonded to the periphery of the front side of the second substrate 200 as shown, and as... Figure 29 The resin bonding surface 500B is shown to be bonded to the periphery of the front side of the third substrate 300.

[0469] The second resin layer 500 does not cover the second semiconductor element 20 and the third semiconductor element 30, nor the second wiring pattern layer forming the circuit on the front side of the second dielectric substrate 201.

[0470] The assembly of the semiconductor device in Embodiment 2, i.e. the manufacturing method of the semiconductor device, is similar to the manufacturing method in Embodiment 1. First, a first substrate 100, a second substrate 200, and a third substrate 300 are prepared.

[0471] Next, similar to the manufacturing method in Embodiment 1, with the third substrate 300 and the second substrate 200 stacked on the front side of the first substrate 100, the solder balls 50 and 70 are melted to manufacture a laminate in which the third substrate 300 is stacked on the first substrate 100 and the second substrate 200 is stacked on the third substrate 300.

[0472] Then, similarly to the manufacturing method in Embodiment 1, as... Figure 20 As shown, a first resin layer 400 is formed by injecting resin sealant material around the entire circumference between the first substrate 100 and the third substrate 300 from the side of the laminate, and a second resin layer 500 is formed by injecting resin sealant material around the entire circumference between the second substrate 200 and the third substrate 300 from the side of the laminate.

[0473] Therefore, the first resin layer 400 is formed only around the four sides of the first dielectric substrate 101 of the first substrate 100, so most of the space between the first substrate 100 and the third substrate 300 becomes hollow.

[0474] Similarly, since the second resin layer 500 is formed only around the four sides of the second dielectric substrate 201 of the second substrate 200, most of the space between the second substrate 200 and the third substrate 300 becomes hollow.

[0475] That is, an airtight rectangular hollow portion 400C surrounded by a first resin layer 400 is formed between the first substrate 100 and the third substrate 300, and an airtight rectangular hollow portion 500C surrounded by a second resin layer 500 is formed between the second substrate 200 and the third substrate 300.

[0476] As described above, the assembly of a semiconductor device having a third substrate 300 stacked on a first substrate 100 and a second substrate 200 stacked on the third substrate 300, i.e., the manufacturing of the semiconductor device, is completed.

[0477] Therefore, similar to the semiconductor device of Embodiment 1, the first semiconductor element 10 and the second semiconductor element 20 can be isolated from the external gas, thereby reducing the influence of the external gas, resulting in excellent shock resistance of the semiconductor device and suppressing the performance degradation of the semiconductor device caused by the first resin layer 400 and the second resin layer 500.

[0478] As described above, the semiconductor device of Embodiment 4 is similar to the semiconductor device of Embodiment 1 in that the first ground conductor 130 and the second ground conductor 230 have good heat diffusion properties for the first semiconductor element 10 and the second semiconductor element 20, thus improving the heat dissipation performance of the semiconductor device. The warpage of the first substrate 100, the second substrate 200 and the third substrate 300 is reduced, thereby improving the yield and stability of the compensation performance of the semiconductor device and improving the reliability of the semiconductor device.

[0479] In addition, the semiconductor device of Embodiment 4, like the semiconductor device of Embodiment 1, can form the output synthesis circuit 105 as a wiring pattern on the front side of the first substrate 100, thereby reducing the influence of unnecessary parasitic components and preventing the deterioration of electrical characteristics.

[0480] Furthermore, similarly to the semiconductor device in Embodiment 1, the third substrate 300 has a ground layer 315 and a ground layer 365 as solid patterns on the front and back sides of the insulating substrate 301, respectively. Therefore, unnecessary coupling between the first semiconductor element 10 and the second semiconductor element 20 can be suppressed, and the first substrate 100, the third substrate 300 and the second substrate 200 can be stacked in the vertical direction to achieve miniaturization of the semiconductor device itself.

[0481] The semiconductor device of Embodiment 4 can be formed into a stacked package by stacking the first substrate 100 and the second substrate 200 in a manner that sandwiches the third substrate 300, thereby improving the reliability of the circuit.

[0482] Furthermore, the semiconductor device of Embodiment 4 is similar to that of Embodiment 1, configured such that the front periphery of the first substrate 100 is bonded to the back periphery of the third substrate 300 by a first resin layer 400 having a hollow portion 400C, and the front periphery of the second substrate 200 is bonded to the front periphery of the third substrate 300 by a second resin layer 500 having a hollow portion 500C. Therefore, the resin sealing material forming the first resin layer 400 and the second resin layer 500 does not cover the various transmission lines, the first semiconductor element 10 and the second semiconductor element 20 formed on the first substrate 100 and the second substrate 200.

[0483] Therefore, it is possible to mitigate the deterioration of electrical properties caused by the physical properties of the resin sealing materials of the first resin layer 400 and the second resin layer 500.

[0484] Furthermore, due to the increased bonding area between the first substrate 100 and the third substrate 300, as well as between the second substrate 200 and the third substrate 300, the substrate becomes more robust against external vibrations and other impacts.

[0485] In the case where a semiconductor device constitutes an amplifier, the first resin layer 400 and the second resin layer 500 prevent the inflow of high-temperature and high-humidity air, which is one of the main causes of amplifier characteristic degradation, and improve environmental resistance.

[0486] Furthermore, in embodiments 1 to 4, the first grounding conductor 130 in the first substrate 100 and the second grounding conductor 230 in the second substrate 200 are respectively made of thick copper. However, from the viewpoint of reducing manufacturing time and cost reduction, the first grounding conductor 130 and the second grounding conductor 230 may be made of ordinary copper foil thickness, while ensuring the required manufacturability and reliability. The first dielectric substrate 101 and the second dielectric substrate 201 may be made of resin substrate or ceramic substrate with ordinary copper foil thickness.

[0487] Furthermore, as semiconductor devices of Embodiments 1 to 3, examples of broadband GaN amplifiers that switch between Doherty mode and out-of-phase mode according to each frequency are mainly shown and used in high-frequency equipment such as communications. As semiconductor devices of Embodiment 4, examples of stacked semiconductor devices that are used in high-frequency equipment such as communications and are equipped with semiconductor elements with high output amplification function and semiconductor elements with power control function are mainly shown. However, as semiconductor devices of Embodiments 1 to 4, they can also be applied to semiconductor devices such as solid-state power amplifier (SSPA) modules, antenna devices with antennas connected to the output of the high-frequency module, and array antenna modules that use multiple such high-frequency modules and are connected to multiple antennas respectively.

[0488] When the semiconductor devices of Embodiments 1 to 4 are applied to these modules, antenna devices, and array antenna devices, the miniaturization, high heat dissipation, reliability, environmental resistance, shock resistance, and ultra-wideband characteristics described in Embodiments 1 to 4 can also be obtained.

[0489] Furthermore, it is possible to freely combine the various embodiments, modify any constituent elements of the various embodiments, or omit any constituent elements in the various embodiments.

[0490] Industrial availability

[0491] The semiconductor device disclosed herein is suitable for use in the field of high-frequency equipment such as communications, and is applicable to semiconductor devices incorporating semiconductor elements as high-output amplifiers. It can be used in GaN amplifiers, solid-state semiconductor amplifiers, antenna devices using solid-state semiconductor amplifiers, and array antenna devices composed of multiple antenna devices.

[0492] Label Explanation

[0493] 10: First semiconductor element; 10A: First heat sink; 20: Second semiconductor element; 20A: Second heat sink; 30: Third semiconductor element; 40: Chip component; 50: First connecting component; 70: Second connecting component; 100: First substrate; 101: First dielectric substrate; 102: First opening; 103, 104: Input lines; 105: Output combining circuit; 1066: First transmission line; 107: Second transmission line; 108: Third transmission line; 109: Output side biasing line; 110: Output line; 111, 112: Input side biasing line; 113: grounding conductor; 130: first grounding conductor; 200: second substrate; 201: second dielectric substrate; 202: second opening; 203: input line; 204: output line; 205a~205i: input side biasing line; 206a~206c: output side biasing line; 207: grounding conductor; 230: second grounding conductor; 300: third substrate; 310~360: 1-layer pattern to 6-layer pattern; 301: insulating substrate; 400: first resin layer; 500: second resin layer; 600: heat sink.

Claims

1. A semiconductor device comprising: A first substrate on which a first semiconductor element is mounted has a plurality of first front-side pads arranged around the front side of the side on which the first semiconductor element is mounted. The second substrate has a second semiconductor element mounted thereon and has a plurality of second front-side pads arranged around the front side of the side on which the second semiconductor element is mounted, and is arranged in a manner that faces each other on the front side relative to the first substrate. A third substrate is disposed between the first substrate and the second substrate, facing the front side of the first substrate and the front side of the second substrate. It has a plurality of third back side pads around its back side, which are respectively arranged opposite to a plurality of first front side pads of the first substrate, and a plurality of third front side pads around its front side, which are respectively arranged opposite to a plurality of second front side pads of the second substrate. Multiple first connecting components electrically connect a corresponding first front-side pad among multiple first front-side pads of the first substrate to a corresponding third back-side pad among multiple third back-side pads of the third substrate. Multiple second connecting components electrically connect a corresponding second front-side pad among a plurality of second front-side pads of the second substrate to a corresponding third front-side pad among a plurality of third front-side pads of the third substrate. A first resin layer, which is in contact with the periphery of the front side of the first substrate and the periphery of the back side of the third substrate, has a hollow portion; and The second resin layer, which is in contact with the periphery of the front side of the second substrate and the periphery of the back side of the third substrate, has a hollow portion.

2. The semiconductor device according to claim 1, wherein, The first substrate has: a first dielectric substrate having the plurality of first front-side pads formed around its front side; and a first wiring pattern layer formed on the front side of the first dielectric substrate. And a first ground conductor, which is formed on the back side of the first dielectric substrate and is made of thick copper, wherein a first semiconductor element electrically connected to the lines constituting the first wiring pattern layer is mounted and fixed on the front side of the first ground conductor in a first opening extending from the front side of the first dielectric substrate to the front side of the first ground conductor. The second substrate has: a second dielectric substrate having the plurality of second front-side pads formed around its front side; and a second wiring pattern layer formed on the front side of the second dielectric substrate. And a second grounding conductor, which is formed on the back side of the second dielectric substrate and is formed of thick copper, wherein a second semiconductor element electrically connected to the lines constituting the second wiring pattern layer is mounted and fixed on the front side of the second grounding conductor in a second opening that extends from the front side of the second dielectric substrate to the front side of the second grounding conductor.

3. The semiconductor device according to claim 2, wherein, The first dielectric substrate of the first substrate and the second dielectric substrate of the second substrate are made of the same material and have the same thickness. The first wiring pattern layer formed on the front side of the first dielectric substrate and the second wiring pattern layer formed on the front side of the second dielectric substrate are made of the same material and have the same thickness. The first grounding conductor of the first substrate and the second grounding conductor of the second substrate are made of the same material and have the same thickness.

4. The semiconductor device according to claim 1, wherein, The third substrate has a ground layer as a solid pattern on both the front and back sides.

5. The semiconductor device according to any one of claims 2 to 4, wherein, The first semiconductor element is a semiconductor element with high output amplification function. The second semiconductor element is a semiconductor element with power control function. The third substrate is a dielectric substrate that relays the electrical connection between the first substrate and the second substrate.

6. The semiconductor device according to claim 5, wherein, In the second opening of the second substrate, a third semiconductor element is provided on the front side of the second ground conductor. The third semiconductor element is electrically connected to the lines constituting the second wiring pattern layer and has a driving amplification function.

7. The semiconductor device according to any one of claims 2 to 4, wherein, The first semiconductor element is a semiconductor element with high output amplification function. The second semiconductor element is a semiconductor element with power control function. The plurality of first front-side pads of the first substrate are arranged around the first dielectric substrate in a manner that surrounds the first wiring pattern. At least one of the plurality of second front-side pads of the second substrate is disposed at the center of the front side of the second dielectric substrate, and the remaining second front-side pads are disposed around the second dielectric substrate in a manner that surrounds the second wiring pattern.

8. The semiconductor device according to any one of claims 2 to 4, wherein, The first semiconductor element is a semiconductor element with high output amplification function. The second semiconductor element is a semiconductor element with power control function. At least one of the plurality of second front-side pads formed on the front side of the second dielectric substrate is disposed in the central portion of the front side of the second dielectric substrate. The third substrate is a substrate that relays the electrical connection between the second front-side pad disposed in the center of the second substrate and the second front-side pad disposed at the edge of the second substrate.

9. The semiconductor device according to any one of claims 2 to 4, wherein, The semiconductor device also has a heat sink mounted on the back side of the first ground conductor of the first substrate.

10. The semiconductor device according to any one of claims 1 to 4, wherein, The third substrate has an intermediate layer pattern between the topmost pattern on the front side having the third front side pad and the bottommost pattern on the back side having the third back side pad. The intermediate layer pattern has lines for electrically connecting the third front-side pad to the third back-side pad corresponding to the third front-side pad.

11. The semiconductor device according to claim 10, wherein, The intermediate layer pattern has a first intermediate layer pattern and a second intermediate layer pattern arranged opposite each other. It also has a third intermediate layer pattern, which is disposed opposite to the first intermediate layer pattern and the second intermediate layer pattern, and uses the area other than the vias that are set to ground potential as the ground layer.

12. The semiconductor device according to any one of claims 2 to 4, wherein, The first semiconductor element is a semiconductor element with high output amplification function. The second semiconductor element is a semiconductor element with power control function. The third back side pad of the third substrate is formed on the back side of the monolayer insulating substrate, and the third front side pad of the third substrate is formed on the front side of the monolayer insulating substrate.

13. The semiconductor device according to any one of claims 2 to 4, wherein, The first semiconductor device is a semiconductor device with high output amplification function, two output terminals, and a characteristic impedance of 100Ω. An output combining circuit is formed in the first wiring pattern layer of the first substrate. The output combining circuit has a first transmission line and a second transmission line connected in series between the output branch and one output terminal of the first semiconductor element, and a third transmission line connected between the output branch and the other output terminal of the first semiconductor element. The characteristic impedance of the first transmission line, the second transmission line, and the third transmission line is 100Ω, and the electrical length of the first transmission line, the second transmission line, and the third transmission line is 50 degrees to 90 degrees.

14. The semiconductor device according to claim 13, wherein, The first transmission line, the second transmission line, and the third transmission line are located within the hollow portion of the first resin layer.

15. The semiconductor device according to claim 13, wherein, The second semiconductor element is a semiconductor element with power control function.

16. The semiconductor device according to claim 15, wherein, The semiconductor device further includes a third semiconductor element, which is mounted and fixed to the front side of the second ground conductor of the second substrate via the second heat sink in the second opening of the second substrate, and is electrically connected to the lines constituting the second wiring pattern layer of the second substrate, and has a driving amplification function.

17. A semiconductor device comprising: A first substrate on which a first semiconductor element is mounted has a plurality of first front-side pads arranged around the front side of the side on which the first semiconductor element is mounted. The second substrate has a second semiconductor element mounted thereon and has a plurality of second front-side pads arranged around the front side of the side on which the second semiconductor element is mounted, and is arranged in a front-facing manner opposite to the first dielectric substrate. Multiple connecting components, which respectively electrically connect a corresponding first front-side pad among a plurality of first front-side pads of the first substrate to a corresponding second front-side pad among a plurality of second front-side pads of the second substrate. as well as A resin layer, which is in contact with the periphery of the front side of the first substrate and the periphery of the front side of the second substrate, has a hollow portion.

18. A method for manufacturing a semiconductor device, comprising the following steps: Prepare a first substrate, a second substrate, and a third substrate. The first substrate is on which a first semiconductor element is mounted and has a plurality of first front-side pads arranged around the front side of the side on which the first semiconductor element is mounted. The second substrate is on which a second semiconductor element is mounted and has a plurality of second front-side pads arranged around the front side of the side on which the second semiconductor element is mounted. The third substrate has a plurality of third back-side pads around the back side and a plurality of third front-side pads around the front side. The first front side pads of the first substrate and the third back side pads of the third substrate are respectively arranged in a state where the corresponding pads are facing each other, so that the front side of the third substrate is facing the front side of the first substrate, and a plurality of first connecting components are arranged, wherein the plurality of first connecting components electrically connect the corresponding pads to each other. The third front-side pads of the third substrate and the second front-side pads of the second substrate are respectively arranged in a state where the corresponding pads are facing each other, so that the front side of the second substrate is facing the front side of the third substrate, and a plurality of second connecting members are arranged, wherein the plurality of second connecting members electrically connect the corresponding pads to each other. Heating is performed with the third substrate and the second substrate stacked on the front side of the first substrate. The third substrate is placed and fixed to the first substrate by the plurality of first connecting components, and the second substrate is placed and fixed to the third substrate to manufacture a laminate. A resin sealant is partially injected around the entire circumference between the first substrate and the third substrate from the side of the laminate to form a first resin layer that is in contact with the periphery of the front side of the first substrate and the periphery of the back side of the third substrate and has a hollow portion. as well as A resin sealant is partially injected from the side of the laminate throughout the entire circumference between the second substrate and the third substrate to form a second resin layer that is in contact with the periphery of the front side of the second substrate and the periphery of the back side of the third substrate and has a hollow portion.

19. A method for manufacturing a semiconductor device, comprising the following steps: Prepare a first substrate and a second substrate. The first substrate is on which a first semiconductor element is mounted and has a plurality of first front side pads arranged around the front side of the side on which the first semiconductor element is mounted. The second substrate is on which a second semiconductor element is mounted and has a plurality of second front side pads arranged around the front side of the side on which the second semiconductor element is mounted. The first front-side pads of the first substrate and the second front-side pads of the second substrate are respectively arranged in a state where the corresponding pads are facing each other, so that the front side of the second substrate is facing the front side of the first substrate, and a plurality of connecting components are configured to electrically connect the corresponding pads to each other. The second substrate is stacked on the front side of the first substrate and heated. The second substrate is then placed and fixed to the first substrate by the plurality of connecting components to manufacture the laminate. as well as A resin sealant is partially injected from the side of the laminate throughout the entire circumference between the first substrate and the second substrate to form a resin layer that is in contact with the periphery of the front surface of the first substrate and the periphery of the front surface of the second substrate and has a hollow portion.

Images