Method and system for operating double-sided double-base bipolar junction transistor

Abstract

The invention relates to a double-sided double-base bipolar junction transistor and a method of operation. One example is a method that includes conducting a primary load current from an upper terminal of a switch assembly through a double-sided double-base bipolar junction transistor (DSDB-BJT) of the switch assembly, and then through a lower terminal of the switch assembly. The conduction may be done by: injecting charge carriers into an upper drift region of the DSDB-BJT as the main load current flows into an upper collector-emitter of the DSDB-BJT; at the same time, charge carriers are injected into a lower drift region of the DSDB-BJT when a main load current flows out of a lower collector-emitter of the DSDB-BJT.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. Patent Application No. 18 / 422,469, filed January 25, 2024, entitled "Methods and Systems of Operating a Double-Sided Double-Base Bipolar Junction Transistor," which claims the benefit of U.S. Provisional Application No. 63 / 504,464, filed May 26, 2023, also entitled "Methods and Systems of Operating a Double-Sided Double-Base Bipolar Junction Transistor." Both applications are incorporated herein by reference as if copied entirely herein. Background Technology

[0003] A double-sided double-base (DSDB) bipolar junction transistor (BJT) is a junction transistor constructed with a base and collector-emitter junction on a first side of the bulk region and separate base and collector-emitter junctions on a second side of the bulk region opposite the first side. When properly configured with an external driver, current can selectively flow through the collector-emitter junction of the DSDB-BJT in either direction, and therefore such devices are considered bidirectional devices. Summary of the Invention

[0004] At least one example is a method comprising: conducting a main load current from an upper terminal of a switching assembly through a double-sided double-base bipolar junction transistor (DSDB-BJT) of the switching assembly, and then through a lower terminal of the switching assembly. The conduction may be performed by: injecting charge carriers into an upper drift region of the DSDB-BJT as the main load current flows into the upper collector-emitter junction of the DSDB-BJT; and simultaneously injecting charge carriers into a lower drift region of the DSDB-BJT as the main load current flows out from the lower collector-emitter junction of the DSDB-BJT.

[0005] In the example method: injecting charge carriers into the upper drift region of the DSDB-BJT can include injecting an upper control current into an upper base of the DSDB-BJT; and injecting charge carriers into the lower drift region of the DSDB-BJT can include injecting a lower control current into a lower base of the DSDB-BJT. A magnitude of the upper control current can be the same as a magnitude of the lower control current. A magnitude of an upper bias voltage between the upper base and the upper collector-emitter can be different than a magnitude of a lower bias voltage between the lower base and the lower collector-emitter. The magnitude of the upper control current can be different than a magnitude of the lower control current.

[0006] Conducting the main load current can include conducting the main load current through the DSDB-BJT as a monolithic structure having a continuous drift region. Conducting the main load current can include conducting the main load current through the upper collector-emitter, then through the upper drift region, then through a metallic material joining the upper drift region to the lower drift region, and then through the lower collector-emitter.

[0007] In the example method: injecting charge carriers into the upper drift region of the DSDB-BJT can include injecting an upper control current through a metallic material joining the upper drift region to the lower drift region; and injecting charge carriers into the lower drift region of the DSDB-BJT can include injecting a lower control current through the metallic material.

[0008] Another example is a switch assembly comprising: an upper terminal, a lower terminal, and a control input; a double-sided double-base bipolar junction transistor (DSDB-BJT) defining an upper base, an upper collector-emitter, a lower base, and a lower collector-emitter; an upper main FET defining a first lead coupled to the upper terminal, a second lead coupled to the upper collector-emitter, and a gate; a lower main FET defining a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate; and a driver coupled to the control input, the gate of the upper main FET, the gate of the lower main FET, and the upper and lower bases of the DSDB-BJT. In response to an assertion of the control input, and for a first applied voltage across the upper terminal and the lower terminal, the driver can be configured to: arrange the DSDB-BJT for conduction; inject charge carriers into an upper drift region of the DSDB-BJT and concurrently inject charge carriers into a lower drift region of the DSDB-BJT; and assert the gate of the lower main FET to cause the lower main FET to conduct, such that a first load current flows from the upper terminal to the lower terminal.

[0009] In the example switch assembly, the DSDB-BJT can include the upper drift region associated with the upper collector-emitter and the lower drift region associated with the lower collector-emitter, and wherein the upper drift region is joined to the lower drift region. When a driver injects charge carriers into the upper drift region, the driver can be configured to inject an upper current into the upper base; and when a driver injects charge carriers into the lower drift region, the driver can be configured to inject a lower current into the lower base. When the driver injects charge carriers into the upper drift region, the driver can be configured to inject an upper control current through a metal layer that joins the upper drift region to the lower drift region; and when the driver injects charge carriers into the lower drift region, the driver can be configured to inject a lower control current through the metal layer.

[0010] In the example switch assembly, the DSDB-BJT can include a monolithic structure having a continuous drift region. When a driver injects charge carriers into the upper drift region, the driver can be configured to inject an upper current into the upper base; and when a driver injects charge carriers into the lower drift region, the driver can be configured to inject a lower current into the lower base.

[0011] In the example switch assembly, responsive to de-assertion of the control input, the driver can be configured to: de-assert the gate of the upper main FET to render the upper main FET non-conductive; de-assert the gate of the lower main FET to render the lower main FET non-conductive, such that no current flows from the lower collector-emitter to the lower terminal; and arrange the DSDB-BJT into a non-conductive state by coupling the upper base to the upper collector-emitter and coupling the lower base to the lower terminal.

[0012] In the example switch assembly, responsive to assertion of the control input, and for a first applied voltage across the upper terminal and the lower terminal, the driver can be further configured to assert the gate of the upper main FET to render the upper main FET conductive. BRIEF DESCRIPTION OF DRAWINGS

[0013] For a detailed description of example embodiments, reference will now be made to the accompanying drawings in which:

[0014] Figure 1 A switch assembly is shown in accordance with at least some embodiments;

[0015] Figure 2 A bidirectional switch is shown in accordance with at least some embodiments;

[0016] Figures 3A to 3F A double-sided double-base bipolar junction transistor of PNP configuration is shown in simplified form, along with example external electrical connections, to illustrate several operating states;

[0017] Figures 4A to 4G A modular double-sided double-base bipolar junction transistor of PNP configuration is shown in simplified form, along with example external electrical connections, to illustrate several operating states;

[0018] Figures 5A to 5F A modular double-sided double-base bipolar junction transistor of PNP configuration is shown in simplified form, along with example external electrical connections, to illustrate several operating states;

[0019] Figure 6 A block diagram of a driver is shown in accordance with at least some embodiments; and

[0020] Figure 7 A method is shown in accordance with at least some embodiments.

[0021] DEFINITIONS

[0022] Various terminology is used to refer to particular system components. Different companies may refer to components by different names, but it is intended that each reference made herein to a component be interpreted in light of the meaning of that component as understood by those skilled in the art. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" or "couples" is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection can be through a direct connection, or through an indirect connection via other devices and connections.

[0023] As used herein, "a," "an," and "the" refer to both the singular and plural unless the context clearly indicates otherwise. By way of example, a "processor" programmed to perform various functions refers to one processor programmed to perform each and every function, or more than one processor collectively programmed to perform each of the various functions. It is to be expressly understood that the initial mention of "[reference] herein" and later reference to "the [reference]" for the purpose of reference should not exclude the possibility that the recited reference can be plural.

[0024] When referring to a recited parameter, "about" shall mean the recited parameter plus or minus ten percent (+ / 10%) of the recited parameter.

[0025] "A assertion" shall mean forming or maintaining a first predetermined state of a Boolean signal. The Boolean signal can be asserted high or have a higher voltage, and the Boolean signal can be asserted low or have a lower voltage, as determined by the circuit designer. Similarly, "de-assertion" shall mean forming or maintaining a second predetermined state of the Boolean opposite the asserted state.

[0026] "FET" shall mean field effect transistor, such as a junction-gate FET (JFET) or a metal-oxide-silicon FET (MOSFET).

[0027] When referring to an electrically controlled switch (e.g., FET), "closed" shall mean placing the electrically controlled switch in conduction. For example, closed as used for a FET of an electrically controlled switch can mean driving the FET to a fully conductive state.

[0028] When referring to an electrically controlled switch (e.g., FET), "open" shall mean placing the electrically controlled switch in non-conduction. The presence of a leakage current shall not negate a finding that the electrically controlled switch is in a non-conductive state.

[0029] “DSDB-BJT” shall mean a double-sided double-base (DSDB) bipolar junction transistor (BJT) having a base and a collector-emitter on a first side of a drift region and a different and separate base and collector-emitter on a second side of the drift region opposite the first side. The drift region can be continuous, or the drift region can include an upper drift region associated with an upper base and an upper collector-emitter, and a lower drift region associated with a lower base and a lower collector-emitter.

[0030] A “collector-emitter” of a bipolar junction transistor shall mean the region in a bipolar junction transistor through which the main load current flows. For purposes of this specification and claims, the designation of a collector-emitter is independent of the underlying device physical structure within the bipolar junction transistor. For example, for a double-sided double-base PNP transistor, the main load current can flow from an upper P-type region through a bulk N-type drift region, and then out of a lower P-type region, and in such use the upper and lower P-type regions are considered to be collector-emitters. However, in other cases, such as described in copending and commonly assigned U.S. Application 18 / 483,939, filed October 10, 2023, and entitled “Methods and Systems of Operating a PNP Bi-Directional Double-Base Bipolar Junction Transistor,” the main load current can flow from an upper N-type region through a bulk N-type drift region, and then through a lower N-type region, and in such use the upper and lower N-type regions are considered to be collector-emitters.

[0031] A “base” of a bipolar junction transistor shall mean the region in a bipolar junction transistor through which a control current flows, the control current being different from the main load current. For purposes of this specification and claims, the designation of a base is independent of the underlying device physical structure within the bipolar junction transistor. For example, for a double-sided double-base PNP transistor, the control current can flow into an upper N-type region or a lower N-type region, and in such use the upper and lower N-type regions are considered to be bases. However, in other cases, such as described in the copending and commonly assigned U.S. Application 18 / 483,939, described above, the control current can flow into an upper P-type region or a lower P-type region, and in such use the upper and lower P-type regions are considered to be bases.

[0032] When referring to a component (e.g., upper collector-emitter, upper base), "upper" should not be interpreted to imply the recited component's position relative to gravity. Upper can be derived from the position of the device in the example figures.

[0033] When referring to a component (e.g., lower collector-emitter, lower base), "lower" should not be interpreted to imply the recited component's position relative to gravity. Lower can be derived from the position of the device in the example figures.

[0034] The terms "input" and "output" when used as nouns refer to connections (e.g., electrical, software), and should not be interpreted as verbs requiring an action to be performed. For example, a timer circuit can define a clock output. An example timer circuit can form or drive a clock signal on the clock output. In systems implemented directly in hardware (e.g., on a semiconductor substrate), these "inputs" and "outputs" define electrical connections. In systems implemented in software, these "inputs" and "outputs" define parameters that are read from or written to, respectively, by instructions implementing the functionality.

[0035] "Controller," alone or in combination, shall mean an individual circuit component, an application specific integrated circuit (ASIC), a microcontroller with control software, a reduced instruction set computer (RISC) with control software, a digital signal processor (DSP) with control software, a processor with control software, a programmable logic device (PLD), a field programmable gate array (FPGA), or a programmable system on a chip (PSOC), configured to read inputs and drive outputs in response to the inputs. DETAILED DESCRIPTION

[0036] The following discussion relates to various embodiments of the application. Although one or more of these embodiments can be preferred, the disclosed embodiments should not be construed as limiting the scope of the disclosure including the claims. In addition, one skilled in the art will appreciate that the following description has broad application and is only meant to be exemplary of any embodiments, and is not intended to limit the scope of the disclosure including the claims to these embodiments.

[0037] Various examples relate to methods and systems of operating a double-sided double-base bipolar junction transistor (DSDB-BJT). More particularly, various examples relate to driving a DSDB-BJT to reduce forward voltage drop. More particularly, various examples relate to techniques of operation to reduce forward voltage drop of a DSDB-BJT, a particular DSDB-BJT formed by joining a drift region of an upper component (along with its upper base and upper collector-emitter) to a drift region of a lower component (along with its lower base and lower collector-emitter).

[0038] Figure 1An example switch assembly 100 is shown. In particular, the example switch assembly 100 defines an upper terminal 102, a lower terminal 104, and a control input or control terminal 106. Internally, the example switch assembly 100 includes a driver 108 and a bidirectional switch 110. The driver 108 defines the control terminal 106, and the driver 108 is coupled to the bidirectional switch 110, as shown by connection 112. As discussed in more detail below, although shown as a single connection, the connection 112 represents multiple electrical connections to the bidirectional switch 110. The driver 108 controls the conduction state of the bidirectional switch 110 by arranging the voltage / current on the connection 112.

[0039] One example of a switch assembly 100 can include a single bidirectional switch 110. Another example switch assembly 100 can have two or more bidirectional switches 110, as Figure 1 A "stacked" arrangement of bidirectional switches 110 is illustrated in the middle. When there are multiple bidirectional switches 110, the bidirectional switches 110 are electrically connected in parallel to share the main load current (forward or reverse). To not overly complicate the specification, the discussion below assumes a single bidirectional switch 110. However, one of ordinary skill in the art and having the benefit of the present disclosure should understand that there can be multiple bidirectional switches, depending on the designed current carrying capability of any particular switch assembly 100.

[0040] Figure 2 A schematic diagram of an example bidirectional switch 110 is shown. In particular, the example bidirectional switch 110 comprises a DSDB-BJT 200. The example DSDB-BJT 200 defines an upper base 202, a lower base 204, an upper collector-emitter 206, and a lower collector-emitter 208. The example bidirectional switch 110 further includes a lower main FET or lower cascode FET 210 that defines a drain 212 coupled to the lower collector-emitter 208, a source 214 coupled to the lower terminal 104, a gate 216 coupled to the driver 108, and a body diode 218. Finally, the example bidirectional switch 110 includes an upper main FET or upper cascode FET 220 that defines a drain 222 coupled to the upper collector-emitter 206, a source 224 coupled to the upper terminal 102, a gate 226 coupled to the driver 108, and a body diode 228.

[0041] The driver 108 is coupled to the bidirectional switch 110 by multiple electrical connections. In Figure 2In the example of FIG. 1, the electrical connections to driver 108 can include connections to gate 226 of upper cascode FET 220, upper base 202, lower base 204, and gate 216 of lower cascode FET 210. To describe when each of these connections to driver 108 can be active, the description turns to example operation of DSDB-BJT 200.

[0042] Figures 3A to 3F A partial cross-sectional view of example DSDB-BJT 200, shown in simplified form to exhibit PNP configuration, to illustrate several operational states. In particular, Figures 3A to 3F Six example states of DSDB-BJT 200 arranged for carrying a primary load current across or through the N-type region are shown, the six states being: passive off (POFF), Figure 3A active off (AOFF), Figure 3B passive on (PON), Figure 3C active on (AON), Figure 3D substitute active on (SAON), and Figure 3E pre-off (PREOFF). In the example of FIG. 1, it is assumed that switch assembly 100 is forward-biased (e.g., upper terminal 102 is associated with higher positive polarity relative to lower terminal 104). Figure 3F Figures 3A to 3F A passive off arrangement of example DSDB-BJT 200 is shown.

[0043] Upper terminal 102 and lower terminal 104 are shown. DSDB-BJT 200 is electrically between upper terminal 102 and lower terminal 104. Upper base 202 is electrically floating by driver 108. Upper collector-emitter 206 is coupled to upper terminal 102, e.g., by upper cascode FET 220 or its body diode 228. Lower base 204 is coupled to lower terminal 104 by driver 108. Lower collector-emitter 208 is electrically floating, e.g., by lower cascode FET 210 being open and its body diode 218 being non-conductive (due to applied voltage). In the arrangement of Figure 3A Figure 3A Figure 3A In the arrangement of FIG. 1, no significant current flows through DSDB-BJT 200 because the barrier is performed by the PN junction formed between lower base 204 and drift region 304. Because the electrical arrangement can be implemented with purely passive components (e.g., diodes and resistors) and thus driver 108 need not use operating power to implement the arrangement of FIG. 1, Figure 3A Figure 3A ​​​The state of the DSDB-BJT 200 is referred to as "passive turn-off." In the passive turn-off arrangement, the DSDB-BJT 200 blocks voltage and current, and thus the non-conducting lower cascode FET 210 can experience a relatively small drain-to-source voltage (e.g., 30 V or less for 1200 V applied across the upper and lower terminals 102, 104).

[0044] Figure 3B An active turn-off arrangement of the example DSDB-BJT 200 is shown. In particular, the upper base 202 is electrically floated by the driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., by the upper cascode FET 220 or its body diode 228. The lower base 204 is coupled to the lower terminal 104 by the voltage source 300, through the driver 108. The lower collector-emitter 208 is electrically floated, e.g., by the lower cascode FET 210 being off and its body diode 218 being non-conducting (due to the applied voltage). The voltage source 300 provides a negative bias to the lower base 204 with respect to the lower collector-emitter 208. In the active turn-off arrangement, no significant current flows through the DSDB-BJT 200 because the blocking is performed by the PN junction formed between the lower base 204 and the drift region 304. Because the lower base 204 is electrically floating, the lower base 204 can be biased to a negative voltage with respect to the lower collector-emitter 208. Figure 3B In the electrical arrangement of the DSDB-BJT 200, the driver 108 uses an operating power source to implement the arrangement (e.g., to power the voltage source 300), thus Figure 3B The example state of the DSDB-BJT 200 is referred to as "active turn-off." In the active turn-off arrangement of the DSDB-BJT 200, the DSDB-BJT 200 blocks voltage and current, and thus the non-conducting lower cascode FET 210 can experience a small drain-to-source voltage (e.g., 30 V or less). Figure 3B In the active turn-off arrangement of the DSDB-BJT 200, likewise, the DSDB-BJT 200 blocks voltage and current, and thus the non-conducting lower cascode FET 210 can experience a small drain-to-source voltage (e.g., 30 V or less).

[0045] Figure 3C A passive turn-on arrangement of the example DSDB-BJT 200 is shown. In particular, the upper base 202 is electrically floated by the driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., by the upper cascode FET 220 or its body diode 228. The lower base 204 is electrically floated by the driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 by the lower cascode FET 210. In the passive turn-on arrangement, no significant current flows through the DSDB-BJT 200 because the blocking is performed by the PN junction formed between the lower base 204 and the drift region 304. Figure 3CIn the passive-on arrangement, the voltage drop across the DSDB-BJT 200 is based on the substrate resistance (e.g., for a 160-micron thick substrate, the substrate resistance is about 2 ohms). For a main load current of 30 amperes (A), in the passive-on arrangement, the DSDB-BJT 200 has a voltage drop of about 60 V measured from the upper collector-emitter 206 to the lower collector-emitter 208. Since the conducting state does not involve injecting charge carriers to lower the forward voltage drop V CEON Thus Figure 3C The example state of the DSDB-BJT 200 is referred to as "passive-on." An example demonstration of injecting charge carriers is shown in Figure 3D the active-on arrangement.

[0046] Figure 3D An active-on arrangement of the example DSDB-BJT 200 is shown, where the switch assembly 100 is likewise forward-biased. In particular, the upper base 202 is coupled to the upper terminal 102 by a voltage source 302 through the driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., through the upper cascode FET 220 or its body diode 228. The lower base 204 is electrically floating through the driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 through the lower cascode FET 210. The voltage source 302 provides a positive bias to the upper base 202 relative to the upper collector-emitter 206, and the voltage source 302 can provide any suitable bias voltage (e.g., 0.2 V to 2 V). The voltage source 302 injects charge carriers across the PN junction into the bulk substrate or drift region 304, which lowers the forward voltage drop V CEON to about 0.2 V for a main load current of 30 A.

[0047] Figure 3EAn alternative active turn-on arrangement of example DSDB-BJT 200 is shown, in which switch assembly 100 is likewise forward biased. In particular, by driver 108, upper base 202 is coupled to upper terminal 102 by voltage source 302. Upper collector-emitter 206 is coupled to upper terminal 102, e.g., by upper cascode FET 220 or its body diode 228. By driver 108, lower base 204 is coupled to lower terminal 104 by voltage source 306. Lower collector-emitter 208 is coupled to lower terminal 104 by lower cascode FET 210. Voltage source 302 provides a positive bias to upper base 202 relative to upper collector-emitter 206, and voltage source 306 provides a positive bias to lower base 204 relative to lower collector-emitter 208. Voltage source 302 injects charge carriers into drift region 304 across upper PN junction, and voltage source 306 injects charge carriers into drift region 304 across lower PN junction. Likewise, for a 30 A main load current, the injection of charge carriers results in a forward voltage drop V CEON to about 0.2 V.

[0048] Figure 3F A pre-turn-off arrangement of example DSDB-BJT 200 is shown. In particular, upper base 202 is coupled to upper terminal 102 by driver 108. Upper collector-emitter 206 is coupled to upper terminal 102, e.g., by upper cascode FET 220 or its body diode 228. Lower base 204 is coupled to lower terminal 104 by driver 108. Lower collector-emitter 208 is coupled to lower terminal 104 by lower cascode FET 210. An equivalent arrangement can be to omit the coupling of upper base 202 to upper terminal 102. In Figure 3F In the pre-turn-off arrangement of example DSDB-BJT 200, there is about 2 ohms of resistance across terminals 102 and 104. Thus, for example 30 A main load current, there is a drop of Figure 3F In the pre-turn-off arrangement of example DSDB-BJT 200, there is about 60 V drop measured from upper collector-emitter 206 to lower collector-emitter 208.

[0049] With respect to the transition of switch assembly 100 from non-conducting to conducting, example DSDB-BJT 200 can be arranged to transition from Figure 3A the passive turn-off arrangement of example 2E or Figure 3B the active turn-off arrangement of example 3E directly into Figure 3D one of the active turn-on arrangements of examples 1E or 3E without implementing an intermediate arrangement or state. Regardless, Figure 3CThe passive turn-on arrangement of FIG. 1 can be used in some cases. With respect to the transition of the switch assembly 100 from conducting to non-conducting, the example DSDB-BJT 200 can transition directly from Figure 3D the active turn-on arrangement of FIG. 2 or 3E to Figure 3B the active turn-off arrangement of FIG. 3 or Figure 3A the passive turn-off arrangement of FIG. 4 without implementing an intermediate arrangement or state. Regardless, Figure 3C the passive turn-on arrangement of FIG. 1 and Figure 3F the pre-turn-off arrangement of FIG. 5 can be used in some cases.

[0050] Figures 3A to 3F The example is for the switch assembly 100 being forward biased. However, the example DSDB-BJT 200 is a symmetric device, and now that it is understood how to control current flow through the DSDB-BJT when the switch assembly 100 is forward biased, it can be directly derived how to control current flow when the switch assembly 100 is reverse biased (i.e., the lower terminal 104 is associated with a higher positive polarity relative to the upper terminal 102). Moreover, now that it is understood the various operational states of the PNP configuration with the main load current flowing through the N-type region, one of ordinary skill in the art can derive the equivalent arrangements of the PNP arrangement and the NPN arrangement with the main load current flowing through the P-type region.

[0051] Reference is made concurrently to Figure 3D and 3E . The example DSDB-BJT 200 is shown as a monolithic structure. That is, the upper base 202 and the upper collector-emitter 206 are associated with or proximate to an upper portion of the drift region 304. Similarly, the lower base 204 and the lower collector-emitter 208 are associated with or proximate to a lower portion of the drift region 304. The example drift region 304 is a continuous structure. The example DSDB-BJT 200 can be fabricated by forming the upper base 202 and the upper collector-emitter 206 on an upper side of a wafer. The wafer is then flipped and bonded to a handle wafer, and thereafter the lower base 204 and the lower collector-emitter 208 are formed on a second side of the wafer. Having a continuous drift region 304 can mean that, for a positive polarity on the upper terminal 102, charge carrier injection (e.g., Figure 3D ) into the upper base 202 sufficiently drops Vceon that charge carrier injection (e.g., Figure 3E ) from both sides provides a small additional benefit. In other words, for a device in which the drift region 304 is continuous, charge carrier injection (e.g., Figure 3D ) into the emitter-base provides sufficient Vceon reduction in many cases, and charge carrier injection (e.g., Figure 3EFurther incremental reductions in the positive voltage drop induced can not be worth the additional component and part count added.

[0052] Referring again to Figure 3A . In Figure 3A a passively turned off arrangement and with the applied voltages shown, a depletion region is formed within the drift region 304. The amount of voltage / current blocking provided by the DSDB-BJT 200 is directly related to the thickness T of the drift region 304. For example, for a drift region 304 of about 150 microns to 160 microns in thickness, the DSDB-BJT 200 can block about 1200 V. Thus, Figure 3A a monolithic DSDB-BJT 200 can be constructed on a wafer that is initially thicker than 160 microns. Once the first side is completed and the wafer is flipped to construct the second side, the wafer can first be thinned to about 150 microns to 160 microns, and then the second side base and collector-emitter regions are formed.

[0053] However, a DSDB-BJT can be formed with a non-continuous drift region. For example, a DSDB-BJT can be fabricated by forming multiple partial components, e.g., each partial component including a base region, a collector-emitter region, and a drift region. The partial components can be diced or singulated, and then the DSDB-BJT can be formed by bonding the drift regions of two partial components.

[0054] Figures 4A to 4G A partial cross-sectional view of an example DSDB-BJT of a modular construction is shown in simplified form. Initially referring to Figure 4A , Figure 4A The example DSDB-BJT 200 includes an upper component 400 and a lower component 402. The upper component 400 defines an upper base 202, an upper collector-emitter 206, and an upper drift region 404. The upper component 400 further defines an inner P-type region 406 and an inner N-type region 408. The example DSDB-BJT 200 further includes a lower component 402. The lower component 402 defines a lower base 204, a lower collector-emitter 208, and a lower drift region 410. The lower component 402 further defines an inner P-type region 412 and an inner N-type region 414.

[0055] The upper component 400 and the lower component 402 can be constructed on the same wafer or on different wafers. After singulating the upper component 400 and the lower component 402, the DSDB-BJT 200 can be assembled by bonding the "backside" of the upper component 400 to the lower component 402. In other words, the DSDB-BJT 200 can be assembled by bonding the respective drift regions 404 and 410 of the upper component 400 and the lower component 402. Figure 4A Figure 4A ​The DSDB-BJT 200. The bonding may involve using a metallic material (e.g., solder, aluminum) to electrically and mechanically couple the upper drift region 404 to the lower drift region 410. Figure 4A In the example, metal material 416 is bonded to P-type regions 406 and 412, and metal material 418 is bonded to N-type regions 408 and 414.

[0056] Figures 4A to 4G This demonstrates seven instance states of the modularly constructed DSDB-BJT 200, arranged to carry the main load current across or through an N-type region. The seven states are: passive shutdown (…). Figure 4A ), active shutdown ( Figure 4B ), passive connection ( Figure 4C ), active connection ( Figure 4D ), First alternative active connection ( Figure 4E ), second alternative active connection ( Figure 4F ), and pre-shutdown ( Figure 4G ).exist Figures 4A to 4G In the example, it is similarly assumed that the switch assembly 100 is positively biased (i.e., the upper terminal 102 is associated with a higher positive polarity relative to the lower terminal 104).

[0057] Figure 4A This demonstrates the passive shutdown arrangement of the DSDB-BJT 200, an example of a modular construction. The upper base 202 is electrically floating via driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, for example, via an upper cascode FET 220 or its body diode 228. The lower base 204 is coupled to the lower terminal 104 via driver 108. The lower collector-emitter 208 is electrically floating, for example, with the lower cascode FET 210 off and its body diode 218 non-conductive (due to the applied voltage). Figure 4A In this arrangement, because the PN junction formed between the lower base 204 and the lower drift region 410 acts as a barrier, no significant current flows through the DSDB-BJT 200. Similarly, because the electrical arrangement can be implemented using purely passive components, therefore... Figure 4A The state is referred to as "passive shutdown". As mentioned earlier, in a passive shutdown arrangement, the DSDB-BJT 200 blocks voltage and current, and therefore the non-conductive lower cascode FET 210 may experience a relatively small drain-to-source voltage (e.g., for a 1200 V applied across the upper terminal 102 and the lower terminal 104, the drain-to-source voltage is 30 V or less).

[0058] Figure 4BAn active turn-off arrangement of the example DSDB-BJT 200 of modular construction is shown. In particular, the upper base 202 is electrically floated by the driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., by the upper cascode FET 220 or its body diode 228. The lower base 204 is coupled to the lower terminal 104 by the voltage source 300, by the driver 108. The lower collector-emitter 208 is electrically floated, e.g., by the lower cascode FET 210 being off and its body diode 218 being non-conductive (due to the applied voltage). The voltage source 300 provides a negative bias to the lower base 204 relative to the lower collector-emitter 208. Thus likewise, in the active turn-off arrangement, no significant current flows through the DSDB-BJT 200 as the PN junction formed between the lower base 204 and the lower drift region 410 performs the blocking.

[0059] Figure 4C An active turn-off arrangement of the example DSDB-BJT 200 of modular construction is shown. In particular, the upper base 202 is electrically floated by the driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., by the upper cascode FET 220 or its body diode 228. The lower base 204 is electrically floated by the driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 by the lower cascode FET 210. As the conductive state does not involve injecting charge carriers to lower the forward voltage drop V CEON Thus Figure 4C The example state is referred to as "passive turn-on." An example of charge carrier injection is shown in the active turn-on arrangement of the DSDB-BJT 200 of modular construction. Figure 4D

[0060] Figure 4D ​An active on configuration of the example DSDB-BJT 200 of the modular construction is shown, and where the switch assembly 100 is likewise forward biased. In particular, by the driver 108, the upper base 202 is coupled to the upper terminal 102 by a voltage source 302. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., by the upper cascode FET 220 or its body diode 228. The lower base 204 is electrically floating by the driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 by the lower cascode FET 210. The voltage source 302 provides a positive bias to the upper base 202 relative to the upper collector-emitter 206, and the voltage source 302 can provide any suitable bias voltage (e.g., 0.2 V to 2 V). The voltage source 302 injects charge carriers into the upper drift region 404 across the PN junction, which for a 30 A main current, reduces the forward voltage drop V CEON to about 0.2 V.

[0061] Figure 4E A first alternative active on configuration of the example DSDB-BJT 200 of the modular construction is shown, where the switch assembly 100 is likewise forward biased. In particular, by the driver 108, the upper base 202 is coupled to the upper terminal 102 by a voltage source 302. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., by the upper cascode FET 220 or its body diode 228. By the driver 108, the lower base 204 is coupled to the lower terminal 104 by a voltage source 306. The lower collector-emitter 208 is coupled to the lower terminal 104 by the lower cascode FET 210. The voltage source 302 provides a positive bias to the upper base 202 relative to the upper collector-emitter 206, and the voltage source 306 provides a positive bias to the lower base 204 relative to the lower collector-emitter 208. The voltage source 302 injects charge carriers into the upper drift region 404 across the upper PN junction, and the voltage source 306 injects charge carriers into the lower drift region 410 across the lower PN junction. The injection of charge carriers reduces the forward voltage drop V CEON drop measured from the upper collector-emitter 206 to the lower collector-emitter 208.

[0062] Figure 4FA second alternative active turn-on arrangement of the example DSDB-BJT 200 exhibiting a modular construction, where the switch assembly 100 is likewise forward biased. In particular, the internal P-type region 406 is coupled to the upper terminal 102 by the voltage source 302 through the driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., through the upper cascode FET 220 or its body diode 228. The internal P-type region 412 is coupled to the lower terminal 104 by the voltage source 306 through the driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 through the lower cascode FET 210. The voltage source 302 injects charge carriers across a PN junction into the upper drift region 404, and the voltage source 306 injects charge carriers across a PN junction in the lower drift region 410. The injection of charge carriers results in a forward voltage drop V CEON is reduced.

[0063] Figure 4G A pre-turn-off arrangement of the example DSDB-BJT 200 exhibiting a modular construction. In particular, the upper base 202 is coupled to the upper terminal 102 through the driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., through the upper cascode FET 220 or its body diode 228. The lower base 204 is coupled to the lower terminal 104 through the driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 through the lower cascode FET 210. An equivalent arrangement can be to omit the coupling of the upper base 202 to the upper terminal 102.

[0064] Here again, with respect to a transition of the switch assembly 100 from non-conductive to conductive, the example DSDB-BJT 200 can be arranged to transition from Figure 4A the passive turn-off arrangement of 2A or Figure 4B the active turn-off arrangement of 2B directly into one of Figure 4D , 4E or 4F without having to implement an intermediate arrangement or state. Regardless, Figure 4C the passive turn-on arrangement of 1A can be used in some cases. With respect to a transition of the switch assembly 100 from conductive to non-conductive, the example DSDB-BJT 200 can transition from Figure 4D , 4E or 4F directly into Figure 4B the active turn-off arrangement of 2A or Figure 4A the passive turn-off arrangement of 2B without having to implement an intermediate arrangement or state. Regardless, Figure 4C the passive turn-on arrangement of 1A and Figure 4G the pre-turn-off arrangement of 3A can be used in some cases.

[0065] Figures 4A to 4G An example is for the switch assembly 100 being forward biased. However, the modularly constructed example DSDB-BJT 200 is a symmetric device, and now that it is understood how to control current flow through the DSDB-BJT when the switch assembly 100 is forward biased, it is a straightforward matter to understand how to control current flow when the switch assembly 100 is reverse biased (i.e., the lower terminal 104 is associated with a higher positive polarity relative to the upper terminal 102).

[0066] Figures 4A to 4G The modularly constructed example DSDB-BJT 200 shown in FIG. 2 can be fabricated by forming the base and collector-emitter, then flipping the wafer and die bonding to a handle wafer, and thereafter forming the internal P-type and N-type regions (or vice versa). Once singulated, the upper component (e.g., 400) is die bonded to the lower component (e.g., 402) to form the overall DSDB-BJT 200.

[0067] Coupling the upper drift region 404 to the lower drift region 410 by the internal P-type and N-type regions can mean that charge carrier injection into either the upper drift region 404 or the lower drift region 410 causes the Vceon to drop sufficiently that charge carrier injection from both sides (e.g., 2F) provides only incremental additional benefit. In other words, for example Figure 4E or 4F) only provides incremental additional benefit. In other words, for example Figures 4A to 4G The device shown in FIG. 2, where the drift regions 404 and 410 are coupled by a PN junction, charge carrier injection into the emitter-base (e.g., 1F) provides sufficient Vceon reduction in many cases, and the incremental reduction in forward voltage drop caused by additionally injecting charge carriers into the collector-base (e.g., 2F) or by the internal P-type region 412 injecting into the lower drift region 410 (e.g., 4F) can not be worth the additional component and part count. Figure 4D Figure 4E Figure 4F

[0068] Referring to FIG. 2 concurrently Figure 4A and 4B In the passive shutdown or active shutdown arrangement of Figure 4A and 4B , a depletion region extending from the lower base 204 is formed within the drift region 410. However, due to the internal P-type and N-type regions, the depletion region formed in association with the lower base 204 can "cross" the bond into the upper drift region 404. This makes the amount of voltage / current blocking provided by the modularly constructed DSDB-BJT 200 directly related to the combined thickness (e.g., T U + T L ​​​correlation. For example, for a combined thickness of about 150 microns to 160 microns, the modularly constructed DSDB-BJT 200 can block about 1200 V.

[0069] Figures 3A to 3F The example monolithic DSDB-BJT 200 of Figures 4A to 4G The example modular DSDB-BJT 200 of Figures 4A to 4G For the components 400 and 402 of the modular DSDB-BJT 200 shown in

[0070] The amount by which a wafer can be thinned, e.g., by backside grinding, depends on the diameter of the wafer. Smaller diameter wafers can be thinned more than larger diameter wafers. For example, a six inch diameter wafer that can have an initial thickness of about 500 microns can be thinned to about 75 microns or 80 microns without significant warping. However, larger diameter wafers, e.g., eight inch or twelve inch diameter wafers, are thicker, e.g., 750 microns, to provide structural stability to the wafer itself. In most cases, it is not practical to thin larger diameter wafers because they tend to warp significantly when thinned. In other words, Figures 3A to 3F The monolithic DSDB-BJT 200 of Figures 4A to 4G The upper / lower components of the modular DSDB-BJT 200 of

[0071] Figures 5A to 5F A partial cross-sectional view of an example DSDB-BJT of a modular construction is shown in simplified form. Initially refer to Figure 5A , Figure 5A The example DSDB-BJT 200 includes an upper component 500 and a lower component 502. The upper component 500 defines the upper base 202, the upper collector-emitter 206, and an upper drift region 504. The example upper component 500 omits the upper emitter 208. Figures 4A to 4GThe embodiment includes internal P-type and N-type regions. Example DSDB-BJT 200 further includes a lower assembly 502. The lower assembly 502 defines a lower base 204, a lower collector-emitter 208, and a lower drift region 510. The lower assembly 502 is omitted. Figures 4A to 4G The internal P-type and N-type regions of the embodiment.

[0072] The upper component 500 and the lower component 502 can be constructed on the same chip or on different chips. After the upper component 500 and the lower component 502 are individualized, they can be assembled by bonding the "back side" of the upper component 500 to the lower component 502. Figure 5A The DSDB-BJT 200. In other words, it can be formed by joining the drift regions 504 and 510 of the upper component 500 and the lower component 502, respectively. Figure 5A The DSDB-BJT 200. The bonding may involve using a metallic material (e.g., solder, aluminum) to electrically and mechanically couple the upper drift region 504 to the lower drift region 510. Figure 5A In this example, metal material 516 bonds N-type drift regions 504 and 510. In other words, metal material 516 mechanically and electrically couples N-type drift regions 504 and 510. To reduce or avoid the formation of a Schottky barrier at the metal / silicon interface, in some examples, a slight N-type doping may be present on the "back side" of each component 500 and 502 adjacent to metal material 516, but doping to reduce or avoid a Schottky barrier is not explicitly shown.

[0073] Still referencing Figure 5A .exist Figure 5A In the passive shutdown arrangement and under the applied voltage shown, a depletion region extending from the lower base 204 is formed within the lower drift region 510. However, the depletion region formed in association with the lower base 204 does not "cross" the junction to reach the upper drift region 504. That is, the metal material 516 can be considered as an infinite electron supply source, and therefore the depletion region formed from the lower base 204 cannot extend through the metal material to the upper drift region 504 because of the presence of an internal P-type region. This makes the voltage / current blocking provided by the modularly constructed DSDB-BJT 200 directly related to the individual thickness T of each of the drift regions 504 and 510. For example, the thickness T of approximately 150 to 160 micrometers for the lower drift region 510. L The modularly constructed DSDB-BJT 200 can block approximately 1200 V. Similarly, but for the opposite applied polarity, for the upper drift region 504 with a thickness of approximately 150 to 160 micrometers T... UThe modularly constructed DSDB-BJT 200 can withstand approximately 1200 V. In most cases, the thickness T... U With T L The values ​​will be approximately the same; however, depending on the externally applied voltage, there may be examples where the DSDB-BJT 200 can benefit from different voltage / current blocking capabilities.

[0074] Figures 5A to 5F This demonstrates six instance states of the modularly constructed DSDB-BJT 200, arranged to carry the main load current across or through an N-type region. The six states are: passive shutdown (…). Figure 5A ), active shutdown ( Figure 5B ), passive connection ( Figure 5C ), and alternative to active connection ( Figure 5D ), active connection ( Figure 5E ), and pre-shutdown ( Figure 5F ).exist Figures 5A to 5F In the example, it is similarly assumed that the switch assembly 100 is positively biased (i.e., the upper terminal 102 is associated with a higher positive polarity relative to the lower terminal 104).

[0075] Figure 5A This demonstrates the passive shutdown arrangement of the DSDB-BJT 200, an example of a modular construction. The upper base 202 is electrically floating via driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, for example, via an upper cascode FET 220 or its body diode 228. The lower base 204 is coupled to the lower terminal 104 via driver 108. The lower collector-emitter 208 is electrically floating, for example, with the lower cascode FET 210 off and its body diode 218 non-conductive (due to the applied voltage). Figure 5A In this arrangement, because the PN junction formed between the lower base 204 and the lower drift region 510 acts as a barrier, no significant current flows through the DSDB-BJT 200. Similarly, because the electrical arrangement can be implemented using purely passive components, Figure 5A The state is referred to as “passive shutdown”. As mentioned earlier, in a passive shutdown arrangement, the DSDB-BJT200 blocks voltage and current, and therefore the non-conductive lower cascode FET 210 may experience a relatively small drain-to-source voltage (e.g., for a 1200 V applied across the upper terminal 102 and the lower terminal 104, the drain-to-source voltage is 30 V or less).

[0076] Figure 5BAn active turn-off arrangement of the example DSDB-BJT 200 of the modular construction is shown. In particular, the upper base 202 is electrically floated by the driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., by the upper cascode FET 220 or its body diode 228. The lower base 204 is coupled to the lower terminal 104 by the voltage source 300 through the driver 108. The lower collector-emitter 208 is electrically floated, e.g., by the lower cascode FET 210 being off and its body diode 218 being non-conductive (due to the applied voltage). The voltage source 300 provides a negative bias to the lower base 204 relative to the lower collector-emitter 208. Thus likewise, in the active turn-off arrangement, no significant current flows through the DSDB-BJT 200 as the PN junction formed between the lower base 204 and the lower drift region 510 performs the blocking.

[0077] Figure 5C An active turn-off arrangement of the example DSDB-BJT 200 of the modular construction is shown. In particular, the upper base 202 is electrically floated by the driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., by the upper cascode FET 220 or its body diode 228. The lower base 204 is electrically floated by the driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 by the lower cascode FET 210. As the conductive state does not involve the injection of charge carriers to lower the forward voltage drop V CEON Thus Figure 5C The example state is referred to as "passive turn-on." In the arrangement of Figure 5C The voltage drop across the DSDB-BJT 200 is based on the substrate resistance of each drift region. Thus, for example, for an upper drift region 504 that is about 160 microns thick, the upper drift region 504 can have a resistance of about two ohms, and for a lower drift region 510 that is about 160 microns thick, the lower drift region 510 can have a resistance of about two ohms, for a total resistance of about 4 ohms across the DSDB-BJT 200. Thus, for the example 30 A main load current, in the passive turn-on arrangement of Figure 5C The DSDB-BJT 200 has a drop of about 120 V measured from the upper collector-emitter 206 to the lower collector-emitter 208 in the passive turn-on arrangement of

[0078] Figure 5DAn active on configuration of example DSDB-BJT 200 is shown, with switch assembly 100 likewise forward biased. In particular, through driver 108, upper base 202 is coupled to upper terminal 102 through voltage source 302. Upper collector-emitter 206 is coupled to upper terminal 102, e.g., through upper cascode FET 220 or its body diode 228. Lower base 204 is electrically floating through driver 108. Lower collector-emitter 208 is coupled to lower terminal 104 through lower cascode FET 210. Voltage source 302 provides a positive bias to upper base 202 relative to upper collector-emitter 206, and voltage source 302 can provide any suitable bias voltage (e.g., 0.2 V to 2 V). Voltage source 302 injects charge carriers into upper drift region 504 across the PN junction, which reduces the forward voltage drop across upper drift region, but does not reduce the forward voltage drop across lower drift region 510, as the charge carriers formed at the PN junction cannot traverse metal material 516. For the main load current of example 30A, the voltage drop across upper drift region 504 can be reduced to about 0.2 V; however, without injection of charge carriers into lower drift region 510, the total V CEON may be about 60.2 V (e.g., 0.2 V across upper drift region 504, and 60 V across lower drift region 510, given the 2 ohm resistance of lower drift region 510).

[0079] Figure 5E An active on configuration of example DSDB-BJT 200 is shown, with switch assembly 100 likewise forward biased. In particular, through driver 108, upper base 202 is coupled to upper terminal 102 through voltage source 302. Upper collector-emitter 206 is coupled to upper terminal 102, e.g., through upper cascode FET 220 or its body diode 228. Through driver 108, lower base 204 is coupled to lower terminal 104 through voltage source 306. Lower collector-emitter 208 is coupled to lower terminal 104 through lower cascode FET 210. Voltage source 302 provides a positive bias to upper base 202 relative to upper collector-emitter 206, and voltage source 306 provides a positive bias to lower base 204 relative to lower collector-emitter 208. Voltage source 302 injects charge carriers into upper drift region 504 across the upper PN junction, and voltage source 306 injects charge carriers into lower drift region 510 across the lower PN junction. For the main load current of example 30A, the injection of charge carriers reduces the forward voltage drop V CEONto about 0.4 V.

[0080] Figure 5F Pre-shutoff arrangement of the example modularly constructed DSDB-BJT 200 is shown. In particular, the upper base 202 is coupled to the upper terminal 102 by the driver 108. The upper collector-emitter 206 is coupled to the upper terminal 102, e.g., by the upper cascode FET 220 or its body diode 228. The lower base 204 is coupled to the lower terminal 104 by the driver 108. The lower collector-emitter 208 is coupled to the lower terminal 104 by the lower cascode FET 210. An equivalent arrangement can be to omit the coupling of the upper base 202 to the upper terminal 102.

[0081] Here again, with respect to the transition of the switch assembly 100 from non-conducting to conducting, the example modularly constructed DSDB-BJT 200 can be arranged to transition from Figure 5A the passive shutoff arrangement of FIG. 1A or Figure 5B the active shutoff arrangement of FIG. 1B directly into one of Figure 5D or the active on arrangement of FIG. 1C without having to implement intermediate arrangements or states. Regardless, Figure 5C the passive on arrangement of FIG. 1A can be used in some cases. With respect to the transition of the switch assembly 100 from conducting to non-conducting, the example modularly constructed DSDB-BJT 200 can transition from Figure 5E the active on arrangement of FIG. 1C directly into Figure 5B the active shutoff arrangement of FIG. 1B or Figure 5A the passive shutoff arrangement of FIG. 1A without having to implement intermediate arrangements or states.

[0082] Here again, Figures 5A to 5F the example is for the switch assembly 100 to be forward biased. However, the modularly constructed DSDB-BJT 200 is a symmetric device, and now that it is understood how to control current through the DSDB-BJT when the switch assembly 100 is forward biased, it can be directly derived how to control current when the switch assembly 100 is reverse biased (i.e., the lower terminal 104 is associated with a higher positive polarity relative to the upper terminal 102).

[0083] Figures 5A to 5F The modularly constructed example DSDB-BJT 200 shown in FIG. 1 can be fabricated by forming the components 500 and 502 on a substrate. The components 500 and 502 can then be singulated. The first modular component (e.g., the upper component 500) is bonded to the second modular component (e.g., the lower component 502) to form the overall DSDB-BJT 200. The example modular components can be initially constructed on thick wafers (e.g., 500 microns), and then the thick wafers can be thinned to about 150 to 160 microns before singulation. This results in, Figures 5A to 5FThe modular components of the present disclosure can be constructed on wafers of any diameter, as the wafers are still relatively thick (e.g., 150-160 microns) prior to bonding, and thus warping is not a major concern.

[0084] In various examples in which charge carriers are injected from both sides of the DSDB-BJT 200, for example Figure 3E 、 4E , the active turn-on arrangements of 4F and 5E, the injection of charge carriers can take many forms. Figure 3E 、 4E Examples of 4F and 5E use voltage sources. In the case of voltage sources, the magnitudes of the voltages can be the same. For example, the magnitude of the voltage of voltage source 302 can be the same as the magnitude of the voltage of voltage source 306. In other cases, the voltages can be different. For example, the magnitude of the voltage on the collector side (e.g., voltage source 302) can be greater than the voltage on the emitter side (e.g., voltage source 306).

[0085] From the perspective of the magnitude of the control current supplied, in some cases, the magnitude of the control current supplied to the upper component 400 / 500 can be the same as the magnitude of the control current supplied to the lower component 402 / 502. In other cases, the magnitude of the control current supplied to the upper component 400 / 500 can be different than the magnitude of the control current supplied to the lower component 402 / 502. The difference in magnitude can be intentional, e.g., voltage sources 302 and 306 have different setpoint voltages, or the difference in magnitude can be unintentional, e.g., a small control current difference due to manufacturing variability for the same applied voltage. In other cases, sources 300 and 302 can be set as controlled current sources, supplying variable voltages to achieve respective setpoint currents, and the setpoints can be the same or different.

[0086] Figure 6 A block diagram of an example driver 108 is shown. In particular, the example driver 108 includes an isolation circuit 600, a controller 602, a driver circuit 604, a comparator 606, a transformer 608, and an AC-DC converter 610. A primary winding of the transformer 608 is coupled to an input AC voltage. The transformer 608 is configured to generate an isolated AC voltage on a secondary winding thereof based on the input AC voltage. In some embodiments, the transformer 608 can include a core made of a ferrous material and / or one or more taps on the secondary winding. Although Figure 6 Although a single transformer is depicted in FIG. 6, in other examples, multiple transformers can be employed to provide different AC voltages to the AC-DC converter 610.

[0087] The AC-DC converter 610 is configured to generate a bus voltage 612. In some examples, the bus voltage 612 can include multiple voltage levels (e.g., 3.3 V, 5 V, 12 V) that are used by the controller 602 to generate voltages for various ones of the control signals 622 applied to the driver circuit 604. Similarly, the bus voltage can be used by the driver circuit 604 to generate voltages for various ones of the control signals 624 applied to the bidirectional switch 110 through the connection 112. The AC-DC converter 610 can be implemented using a rectifier circuit, one or more capacitors, one or more power converter circuits (e.g., a buck converter), or any other suitable circuit components or sub-circuits.

[0088] The driver 108 can be in a different electrical domain from a circuit that generates the switching signal 616 applied to the control terminal 106. To account for the difference in electrical domains, the isolation circuit 600 is employed. The isolation circuit 600 is configured to generate the signal 618 based on the switching signal 616 such that the signal 618 is in a different electrical domain from the switching signal 616. The isolation circuit 600 can be implemented using an opto-coupler, a capacitive isolation device, or any other circuit configured to translate a signal from one electrical domain to another.

[0089] The comparator 606 has a first input coupled to the upper terminal 102, a second input coupled to the lower terminal 104, and defines a comparison output. The comparator 606 is configured to generate a comparison signal 620 on the comparison output based on respective voltage levels of the terminals 102 and 104. The voltage level of the comparison signal 620 can indicate which of the terminals 102 or 104 has a greater voltage, and thus whether the switch assembly 100 is forward-biased or reverse-biased. For example, an asserted state of the comparison signal 620 can indicate forward-biasing, while a non-asserted state of the comparison signal 620 can indicate reverse-biasing. The comparator 606 can be implemented using a differential amplifier circuit, a Schmitt trigger circuit, or any other suitable circuit configured to generate an output signal whose voltage level is based on a comparison of respective voltage levels of at least two input signals.

[0090] The controller 602 is configured to generate the signals 622 applied to the driver circuit 604. In response to the signals 622, the driver circuit 604 arranges the bidirectional switch 110 into Figures 3A to 3FThe various states described in Figures 4A-4G and 5A-5F. In various embodiments, the driver circuit 604 can be implemented using individual circuit components, application specific integrated circuits (ASICs), microcontrollers configured to execute software or program instructions, reduced instruction set computers (RISC), digital signal processor (DSP) circuits, processors or processor cores configured to execute software or program instructions, programmable logic devices (PLDs), field programmable gate arrays (FPGAs), programmable system on a chip (SoC), or any suitable combination thereof.

[0091] The driver circuit 604 is configured to generate the control signal 624 using one or more of the voltage levels included in the signal 622 and the bus voltage 612. The driver circuit 604 can be used to place the upper cascode FET 220, the DSDB-BJT 200, and the lower cascode FET 210 in Figures 3A to 3F The various states described in Figures 4A-4G and 5A-5F. In various embodiments, the driver circuit 604 can be implemented using a plurality of switches, FETs, or any other suitable switching devices.

[0092] Figure 7 A method according to at least some embodiments is shown. In particular, the method begins (block 700) and includes conducting a main load current from an upper terminal of a switching assembly through a DSDB-BJT of the switching assembly and then through a lower terminal of the switching assembly (block 702). The conducting can be done by injecting charge carriers into an upper drift region of the DSDB-BJT while the main load current is flowing into an upper collector-emitter (block 704) and simultaneously injecting charge carriers into a lower drift region of the DSDB-BJT while the main load current is flowing out of a lower collector-emitter (block 706). Thereafter, the method ends (block 708), possibly to be restarted in a next cycle in which a voltage is applied to the switching assembly 100.

[0093] Many of the electrical connections in the drawings are shown as directly coupled without intervening devices, but are not explicitly stated as such in the above description. In any event, this paragraph serves as a basis of reference for the claims to refer to any electrical connection as being a "direct coupling" of the electrical connection shown in the drawings without intervening devices. Moreover, this paragraph should not negate that a base electrode is electrically connected to a collector-emitter through a transistor can be referred to as a "direct coupling."

[0094] The above discussion is meant to be illustrative of the principles and various embodiments of the present application. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be construed to include all such variations and modifications.

Claims

1. A method comprising: The main load current is conducted from the upper terminal of the switching assembly through the double-sided double-base bipolar junction transistor (DSDB-BJT) of the switching assembly, and then through the lower terminal of the switching assembly, the conduction being performed as follows: As the main load current flows into the upper collector-emitter region of the DSDB-BJT, charge carriers are injected into the upper drift region of the DSDB-BJT; and simultaneously When the main load current flows out from the lower collector-emitter junction of the DSDB-BJT, charge carriers are injected into the lower drift region of the DSDB-BJT.

2. The method according to claim 1, wherein: Injecting charge carriers into the upper drift region of the DSDB-BJT includes injecting an upper control current into the upper base of the DSDB-BJT; and Injecting charge carriers into the lower drift region of the DSDB-BJT includes injecting a lower control current into the lower base of the DSDB-BJT.

3. The method according to claim 2, wherein the magnitude of the upper control current is the same as the magnitude of the lower control current.

4. The method of claim 2, wherein the magnitude of the upper bias voltage between the upper base and the upper collector-emitter is different from the magnitude of the lower bias voltage between the lower base and the lower collector-emitter.

5. The method according to claim 2, wherein the magnitude of the upper control current is different from the magnitude of the lower control current.

6. The method of claim 2, wherein conducting the main load current includes conducting the main load current through the DSDB-BJT, which is a monolithic structure having a continuous drift region.

7. The method of claim 2, wherein conducting the main load current comprises conducting the main load current through the upper collector-emitter, then through the upper drift region, then through the metal material that bonds the upper drift region to the lower drift region, and then through the lower collector-emitter.

8. The method according to claim 1, wherein: Injecting charge carriers into the upper drift region of the DSDB-BJT includes injecting an upper control current through a metallic material that bonds the upper drift region to the lower drift region; and Injecting charge carriers into the lower drift region of the DSDB-BJT includes injecting a lower control current through the metal material.

9. A switch assembly comprising: Upper terminals, lower terminals, and control inputs; A double-sided double-base bipolar junction transistor (DSDB-BJT) defines an upper base, an upper collector-emitter junction, a lower base, and a lower collector-emitter junction. The upper main FET defines a first lead coupled to the upper terminal, a second lead coupled to the upper collector-emitter, and a gate; The lower main FET defines a first lead coupled to the lower collector-emitter, a second lead coupled to the lower terminal, and a gate; A driver coupled to the control input, the gate of the upper main FET, the gate of the lower main FET, and the upper and lower bases of the DSDB-BJT; In response to the assertion of the control input, and for a first applied voltage across the upper terminal and the lower terminal, the driver is configured to: The DSDB-BJT is arranged for conduction; Charge carriers are injected into the upper drift region of the DSDB-BJT and simultaneously into the lower drift region of the DSDB-BJT. and Assert the gate of the lower main FET to conduct the lower main FET such that a first load current flows from the upper terminal to the lower terminal.

10. The switch assembly of claim 9, wherein the DSDB-BJT includes an upper drift region associated with the upper collector-emitter and a lower drift region associated with the lower collector-emitter, and wherein the upper drift region is engaged with the lower drift region.

11. The switch assembly according to claim 10: Wherein, when the driver injects charge carriers into the upper drift region, the driver is configured to inject upper current into the upper base; and When the driver injects charge carriers into the lower drift region, the driver is configured to inject a lower current into the lower base.

12. The switch assembly according to claim 10: When the driver injects charge carriers into the upper drift region, the driver is configured to inject an upper control current through a metal layer that bonds the upper drift region to the lower drift region; and When the driver injects charge carriers into the lower drift region, the driver is configured to inject a lower control current through the metal layer.

13. The switch assembly of claim 9, wherein the DSDB-BJT comprises a monolithic structure having a continuous drift region.

14. The switch assembly according to claim 13: Wherein, when the driver injects charge carriers into the upper drift region, the driver is configured to inject upper current into the upper base; and When the driver injects charge carriers into the lower drift region, the driver is configured to inject a lower current into the lower base.

15. The switch assembly according to claim 9, wherein, In response to the release assertion of the control input, the driver is configured to: Release the assertion on the gate of the upper main FET to make the upper main FET non-conductive; Release the assertion on the gate of the lower main FET to make the lower main FET non-conductive, so that no current flows from the lower collector-emitter to the lower terminal; and The DSDB-BJT is arranged in a non-conductive state by coupling the upper base to the upper collector-emitter and coupling the lower base to the lower terminal.

16. The switch assembly according to claim 9, wherein, In response to the assertion of the control input, and for a first applied voltage across the upper terminal and the lower terminal, the driver is further configured to assert the gate of the upper main FET to conduct the upper main FET.

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