Isolation structure in semiconductor device

Abstract

The disclosure relates to methods, devices, systems, and techniques for managing isolation structures in semiconductor devices. An exemplary semiconductor device includes an array region, a connection region, and a stack of conductive layers and insulating layers alternating with each other in a first direction. The semiconductor device further includes a gate line structure having at least a first section and a second section. The gate line structure extends in a second direction perpendicular to the first direction. The semiconductor device further includes an isolation structure separating the first section from the second section. The size of the isolation structure along the third direction is the same as the size of the first section along the third direction. The third direction is perpendicular to the first direction and the second direction.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because of their ability to increase array density by stacking more layers within a similar coverage area. 3D memory devices generally include a memory array composed of memory cells and peripheral circuitry to facilitate the operation of the memory array. Summary of the Invention

[0003] This disclosure describes methods, devices, systems, and techniques for managing isolation structures in semiconductor devices.

[0004] One aspect of this disclosure is characterized by a semiconductor device. The semiconductor device includes an array region, a connection region, a stack of conductive and insulating layers alternating along a first direction, a gate line structure including at least a first segment and a second segment, and an isolation structure separating the first segment and the second segment. The gate line structure extends along a second direction perpendicular to the first direction. The isolation structure has the same dimension along a third direction as the first segment along the third direction. The third direction is perpendicular to both the first and second directions.

[0005] In some embodiments, the dimension of the isolation structure along the second direction is smaller than the dimension of the first segment along the second direction, and the dimension of the isolation structure along the third direction is the same as the dimension of the second segment along the third direction.

[0006] In some embodiments, the isolation structure extends through the stack in a first direction, the isolation structure is located between dummy channel structures in a third direction, a portion of at least one insulating layer of the stack spaced the isolation structure from the dummy channel structures in a third direction, the gate line structure extends through the stack in the first direction, and the gate line structure extends into the array region and the connection region in a second direction.

[0007] In some embodiments, the isolation structure includes a first sidewall contacting a first segment and a second sidewall contacting a second segment, both the first and second sidewalls having concave surfaces extending along a first direction. The isolation structure also includes third and fourth sidewalls contacting the stack along a third direction. Both the third and fourth sidewalls include a series of curved portions.

[0008] In some embodiments, the bottom of the isolation structure includes a series of substrates arranged in a line along a second direction, wherein the size of a first cross section of each substrate is larger than the size of a second cross section of the substrate, the first and second cross sections are perpendicular to the first direction, and the first cross section is closer to the stack along the first direction than the second cross section.

[0009] In some implementations, the first segment is located in the array region and the second segment and the isolation structure are located in the connection region.

[0010] In some implementations, the first segment, the second segment, and the isolation structure are located in the array region.

[0011] In some implementations, the isolation structure includes a dielectric material.

[0012] In some embodiments, the isolation structure includes an inner structure and an outer layer surrounding the inner structure, and the inner structure and the outer layer comprise different materials.

[0013] Another aspect of this disclosure is characterized by a method comprising providing a semiconductor structure including a substrate and a stack consisting of sacrificial layers and insulating layers alternating along a first direction. The method further comprises forming gate line vias and channel vias by the same etching process, wherein the gate line vias and channel vias extend through the stack into the substrate along the first direction, the gate line vias are arranged in a line along a second direction perpendicular to the first direction, and the gate line vias include a first group of gate line vias. The method further comprises forming an isolation trench by enlarging the first group of gate line vias. The method further comprises forming a first isolation structure by filling the isolation trench with at least one isolation material.

[0014] In some embodiments, the gate vias further include a second group of gate vias and a third group of gate vias, with the first group of gate vias located between the second group of gate vias and the third group of gate vias, and the first group of gate vias being adjacent to the second group of gate vias and the third group of gate vias.

[0015] In some embodiments, the isolation trench includes enlarged gate line vias formed by a first group of gate line vias, and these enlarged gate line vias are interconnected along a second direction.

[0016] In some embodiments, the first isolation structure includes a solid dielectric structure, and forming the first isolation structure includes filling the isolation trench with dielectric material.

[0017] In some embodiments, the first isolation structure includes an inner structure and an outer layer surrounding the inner structure, and forming the first isolation structure includes: forming the outer layer by depositing a dielectric material on the bottom and inner surface of an isolation trench; and forming the inner structure by filling the isolation trench with a filler material.

[0018] In some embodiments, the method further includes: forming a channel structure in the channel vias; filling the gate vias with polysilicon; and removing the polysilicon from the second group of gate vias and the third group of gate vias.

[0019] In some embodiments, the method further includes: forming a first segment of a gate line trench, a second segment of a gate line trench, and a second isolation structure by enlarging the gate line vias of the second group and the third group.

[0020] In some embodiments, a first section of the gate line trench includes enlarged gate line vias formed by a second group of gate line vias and interconnected along a second direction; a second section of the gate line trench includes enlarged gate line vias formed by a third group of gate line vias and interconnected along a second direction; and a second isolation structure is formed by removing a first end and a second end of a first isolation structure. The first end overlaps with the first section of the gate line trench, and the second end overlaps with the second section of the gate line trench.

[0021] In some implementations, the first segment of the gate line trench is located in the array region of the semiconductor structure, and the second isolation structure and the second segment of the gate line trench are located in the connection region of the semiconductor structure.

[0022] In some embodiments, the method further includes: forming a recessed space in the connection region by filling a second segment of the gate line trench with an etchant to recess the sacrificial layer in the connection region; filling the second segment of the gate line trench and the recessed space with carbon; removing the sacrificial layer in the array region by filling a first segment of the gate line trench with an etchant; removing the carbon in the connection region; and forming a conductive layer between insulating layers by depositing at least one conductive material through the first segment of the gate line trench.

[0023] Another aspect of this disclosure is characterized by a memory system. The memory system includes a memory device and a memory controller coupled to and configured to control the memory device. The memory device includes an array region, a connection region, a stack of alternating conductive and insulating layers along a first direction, a gate line structure including at least a first segment and a second segment, and an isolation structure separating the first segment and the second segment. The gate line structure extends along a second direction perpendicular to the first direction. The isolation structure has the same dimension along a third direction as the first segment along the third direction. The third direction is perpendicular to both the first and second directions.

[0024] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. Attached Figure Description

[0025] Figure 1A-1D An exemplary semiconductor device is shown.

[0026] Figure 2A-2R An exemplary process for manufacturing a semiconductor device is shown.

[0027] Figure 3 A flowchart illustrating an exemplary process for manufacturing a semiconductor device is shown.

[0028] Figure 4 A block diagram of an exemplary system is shown.

[0029] Similar reference numerals and names in the accompanying figures denote similar elements. It should be understood that the various exemplary embodiments shown in the figures are merely illustrative and not necessarily drawn to scale. Detailed Implementation

[0030] Due to the demand for higher-density, cheaper memory devices, memory devices (e.g., 3D NAND flash memory) can be formed with multiple decks, each of which can have a large number of layers. The large number of layers and high aspect ratio of such memory devices can pose challenges to the manufacturing process. For example, stress issues can become more severe and cause XY bowing problems during conductive layer filling. In another example, components with high aspect ratios in the memory device (e.g., gate line structures and memory blocks) may tilt, shift, or even collapse during the manufacturing process. Furthermore, increased depth of the memory device can introduce or exacerbate overlay (OVL) problems during manufacturing. In some implementations, the same etch mask can be used to form channel vias and gate line vias in the same etch process. Gate line vias can be enlarged to form gate line trenches (also known as gate line gaps). This process can be referred to as channel and gate line via fusion and can expand the process window during manufacturing and mitigate or resolve OVL problems. In some implementations, isolation structures can be formed to divide the gate line structure into multiple segments, thereby releasing stress in the gate line structure. The isolation structure can also divide the gate line trench into multiple segments and allow conductive layer filling to be performed in separate processes, thereby improving the quality and reliability of the conductive layer. Therefore, an isolation structure that is compatible with the fusion of channel vias and gate line vias and can solve the aforementioned problems is desirable.

[0031] In one or more embodiments, an exemplary semiconductor device is provided. The semiconductor device includes an array region, a connection region, and a stack consisting of conductive and insulating layers alternating along a first direction. The semiconductor device includes a gate line structure having at least a first segment and a second segment. The semiconductor device further includes an isolation structure separating the first segment and the second segment. The cross-section of the isolation structure has a partially circular shape. The cross-section is perpendicular to the first direction.

[0032] The embodiments of this disclosure can provide one or more of the following technical advantages and / or benefits. The isolation structure avoids occupying space in the array region used for the channel structure, thereby increasing the storage density and capacity of the memory device. Furthermore, the manufacturing process of the isolation structure avoids affecting the electrical function of the surrounding channel structure. The isolation structure provides isolation by forming sidewalls that contact adjacent structures rather than removing the dielectric material of adjacent structures, thereby avoiding seams formed in later processes (which could lead to isolation failure). This isolation structure allows the sacrificial layer removal process in the array region to be separated from the sacrificial layer removal process in the connection region, thereby improving product yield and structural stability and reducing manufacturing costs.

[0033] The technology can be applied to various semiconductor devices, namely volatile memory devices such as DRAM memory devices, or non-volatile memory (NVM) devices such as NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) such as phase-change random access memory (PCRAM), spin-transfer torque (STT)-magnetoresistive random access memory (MRAM), and others. The technology can also be applied to charge-trapping based memory devices (e.g., silicon-oxide-nitride-oxide-silicon (SONOS) memory devices) and floating-gate based memory devices. The technology can also be applied to three-dimensional (3D) memory devices. The technology can also be applied to various memory types such as SLC (single-level cell) devices, MLC (multi-level cell) devices (e.g., two-level cell devices), TLC (three-level cell) devices, QLC (four-level cell) devices, or PLC (five-level cell) devices. In addition, or alternatively, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems and others.

[0034] It should be pointed out that, in Figure 1A-1D The X, Y, and Z axes (also referred to as the X, Y, and Z directions) are included to further illustrate the spatial relationships of various components in a semiconductor device. The substrate of a semiconductor device may include two laterally extending surfaces in the XY plane: a top surface located on the front side of the substrate on which components of the semiconductor device can be formed, and a bottom surface located on the back side opposite the front side of the substrate. The Z direction is perpendicular to both the X and Y directions. As used in this disclosure, when the substrate of a semiconductor device is located in the lowest plane of the semiconductor device in the Z direction (a direction perpendicular to the XY plane, e.g., the thickness direction of the substrate), whether a component (e.g., a layer or device) of the semiconductor device is "on," "above," or "below" another component (e.g., a layer or device) is determined relative to the substrate along the Z direction. The same concepts will be used throughout this disclosure to describe spatial relationships.

[0035] Figure 1A A perspective view of an exemplary semiconductor device 100 is shown. In some embodiments, the semiconductor device 100 may be a memory device, such as a three-dimensional (3D) NAND memory device. The semiconductor device 100 may include one or more array regions and one or more connection regions configured to provide conductive connections to the one or more array regions. In some embodiments, such as Figure 1AAs shown, the semiconductor device 100 includes an array region 102 and a connection region 104 adjacent to the array region 102 along a first horizontal direction (e.g., the X direction). In some embodiments, an array of channel structures 108 may be located in the array region 102. Each channel structure 108 may be used to form a string of memory cells coupled in series along a vertical direction perpendicular to the first horizontal direction (e.g., the Z direction). In some embodiments, a stepped structure (not shown) and an array of contact structures (not shown) formed on the stepped structure may be located in the connection region 104. In some other embodiments, a conductive layer in the connection region 104 (e.g., as described below) Figure 1C The conductive layer 105A in the array can be formed into a structure different from the stepped structure. For example, contact structures can be connected to corresponding conductive layers and can extend through other conductive layers, and spacers for insulation can be formed between the contact structures and other conductive layers. In some embodiments, the semiconductor device 100 may include dummy channel structures 110 (also referred to as dummy memory strings) for process variation control and / or additional mechanical support during manufacturing. In some embodiments, the dummy channel structures 110 are located in the connection region 104. For example, some dummy channel structures 110 may be located in the edge or peripheral region of the connection region 104. In some cases, the edge region of the connection region 104 is adjacent to the array region 102. In some other cases, the edge region of the connection region 104 is adjacent to the gate line structure (e.g., Figure 1A The gate line structure 112 shown is adjacent to the array region 102 (e.g., the region adjacent to the connection region 104). In some embodiments, the dummy channel structure 110 is located in the array region 102 (e.g., the region adjacent to the connection region 104). It should be understood that... Figure 1A The examples in the text are for illustrative purposes and are not intended to be interpreted in a limiting sense. In practice, any suitable arrangement of various regions in the semiconductor device 100 can be applied. In some cases, the semiconductor device 100 may have two connection regions 104 and an array region 102 arranged along the X direction between the two connection regions 104. In some other cases, the semiconductor device 100 may have two array regions 102 and a connection region 104 located along the X direction between the two array regions 102.

[0036] In some implementations, the array of sub-regions 103 may be located within the connection region 104. In some cases, Figure 1A Through-array contacts (TACs), not shown, may be formed in sub-region 103. The TACs may pass through a stack consisting of alternating conductive and insulating layers (e.g., Figure 1C The stack 105 extends and connects components located on opposite sides of the stack (e.g., in the vertical direction). The dummy channel structure 110 may be located outside the sub-region 103 and may laterally surround the sub-region 103.

[0037] Semiconductor device 100 may include one or more gate line structures 112. Each gate line structure 112 may extend in the X direction. The gate line structure 112 may extend into both the array region 102 and the connection region 104. In some embodiments, the gate line structure 112 may divide the array region into multiple memory blocks. In some embodiments, the gate line structure 112 may function as a common source contact for the channel structure 108 in the array region 102. Figure 1A As shown, each gate line structure 112 may include a plurality of segments 114 extending along the X direction. The segments 114 may be separated and spaced along the X direction by an isolation structure 106. The isolation structure 106 may eliminate or reduce stress established in the gate line structure 112 during the manufacturing process, thereby preventing the gate line structure 112 from bending or breaking. In some embodiments, such as Figure 1A-1B As shown, isolation structure 106 is located in connection region 104 and adjacent to array region 102. In some other embodiments, isolation structure 106 is located in array region 102 and adjacent to connection region 104. In some other embodiments, isolation structure 106 may have a portion located in array region 102 and another portion located in connection region 104. In some embodiments ( Figure 1A (Not shown in the diagram), the gate line structure 112 may further include one or more segments 114 extending along a second horizontal direction (e.g., the Y direction). In some embodiments, the gate line structure 112 may include a plurality of segments 114 connected in an H-shape or T-shape.

[0038] Figure 1B An example of portion 116 of semiconductor device 100 is shown. Figure 1B A top view (also an enlarged view) is provided, including isolation structure 106 and a portion 116 of a structure adjacent to isolation structure 106. Isolation structure 106 separates segment 114a of gate line structure 112 from segment 114 of gate line structure 112. Isolation structure 106 can be located anywhere suitable along the X direction on gate line structure 112. In this example, isolation structure 106 and segment 114b are located in connection region 104, and segment 114a is located in array region 102. In some other examples (such as...) Figure 1A As shown in the diagram, the isolation structure 106 can be located in the array region 102 and can be located between two segments 114. One of the two segments 114 adjacent to the isolation structure 106 can be located in the array region 102. The other of the two segments 114 can be located in the array region 102, or the other segment 114 can have a portion located in the array region 102 and another portion located in the connection region 104. Figure 1BAs shown, the cross-section of the isolation structure 106 may be in the shape of a connected partial circle. This cross-section of the isolation structure 106 lies in the XY plane and is perpendicular to the Z direction. In some embodiments, the isolation structure 106 includes two sidewalls 118a and 118b that are opposite to each other along the X direction. Sidewall 118a may contact segment 114a, and sidewall 118b may contact segment 114b. Both sidewalls 118a and 118b may have a Z-direction (e.g., as shown in the diagram). Figure 1C (c) shown) extended concave surface (e.g., as shown) Figure 1B (As shown in the diagram). For example, a concave surface curves inward from segment 114a or 114b toward the isolation structure 106. The isolation structure 106 further includes two sidewalls 118c and 118d that are opposite to each other along the Y direction. The sidewalls 118c and 118d extend along the Z direction and contact the stack 105 (e.g., as shown in the diagram). Figure 1C (as shown in (b)). Sidewalls 118c and 118d may both be non-straight and may include a series of curved portions connected together (e.g., along the X direction). For example, this series of curved portions may be wavy or caterpillar-shaped. In some embodiments, the dimension of the isolation structure 106 along the X direction is smaller than the dimensions of segment 114a and segment 114b along the X direction. In some embodiments, the dimension of the isolation structure 106 along the Y direction is similar to or the same as the dimensions of segment 114a and segment 114b along the Y direction.

[0039] Figure 1C (a)-(c) respectively show portions 116 of the semiconductor device 100 along... Figure 1B Cross-sectional views of cutting lines AA', BB', and CC'. In some implementations, such as... Figure 1C (a) and Figure 1C As illustrated in (b), the semiconductor device 100 includes a substrate 101 and a stack 105 provided on the substrate 101, consisting of alternating conductive layers 105A and insulating layers 105B. In some embodiments, the substrate 101 may be removed from the semiconductor device 100 in a subsequent process. The substrate 101 may be any suitable semiconductor substrate having any suitable semiconductor material such as a single-crystal semiconductor, a polycrystalline semiconductor, or a single-crystal semiconductor. For example, the substrate 101 may include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. The semiconductor device 100 may include a top layer 107 made of an insulating material (e.g., oxide).

[0040] The stack 105 can extend in a second horizontal direction (e.g., Y direction) parallel to the top surface of the substrate 101 and perpendicular to the first horizontal direction (e.g., X direction). Conductive layers 105A and insulating layers 105B can alternate in a vertical direction (e.g., Z direction) perpendicular to the second direction. Each conductive layer 105A can be the same or different in thickness, for example, its thickness is in the range of 10-500 nm, for example, about 35 nm. Each insulating layer 105B can also be the same or different in thickness, for example, its thickness is in the range of 10-500 nm, for example, about 25 nm. It should be noted that... Figure 1C (a) or Figure 1C The number of conductive layers 105A and insulating layers 105B shown in (b) is for illustrative purposes only, and any suitable number of conductive layers 105A and insulating layers 105B may be included in the stack 105. Conductive layer 105A may comprise any suitable conductive material, such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, doped silicon, silicide, or any combination thereof. Insulating layer 105B may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, insulating layer 105B may also comprise a high-k dielectric material, such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, or any combination thereof.

[0041] In some implementations, such as Figure 1C (a) or Figure 1C As illustrated in (b), the stack 105 includes a liner 105C. The liner 105C may cover part or all sides of the corresponding conductive layer 105A and is located between the conductive layer 105A and two insulating layers 105B adjacent to the corresponding conductive layer 105A. The liner 105C may include a high-k dielectric material (e.g., Al2O3). In some examples, the conductive layer 105A includes a metallic material (e.g., W) and a binder material (e.g., TiN), and the binder material may be deposited between the metallic material and the high-k dielectric material. In some examples, the conductive layer 105A includes a metallic material (e.g., W), and the liner 105C includes a binder material (TiN) and a high-k dielectric material.

[0042] In some implementations, such as Figure 1CAs shown, channel structure 108 and dummy channel structure 110 can extend through stack 105 in a vertical direction (e.g., the Z direction). Gate line structure 112 can also extend through stack 105 in a vertical direction (e.g., the Z direction). Dummy channel structure 110 and channel structure 108 can have similar or identical structures and can be formed in the same manufacturing process. Each channel structure 108 (or dummy channel structure 110) can have a cylindrical or columnar shape and can include a high-K layer extending through conductive layer 105A and insulating layer 105B of stack 105, a barrier layer surrounded by the high-K layer, a charge trapping layer (or storage layer) surrounded by the barrier layer, a tunneling layer surrounded by the charge trapping layer, a channel layer surrounded by the tunneling layer, and a core filler layer surrounded by the channel layer, and also includes a channel contact formed on the core filler layer and in contact with the channel layer. In some embodiments, the channel layer may include silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon; the tunneling layer may include silicon oxide, silicon nitride, or any combination thereof; the barrier layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof; and the charge trapping layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the tunneling layer, charge trapping layer, and barrier layer, collectively referred to as a memory film, may include an ONO dielectric (silicon oxide-silicon nitride-silicon oxide).

[0043] like Figure 1C As shown in (b), the isolation structure 106 may extend through the stack 105 along the Z direction. In some embodiments, the isolation structure 106 may be located between the dummy channel structures 110 along the Y direction. The isolation structure 106 may not contact the dummy channel structures 110. That is, at least a portion of each conductive layer 105A and each insulating layer 105B in the stack 105 may space the isolation structure 106 and the dummy channel structures 110 apart from each other along the Y direction.

[0044] In some implementations, such as Figure 1DAs shown, the stack 105 may include multiple layers (e.g., layers 120a, 120b, and 120c) stacked along a vertical direction (e.g., the Z direction). Each of the multiple layers may include a subset of conductive layers 105A and insulating layers 105B in the stack 105. The isolation structure 106 may have multiple body portions (e.g., 122a, 122b, and 122c) and a bottom portion (e.g., 124) sequentially connected along a vertical direction. Each body portion may be located in a corresponding layer of the stack 105, and the bottom portion 124 may extend beyond the stack 105. The bottom portion 124 may include a series of substrates arranged in a line along the X direction. Each substrate may have a truncated cone shape. In some embodiments, the size of a first cross-section of the substrate is larger than the size of a second cross-section of the substrate. The first and second cross-sections are perpendicular to the Z direction. The first cross-section is closer to (e.g., along the Z direction) the stack 105 than the second cross-section.

[0045] like Figure 1D As shown in (a), each of the main body portions 122a, 122b, and 122c of the isolation structure 106 can have dimensions that gradually decrease in the vertical direction (e.g., the Z direction) along the Y direction. For example, main body portion 122b has sections 126 and 128, both of which are perpendicular to the vertical direction. Section 126 is closer to the top layer 107 in the vertical direction than section 128. The dimension of section 126 in the Y direction is larger than the dimension of section 128 in the Y direction. Main body portion 122b has a top end 130 and a bottom end 132 that are opposite to each other in the Z direction. Top end 130 is closer to the top layer 107 in the vertical direction than bottom end 132. Top end 130 of main body portion 122b connects to bottom end 134 of main body portion 122a. The dimension of the section of top end 130 in the Y direction is larger than the dimension of the section of bottom end 134 in the Y direction. Bottom end 132 of main body portion 122b connects to top end 136 of main body portion 122c. The dimension of the cross-section at the bottom 132 along the Y direction is smaller than the dimension of the cross-section at the top 136 along the Y direction. For example... Figure 1D As shown in (a), the dummy channel structure 110 may also have multiple parts, which may have a structure similar to the main body parts 122a, 122b and 122c of the isolation structure 106 along the Y direction, as described above.

[0046] like Figure 1D As shown in (b), the dimension of section 126 along the X direction is smaller than the dimension of section 128 along the X direction. The dimension of the section at the top end 130 along the X direction is smaller than the dimension of the section at the bottom end 134 along the X direction. The dimension of the section at the bottom end 132 along the X direction is larger than the dimension of the section at the top end 136 along the X direction.

[0047] In some implementations, such as Figure 1D (a) and Figure 1D As shown in (b), the isolation structure 106 can be a solid structure made of a dielectric material (e.g., silicon oxide). In some embodiments, such as Figure 1C (b) and Figure 1C As shown in (c), the isolation structure 106 may include an inner structure 138 and an outer layer 140 surrounding the inner structure 138. The inner structure 138 and the outer layer 140 may include different materials. For example, the inner structure 138 may include a semiconductor material such as polysilicon, and the outer layer 140 may include a dielectric material such as silicon oxide.

[0048] Figure 2A-2R This illustrates the manufacture of semiconductor devices (e.g., such as...). Figure 1A-1D An exemplary process of the illustrated semiconductor device 100. Figure 2A-2R Cross-sectional views of exemplary semiconductor devices at various stages of the manufacturing process are shown. Specifically, Figure 2A (a)-2R(a) illustrates the exemplary semiconductor structure along Figure 1B The cross-sectional view of the cutting line AA'. Figure 2A (b)-2R(b) illustrates the exemplary semiconductor structure along... Figure 1B The cross-sectional view of the cutting line BB'. Figure 2A (c)-2R(c) illustrates the exemplary semiconductor structure along... Figure 1B The cross-sectional view of the cutting line CC'.

[0049] like Figure 2A As shown, a semiconductor structure 200a is formed. The semiconductor structure 200a may have an array region 202 and a connection region 204 adjacent to the array region 202 (e.g., along the X direction). The array region 202 may be... Figure 1A-1D An example of an array region 102 of a semiconductor device 100, and an example of a connection region 204 may be a connection region 104 of the semiconductor device 100. A semiconductor structure 200a includes a substrate 201 and a stack 205 provided on the substrate 201, consisting of alternating sacrificial layers 205D and insulating layers 205B. The stack 205 may extend across the array region 202 and the connection region 204. The sacrificial layers 205D and insulating layers 205B may alternate in a vertical direction (e.g., the Z direction). The insulating layer 205B may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the sacrificial layer 205D may include a dielectric material different from the dielectric material of the insulating layer 205B. For example, the insulating layer 205B may include silicon oxide, and the sacrificial layer 205D may include silicon nitride. In some embodiments, the semiconductor structure 200a may further include a polysilicon layer 221 located vertically between the stack 205 and the substrate 201.

[0050] Semiconductor structure 200a may include channel vias 209 located in array region 202 and connection region 204. Semiconductor structure 200a may further include gate line vias 211 arranged and spaced apart along lines extending in the X direction in array region 202 and connection region 204. Channel vias 209 and gate line vias 211 may extend in the Z direction through stack 205 into substrate 201. In some embodiments, channel vias 209 and gate line vias 211 may be formed by the same etching process. For example, channel vias 209 and gate line vias 211 may be formed by using an etching mask applied to the top of semiconductor structure 200a. Figure 2A The etching process (not shown) forms these holes. The etching mask may have a pattern designed for these holes. The etching process forms these holes as they extend down into the substrate 201 through the sacrificial layer 205D and insulating layer 205B of the stack 205.

[0051] like Figure 2A As shown in (c), the gate via 211 may include a first group of gate vias 211a, a second group of gate vias 211b, and a third group of gate vias 211c. In some embodiments, the gate vias in each group may be continuous. The continuous gate vias 211a of the first group are located between the continuous gate vias 211b of the second group and the continuous gate vias 211c of the third group (e.g., along the X direction). The continuous gate vias 211a of the first group are adjacent to the continuous gate vias 211b of the second group and the continuous gate vias 211c of the third group (e.g., along the X direction).

[0052] Figure 2B A semiconductor structure 200b including a channel structure in a channel via 209 is shown. The channel structure can be formed by filling each of the channel vias 209 with components of the channel structure (e.g., a high-k layer, a barrier layer, a charge trapping layer, a tunneling layer, a channel layer, a core filler layer, and channel contacts). In some embodiments, the channel structure in array region 202 may be referred to as a channel structure (e.g., channel structure 208), and the channel structure in connection region 204 may be referred to as a dummy channel structure (e.g., dummy channel structure 210). A filler material (e.g., polysilicon) may be filled into the gate line via 211. In some embodiments, a protective structure (e.g., polymeric oxide) may be formed on the bottom of the gate line via 211 (which may contact the substrate 201) to protect the substrate 201 before filling with the filler material. A dielectric layer (e.g., including silicon oxide) may be deposited on top of the channel vias 209 and the gate line via 211.

[0053] like Figure 2CAs shown, a semiconductor structure 200c is formed by forming an opening in the top dielectric layer to expose the first group of continuous gate line vias 211a and removing the filler material from the first group of continuous gate line vias 211a.

[0054] like Figure 2D As shown, a semiconductor structure 200d including an isolation trench 213a is formed. The isolation trench 213a can be formed by enlarging a first group of continuous gate line vias 211a in an etching process. For example, an etchant can be filled into the first group of continuous gate line vias 211a to etch away the portion of the stack 205 exposed through the first group of continuous gate line vias 211a. The enlarged first group of continuous gate line vias 211a are interconnected along the X direction and form the isolation trench 213a. Figure 2D As shown in (b), each enlarged gate line via 211a may include a body portion 211a-1 located above the substrate 201 and a bottom portion 211a-2 located within the substrate 201. The bottom portion 211a-2 may be narrower in the Y direction than the body portion 211a-1 because during the etching process, the substrate 201 may not be etched away by the etchant or may be etched away at a slower rate than the stack 205. For example, the Y-direction dimension of the cross-section of the bottom portion 211a-2 may be smaller than the Y-direction dimension of the cross-section of the body portion 211a-1.

[0055] Figure 2E A semiconductor structure 200e is shown, including an isolation structure 215 in an isolation trench 213a. The isolation structure 215 can be formed by filling the isolation trench 213a with at least one isolation material. The isolation material may include a dielectric material and / or a filling material. In some embodiments, such as Figure 2E (b) and Figure 2E As shown in (c), the isolation structure 215 includes an inner structure 215a and an outer layer 215b surrounding the inner structure. The outer layer 215b may be formed by, for example, depositing a dielectric material (e.g., silicon oxide) on the bottom and inner surface of the isolation trench 213a. The inner structure 215a may be formed by, for example, filling the isolation trench with a filler material (e.g., polysilicon). In some embodiments, such as Figure 2E As shown in (a)-2E(c), the outer layer 215b may extend to the top of the semiconductor structure 200e and form a layer of the semiconductor structure 200e. In some embodiments ( Figure 2E (Not shown in the diagram), the isolation structure 215 can be completely filled with a dielectric material (e.g., silicon oxide) and can be formed by filling the isolation trench 213a with a dielectric material. In other words, the isolation structure 215 can be a solid dielectric structure.

[0056] Figure 2F A semiconductor structure 200f including a dielectric layer 217 is shown. The dielectric layer 217 may be formed by depositing a dielectric material (e.g., silicon oxide) on top of the semiconductor structure 200e. The dielectric layer 217 may cover the top of the internal structure 215a of the isolation structure 215.

[0057] Figure 2G A semiconductor structure 200g including an opening 219 is shown. The opening 219 extends from the top surface of the semiconductor structure 200g along the Z direction through the dielectric layer 217. The opening 219 can expose the filling material in the second group of continuous gate line vias 211b and the third group of continuous gate line vias 211c.

[0058] like Figure 2H As shown in the semiconductor structure 200h, the filling material in the continuous gate line vias 211b of the second group and the continuous gate line vias 211c of the third group can be removed.

[0059] Figure 2I A semiconductor structure 200i including a gate line trench 223 is shown. The gate line trench 223 includes segments 223a and 223b. The gate line trench 223 can be formed by enlarging a second group of consecutive gate line vias 211b and a third group of consecutive gate line vias 211c in the same etching process. The enlarged second group of consecutive gate line vias 211b are interconnected along the X direction and form segment 223a of the gate line trench 223. The enlarged third group of consecutive gate line vias 211c are interconnected along the X direction and form segment 223b of the gate line trench 223. In some embodiments, the etching process may remove a portion of the isolation structure 215. For example, the portion of the isolation structure 215 that overlaps with segment 223a of the gate line trench 223 (also referred to as the end along the X direction) may be removed. Similarly, another portion of the isolation structure 215 that overlaps with segment 223b of the gate line trench 223 (also referred to as the other end along the X direction) may be removed. The removal portion of the isolation structure 215 may include at least a portion of the outer layer 215b extending along the Z direction. In some embodiments, the top dielectric portion of the semiconductor structure 200h may also be removed (e.g., including the dielectric layer 217 and another portion of the outer layer 215b of the isolation structure 215 extending along the XY plane).

[0060] Figure 2JSemiconductor structure 200j is shown. Semiconductor structure 200j may be formed by removing some excess material from semiconductor structure 200i. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), may be performed to smooth and / or flatten the top surface of semiconductor structure 200j. In some embodiments, portions of the internal structure 215a of isolation structure 215 that expose to the gate line trench 223 may be removed (e.g., by an etching process). In other words, the internal structure 215a of isolation structure 215 is shortened along the X direction. In some embodiments, portions of the polysilicon layer 221 located in the gate line trench 223 may be removed (e.g., by an etching process).

[0061] Figure 2K Semiconductor structure 200k is shown. Semiconductor structure 200k includes protective structures (e.g., polymeric oxidation) formed on the bottom of segments 223a and 223b of the gate line trench 223 (which may contact the substrate 201) (e.g., to protect the substrate 201) and on the outer surface of the inner structure 215a of the isolation structure 215 (e.g., to protect the inner structure 215a). Figure 2K (b) and Figure 2K As shown in (c), the protective structure 225, which contacts the inner structure 215a along the X direction, and the remaining portion of the outer layer 215b, which contacts the inner structure 215a along the Y direction, can be referred to as the new outer layer 227. In some embodiments, the protective structure 225 comprises a dielectric material (e.g., silicon oxide). Therefore, the semiconductor structure 200k includes a new isolation structure 206. The isolation structure 206 includes the inner structure 215a and the outer layer 227. In some embodiments, the inner structure 215a comprises a polycrystalline silicon material, and the outer layer 227 comprises a dielectric material. In some other embodiments ( Figure 2K (not shown in the figure), the internal structure 215a may also include a dielectric material (e.g., as shown in the reference). Figure 2E (As described in the manufacturing process of isolation structure 215), therefore isolation structure 206 can be a solid dielectric material.

[0062] like Figure 2L As shown, the semiconductor structure 200l may be formed by filling the sections 223a and 223b of the gate line trench 223 with a filler material (e.g., polysilicon).

[0063] like Figure 2MAs shown, a semiconductor structure 200m including a dielectric layer 229 can be formed. The dielectric layer 229 can be formed by depositing a dielectric material (e.g., silicon oxide) on top of the semiconductor structure 200m. The dielectric layer 229 can cover the filling material in sections 223a and 223b of the gate line trench 223.

[0064] like Figure 2N As shown, a semiconductor structure 200n is formed. The semiconductor structure 200n may include gate line openings 228a and 228b located in the dielectric layer 229. Gate line opening 228a may be located on top of a segment 223a of the gate line trench 223, and may expose the filling material in the segment 223a of the gate line trench 223. Gate line opening 228b may be located on top of a segment 223b of the gate line trench 223, and may expose the filling material in the segment 223b of the gate line trench 223.

[0065] like Figure 2O As shown, a semiconductor structure 200o can be formed by removing the filler material in sections 223a and 223b of the gate line trench 223. For example, the filler material can be removed by filling sections 223a and 223b of the gate line trench 223 with etchant through gate line openings 228a and 228b, respectively.

[0066] Figure 2P Semiconductor structure 200p is shown. Semiconductor structure 200p can be formed by replacing sacrificial layer 205D in stack 205 with conductive layer 205A. For example, sacrificial layer 205D can be removed by an etching process, for example, by filling segments 223a and 223b of gate line trench 223 via gate line openings 228a and 228b with etchant. Conductive layer 205A and insulating layer 205B can alternate with each other in a vertical direction (e.g., Z direction). Conductive layer 205A can be formed by filling segments 223a and 223b of gate line trench 223 with at least one conductive material (e.g., W). In some embodiments, a high-k dielectric material (e.g., Al2O3) can be deposited on the surface of insulating layer 205B before forming conductive layer 205A to form substrate 205C. Conductive material 205A can contact substrate 205C. In some embodiments, each liner 205C may include an adhesive material (e.g., TiN) and a high-k dielectric material.

[0067] although Figure 2N and Figure 2OThe process is illustrated by opening sections 223a and 223b of the gate line trench 223 by forming gate line openings 228a and 228b and removing the filler material from sections 223a and 223b of the gate line trench 223. However, it should be understood that sections 223a and 223b may not be opened simultaneously. Due to the isolation structure 206, etchant can be filled into sections 223a and 223b of the gate line trench 223 in a separate process. In some embodiments, such a separate process can yield a more reliable conductive layer 205A, thereby improving product quality and manufacturing yield. For example, the conductive layer 205A can be formed by the following process: Section 223b in the connection region 204 can be opened first (e.g., the filler material in section 223b is removed). The sacrificial layer 205D in the connection region 204 can be recessed by filling an etchant into a segment 223b of the gate line trench 223, thereby forming a recessed space in the connection region 204. A sacrificial material (e.g., carbon) can be used to fill the segment 223b of the gate line trench 223 and the recessed space. A segment 223a in the array region 202 can be opened (e.g., the filling material in segment 223a can be removed). The sacrificial layer 205D in the array region 202 can be removed by filling an etchant into a segment 223a of the gate line trench 223. The sacrificial material in segment 223b and the recessed space can be removed. Subsequently, a conductive layer 205A can be formed between the insulating layers 205B by depositing at least one conductive material via a segment 223a of the gate line trench 223.

[0068] Figure 2Q A semiconductor structure 200q including a gate line structure 212 is shown. The gate line structure 212 includes segments 214a and 214b formed by filling segments 223a and 223b of a gate line trench 223 with semiconductor material (e.g., polysilicon), respectively. The semiconductor structure 200q may be Figure 1A-1D Examples of semiconductor device 100. Stack 205 may be similar to or the same as stack 105 of semiconductor device 100. Gate line structure 212 may be similar to or the same as gate line structure 112 of semiconductor device 100. Isolation structure 206 may be similar to or the same as isolation structure 106 of semiconductor device 100.

[0069] Figure 2R It shows that it can be Figure 1A-1D Another example of the semiconductor device 100 is a semiconductor structure 200r. The isolation structure 206 of the semiconductor structure 200r is a solid dielectric structure and can be formed as described above (e.g., see reference). Figure 2E and Figure 2K ).

[0070] In some embodiments, the substrate 201 and the polysilicon layer 221 of the semiconductor structures 200q or 200r can be removed in subsequent processes. The portion of each channel structure 208 that was previously located in the substrate 301 can be removed. For example, the portion of the memory film of the channel structure 208, including the ONO dielectric (silicon oxide-silicon nitride-silicon oxide), can be removed to expose the core fill layer of the channel structure. The portion of the gate line structure 212 that was previously located in the substrate 201 can also be removed to expose the semiconductor material of the gate line structure 212. A semiconductor layer (not shown) connecting the gate line structure 212 and the channel structure 208 can be formed. In some embodiments, this semiconductor layer can include any suitable semiconductor material (e.g., polysilicon) and can function as the common source of the array of memory strings (e.g., channel structures 208) of the semiconductor structures 200q or 200r.

[0071] Figure 3 A flowchart of an exemplary process 300 is shown. Process 300 can be performed to form a semiconductor device (e.g., via...). Figure 1A-1D (Example semiconductor device 100). See also... Figure 2A-2R To describe process 300. Process 300 may include forming Figure 2A-2R The process of manufacturing a semiconductor structure in [the process described in the text] includes one or more steps. It should be understood that the operations shown in process 300 are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in a sequence different from [the steps described in the text]. Figure 3 The execution is performed in the order shown.

[0072] In operation 302, a semiconductor structure (e.g., Figure 2A Semiconductor structure 200a). The semiconductor structure may include a substrate (e.g., semiconductor structure 200a). Figure 2A The substrate 201) and the sacrificial layers (e.g., along the first direction (e.g., the Z direction) that alternate with each other. Figure 2A The sacrificial layer 205D) and the insulating layer (e.g., Figure 2A A stack of insulating layers 205B (e.g., Figure 2A Stacked body 205).

[0073] In operation 304, it can be resolved by (for example, as referenced) Figure 2A The same etching process forms gate line vias (e.g., Figure 2A Gate line via 211) and channel via (e.g., Figure 2AThe gate line vias 209. Gate line vias and channel vias can extend into the substrate through the stack along a first direction. Gate line vias are arranged in lines along a second direction perpendicular to the first direction (e.g., the X direction). Gate line vias include a first group of gate line vias (e.g., ...). Figure 2A Gate wire hole 211a).

[0074] In operation 306, the gate line vias of the first group can be enlarged (e.g., as referenced). Figure 2D As described above) to form isolation trenches (e.g., Figure 2D (Isolation trench 213a).

[0075] In operation 308, at least one insulating material (e.g., reference) can be used. Figure 2E The dielectric material and / or filler material are filled into the isolation trench to form a first isolation structure (e.g., Figure 2E The isolation structure 215).

[0076] In some embodiments, the gate vias further include a second group of gate vias (e.g., Figure 2A Gate line via 211b) and the third group of gate line vias (e.g., Figure 2A (Gate vias 211c). The first group of gate vias is located between the second group of gate vias and the third group of gate vias. The first group of gate vias is adjacent to the second group of gate vias and the third group of gate vias.

[0077] In some embodiments, the isolation trench includes enlarged gate line vias formed by a first group of gate line vias, and these enlarged gate line vias are interconnected along a second direction (e.g., as referenced). Figure 2D As described above).

[0078] In some embodiments, the first isolation structure includes a solid dielectric structure, and forming the first isolation structure includes filling an isolation trench with a dielectric material (e.g., silicon oxide) (e.g., as referenced). Figure 2E As described above).

[0079] In some implementations, the first isolation structure includes an internal structure (e.g., Figure 2E The internal structure 215a) and the external structure surrounding the internal structure (e.g., Figure 2E The external structure 215b). Forming the first isolation structure includes forming an outer layer by depositing a dielectric material (e.g., silicon oxide) on the bottom and inner surface of the isolation trench and forming an internal structure by filling the isolation trench with a filler material (e.g., polysilicon).

[0080] In some embodiments, process 300 further includes (e.g., as referenced) Figure 2B The aforementioned channel structure is formed in the channel hole (e.g., Figure 2B The channel structure 208 and the dummy channel structure 210); the gate line vias are filled with polysilicon (e.g., as shown in the reference). Figure 2B As described above); and removing polysilicon from the gate wire vias of the second group and the third group (e.g., as referenced). Figure 2H As described above).

[0081] In some embodiments, process 300 further includes enlarging the second group of gate line vias and the third group of gate line vias (e.g., as referenced). Figure 2I-2K As described above) to form gate line trenches (e.g., Figure 2I The first section of the gate trench 223 (e.g., Figure 2I Section 223a), the second section of the gate line trench (e.g., Figure 2I Section 223b) and the second isolation structure (e.g., Figure 2K The isolation structure 206).

[0082] In some implementations, the first section of the gate line trench includes enlarged gate line vias formed by a second group of gate line vias (e.g., Figure 2A The gate line vias 211b are formed and interconnected along the second direction. The second section of the gate line trench includes enlarged gate line vias formed by a third group of gate line vias (e.g., Figure 2A Gate line vias 211c are formed and interconnected along the second direction. The second isolation structure is formed by removing the first end and the second end of the first isolation structure. For example, the first end and the second end of the first isolation structure can be two ends or portions opposite to each other along the X direction, as shown in the reference. Figure 2I As described above, the first end overlaps with the first segment of the gate line trench, and the second end overlaps with the second segment of the gate line trench.

[0083] In some implementations, the first segment of the gate line trench is located in the array region of the semiconductor structure (e.g., Figure 2A-2R In the array region 202), the second isolation structure and the second segment of the gate line trench are located in the connection region of the semiconductor structure (e.g., Figure 2A-2R In the connection area 204).

[0084] In some embodiments, process 300 further includes filling a second segment of the gate line trench with an etchant to create a sacrificial layer (e.g., ...) in the connection region. Figure 2AThe sacrificial layer 205D is recessed, forming a recessed space in the connection region. Process 300 further includes filling a second segment of the gate line trench and the recessed space with carbon. Process 300 further includes removing the sacrificial layer in the array region by filling the first segment of the gate line trench with etchant. Process 300 further includes removing carbon from the connection region. Process 300 further includes depositing at least one conductive material in the insulating layer (e.g., through the first segment of the gate line trench). Figure 2P A conductive layer is formed between the insulating layer 205B and the conductive layer (e.g., Figure 2P (Conductive layer 205A).

[0085] Figure 4 A block diagram of an exemplary system 400 is shown. System 400 may have one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of this disclosure. System 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other electronic device with storage devices. Figure 4 As shown, system 400 may include a host device 408 and a memory system 402, the memory system 402 having one or more memory devices 404 and a memory controller 406. Host device 408 may include a processor of an electronic device, such as a central processing unit (CPU), or may include a system-on-a-chip (SoC), such as an application processor (AP). Host device 408 may be configured to send or receive data to or from the one or more memory devices 404.

[0086] Memory device 404 can be any memory device disclosed in this disclosure, for example, Figure 1A-1D The memory device shown is an example of a NAND flash memory. A memory controller 406 (also known as controller circuitry) is coupled to the memory device 404 and the host device 408. Consistent with embodiments of this disclosure, the memory device 404 may include a plurality of conductive interconnects that pass through a cover layer and contact conductive pads in a conductive pad layer, and the memory controller 406 may be coupled to the memory device 404 through at least one of the plurality of conductive interconnects. The memory controller 406 is configured to control the memory device 404. For example, the memory controller 406 may be configured to operate a plurality of channel structures via word lines. The memory controller 406 may manage data stored in the memory device 404 and communicate with the host device 408.

[0087] In some embodiments, the memory controller 406 is designed / configured to operate in a low-duty environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 406 is designed / configured to operate in a high-duty environment, such as an SSD or embedded multimedia card (eMMC), used as a data storage device in mobile devices such as smartphones, tablet computers, laptop computers, etc., and in enterprise storage arrays. The memory controller 406 may be configured to control the operation of the memory device 404, such as read, erase, and program (or write) operations. The memory controller 406 may also be configured to manage various functions related to data stored in or to be stored in the memory device 404, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 406 is further configured to process error correction codes (ECC) related to data read from or written to the memory device 404. The memory controller 406 may also perform any other appropriate function, such as formatting the memory device 404.

[0088] The memory controller 406 can communicate with external devices (e.g., host device 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0089] The memory controller 406 and one or more memory devices 404 can be integrated into various types of memory devices, for example, contained in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 402 can be implemented and packaged into different types of end electronic products. Figure 4In one example shown, the memory controller 406 and a single memory device 404 may be integrated into a memory card 402. The memory card 402 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0090] The embodiments, actions, and operations of the subject matter described in this disclosure can be implemented in digital electronic circuit systems, in computer software or firmware tangibly embodied, in computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or in one or more combinations of these options. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by a data processing device or for controlling the operation of the data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagated signal, such as a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiving device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of or part thereof. The computer storage medium is not a propagated signal.

[0091] It should be noted that in this disclosure, references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," "some implementations," etc., indicate that the described embodiments may include specific features, structures, or characteristics, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other implementations, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0092] Generally, terms should be understood at least partly by their use in context. For example, the word "one or more" in a text can be used, at least partly depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, the words "a," "one," or "the" can be understood to convey either singular or plural usage, at least partly depending on the context. Furthermore, the word "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for other factors that are not explicitly stated, again at least partly depending on the context.

[0093] It should be understood that the meanings of "on," "above," and "on top of" in this disclosure should be interpreted in the broadest sense. Thus, "on" not only means being directly on something, but also includes being on something with an intermediate feature or layer in between. Furthermore, "above" or "on top of" not only means being above or on something, but can also include being above or on something without any intermediate feature or layer in between (i.e., being directly on something).

[0094] In addition, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship of one element or feature to other elements or features(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the apparatus in use or process steps other than those shown in the figures. The apparatus may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0095] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed; therefore, semiconductor devices are formed on the top side of the substrate unless otherwise specified. The bottom surface is opposite to the top surface; therefore, the bottom side of the substrate is opposite to the top side. The substrate itself can be patterned. The material added to the top of the substrate can be patterned or left unpatterned. Furthermore, the substrate can comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or sapphire wafers.

[0096] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entirety of the underlying or overlying structure, or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than the thickness of the continuous structure. For example, a layer may lie between any set of horizontal planes between the top and bottom surfaces of the continuous structure, or at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers therein, and / or may have one or more layers located on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (in which contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0097] As used herein, the term “nominal / nominally” refers to the expected or target value of a feature or parameter of a component or process step set during the design phase of a product or process, along with a range of values ​​that are higher and / or lower than the expected value. As used herein, this range may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the term “around” means that the value of a given quantity may vary based on a specific technology node associated with the semiconductor device in question. Based on a specific technology node, the term “approximately” may indicate that the value of a given quantity varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or 30% of that value).

[0098] In this disclosure, the terms "horizontal / horizontally / laterally" refer to a lateral surface that is nominally parallel to the substrate, and the terms "vertical" or "perpendicularly" refer to a lateral surface that is nominally perpendicular to the substrate.

[0099] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” e.g., NAND strings) located on a substrate having a lateral orientation, such that the memory strings extend vertically relative to the substrate.

[0100] This disclosure provides numerous different implementations or examples of various features for carrying out the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to constitute limitation. For example, the description below of forming a first feature on or above a second feature may include implementations where the first and second features can be in direct contact, and may also include implementations where an additional feature can be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0101] The descriptions of specific implementation methods described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidelines provided herein, it is intended that such adjustments and modifications fall within the meaning of the disclosed implementation methods and equivalents.

[0102] Although this disclosure contains many specific implementation details, these should not be construed as limiting the scope of the claimed protection, which is defined by the claims themselves. These details should be understood only as descriptions of features specific to particular embodiments of the invention. Certain features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, while certain features may be described above as functioning in certain combinations and even initially claimed accordingly, one or more features from the claimed combination may be removed from that combination in certain circumstances, and the claims may relate to sub-combinations or variations thereof.

[0103] Similarly, although the operations are depicted in a specific order in the accompanying drawings and are described in a specific order in the claims, this should not be construed as requiring the operations to be performed in the specific order shown or in a sequential manner to obtain the desired result, or as requiring all illustrated operations to be performed. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the division of various system modules and components in the embodiments described above should not be construed as requiring such division in all embodiments, and it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0104] Specific embodiments of this subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions set forth in the claims can be performed in different orders and still achieve the desired result. As an example, the processes shown in the accompanying drawings do not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0105] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but only by the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: an array region; a connection region; a stack of conductive layers and insulating layers alternating with each other along a first direction; a gate line structure including at least a first section and a second section, wherein the gate line structure extends along a second direction perpendicular to the first direction; and an isolation structure separating the first section from the second section, wherein a dimension of the isolation structure along a third direction is the same as a dimension of the first section along the third direction, the third direction being perpendicular to the first direction and the second direction.

2. The semiconductor device according to claim 1, wherein a dimension of the isolation structure along the second direction is smaller than a dimension of the first section along the second direction, the dimension of the isolation structure along the third direction being the same as a dimension of the second section along the third direction.

3. The semiconductor device according to claim 2, wherein the isolation structure extends through the stack along the first direction, the isolation structure is located between dummy channel structures along the third direction, portions of at least one insulating layer of the stack separate the isolation structure from the dummy channel structures from each other along the third direction, the gate line structure extends through the stack along the first direction, and the gate line structure extends into the array region and the connection region along the second direction.

4. The semiconductor device according to any one of Claims 1 to 3, wherein the isolation structure includes a first sidewall in contact with the first section and a second sidewall in contact with the second section, the first sidewall and the second sidewall each have a concave surface extending along the first direction, the isolation structure includes a third sidewall and a fourth sidewall in contact with the stack along the third direction and the third sidewall and the fourth sidewall each include a series of curved portions.

5. The semiconductor device according to any one of Claims 1 to 4, wherein a bottom of the isolation structure includes a series of bases arranged in a line along the second direction, a first cross section of each base of the series of bases has a dimension larger than a dimension of a second cross section of the base, the first cross section and the second cross section are perpendicular to the first direction and the first cross section is closer to the stack along the first direction than the second cross section.

6. The semiconductor device according to any one of Claims 1 to 5, wherein the first section is located in the array region, the second section and the isolation structure are located in the connection region.

7. The semiconductor device according to any one of Claims 1 to 6, wherein the first section, the second section, and the isolation structure are located in the array region.

8. The semiconductor device according to any one of Claims 1 to 7, wherein the isolation structure includes a dielectric material.

9. The semiconductor device according to any one of Claims 1 to 8, wherein the isolation structure includes an inner structure and an outer layer surrounding the inner structure, and the inner structure and the outer layer include different materials.

10. A method, comprising: providing a semiconductor structure including a substrate and a stack of sacrificial layers and insulating layers alternating with each other along a first direction; forming gate line holes and channel holes through a same etching process, wherein the gate line holes and the channel holes extend through the stack into the substrate along the first direction, the gate line holes are arranged in a line along a second direction perpendicular to the first direction, and the gate line holes include a first group of gate line holes; forming an isolation trench by enlarging the first group of gate line holes; and forming a first isolation structure by filling at least one isolation material into the isolation trench.

11. The method of claim 10, wherein, The gate line holes further include a second group of gate line holes and a third group of gate line holes, the first group of gate line holes is between the second group of gate line holes and the third group of gate line holes, and the first group of gate line holes is adjacent to the second group of gate line holes and the third group of gate line holes.

12. The method of claim 10 or claim 11, wherein, The isolation trenches include enlarged gate line holes formed by the first group of gate line holes, and the enlarged gate line holes are connected to each other along the second direction.

13. The method of any one of claims 10 to 12, wherein, The first isolation structure includes a solid dielectric structure, and forming the first isolation structure includes: filling a dielectric material into the isolation trenches.

14. The method of any one of claims 10 to 13, wherein, The first isolation structure includes an inner structure and an outer layer surrounding the inner structure, and forming the first isolation structure includes: forming the outer layer by depositing a dielectric material on a bottom and inner surfaces of the isolation trenches; and forming the inner structure by filling a fill material into the isolation trenches.

15. The method of claim 11, further comprising: forming a channel structure in the channel holes; filling the gate line holes with polysilicon; and removing the polysilicon in the second group of gate line holes and the third group of gate line holes.

16. The method of claim 15, further comprising: forming a first section of a gate line trench, a second section of the gate line trench, and a second isolation structure by enlarging the second group of gate line holes and the third group of gate line holes.

17. The method of claim 16, wherein: the first section of the gate line trench includes enlarged gate line holes formed by the second group of gate line holes and connected to each other along the second direction; the second section of the gate line trench includes enlarged gate line holes formed by the third group of gate line holes and connected to each other along the second direction; and the second isolation structure is formed by removing a first end of the first isolation structure and a second end of the first isolation structure, wherein the first end overlaps the first section of the gate line trench and the second end overlaps the second section of the gate line trench.

18. The method of claim 16, wherein, the first section of the gate line trench is in an array region of the semiconductor structure, and the second isolation structure and the second section of the gate line trench are in a connection region of the semiconductor structure.

19. The method of claim 18, further comprising: forming a recessed space in the connection region by filling an etchant into the second section of the gate line trench to recess the sacrificial layer in the connection region; filling carbon into the second section of the gate line trench and the recessed space; removing the sacrificial layer in the array region by filling an etchant into the first section of the gate line trench; removing the carbon in the connection region; and forming a conductive layer between the insulating layers by depositing at least one conductive material through the first section of the gate line trench.

20. A memory system, comprising: a memory device; and ​ A memory controller coupled to the memory device and configured to control the memory device. The memory device includes: Array area; Connection area; A stack consisting of conductive and insulating layers alternating along a first direction; A gate line structure comprising at least a first segment and a second segment, wherein the gate line structure extends along a second direction perpendicular to the first direction; and An isolation structure separating the first segment and the second segment, wherein the dimension of the isolation structure along a third direction is the same as the dimension of the first segment along the third direction, and the third direction is perpendicular to the first direction and the second direction.

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