Implantable chip-based running environment simulation data analysis method and system

Abstract

The invention discloses a running environment simulation data analysis method and system based on an implantable chip, and belongs to the technical field of implantable chip data processing. According to the method and the device, the running state data of the implantable chip equipment in the simulated running environment is acquired, and the target chip state evaluation algorithm which has completed environment simulation response vector training debugging is utilized, so that comprehensive and accurate evaluation of the performance of the implantable chip equipment is realized. Meanwhile, by introducing attention features, key factors influencing the performance of the implantable chip equipment can be explored more deeply, and more specific and targeted optimization viewpoints are generated accordingly. Through the design, risk assessment and optimization in the design stage of the implantable chip equipment are facilitated, and the reliability and stability of the implantable chip equipment are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of implantable chip data processing, and particularly relates to a running environment simulation data analysis method and system based on an implantable chip. BACKGROUND

[0002] In the research and application process of implantable chip devices (such as monitoring devices and regulation devices), accurate evaluation and optimization of chip performance have always been important challenges faced by technical personnel. Traditional evaluation methods often rely on limited experimental data and experience, and it is difficult to comprehensively and accurately reflect the performance of the chip in the actual living body implantation environment. At the same time, due to the complexity and diversity of the living body implantation environment, the traditional evaluation method is often difficult to simulate all possible environmental conditions, resulting in great limitations and uncertainties in the evaluation of chip performance. SUMMARY

[0003] The application provides a running environment simulation data analysis method and system based on an implantable chip, which can solve or partially solve the technical problems involved in the background technology.

[0004] The embodiment of the application provides a running environment simulation data analysis method based on an implantable chip, applied to a data analysis system, and the method comprises the following steps:

[0005] Obtaining chip running environment simulation data, wherein the chip running environment simulation data comprises running state data of an implantable chip device in a simulated running environment, and the implantable chip device and the simulated running environment are in a one-to-many relationship;

[0006] For a current performance simulation label corresponding to the implantable chip device in the chip running environment simulation data, a target chip state evaluation algorithm is called to obtain a first group of chip evaluation optimization viewpoints corresponding to the current performance simulation label based on the chip running environment simulation data, and the target chip state evaluation algorithm has completed training and debugging based on an environment simulation response vector of the simulated running environment;

[0007] The target chip state evaluation algorithm is called to obtain at least one second group of chip evaluation optimization viewpoints corresponding to the current performance simulation label based on the chip running environment simulation data and at least one attention feature, and the attention feature is a feature generated based on the chip running environment simulation data and used as an output chip evaluation optimization viewpoint;

[0008] From the first group of chip evaluation optimization viewpoints and the at least one second group of chip evaluation optimization viewpoints, a target chip evaluation optimization viewpoint corresponding to the current performance simulation label is determined.

[0009] In an implementation manner, the calling the target chip state evaluation algorithm based on the chip running environment simulation data and at least one attention feature obtains at least one second group of chip evaluation optimization viewpoints corresponding to the current performance simulation label, and the method comprises the following steps:

[0010] For a target attention feature in the at least one attention feature, the target attention feature is combined with the chip running environment simulation data to obtain chip running environment attention data;

[0011] The target chip state evaluation algorithm is called to process the chip running environment attention data, so as to obtain a second group of chip evaluation optimization viewpoints output by the current performance simulation label under the indication of the target attention feature.

[0012] In an implementation manner, the calling the target chip state evaluation algorithm based on the chip running environment simulation data and at least one attention feature obtains at least one second group of chip evaluation optimization viewpoints corresponding to the current performance simulation label, and the method comprises the following steps:

[0013] A state simulation time sequence vector of the chip running environment attention data is obtained;

[0014] For each attention data unit in the chip running environment attention data, a data unit distribution feature, a state running correlation feature and a simulation task demand feature corresponding to the attention data unit are integrated with a state simulation time sequence vector corresponding to the attention data unit, so as to obtain a linkage state simulation time sequence vector corresponding to the target chip state evaluation algorithm;

[0015] The target chip state evaluation algorithm is called to process the linkage state simulation time sequence vector, so as to obtain a second group of chip evaluation optimization viewpoints output by the current performance simulation label under the indication of the target attention feature.

[0016] In an implementation manner, the attention feature comprises an environment simulation response vector of the simulation running environment or a noise label feature of the chip running environment simulation data; wherein the environment simulation response vector comprises at least one of the following: a response state feature, a response state heat map, an environment element offset and a potential anomaly description vector; and the combination of the target attention feature and the chip running environment simulation data to obtain chip running environment attention data comprises the following steps:

[0017] On the basis that the target attention feature is the environment simulation response vector, the environment simulation response vector is fused into a local environment data set corresponding to the implantable chip device in the chip running environment simulation data, so as to obtain the chip running environment attention data.

[0018] Or, on the basis that the target attention feature is the noise-labeled feature, the noise-labeled feature is fused into the environmental noise data set of the chip running environment simulation data to obtain the chip running environment attention data.

[0019] In an implementation manner, the target chip evaluation optimization viewpoint corresponding to the current performance simulation label is determined from the first group of chip evaluation optimization viewpoints and the at least one second group of chip evaluation optimization viewpoints, and the determination comprises the following steps.

[0020] The confidence weight coefficients corresponding to the first group of chip evaluation optimization viewpoints and the confidence weight coefficients respectively corresponding to each second group of chip evaluation optimization viewpoints are obtained through the weight decision tree network, and the confidence weight coefficients are used to indicate the matching degree of the chip evaluation optimization viewpoint and the simulated running environment.

[0021] The chip evaluation optimization viewpoint with the largest confidence weight coefficient in the first group of chip evaluation optimization viewpoints and each second group of chip evaluation optimization viewpoints is determined as the target chip evaluation optimization viewpoint.

[0022] In an implementation manner, before the chip evaluation optimization viewpoint with the largest confidence weight coefficient in the first group of chip evaluation optimization viewpoints and each second group of chip evaluation optimization viewpoints is determined as the target chip evaluation optimization viewpoint, the following steps are further included.

[0023] On the basis that there is an evaluation optimization label with a real performance prediction weight not less than a prediction weight threshold in the preliminary screening chip evaluation optimization viewpoint, the confidence weight coefficient corresponding to the preliminary screening chip evaluation optimization viewpoint is increased.

[0024] Or, on the basis that the feature commonality value between the preliminary screening chip evaluation optimization viewpoint and the key performance characterization vector is not less than a preset commonality value, the confidence weight coefficient corresponding to the preliminary screening chip evaluation optimization viewpoint is increased, and the key performance characterization vector is used to represent the environmental simulation response vector of the simulated running environment.

[0025] The preliminary screening chip evaluation optimization viewpoint comprises the first group of chip evaluation optimization viewpoints and each second group of chip evaluation optimization viewpoints.

[0026] In an implementation manner, the debugging steps of the target chip state evaluation algorithm are as follows.

[0027] The basic chip state evaluation algorithm is obtained, and the basic chip state evaluation algorithm is obtained through pre-debugging of the running environment simulation data pool.

[0028] determining an algorithm debugging example set from the chip simulation involvement log corresponding to the simulated running environment, the algorithm debugging example set including a first group of algorithm debugging examples carrying environment simulation parameters corresponding to the simulated running environment and a second group of algorithm debugging examples not carrying the environment simulation parameters, and an algorithm debugging example in the algorithm debugging example set being composed of chip environment interaction response information;

[0029] debugging the basic chip state evaluation algorithm through the algorithm debugging example set to obtain the target chip state evaluation algorithm after debugging.

[0030] In an implementation manner, the chip simulation involvement log includes an initial chip state simulation log and a derived chip state simulation log; and the method further includes:

[0031] screening the first group of algorithm debugging examples from the initial chip state simulation log according to a sample screening strategy; wherein the initial chip state simulation log includes visual chart information related to the simulated running environment;

[0032] constructing positive debugging examples of a log extraction network according to the first group of algorithm debugging examples, and constructing negative debugging examples of the log extraction network based on remaining chip state simulation logs irrelevant to the simulated running environment;

[0033] debugging the log extraction network based on the positive debugging examples and the negative debugging examples of the log extraction network to obtain a log extraction network after debugging;

[0034] obtaining the derived chip state simulation log from a chip state simulation log library through the log extraction network after debugging.

[0035] In an implementation manner, the debugging step of the weight decision tree network is as follows:

[0036] adding a multiple regression branch in the basic chip state evaluation algorithm to obtain an adjusted weight decision tree network; wherein the basic chip state evaluation algorithm is obtained through pre-debugging of running environment simulation data pool;

[0037] constructing a positive debugging example set and a negative debugging example set based on a first group of algorithm debugging examples corresponding to the simulated running environment, a positive debugging example in the positive debugging example set being the first group of algorithm debugging examples, and a negative debugging example in the negative debugging example set being obtained by adjusting a chip evaluation optimization viewpoint in the first group of algorithm debugging examples;

[0038] The weight decision tree network is debugged through the positive debugging example set and the negative debugging example set, and a completed debugging weight decision tree network is obtained.

[0039] The data analysis system comprises at least one processor and a memory.

[0040] The data analysis system comprises at least one processor and a memory.

[0041] The data analysis system comprises at least one processor and a memory. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 The data analysis system comprises at least one processor and a memory.

[0043] Figure 2 The data analysis system comprises at least one processor and a memory. DETAILED DESCRIPTION

[0044] The data analysis system comprises at least one processor and a memory.

[0045] The terms "first", "second", and the like in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of a kind and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the present invention means at least one of the connected objects, and the character " / " generally means that the objects before and after are in an "or" relationship.

[0046] Figure 1 A running environment simulation data analysis method based on an implanted chip is shown, applied to a data analysis system, and the method comprises the following steps 110-140.

[0047] In the research and application process of implanted chip devices (which can be divided into two types according to the two functions of physiological index monitoring and active intervention: monitoring devices and control devices; among them, the monitoring device is the basis, and the further development is the control device; The control device is based on the data obtained by monitoring, and then generates a control signal), simulating and analyzing the data of its running environment is a crucial task, which not only helps to optimize the design of the chip, but also improves its performance and stability in real application scenarios.

[0048] Step 110, obtaining chip running environment simulation data, the chip running environment simulation data comprising running state data of the implanted chip device in the simulated running environment, the implanted chip device and the simulated running environment being in a one-to-many relationship.

[0049] First, the data analysis system needs to obtain the running state data of the implanted chip device in the simulated running environment. The running state data is generated by a professional simulator, which can accurately replicate various environments and conditions that the chip may encounter in actual application. There is a one-to-many relationship between the implanted chip device and the simulated running environment, that is, a type of chip can be tested in multiple different simulated environments to comprehensively evaluate its performance.

[0050] The running state data includes but is not limited to the chip's power consumption, signal transmission efficiency, data processing speed, temperature fluctuation, electromagnetic compatibility, etc. These data are recorded in the form of time series, and each time point corresponds to the specific performance of the chip at that time. Through such a data collection method, comprehensive and detailed monitoring of the performance of the chip can be ensured.

[0051] Step 120, for the current performance simulation tag corresponding to the implanted chip device in the chip running environment simulation data, call the target chip state evaluation algorithm to obtain the first group of chip evaluation optimization viewpoints corresponding to the current performance simulation tag based on the chip running environment simulation data. The target chip state evaluation algorithm has completed the training and debugging based on the environment simulation response vector of the simulated running environment.

[0052] Next, the data analysis system calls a pre-trained target chip state evaluation algorithm for the current performance simulation tag in the chip running environment simulation data. The target chip state evaluation algorithm has completed training and debugging based on the environment simulation response vector of the simulated running environment, and can accurately output evaluation and optimization suggestions for chip performance based on the input running state data.

[0053] The current performance simulation tag refers to one or more key performance indicators of the chip in a specific simulation environment, such as power consumption optimization, signal stability, etc. The target chip state evaluation algorithm generates the first group of chip evaluation optimization viewpoints by analyzing the running state data corresponding to these tags. The first group of chip evaluation optimization viewpoints can include adjusting the design parameters of the chip, optimizing the power management strategy, improving the signal transmission protocol, etc., aiming to improve the overall performance of the chip in the simulation environment.

[0054] Step 130, call the target chip state evaluation algorithm to obtain at least one second group of chip evaluation optimization viewpoints corresponding to the current performance simulation tag based on the chip running environment simulation data and at least one attention feature, the attention feature is generated based on the chip running environment simulation data and used as a feature to indicate the output chip evaluation optimization viewpoint.

[0055] In order to further tap the potential of chip performance optimization, the data analysis system further calls the target chip state evaluation algorithm, but this time, in addition to the chip running environment simulation data, at least one attention feature is introduced. The attention feature is generated based on the chip running environment simulation data and used as a feature to indicate the output chip evaluation optimization viewpoint, which can help the algorithm pay more attention to factors that have a significant impact on chip performance.

[0056] For example, if the attention feature points to abnormal power fluctuations of the chip within a certain time period, the target chip state evaluation algorithm will focus more on analyzing the data within this period of time, trying to find out the reasons for the power fluctuations and proposing corresponding optimization measures. In this way, at least one second group of chip evaluation optimization viewpoints can be generated, which are more specific and targeted, and can directly point to the key points of chip performance optimization.

[0057] Step 140: From the first set of chip evaluation optimization perspectives and the at least one second set of chip evaluation optimization perspectives, determine the target chip evaluation optimization perspective corresponding to the current performance simulation label.

[0058] Finally, the data analysis system needs to determine the target chip evaluation optimization perspective corresponding to the current performance simulation label from the first set of chip evaluation optimization perspectives and the at least one second set of chip evaluation optimization perspectives. This step involves comprehensive consideration of multiple optimization perspectives, including their feasibility, expected effect, implementation cost, and other factors.

[0059] Specifically, the data analysis system can use a multi-objective decision-making method such as the Analytic Hierarchy Process (AHP) or Grey Relational Analysis (GRA) to assign weights and rank the optimization perspectives. Through this method, the priority relationship between different optimization perspectives can be quantified, so that the target chip evaluation optimization perspective that best meets the current needs can be selected.

[0060] For example, if an optimization perspective can significantly improve the power efficiency of the chip while the implementation cost is relatively low, it is likely to be selected as the target chip evaluation optimization perspective. Once the target perspective is determined, the data analysis system will feed it back to the chip design team so that they can make adjustments and optimizations based on actual conditions.

[0061] Through the above steps, the data analysis system can comprehensively and deeply analyze the performance of the implantable chip device in the simulated running environment and provide specific optimization suggestions. In this way, it not only helps to improve the design quality of the chip, but also speeds up its promotion and application in actual application scenarios.

[0062] It should be noted that implantable chip devices are implanted in vivo for patients in actual applications, so their actual running environment is extremely complex, involving multiple physiological, physical, and biochemical factors. In order to better understand and optimize the performance of such chips, a simulated running environment has become an indispensable tool. The one-to-many relationship between implantable chip devices and simulated running environments is established based on the complexity and diversity of such needs.

[0063] The one-to-many relationship means that one type of implantable chip device can be tested in multiple different simulation environments. This is because the actual in vivo implantation environment is constantly changing, and each patient's physiological condition, implantation site, surrounding tissue characteristics, and other factors may be different. Therefore, in order to comprehensively evaluate the performance of the chip, it needs to be tested in multiple simulation environments to ensure that it can perform well in various possible actual environments.

[0064] Based on this, the simulation running environment needs to match the actual living body implant running environment as much as possible. First, the simulation environment will consider the physiological factors of the patient. For example, patients of different ages, genders, weights, and health conditions have significant differences in their internal environment. The simulation environment will simulate the physiological conditions of different patients by adjusting parameters such as temperature, humidity, and pH, etc., to test the stability and performance of the chip under these conditions. Second, the simulation environment will also consider the impact of the implant site. Implantable chip devices may be implanted in the brain, spinal cord, or other neural tissues, and the microenvironment of each site is different. The simulation environment will simulate the microenvironment of these different sites, including blood flow speed, cell density, and electrolyte concentration, to evaluate the adaptability and effect of the chip in different implant sites. Then, the simulation environment will also consider external interference factors. In actual operation, the chip may be affected by electromagnetic interference, mechanical vibration, chemical corrosion, and other external factors. The simulation environment will simulate these interference factors to test the anti-interference ability and stability of the chip. Finally, the simulation environment will also conduct long-term running tests. The actual living body implant environment is a long-term and dynamic environment, and the chip needs to run stably for a long time. The simulation environment will conduct long-term continuous tests to evaluate the durability and long-term performance of the chip.

[0065] As can be seen, the simulation running environment considers the physiological factors of the patient, the impact of the implant site, external interference factors, and long-term running tests, etc., to match the actual living body implant running environment as much as possible. In this way, the test results of the implantable chip device in the simulation environment can more accurately reflect its performance in actual operation, providing strong support for the optimization and improvement of the chip.

[0066] It is worth mentioning that in step 120, the focus is on in-depth evaluation and optimization of the performance of the implantable chip device in the simulation running environment. The core of this process is to call a carefully designed target chip state evaluation algorithm that has been strictly trained and debugged based on the environment simulation response vector, ensuring that it can accurately capture and analyze the behavior characteristics of the chip under different simulation environments.

[0067] First of all, these labels of "current performance performance simulation labels" are predefined to identify the performance dimensions of the chip under specific simulation environments, such as power efficiency, signal stability, electromagnetic compatibility, etc. Each label represents an important aspect of chip performance and is a key indicator for evaluating its overall performance.

[0068] Next, the core of the algorithm lies in how to utilize the chip running environment simulation data to generate optimization viewpoints for the current performance simulation label. Here, the environment simulation response vector plays a crucial role. The environment simulation response vector is a multidimensional dataset that comprehensively reflects the impact of the simulation environment on chip performance. The environment simulation response vector contains various parameters such as temperature, humidity, electromagnetic field strength, and implant site microenvironment characteristics, each representing an aspect of the simulation environment and closely related to the specific performance of the chip.

[0069] During the training and debugging phase of the algorithm, the environment simulation response vector is used as input to train the algorithm model through a large amount of simulation experiment data. These experimental data cover a wide range of simulation environment conditions and chip performance, ensuring that the algorithm can learn the complex relationship between the environment and performance. Through this process, the algorithm learns how to predict and evaluate the performance of the chip based on the environment simulation response vector.

[0070] When entering the actual application stage, i.e., step 120, the algorithm first receives the current performance simulation label and the corresponding chip running environment simulation data. Then, it extracts the environment simulation response vector as the input of the algorithm. Inside the algorithm, a series of complex calculations and analysis processes are carried out. These processes can include feature extraction, pattern recognition, regression analysis, etc., aiming to extract key information related to the current performance simulation label from the environment simulation response vector.

[0071] Finally, the algorithm outputs the first set of chip evaluation optimization viewpoints. The first set of chip evaluation optimization viewpoints is based on the comprehensive evaluation of the chip performance in the current simulation environment, and they may point to the improvement direction of the chip design, such as adjusting the circuit design, optimizing material selection, improving packaging process, etc. The specific content of the optimization viewpoints depends on the specific content of the current performance simulation label and the environment simulation response vector, but in any case, they are important suggestions aimed at improving the performance and stability of the chip in actual application.

[0072] For example, if the current performance simulation label is "power efficiency" and the environment simulation response vector shows that the power consumption of the chip is abnormally high in the current simulation environment, the algorithm may output optimization viewpoints such as optimizing power management strategy, reducing circuit leakage current, and using low-power materials. These viewpoints will directly guide the chip design team to carry out subsequent improvement work, thus promoting the continuous progress of implantable chip device technology.

[0073] In combination with the above, step 130 further deepens the performance evaluation and optimization work of the implanted chip device in the simulated running environment. In this step, the target chip state evaluation algorithm that has been trained and debugged is called again, but this time at least one attention feature is introduced in addition to the basic chip running environment simulation data. These attention features are carefully generated based on the chip running environment simulation data, and they act like a compass, guiding the algorithm to focus more on specific aspects that have a significant impact on chip performance.

[0074] First of all, it is necessary to understand the importance of attention features. In a complex simulation environment, the performance of a chip may be influenced by multiple factors, and attention features can be a tool to help identify the most critical factors. They may be a certain parameter in the simulation environment, such as the strength of electromagnetic interference, or a prominent fluctuation in chip performance, such as a sudden increase in power consumption. By introducing attention features, the algorithm can be guided to explore the specific impact of these key factors on chip performance more deeply.

[0075] Next, when the algorithm receives the chip running environment simulation data and the attention features, it will analyze these information comprehensively. In this process, the algorithm will pay special attention to the environment simulation response vectors related to the attention features. As mentioned earlier, the environment simulation response vector is a multidimensional data set that reflects the overall impact of the simulation environment on chip performance. In step 130, the algorithm will use this vector to more accurately evaluate the performance of the chip in the current simulation environment, especially those aspects closely related to the attention features.

[0076] Then, based on this in-depth analysis, the algorithm will generate at least one second set of chip evaluation and optimization viewpoints. These viewpoints are further refinement and supplement to the current performance simulation labels, which may reveal previously undiscovered performance optimization potential, or provide more specific improvement suggestions. For example, if the attention features point to the impact of electromagnetic interference on chip signal stability, the second set of optimization viewpoints may include adjusting the electromagnetic shielding design of the chip, or optimizing the signal transmission protocol to reduce interference.

[0077] Finally, these second set of chip evaluation and optimization viewpoints will be combined with the previous first set of viewpoints to form a comprehensive evaluation and optimization suggestion for the performance of the chip. Such a double evaluation mechanism ensures that the optimization work of the chip performance is both comprehensive and in-depth, and can fully tap the potential optimization space of the chip in the simulation environment.

[0078] The present application realizes comprehensive evaluation and optimization of chip performance by obtaining running state data of implanted chip devices in simulated running environments.

[0079] Firstly, by constructing a one-to-many relationship, the application can simulate a variety of different living implant environments, thereby ensuring a more comprehensive and accurate evaluation of chip performance. Secondly, by using a target chip state evaluation algorithm that has completed environment simulation response vector training and debugging based on a simulated operating environment, the application can simulate a label for the current performance of the chip, generate a first set of chip evaluation optimization points, and provide strong guidance for the design and improvement of the chip. Further, by introducing at least one attention feature generated based on chip operating environment simulation data, the application can more deeply explore key factors affecting chip performance and generate at least a second set of chip evaluation optimization points, further enriching the dimensions and depth of chip performance optimization. Finally, by integrating the first and second sets of chip evaluation optimization points, the application can determine a target chip evaluation optimization point for the current performance simulation label, providing a clear direction for the final optimization and practical application of the chip.

[0080] In summary, the application significantly improves the performance evaluation and optimization efficiency of implantable chip devices in a simulated operating environment, laying a solid foundation for the practical application of implantable chip devices.

[0081] In some optional embodiments, the calling of the target chip state evaluation algorithm based on the chip operating environment simulation data and at least one attention feature to obtain at least one second set of chip evaluation optimization points corresponding to the current performance simulation label includes: for a target attention feature in the at least one attention feature, combining the target attention feature with the chip operating environment simulation data to obtain chip operating environment attention data; calling the target chip state evaluation algorithm to process the chip operating environment attention data to obtain a second set of chip evaluation optimization points output by the current performance simulation label under the indication of the target attention feature.

[0082] In actual implementation, the process of calling the target chip state evaluation algorithm based on the chip operating environment simulation data and at least one attention feature to obtain at least one second set of chip evaluation optimization points corresponding to the current performance simulation label is a key and innovative technical implementation. This process not only requires the algorithm to have high accuracy and sensitivity, but also requires it to effectively process and analyze complex data sets, thereby deriving points that have practical guiding significance for chip performance optimization.

[0083] Firstly, attention features play a crucial role in this process. Attention features are generated based on the chip runtime environment simulation data, and they guide the algorithm to focus more on specific aspects that have a significant impact on chip performance. These features could be a key parameter in the simulation environment, such as the strength of electromagnetic interference, or a prominent fluctuation in chip performance, such as a sudden increase in power consumption. By introducing attention features, the data analysis system can delve deeper into the specific impact of these key factors on chip performance, leading to more accurate and targeted optimization insights.

[0084] After determining the attention features, the next step is to combine the target attention features with the chip runtime environment simulation data. The purpose of this step is to generate a new dataset, namely the chip runtime environment attention data. This dataset not only contains the original simulation environment data but also incorporates the key information indicated by the attention features. Through such a combination, the algorithm can focus more on aspects related to attention features when processing data, leading to more accurate and in-depth evaluation results.

[0085] Next, the chip runtime environment attention data can be processed by invoking the target chip state evaluation algorithm. This algorithm has already completed the training and debugging of the environment simulation response vector based on the simulated runtime environment, so it has the ability to evaluate the performance of the chip in the simulated environment. When the algorithm receives the chip runtime environment attention data, it will use its internal complex calculation and analysis mechanism to deeply mine and analyze the data. This process can include feature extraction, pattern recognition, regression analysis, and other steps, aiming to extract key information related to the current performance simulation label from the data.

[0086] Finally, after processing and analysis by the algorithm, the data analysis system will obtain a second set of chip evaluation optimization insights output by the current performance simulation label under the guidance of the target attention features. These insights are further refinement and supplement to the chip performance, which may reveal previously undiscovered performance optimization potential or provide more specific improvement suggestions. For example, if the attention features point to the impact of electromagnetic interference on chip signal stability, the second set of optimization insights may include adjusting the electromagnetic shielding design of the chip or optimizing the signal transmission protocol to reduce interference.

[0087] In this way, by introducing attention features and combining them with chip running environment simulation data, and then calling the target chip state evaluation algorithm for processing and analysis, more accurate and targeted chip evaluation optimization views are ultimately obtained. This process not only improves the accuracy and efficiency of chip performance evaluation, but also provides more specific and targeted guidance for chip optimization and improvement. In this way, the data analysis system can more confidently apply these optimized chips to actual living implantation environments.

[0088] In some alternative embodiments, the calling of the target chip state evaluation algorithm to process the chip running environment attention data to obtain a second set of chip evaluation optimization views output by the current performance simulation label under the indication of the target attention feature includes: obtaining a state simulation time sequence vector of the chip running environment attention data; for each attention data unit in the chip running environment attention data, integrating the data unit distribution feature, state running association feature and simulation task demand feature corresponding to the attention data unit with the state simulation time sequence vector corresponding to the attention data unit to obtain a linkage state simulation time sequence vector corresponding to the target chip state evaluation algorithm; calling the target chip state evaluation algorithm to process the linkage state simulation time sequence vector to obtain a second set of chip evaluation optimization views output by the current performance simulation label under the indication of the target attention feature.

[0089] In this embodiment, calling the target chip state evaluation algorithm to process the chip running environment attention data to obtain a second set of chip evaluation optimization views output by the current performance simulation label under the indication of the target attention feature is a complex and delicate process. This process not only involves in-depth processing of attention data, but also requires the algorithm to accurately capture and analyze key information in the data, so as to derive views that have practical guiding significance for chip performance optimization.

[0090] First, the data analysis system needs to obtain a state simulation time sequence vector of the chip running environment attention data. The state simulation time sequence vector is an important data structure that records the state information of the chip changing over time in the simulated running environment. This vector contains multiple time points, each of which corresponds to the running state of the chip at a specific time. By obtaining the state simulation time sequence vector, the data analysis system can more comprehensively understand the performance of the chip in the simulation environment, thereby providing strong data support for subsequent evaluation and optimization work.

[0091] Secondly, for each attention data unit in the chip running environment attention data, the data analysis system needs to integrate its corresponding data unit distribution features, state running correlation features, and simulation task demand features with the state simulation time sequence vector corresponding to the attention data unit. The purpose of this step is to combine the key information in the attention data unit with the state simulation time sequence vector to generate a linked state simulation time sequence vector containing rich information. The data unit distribution features describe the distribution of the attention data unit in the overall data set, which helps the data analysis system understand the importance and representativeness of the data unit. The state running correlation features reveal the correlation between the attention data unit and the chip running state, which helps the data analysis system identify factors that have a significant impact on chip performance. The simulation task demand features reflect the specific requirements of the simulation task on chip performance, which ensures that the data analysis system can closely focus on actual needs when evaluating and optimizing chip performance.

[0092] After completing the integration work described above, the data analysis system obtains the linked state simulation time sequence vector corresponding to the target chip state evaluation algorithm. This vector not only contains comprehensive state information of the chip in the simulation environment, but also integrates key features in the attention data unit. This enables the data analysis system to more accurately capture factors that have a significant impact on performance when evaluating and optimizing chip performance, and to provide targeted optimization recommendations accordingly.

[0093] Finally, the linked state simulation time sequence vector can be processed by calling the target chip state evaluation algorithm. This algorithm has completed the training and debugging of the environment simulation response vector based on the simulation running environment, so it has the ability to evaluate the performance of the chip in the simulation environment. When the algorithm receives the linked state simulation time sequence vector, it uses its internal complex calculation and analysis mechanism to deeply mine and analyze the data. This process may include feature extraction, pattern recognition, regression analysis, and other steps aimed at extracting key information related to the current performance simulation label from the data.

[0094] After processing and analysis by the algorithm, the data analysis system ultimately obtains a second set of chip evaluation and optimization viewpoints output by the current performance simulation label under the guidance of the target attention features. These viewpoints are further refinement and supplement to the chip performance, which may reveal previously undiscovered performance optimization potential or provide more specific improvement suggestions. For example, if the attention features point to the impact of electromagnetic interference on chip signal stability, the second set of optimization viewpoints may include adjusting the electromagnetic shielding design of the chip or optimizing the signal transmission protocol to reduce interference.

[0095] With this design, by obtaining the state simulation time series vector of the chip running environment attention data and integrating it with the key features in the attention data unit, and then calling the target chip state evaluation algorithm for processing and analysis, a more accurate and targeted chip evaluation and optimization view is obtained. This process not only improves the accuracy and efficiency of chip performance evaluation, but also provides more specific and targeted guidance for chip optimization and improvement. In this way, the data analysis system can more confidently apply these optimized chips to actual living implantation environments, providing patients with more secure and accurate monitoring and control processing.

[0096] At the same time, this embodiment also fully demonstrates the important role of data processing and algorithm analysis in the chip development and optimization process. Through in-depth mining and analysis of chip running environment attention data, the data analysis system can more accurately capture factors that have a significant impact on chip performance and make targeted optimization recommendations accordingly.

[0097] In the application scenario of implantable chip devices, state simulation time series vector, data unit distribution feature, state running correlation feature, simulation task demand feature, and linkage state simulation time series vector are key technical features, which together form the basis of chip performance evaluation and optimization.

[0098] First, in the simulation environment of implantable chip devices, the state simulation time series vector records the state information of the chip over time, such as signal transmission stability, power consumption fluctuations, etc. For example, in a simulation experiment, the signal stability state of the chip at five consecutive time points is recorded, and the possible state simulation time series vector can be [0.9, 0.85, 0.9, 0.8, 0.95]. These values represent the simulation evaluation results of the chip signal stability at each time point, with a value close to 1 indicating signal stability and a value close to 0 indicating signal instability.

[0099] Second, data unit distribution features are particularly important in implantable chip devices, as they involve the complexity of the chip running environment. Suppose the data analysis system classifies attention data units according to their sources, such as physiological signal data, external interference data, etc., and calculates the proportion of each type of data unit in the overall data set. Then, an example data unit distribution feature vector can be [0.6, 0.4], indicating that physiological signal data accounts for 60% and external interference data accounts for 40%.

[0100] Then, the state-operation correlation feature needs to be considered. In the development of the implantable chip device, this feature reveals the correlation between the attention data unit and the chip's operational state, such as whether the fluctuations in physiological signal data are related to the rise in chip power consumption. For example, a correlation analysis is conducted, and a state-operation correlation feature matrix is obtained: [[0.75, -0.5], [0.3, 0.2]]. The first row of this matrix represents the correlation strength between physiological signal data and signal stability, power consumption, and the second row represents the correlation strength between external interference data and these two. Positive values indicate positive correlation, and negative values indicate negative correlation.

[0101] Next is the simulation task requirement feature. In the development process of the implantable chip device, simulation tasks usually have clear requirements, such as ensuring signal transmission stability, reducing power consumption, etc. These requirements can be represented by a numerical vector, where each element corresponds to a performance requirement, and the value of the vector represents the priority of the requirement. For example, the simulation task requirement feature vector can be [0.8, 0.6], indicating that the priority of signal stability is higher than that of power consumption reduction.

[0102] Finally, the data analysis system integrates these key features into the linkage state simulation time series vector. This vector not only contains comprehensive state information of the chip in the simulation environment, but also incorporates key features in the attention data unit and specific requirements of the simulation task. Through some form of integration, such as weighted summation or splicing, the data analysis system can obtain a linkage state simulation time series vector that contains all the key information. The data analysis system chooses splicing operation for integration, and constructs each feature vector and matrix according to the above example, then a possible linkage state simulation time series vector can be [0.9, 0.85, 0.9, 0.8, 0.95, 0.6, 0.4, 0.75, -0.5, 0.3, 0.2, 0.8, 0.6]. This vector comprehensively reflects the performance of the implantable chip device in the simulation environment, as well as the influence of the attention data unit and the simulation task requirements on performance evaluation.

[0103] In some possible embodiments, the attention feature includes an environment simulation response vector of the simulated running environment or a noisy label feature of the chip running environment simulation data; wherein the environment simulation response vector includes at least one of the following: a response state feature, a response state heat map, an environmental element offset, and a potential anomaly description vector; and the combining the target attention feature with the chip running environment simulation data to obtain chip running environment attention data includes: on the basis that the target attention feature is the environment simulation response vector, fusing the environment simulation response vector to a corresponding local environment data set of the implantable chip device in the chip running environment simulation data to obtain the chip running environment attention data; or on the basis that the target attention feature is the noisy label feature, fusing the noisy label feature to an environment noise data set of the chip running environment simulation data to obtain the chip running environment attention data.

[0104] In this embodiment, it is related to how to effectively combine the target attention feature with the chip running environment simulation data to generate the chip running environment attention data. The core of this technical solution is that by finely combining the attention feature with the simulation data, the data analysis system can more accurately simulate and evaluate the performance of the implantable chip device in the actual running environment.

[0105] Firstly, the attention feature can include an environment simulation response vector of the simulated running environment or a noisy label feature of the chip running environment simulation data. The environment simulation response vector is a multi-dimensional representation that contains various information about how the simulation environment responds to the chip running. Specifically, the environment simulation response vector can include a response state feature, which describes various states of the chip when running in the simulation environment; a response state heat map, which graphically displays the response intensity of the chip in different states; an environmental element offset, which reflects the deviation degree of various elements (such as temperature, humidity, etc.) in the simulation environment; and a potential anomaly description vector, which provides a quantitative description of possible abnormal situations in the simulation environment.

[0106] Next, the data analysis system considers how to combine the target attention feature with the chip running environment simulation data. According to the different attention features, the data analysis system adopts two different strategies.

[0107] In the first strategy, if the target attention feature is an environmental simulation response vector, the data analysis system fuses it into the corresponding local environmental data set in the chip operation environment simulation data of the implanted chip device. The key to this step is that the data analysis system identifies the local environmental data set in the simulation data that is directly related to the operation of the specific chip, and injects the rich information in the environmental simulation response vector into it. In this way, the data analysis system obtains the chip operation environment attention data, which not only contains the original simulation environment information, but also integrates the detailed description of how the environment responds to the chip operation. For example, if the environmental simulation response vector indicates that the response state of the chip will change under certain temperature and humidity conditions, the data analysis system will pay special attention to the local environmental data set under this condition when generating the chip operation environment attention data, and embed the corresponding response state feature in it.

[0108] In the second strategy, if the target attention feature is a noise label feature, the data analysis system fuses it into the environmental noise data set of the chip operation environment simulation data. The noise label feature is an abstract representation of the environmental noise in the simulation data, which may contain information about the type, intensity, frequency, etc. of the noise. By fusing the noise label feature into the environmental noise data set, the data analysis system can generate more realistic chip operation environment attention data. This is because, in the actual chip operation environment, noise is an inevitable factor, and the noise label feature allows the data analysis system to accurately simulate and control the impact of noise in the simulation data. For example, if the noise label feature indicates that the intensity of environmental noise will increase significantly within a certain time period, the data analysis system will adjust the environmental noise data set accordingly when generating the chip operation environment attention data to reflect the impact of this noise change on the chip operation.

[0109] Regardless of the strategy, the goal of the data analysis system is to generate more accurate and more useful chip operation environment attention data by skillfully combining attention features with chip operation environment simulation data. These data not only contain detailed information about the simulation environment, but also integrate deep insights into how the environment affects the operation of the chip. This has extremely important value for the research and optimization of implanted chip devices, as it allows the data analysis system to accurately simulate and evaluate the performance of the chip under various possible environmental conditions before actual deployment.

[0110] Furthermore, generating chip operating environment attention data is a highly complex and sophisticated task. It requires the data analysis system to not only deeply understand the chip's operating mechanisms and the impact of environmental factors, but also to master advanced simulation and data processing techniques. To achieve this, the data analysis system may need to utilize a range of advanced algorithms and tools, such as machine learning algorithms, data fusion techniques, and multidimensional data analysis tools. Through these techniques, the data analysis system can effectively mine and utilize information from attention features, deeply integrating it with chip operating environment simulation data to generate rich and highly accurate chip operating environment attention data.

[0111] Furthermore, it's worth noting that generating chip operating environment attention data is not a one-time event. In actual R&D and optimization, the data analysis system may need to continuously iterate and update this data. This is because, as the data analysis system's understanding of chip and environmental factors deepens, and with the emergence of new simulation and data processing technologies, the system has the opportunity to generate more accurate and comprehensive chip operating environment attention data. This continuous data iteration and updating process is a crucial driving force behind the continuous progress and optimization of implantable chip device technology.

[0112] It is evident that by cleverly combining target attention features with simulated chip operating environment data, the data analysis system can generate rich and highly accurate chip operating environment attention data. This data is of paramount value for the research and optimization of implantable chip devices, as it allows the data analysis system to accurately simulate and evaluate their performance under various possible environmental conditions before actual chip deployment. Through continuous iteration and updating of this data, the data analysis system is expected to drive the continuous advancement and optimization of implantable chip device technology.

[0113] In another preferred design approach, determining the target chip evaluation and optimization viewpoint corresponding to the current performance simulation label from the first group of chip evaluation and optimization viewpoints and the at least one second group of chip evaluation and optimization viewpoints includes: obtaining the confidence weight coefficients corresponding to the first group of chip evaluation and optimization viewpoints and the confidence weight coefficients corresponding to each of the second group of chip evaluation and optimization viewpoints through a weighted decision tree network, wherein the confidence weight coefficients are used to indicate the degree of matching between the chip evaluation and optimization viewpoints and the simulated operating environment; and determining the chip evaluation and optimization viewpoint with the largest confidence weight coefficient among the first group of chip evaluation and optimization viewpoints and each of the second group of chip evaluation and optimization viewpoints as the target chip evaluation and optimization viewpoint.

[0114] Under this design idea, the process of determining the target chip evaluation optimization viewpoint corresponding to the current performance simulation label by the data analysis system from the first group of chip evaluation optimization viewpoints and at least one second group of chip evaluation optimization viewpoints is a complex task of comprehensively considering various factors and making the best choice. The core goal of this task is to find the evaluation optimization viewpoint that best matches the simulated running environment and most accurately reflects the performance of the chip. To achieve this goal, the data analysis system adopts a weight decision tree network-based method that can accurately calculate the matching degree of each chip evaluation optimization viewpoint with the simulated running environment, i.e., the confidence weight coefficient.

[0115] Firstly, the data analysis system needs to understand what a chip evaluation optimization viewpoint is. Simply put, a chip evaluation optimization viewpoint is a subjective or objective evaluation or suggestion of the performance of a chip, which may be based on data and experience from various aspects such as chip design, manufacturing, testing, etc. In the context of the data analysis system, there are two main types of chip evaluation optimization viewpoints: the first group is based on general or standard evaluation indicators, while the second group is based on customized evaluation indicators according to specific application scenarios or requirements.

[0116] Next, the data analysis system introduces how to obtain the confidence weight coefficient of these chip evaluation optimization viewpoints through the weight decision tree network. The weight decision tree network is a machine learning model that can predict the output of new data by learning a large amount of historical data and patterns. In this scenario, the data analysis system takes the first and second groups of chip evaluation optimization viewpoints as input and various features of the simulated running environment (such as temperature, humidity, electromagnetic interference, etc.) as contextual information to train the weight decision tree network. After training, this network can output a confidence weight coefficient based on the input chip evaluation optimization viewpoints and the features of the simulated running environment. This coefficient is a value between 0 and 1, which represents the matching degree of the chip evaluation optimization viewpoint with the simulated running environment. The closer the coefficient is to 1, the higher the matching degree; the closer the coefficient is to 0, the lower the matching degree.

[0117] After obtaining the confidence weight coefficients of all chip evaluation optimization viewpoints, the data analysis system enters the stage of determining the target chip evaluation optimization viewpoint. The key to this step is to select the viewpoint with the largest confidence weight coefficient from all candidate viewpoints. This is because the largest confidence weight coefficient means that this viewpoint has the highest matching degree with the simulated running environment and can most accurately reflect the performance of the chip in the simulated running environment. Therefore, the data analysis system determines this viewpoint as the target chip evaluation optimization viewpoint.

[0118] However, this process is not always the same. In practical applications, the data analysis system may also need to consider other factors. For example, if the confidence weight coefficient of a second group of chip evaluation optimization views is not the largest, but it is not much different from the coefficients of other views, and this view is based on a very important application scenario, the data analysis system may give it more attention. In addition, if the confidence weight coefficient of a view is always low, the data analysis system may reconsider the effectiveness of this view, or even exclude it from the candidate views.

[0119] In addition, the weight decision tree network is not a one-time thing. It needs the data analysis system to continuously train and optimize with new data and feedback. Only in this way, it can more accurately calculate the confidence weight coefficients of each chip evaluation optimization view, so as to help the data analysis system better determine the target chip evaluation optimization view.

[0120] Therefore, from the first group of chip evaluation optimization views and at least one second group of chip evaluation optimization views, the target chip evaluation optimization view corresponding to the current performance simulation label is determined, which is a complex process that needs to consider various factors and task objectives. By using the weight decision tree network-based method, the data analysis system can more scientifically and accurately complete this task. This not only helps to improve the understanding and evaluation ability of the data analysis system for chip performance, but also can provide more powerful support and guidance for the research and optimization of chips. In future work, the data analysis system will continue to explore and optimize this method, in order to make greater breakthroughs and progress in the field of chip evaluation and optimization.

[0121] In the following steps, before the first group of chip evaluation optimization views and each second group of chip evaluation optimization views are determined as the target chip evaluation optimization view with the largest confidence weight coefficient, the following steps are further included: on the basis that there is an evaluation optimization label with a real performance prediction weight not less than a prediction weight threshold in the preliminary screening chip evaluation optimization view, the confidence weight coefficient corresponding to the preliminary screening chip evaluation optimization view is increased; or, on the basis that the feature commonality value between the preliminary screening chip evaluation optimization view and the key performance characterization vector is not less than a preset commonality value, the confidence weight coefficient corresponding to the preliminary screening chip evaluation optimization view is increased, the key performance characterization vector is used to represent the environment simulation response vector of the simulation running environment; wherein, the preliminary screening chip evaluation optimization view includes the first group of chip evaluation optimization views and each second group of chip evaluation optimization views.

[0122] In the next step, for the specific application scenario of implantable chip devices, the data analysis system conducts a series of in-depth and meticulous preprocessing and judgment before determining the target chip evaluation optimization view as the first group of chip evaluation optimization views and the chip evaluation optimization view with the largest confidence weight coefficient in each second group. This process aims to ensure that the selected target chip evaluation optimization view not only has the largest confidence weight coefficient, but also meets the key performance and feature requirements of implantable chip devices in real application scenarios.

[0123] First, the preliminary screening chip evaluation optimization view includes the first group of chip evaluation optimization views based on general or standard evaluation indicators, and the second group of views based on customized evaluation indicators for specific application scenarios or requirements of implantable chip devices. These views may be quite large in number, but they all have certain potential value and significance. However, to determine the target chip evaluation optimization view that is most suitable for implantable chip devices, the data analysis system cannot simply rely on the size of the confidence weight coefficient. This is because, although the confidence weight coefficient can reflect the matching degree of the chip evaluation optimization view and the simulation running environment, it may not fully reflect the practicality and accuracy of the view in real application scenarios.

[0124] Therefore, other important factors need to be considered, one of which is the real performance prediction weight. The real performance prediction weight is an indicator that measures the chip evaluation optimization view's ability to predict the performance of chips in real application scenarios. For implantable chip devices, their real application scenarios may involve complex physiological environments, electromagnetic interference, biocompatibility, and other aspects. If the real performance prediction weight of a preliminary screening chip evaluation optimization view is not less than the prediction weight threshold set by the data analysis system, it means that this view has high accuracy in predicting the performance of implantable chip devices in real application scenarios. In this case, the data analysis system will increase the confidence weight coefficient corresponding to this preliminary screening chip evaluation optimization view to indicate that it is more important in determining the target chip evaluation optimization view.

[0125] Another important factor is the feature commonality value between the screening chip evaluation optimization view and the key performance characterization vector. The key performance characterization vector is an important indicator for representing the environment simulation response vector of the simulated running environment, which contains key information about the impact of the simulated running environment on chip performance. For implantable chip devices, their key performance characterization vector may include signal transmission stability, biocompatibility, performance attenuation after long-term implantation, and other aspects. If the feature commonality value between a certain screening chip evaluation optimization view and the key performance characterization vector is not less than the preset commonality value of the data analysis system, it means that this view has a high commonality with the key performance characteristics of the implantable chip device in the real application scenario. In this case, the data analysis system will also increase the confidence weight coefficient corresponding to this screening chip evaluation optimization view, indicating that it is more important in determining the target chip evaluation optimization view.

[0126] By increasing the confidence weight coefficient corresponding to the screening chip evaluation optimization view that meets the above conditions, the data analysis system can more comprehensively and accurately determine the target chip evaluation optimization view suitable for implantable chip devices. This is because the data analysis system not only considers the size of the confidence weight coefficient, but also considers the prediction ability of the chip evaluation optimization view in the real application scenario and the commonality with the key performance characteristics. This can ensure that the finally selected target chip evaluation optimization view not only has a high confidence, but also has high practicality and accuracy.

[0127] In practical applications, there are many ways to increase the confidence weight coefficient corresponding to the screening chip evaluation optimization view. For example, the data analysis system can use a rule-based increasing method, that is, when a certain screening chip evaluation optimization view meets the above conditions, it increases its confidence weight coefficient according to the predetermined rules. The advantage of this method is simple and easy to understand, and easy to operate. Another method is a model-based increasing method, that is, the data analysis system can establish a model to predict the size of the confidence weight coefficient that the screening chip evaluation optimization view should increase when it meets the above conditions. The advantage of this method is that it can more accurately predict and increase the confidence weight coefficient, but it requires certain modeling and calculation costs. No matter which method is used, the data analysis system needs to ensure that the increased amplitude and method are reasonable and scientific to avoid adverse effects on the final target chip evaluation optimization view.

[0128] Moreover, in determining the target chip evaluation optimization perspective, the relative importance and relevance between different preliminary screening chip evaluation optimization perspectives also need to be considered. Since the application scenarios of implantable chip devices may involve multiple different aspects and factors, different preliminary screening chip evaluation optimization perspectives may have different importance and relevance. For example, one perspective may mainly focus on the stability of signal transmission, while another perspective may mainly focus on biocompatibility. In determining the target chip evaluation optimization perspective, the data analysis system needs to consider these factors comprehensively to ensure that the finally selected perspective is the optimal choice that can fully reflect the performance of implantable chip devices in real application scenarios.

[0129] In this way, before determining the chip evaluation optimization perspective with the largest confidence weight coefficient in the first group of chip evaluation optimization perspectives and each second group of chip evaluation optimization perspectives as the target chip evaluation optimization perspective, the data analysis system has carried out a series of in-depth and meticulous preprocessing and judgment. This includes considering the real performance prediction weight of the preliminary screening chip evaluation optimization perspective and the feature commonality value between the key performance characterization vector, and increasing the corresponding confidence weight coefficient according to these factors. Through this process, the data analysis system can more comprehensively and accurately determine the target chip evaluation optimization perspective suitable for implantable chip devices. The implementation of this technical solution not only can improve the understanding and evaluation ability of the data analysis system for the performance of implantable chip devices, but also can provide more powerful support and guidance for the research and optimization of chips.

[0130] In some preferred embodiments, the debugging step of the target chip state evaluation algorithm is as follows: obtaining a basic chip state evaluation algorithm, which is obtained by pre-debugging the simulation data pool of the running environment; determining an algorithm debugging example set from the chip simulation involvement log corresponding to the simulated running environment, the algorithm debugging example set including a first group of algorithm debugging examples carrying environmental simulation parameters corresponding to the simulated running environment, and a second group of algorithm debugging examples not carrying the environmental simulation parameters, the algorithm debugging examples in the algorithm debugging example set consisting of chip environment interaction response information; debugging the basic chip state evaluation algorithm through the algorithm debugging example set to obtain the target chip state evaluation algorithm after debugging.

[0131] In the specific application scenario of implantable chip devices, the debugging of the target chip state evaluation algorithm is a crucial step. This process aims to ensure that the algorithm can accurately and reliably evaluate the state of the chip in the real running environment, thereby providing strong support for the research, optimization and application of the chip. The following is a detailed and smooth exposition of this technical solution.

[0132] First, the basic chip state evaluation algorithm is obtained. The basic chip state evaluation algorithm does not come out of thin air, but is obtained through pre-debugging of the simulation data pool of the running environment. The simulated running environment is a highly simulated virtual environment that can simulate various situations and conditions that the implantable chip device may encounter in actual application. Through pre-debugging of this simulation data pool, the data analysis system can obtain a preliminary basic chip state evaluation algorithm, which already has certain evaluation ability and accuracy.

[0133] However, the algorithm obtained from the simulation data pool alone is not enough to cope with all the challenges in real application scenarios. Therefore, the data analysis system needs to further debug and optimize the basic chip state evaluation algorithm. This requires determining the algorithm debugging example set from the chip simulation involvement logs corresponding to the simulated running environment. This set includes two groups of algorithm debugging examples: the first group carries environmental simulation parameters corresponding to the simulated running environment, and the second group does not carry these environmental simulation parameters. Both groups of examples are composed of response information when the chip interacts with the environment, which contains various states and performances of the chip when running in the simulated running environment.

[0134] With this algorithm debugging example set, the data analysis system can begin to debug the basic chip state evaluation algorithm. The debugging process is a process of continuous trial and error and continuous optimization. The data analysis system needs to input the examples in the algorithm debugging example set into the basic chip state evaluation algorithm and observe whether the output results of the algorithm are consistent with the expectations. If they are consistent, it means that the algorithm performs well on this example; if they are not consistent, the algorithm needs to be adjusted and optimized accordingly.

[0135] During the debugging process, the data analysis system needs to pay special attention to the first group of algorithm debugging examples that carry environmental simulation parameters. Because these examples are closer to the situation in real application scenarios, they have higher value for the debugging and optimization of the algorithm. The data analysis system needs to ensure that the algorithm performs as expected on these examples, so as to have more confidence in applying the algorithm to real application scenarios.

[0136] Of course, the data analysis system cannot ignore the second group of algorithm debugging examples that do not carry environmental simulation parameters. Although they do not contain specific parameter information of the simulated running environment, they still contain response information when the chip interacts with the environment. These information also have important reference value for the debugging and optimization of the algorithm. The data analysis system needs to ensure that the algorithm performs well on these examples, so as to ensure the universality and stability of the algorithm.

[0137] Through repeated debugging and optimization, the data analysis system can gradually obtain the target chip state evaluation algorithm that has been debugged. This algorithm has been fully verified and tested, and has high accuracy and reliability. It can accurately evaluate the state of the implanted chip device in the real running environment, providing strong support for the research, optimization and application of the chip.

[0138] It is worth mentioning that during the debugging process, the data analysis system also needs to continuously verify and test the algorithm. Verification is to ensure that the output of the algorithm is consistent with the expectation, while testing is to test the performance of the algorithm in real application scenarios. Only through sufficient verification and testing, the data analysis system can ensure the accuracy and reliability of the algorithm.

[0139] In addition, during the debugging process, attention should be paid to some details. For example, the data analysis system needs to ensure that the examples in the algorithm debugging example set are comprehensive and representative, so as to ensure that the algorithm can learn the performance in various situations during the debugging process. At the same time, the data analysis system also needs to pay attention to the computational complexity and running time of the algorithm, to ensure that the algorithm can meet the real-time requirements in actual application.

[0140] In this way, the debugging of the target chip state evaluation algorithm of the implanted chip device is a complex and meticulous process. The data analysis system needs to determine the algorithm debugging example set from the chip simulation involvement logs corresponding to the simulated running environment, and debug and optimize the basic chip state evaluation algorithm through this set. Through repeated debugging, verification and testing, the data analysis system can gradually obtain the target chip state evaluation algorithm that has been debugged. This algorithm will provide strong support for the research, optimization and application of implanted chip devices.

[0141] In some other possible embodiments, the chip simulation involvement logs include initial chip state simulation logs and derived chip state simulation logs; the method further includes: according to a sample screening strategy, screening the first set of algorithm debugging examples from the initial chip state simulation logs; wherein the initial chip state simulation logs include visual chart information related to the simulated running environment; constructing positive debugging examples of a log extraction network according to the first set of algorithm debugging examples, and constructing negative debugging examples of the log extraction network based on remaining chip state simulation logs unrelated to the simulated running environment; debugging the log extraction network based on the positive and negative debugging examples of the log extraction network, to obtain a completed log extraction network that has been debugged; and obtaining the derived chip state simulation logs from a chip state simulation log library through the completed log extraction network that has been debugged.

[0142] In the application scenario of implantable chip devices, the debugging of the target chip state evaluation algorithm is a crucial step. In order to ensure that the algorithm can accurately and reliably evaluate the state of the chip in the real running environment, the data analysis system needs to go through a series of fine and careful debugging steps.

[0143] First of all, it is necessary to clarify the importance of chip simulation logs. These logs record various states and performances of the chip in the simulation running environment, and are a valuable data source for the data analysis system to debug the algorithm. Among these logs, the initial chip state simulation log is particularly worth paying attention to, as it contains visual chart information related to the simulation running environment, providing a comprehensive and intuitive overview of the chip state for the data analysis system.

[0144] In order to make more effective use of these logs, the data analysis system adopts a sample screening strategy. This strategy helps the data analysis system to screen out the most representative first set of algorithm debugging examples from the vast initial chip state simulation logs. These examples will serve as the core data set for subsequent algorithm debugging of the data analysis system, ensuring that the debugging work of the data analysis system is more targeted and specific.

[0145] Next, the data analysis system constructs positive debugging examples of the log extraction network based on the first set of algorithm debugging examples. The log extraction network is a key tool that helps the data analysis system extract valuable information from the massive chip state simulation logs. By constructing positive debugging examples, the data analysis system can train the log extraction network to learn how to accurately identify and extract information related to chip state evaluation.

[0146] At the same time, the data analysis system also needs to construct negative debugging examples of the log extraction network based on the remaining chip state simulation logs that are not related to the simulation running environment. These negative debugging examples are also important, as they help the log extraction network learn to identify and filter out information unrelated to chip state evaluation, thereby improving the accuracy and efficiency of extraction.

[0147] With positive and negative debugging examples, the data analysis system can begin to debug the log extraction network. This is an iterative optimization process, and the data analysis system needs to constantly adjust network parameters and structures so that it can perform well in the face of various complex chip state simulation logs. Through repeated training and testing, the data analysis system can gradually obtain a completed log extraction network that will become a powerful tool for the data analysis system to obtain derived chip state simulation logs in the future.

[0148] Finally, the data analysis system utilizes the completed log extraction network to obtain derived chip state simulation logs from the chip state simulation log library. These derived logs are further mined and refined based on the initial logs, containing more detailed and in-depth information about the chip state. Through these derived logs, the data analysis system can more comprehensively and deeply understand the performance of the chip in the simulation environment, providing richer and more accurate data support for the debugging of the target chip state evaluation algorithm.

[0149] It is worth mentioning that throughout the entire debugging process, the data analysis system always maintains a high level of attention to the performance and accuracy of the algorithm. The data analysis system adopts various verification and testing methods to ensure that the algorithm can achieve the expected effect after each step of debugging. At the same time, the data analysis system also strictly controls the computational complexity and running time of the algorithm to ensure that it can meet the real-time requirements in actual application.

[0150] In addition, during the debugging process, the data analysis system also fully utilizes the advantages of visual chart information. Through in-depth analysis and mining of this information, the data analysis system can more intuitively understand the trends and rules of chip state changes, thereby providing stronger support for the debugging and optimization of the algorithm.

[0151] In summary, the debugging of the target chip state evaluation algorithm for implantable chip devices is a complex and meticulous process. The data analysis system needs to fully utilize the chip simulation involvement log as a valuable data source, and through a series of steps such as sample screening and log extraction network debugging, gradually obtain an accurate, reliable, and efficient evaluation algorithm. This algorithm will provide strong support for the research, optimization, and application of implantable chip devices.

[0152] In other possible embodiments, the debugging steps of the weight decision tree network are as follows: a multiple regression branch is added to the basic chip state evaluation algorithm to obtain an adjusted weight decision tree network; the basic chip state evaluation algorithm is obtained by pre-debugging the simulation data pool of the running environment; based on a first set of algorithm debugging examples corresponding to the simulation running environment, a positive debugging example set and a negative debugging example set are constructed, the positive debugging examples in the positive debugging example set are the first set of algorithm debugging examples, and the negative debugging examples in the negative debugging example set are obtained by adjusting the chip evaluation optimization points in the first set of algorithm debugging examples; the adjusted weight decision tree network is debugged through the positive debugging example set and the negative debugging example set to obtain the completed weight decision tree network.

[0153] In the application scenario of implantable chip devices, the debugging of the weight decision tree network is a core link, which directly relates to the accuracy and reliability of chip state evaluation. In order to obtain a finely debugged weight decision tree network that can accurately reflect the state of the chip, a series of scientific and rigorous debugging steps need to be followed.

[0154] Firstly, the data analysis system needs to add a multiple regression branch in the basic chip state evaluation algorithm. This step is the key to building the adjusted weight decision tree network. The basic chip state evaluation algorithm is obtained by pre-debugging the simulation data pool of the running environment, which already has a certain evaluation ability. However, in order to further improve the accuracy of evaluation, the data analysis system needs to add a multiple regression branch on this basis. The multiple regression branch can consider more influencing factors and make a more comprehensive and in-depth evaluation of the chip state. Through this step, the data analysis system obtains a preliminary adjusted weight decision tree network, which has more abundant evaluation ability and higher accuracy.

[0155] Next, the data analysis system needs to construct a positive debugging example set and a negative debugging example set based on the first set of algorithm debugging examples corresponding to the simulated running environment. This step is to provide sufficient and diversified data sets for subsequent debugging work. The positive debugging examples in the positive debugging example set are the first set of algorithm debugging examples, which represent the normal state of the chip in the simulated running environment. The negative debugging examples in the negative debugging example set are obtained by adjusting the chip evaluation optimization points in the first set of algorithm debugging examples, which represent the abnormal or optimized state of the chip in the simulated running environment. By constructing these two sets, the data analysis system can ensure that the subsequent debugging work can cover various possible situations, thereby improving the generalization ability and accuracy of the weight decision tree network.

[0156] Then, the data analysis system can debug the adjusted weight decision tree network through the positive debugging example set and the negative debugging example set. This step is the core of the entire debugging process. The data analysis system needs to input the examples in these two sets into the weight decision tree network and observe whether the output results of the network are consistent with the expectations. If they are consistent, it means that the network performs well on this example; if they are not consistent, the network needs to be adjusted and optimized accordingly. Through repeated debugging and optimization, the data analysis system can gradually obtain a completed weight decision tree network. This network has been fully verified and tested, has high accuracy and reliability, and can accurately evaluate the state of the implantable chip device in the real running environment.

[0157] During the debugging process, the data analysis system also needs to pay special attention to some details. For example, the data analysis system needs to ensure that the examples in the positive and negative debugging example sets are comprehensive and representative, so that the weight decision tree network can fully learn the performance in various situations during the debugging process. At the same time, the data analysis system also needs to pay attention to the computational complexity and running time of the network, to ensure that the network can meet the real-time requirements in practical applications. In order to further improve the efficiency and quality of debugging, the data analysis system can also use some advanced machine learning techniques and algorithms, such as cross-validation, grid search, etc., to optimize the parameters and structure of the weight decision tree network.

[0158] In addition, after the debugging is completed, the data analysis system also needs to conduct a comprehensive verification and test of the weight decision tree network. This step is to ensure the performance and accuracy of the network in real application scenarios. The data analysis system can apply the network to the actual implantable chip device and observe whether the evaluation results of the chip state are consistent with the actual situation. At the same time, the data analysis system can also compare with other advanced chip state evaluation algorithms to verify the superiority and accuracy of the weight decision tree network.

[0159] In this way, an accurate, reliable and efficient weight decision tree network can be gradually obtained, providing strong support for the research, optimization and application of implantable chip devices.

[0160] In some independent embodiments, after determining the target chip evaluation optimization point corresponding to the current performance simulation label from the first set of chip evaluation optimization points and the at least one second set of chip evaluation optimization points, the method further comprises: generating a design optimization report for the implantable chip device according to the target chip evaluation optimization point.

[0161] In the application scenario of implantable chip devices, generating a design optimization report for the chip is a crucial step. This step not only relates to the improvement of chip performance, but also directly affects the actual application effect in the fields of medical treatment, scientific research, etc. In order to achieve this goal, after step 140, a detailed and guiding design optimization report needs to be generated according to the obtained target chip evaluation optimization point.

[0162] First of all, the core content of the target chip evaluation optimization point needs to be clarified. The target chip evaluation optimization point is obtained after a comprehensive and in-depth evaluation of the implantable chip device, which reveals the potential problems in the design, performance, stability, etc. of the chip and the possible optimization direction. These points are the basis and basis for the data analysis system to generate a design optimization report.

[0163] With these evaluation optimization points, the design optimization report can be generated. The opening part of the report, the data analysis system needs to introduce the basic situation of the implanted chip device, including its design principle, functional characteristics, application scenarios, etc. This can give the reader a basic understanding of the chip, providing background support for subsequent optimization recommendations.

[0164] Next, the core part of the report, the design optimization recommendations for the chip. In this part, specific and feasible optimization recommendations should be made based on the evaluation optimization points of the target chip. These recommendations should cover all aspects of chip design, manufacturing, testing, etc., to ensure that the overall performance of the chip is improved. For example, if the evaluation results show that the chip has high power consumption, the suggestion of using low-power design technology can be made; if the stability of the chip is a problem, the suggestion of optimizing the circuit design to improve the anti-interference ability of the chip can be made.

[0165] At the same time of putting forward optimization suggestions, detailed explanation and demonstration should be made for each suggestion. This includes the implementation method, expected effect, possible challenges and solutions of the suggestion. This can make the reader of the report more clearly understand the background and feasibility of each suggestion, and increase the persuasiveness of the report.

[0166] In addition to optimization recommendations, some additional supporting information can be provided in the report. For example, some successful cases of similar chips can be listed to illustrate the effect of optimization recommendations in practical application; some relevant research literature and patent information can be provided to support the theoretical basis of the report's points.

[0167] In the concluding part of the report, all optimization recommendations should be summarized and summarized to form a clear optimization scheme. At the same time, the prospect of the implementation of the scheme can be looked forward to, and the application potential of the optimized implanted chip device in the fields of medical treatment, scientific research, etc. can be explained.

[0168] It is worth mentioning that the generation of design optimization report is not a one-time process. In actual operation, the report needs to be revised and improved constantly to ensure that each point and suggestion in the report is based on the latest evaluation results and scientific research. At the same time, the data analysis system also needs to communicate and exchange with the design team, manufacturing team and experts in the application field of the chip, to ensure that the recommendations of the report have feasibility and practicality in actual application.

[0169] In addition, special attention should be paid to the readability and easy understanding of the report in the process of generating the design optimization report. Since the readers of the report may come from different professional backgrounds, it is necessary to use simple and easy-to-understand language and charts to explain complex points and suggestions. At the same time, the report can be formatted and formatted to make it more beautiful and easy to read.

[0170] It can be seen that generating a design optimization report for an implantable chip device is a complex and meticulous process. The data analysis system needs to evaluate optimization ideas based on the target chip, provide specific and feasible optimization suggestions, and provide detailed explanations and justifications for each suggestion. At the same time, the data analysis system also needs to pay attention to the readability and ease of understanding of the report to ensure that it has guiding significance in practical applications.

[0171] Based on the above, in other independent embodiments, the method further includes performing text labeling processing on the design optimization report.

[0172] In detail, the text labeling processing on the design optimization report includes embedding optimization suggestion semantics and embedding argument index semantics in multiple report text paragraphs in the design optimization report, respectively, to obtain an optimization suggestion semantic embedding feature set and an argument index semantic embedding feature set; performing first feature updating on the optimization suggestion semantic embedding feature set by a first set feature updating strategy to obtain a first set of text paragraphs to be labeled including optimization suggestion semantics; performing second feature updating on the argument index semantic embedding feature set by a second set feature updating strategy to obtain a second set of text paragraphs to be labeled including argument index semantics; performing integration processing based on the first set of text paragraphs to be labeled and the second set of text paragraphs to be labeled to obtain a set of report text to be labeled in the design optimization report that matches a target semantic; the target semantic includes at least one of optimization suggestion semantics and argument index semantics, and the set of report text to be labeled is subjected to text labeling processing.

[0173] In the application scenario of implantable chip devices, text labeling processing of design optimization reports is a crucial link. This link not only concerns the readability and ease of use of the report, but also directly affects the effectiveness of the report in practical applications. To achieve this goal, this embodiment adds the step of performing text labeling processing on the design optimization report.

[0174] First, multiple report text paragraphs in the design optimization report need to be embedded with optimization suggestion semantics and argument index semantics, respectively. The purpose of this step is to convert the text paragraphs in the report into feature vectors with semantic information for subsequent processing and analysis. Optimization suggestion semantic embedding is performed on the optimization suggestions in the report, which converts the text of the suggestions into feature vectors that can express the semantics of the suggestions. Argument index semantic embedding is performed on the argument part of the report, which converts the text of the argument into feature vectors that can express the argument index. Through these two steps, the data analysis system can obtain an optimization suggestion semantic embedding feature set and an argument index semantic embedding feature set.

[0175] Next, the first feature update needs to be performed on the optimized suggestion semantic embedding feature set by the first set feature update strategy. The purpose of this step is to further optimize and process the feature set to make it more in line with actual needs. Through the first feature update, a first set of text passages to be labeled including optimized suggestion semantics can be obtained. The text passages in this set already have semantic information of optimization suggestions and can be used for subsequent labeling and processing.

[0176] Similarly, the second feature update also needs to be performed on the argument index semantic embedding feature set by the second set feature update strategy. This step is similar to the first feature update and is also a further optimization and processing of the feature set. Through the second feature update, a second set of text passages to be labeled including argument index semantics can be obtained. The text passages in this set already have semantic information of argument index and can also be used for subsequent labeling and processing.

[0177] After obtaining the first set of text passages to be labeled and the second set of text passages to be labeled, the data analysis system needs to perform integration processing based on the two sets. The purpose of this step is to merge and sort the text passages in the two sets to obtain an ordered and complete set of labeled report texts. The text passages in this set contain both semantic information of optimization suggestions and semantic information of argument index, which can serve as the basis for subsequent text labeling.

[0178] Finally, text labeling processing needs to be performed on the set of labeled report texts. This step is the core link of text labeling processing, which will label each text passage in the set to make it easier to understand and use. The contents of labeling can include the serial number of the passage, the title, the specific content of the optimization suggestion, the index of the argument, etc. Through labeling processing, a design optimization report with clear structure, complete content, easy to understand and use can be obtained.

[0179] In actual operation, some details need to be paid attention to when performing text labeling processing on the design optimization report. For example, it is necessary to ensure the accuracy and consistency of labeling to avoid labeling errors or inconsistencies. At the same time, attention should be paid to the standardization and readability of labeling to ensure that the labeled content meets the relevant standards and is easy for users to understand and use.

[0180] In addition, in order to improve the efficiency and quality of text labeling processing, some advanced natural language processing techniques and algorithms can be used. For example, machine learning algorithms can be used to classify and cluster text passages to better organize and present the content of the report. Natural language generation technology can also be used to automatically generate labeled content and format, further improving the efficiency and accuracy of labeling.

[0181] In this way, more comprehensive, accurate and useful information can be provided to support the design and optimization of implantable chip devices.

[0182] In yet some independent embodiments, the optimization suggestion semantic embedding and the argument index semantic embedding of the multiple report text paragraphs in the design optimization report are performed respectively to obtain the optimization suggestion semantic embedding feature set and the argument index semantic embedding feature set, including: performing the optimization suggestion semantic embedding of the multiple report text paragraphs in the design optimization report respectively to obtain the optimization suggestion semantic embedding mask in each report text paragraph and the initial semantic label corresponding to each optimization suggestion semantic embedding mask; determining the optimization suggestion semantic embedding feature set based on the optimization suggestion semantic embedding mask in each report text paragraph and the corresponding initial semantic label; and performing the argument index semantic embedding of the multiple report text paragraphs in the design optimization report respectively to obtain the argument index semantic embedding feature set.

[0183] In the application scenario of implantable chip devices, the text paragraphs of the design optimization report contain rich optimization suggestion and argument index information. In order to effectively extract and utilize these information, the optimization suggestion semantic embedding and the argument index semantic embedding of the multiple text paragraphs in the report need to be performed respectively, and then the optimization suggestion semantic embedding feature set and the argument index semantic embedding feature set are obtained.

[0184] Firstly, the optimization suggestion semantic embedding of the multiple report text paragraphs in the design optimization report is performed. This step aims to convert the optimization suggestions in the text paragraphs into semantic embedding masks that can be understood and processed by machine learning algorithms. In order to achieve this goal, the data analysis system adopts advanced natural language processing technology to deeply analyze and understand the text paragraphs. Through this processing, the data analysis system can obtain the optimization suggestion semantic embedding mask in each report text paragraph and the initial semantic label corresponding to each optimization suggestion semantic embedding mask. These initial semantic labels are a preliminary summary and classification of the optimization suggestions, which provide an important basis for subsequent feature set determination.

[0185] Secondly, based on the optimization suggestion semantic embedding mask in each report text paragraph and the corresponding initial semantic label, the data analysis system further determines the optimization suggestion semantic embedding feature set. This step is a further processing and handling of the results obtained in the previous step. The data analysis system extracts the key information and features from the optimization suggestion semantic embedding mask and the initial semantic label through integration and analysis, and then forms the optimization suggestion semantic embedding feature set. This feature set is a comprehensive and accurate representation of the optimization suggestions in the design optimization report, which provides strong support for subsequent applications.

[0186] Meanwhile, the data analysis system also needs to process the argument index semantic embedding of multiple report text paragraphs in the design optimization report. This step is similar to the optimization suggestion semantic embedding, but focuses on the argument index information in the text paragraphs. The argument index is important information that supports and justifies the optimization suggestions, and plays a crucial role in understanding and optimizing the feasibility and effectiveness of the suggestions. The data analysis system extracts and embeds the argument index in the text paragraphs through natural language processing technology, obtaining an argument index semantic embedding feature set. This feature set is a comprehensive and accurate representation of the argument index in the design optimization report, providing an important basis for subsequent applications.

[0187] In the process of implementing the optimization suggestion semantic embedding and argument index semantic embedding, the data analysis system uses a variety of advanced natural language processing techniques and algorithms. For example, the data analysis system uses word embedding technology to convert words in the text into vector form that can be processed by machine learning algorithms. The data analysis system also uses techniques such as recurrent neural networks and attention mechanisms to deeply understand and analyze the semantics of the text paragraphs. Through the application of these techniques and algorithms, the data analysis system can effectively extract and utilize the optimization suggestions and argument index information in the text paragraphs, providing strong support for subsequent design optimization and decision-making.

[0188] In addition, in the process of implementing this technical solution, the data analysis system also focuses on data preprocessing and post-processing. In the preprocessing stage, the data analysis system performs cleaning, word segmentation, and stop word removal on the design optimization report to improve the accuracy and efficiency of subsequent processing. In the post-processing stage, the data analysis system further integrates and analyzes the optimization suggestion semantic embedding feature set and the argument index semantic embedding feature set to extract key information and features. Through these processing steps, the data analysis system can obtain a more accurate and comprehensive design optimization report feature set, providing stronger support for subsequent applications.

[0189] In this way, by performing optimization suggestion semantic embedding and argument index semantic embedding on multiple report text paragraphs in the design optimization report, the data analysis system can obtain an optimization suggestion semantic embedding feature set and an argument index semantic embedding feature set. This technical solution can effectively extract and utilize the optimization suggestions and argument index information in the text paragraphs, providing strong support for subsequent design optimization and decision-making.

[0190] Further, Figure 2 A structural diagram of a data analysis system 200 according to an embodiment of the present application is provided. As shown in the structural diagram of the data analysis system 200, the data analysis system 200 includes a processor 210, which can call and run computer programs from a memory to implement the method in the embodiment of the present application. Figure 2 The processor 210 can call and run computer programs from the memory to implement the method in the embodiment of the present application.

[0191] Optionally, as shown in Figure 2 the data analysis system 200 can further include a memory 230. Wherein the processor 210 can call and run a computer program from the memory 230 to implement the method in the embodiments of the application.

[0192] Wherein the memory 230 can be a separate device independent of the processor 210, or can be integrated in the processor 210.

[0193] Optionally, as shown in Figure 2 the data analysis system 200 can further include a transceiver 220, and the processor 210 can control the transceiver 220 to interact with other devices, specifically, can send information or data to other devices, or receive information or data sent by other devices.

[0194] Optionally, the data analysis system 200 can implement the corresponding processes of the storage engine or the components (such as processing modules) in the storage engine or the devices deployed with the storage engine in the various methods of the embodiments of the application, and for the sake of brevity, will not be repeated here.

[0195] It should be understood that the processor of the embodiments of the application can be an integrated circuit chip with signal processing capability.

[0196] It can be understood that the memory in the embodiments of the application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. It should be noted that the memory of the system and method described herein is intended to include, but not limited to, suitable types of memory.

[0197] On the basis of the above, a readable storage medium is provided, the readable storage medium stores a program or instructions, and the program or instructions are executed by the processor to implement the steps of the above method.

[0198] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. Additionally, it should be noted that the methods and apparatus of the present embodiments are not limited by the order of the steps or the sequence for performing the steps, as some steps can occur in different orders and some steps can be performed concurrently. Furthermore, an element proceeded by "comprises a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. Additionally, any reference to a method comprising an action is intended to mean that the method can comprise the action or a similar action.

[0199] Those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, or network equipment, etc.) execute the method described in various embodiments of the present application.

[0200] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are merely illustrative, not restrictive. Those skilled in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope of the present application, which are all within the protection of the present application.

Claims

1. A method for analyzing simulation data of an operating environment based on an implanted chip, characterized in that, The method is applied to a data analysis system, and the method includes: Acquire chip operating environment simulation data, which includes operating status data of the implanted chip device in a simulated operating environment, wherein the implanted chip device and the simulated operating environment have a one-to-many relationship; For the current performance simulation label of the implanted chip device in the chip operating environment simulation data, the target chip state evaluation algorithm is called to obtain the first set of chip evaluation optimization viewpoints corresponding to the current performance simulation label based on the chip operating environment simulation data. The target chip state evaluation algorithm has completed the training and debugging of the environment simulation response vector based on the simulated operating environment. The target chip state evaluation algorithm is invoked to obtain at least one second set of chip evaluation optimization views corresponding to the current performance simulation label based on the chip operating environment simulation data and at least one attention feature. The attention feature is a feature generated based on the chip operating environment simulation data and used as an indicator to output the chip evaluation optimization view. From the first set of chip evaluation and optimization viewpoints and the at least one second set of chip evaluation and optimization viewpoints, determine the target chip evaluation and optimization viewpoint corresponding to the current performance simulation label.

2. The method as described in claim 1, characterized in that, The invocation of the target chip state evaluation algorithm, based on the chip operating environment simulation data and at least one attention feature, obtains at least one second set of chip evaluation optimization viewpoints corresponding to the current performance simulation label, including: For the target attention feature among the at least one attention feature, the target attention feature is combined with the chip operating environment simulation data to obtain chip operating environment attention data; The target chip state evaluation algorithm is invoked to process the chip operating environment attention data, resulting in a second set of chip evaluation and optimization viewpoints output by the current performance simulation label under the indication of the target attention features.

3. The method as described in claim 2, characterized in that, The process of calling the target chip state evaluation algorithm to process the chip operating environment attention data yields a second set of chip evaluation optimization viewpoints output by the current performance simulation label under the indication of the target attention features, including: Obtain the state simulation timing vector of the attention data of the chip's operating environment; For each attention data unit in the chip operating environment attention data, the data unit distribution characteristics, state operation correlation characteristics and simulation task requirement characteristics corresponding to the attention data unit are integrated with the state simulation time sequence vector corresponding to the attention data unit to obtain the linkage state simulation time sequence vector corresponding to the target chip state evaluation algorithm. The target chip state evaluation algorithm is invoked to process the linkage state simulation time vector to obtain the second set of chip evaluation optimization viewpoints output by the current performance simulation label under the indication of the target attention feature.

4. The method as described in claim 2, characterized in that, The attention features include the simulated environment response vector of the simulated operating environment or the noise-added label features of the simulated chip operating environment data; wherein, the simulated environment response vector includes at least one of the following: response state features, response state heatmap, environmental element offset, and potential anomaly description vector; the combination of the target attention features with the simulated chip operating environment data to obtain chip operating environment attention data includes: Based on the target attention feature being the environment simulation response vector, the environment simulation response vector is fused into the local environment dataset corresponding to the chip operating environment simulation data of the implanted chip device to obtain the chip operating environment attention data; Alternatively, based on the noisy label features, the noisy label features can be fused into the environmental noise dataset of the chip operating environment simulation data to obtain the chip operating environment attention data.

5. The method as described in claim 1, characterized in that, Determining the target chip evaluation and optimization viewpoint corresponding to the current performance simulation label from the first group of chip evaluation and optimization viewpoints and the at least one second group of chip evaluation and optimization viewpoints includes: The confidence weight coefficients corresponding to the first group of chip evaluation and optimization viewpoints and the confidence weight coefficients corresponding to each of the second group of chip evaluation and optimization viewpoints are obtained through a weighted decision tree network. The confidence weight coefficients are used to indicate the degree of matching between the chip evaluation and optimization viewpoints and the simulated operating environment. The chip evaluation and optimization viewpoint with the largest confidence weight coefficient among the first group of chip evaluation and optimization viewpoints and each of the second group of chip evaluation and optimization viewpoints is determined as the target chip evaluation and optimization viewpoint.

6. The method as described in claim 5, characterized in that, Before determining the chip evaluation and optimization viewpoint with the largest confidence weight coefficient among the first group of chip evaluation and optimization viewpoints and each of the second group of chip evaluation and optimization viewpoints as the target chip evaluation and optimization viewpoint, the method further includes: Based on the existence of an evaluation and optimization label in the initial chip evaluation and optimization viewpoint where the actual performance prediction weight is not less than the prediction weight threshold, the confidence weight coefficient corresponding to the initial chip evaluation and optimization viewpoint is increased. Alternatively, based on the premise that the common feature value between the initial chip evaluation optimization viewpoint and the key performance characterization vector is not less than a preset common value, the confidence weight coefficient corresponding to the initial chip evaluation optimization viewpoint is increased, and the key performance characterization vector is used to represent the environmental simulation response vector of the simulated operating environment. The initial screening chip evaluation and optimization viewpoints include the first group of chip evaluation and optimization viewpoints and each of the second group of chip evaluation and optimization viewpoints.

7. The method as described in claim 1, characterized in that, The debugging steps for the target chip state evaluation algorithm are as follows: A basic chip state assessment algorithm is obtained, which is obtained by pre-debugging a simulated data pool of the operating environment. From the chip simulation-related logs corresponding to the simulated operating environment, an algorithm debugging example set is determined. The algorithm debugging example set includes a first set of algorithm debugging examples carrying the environment simulation parameters corresponding to the simulated operating environment, and a second set of algorithm debugging examples not carrying the environment simulation parameters. The algorithm debugging examples in the algorithm debugging example set are composed of chip environment interaction response information. The basic chip state evaluation algorithm is debugged using the algorithm debugging example set to obtain the target chip state evaluation algorithm after debugging.

8. The method as described in claim 7, characterized in that, The chip simulation-related logs include initial chip state simulation logs and derived chip state simulation logs; the method further includes: According to the sample selection strategy, the first group of algorithm debugging examples are selected from the initial chip state simulation log; wherein, the initial chip state simulation log includes visual chart information related to the simulated running environment; An active debugging example for constructing the log extraction network is based on the first set of algorithm debugging examples, and a passive debugging example for constructing the log extraction network is based on the simulated logs of the remaining chip states that are unrelated to the simulated operating environment. Based on the active and passive debugging examples of the log extraction network, the log extraction network is debugged to obtain a fully debugged log extraction network. The derived chip status simulation logs are obtained from the chip status simulation log library through the log extraction network that has been debugged.

9. The method as described in claim 5, characterized in that, The debugging steps for the weighted decision tree network are as follows: A multivariate regression branch is added to the basic chip state assessment algorithm to obtain an adjusted weighted decision tree network; wherein, the basic chip state assessment algorithm is obtained by pre-tuning the simulation data pool of the operating environment; Based on the first set of algorithm debugging examples corresponding to the simulated operating environment, an active debugging example set and a passive debugging example set are constructed. The active debugging examples in the active debugging example set are the first set of algorithm debugging examples, and the passive debugging examples in the passive debugging example set are obtained by adjusting the chip evaluation and optimization perspective in the first set of algorithm debugging examples. The adjusted weight decision tree network is debugged using the active debugging example set and the passive debugging example set to obtain the debugged weight decision tree network.

10. A data analysis system, characterized in that, The method includes at least one processor and a memory; the memory stores computer-executable instructions; the at least one processor executes the computer-executable instructions stored in the memory, causing the at least one processor to perform the method according to any one of claims 1-9.

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