Semiconductor device and semiconductor element

Abstract

The invention relates to a semiconductor device and a semiconductor element. Provided is a semiconductor device in which peeling of a protective film on the surface of a semiconductor element is suppressed even when the semiconductor element is subjected to stress from a sealing resin due to stress caused by a temperature cycle. The present invention comprises: a substrate; a semiconductor element bonded to the substrate; and a sealing resin that seals at least a part of the substrate and the semiconductor element, the semiconductor element having: an active region through which a main current flows in an on state of the semiconductor element; a tip region around the active region; an anchor film provided over the insulating film in the terminal region; and a protective film that covers at least a terminal region including the anchor film, the anchor film comprising a material different from that of the insulating film and having a plurality of openings provided dispersedly.

Description

[0001] This application is a divisional application of Chinese National Application No. 2020108861165 (Semiconductor Device and Semiconductor Component), filed on August 28, 2020, the contents of which are quoted below. Technical Field

[0002] This invention relates to semiconductor devices, and more particularly to semiconductor devices in which semiconductor elements are resin-encapsulated, and to semiconductor devices in which peeling of the protective film protecting the semiconductor elements is suppressed. Background Technology

[0003] Patent Document 1 discloses a semiconductor device in which a semiconductor element is encapsulated using a curable resin such as an epoxy resin. Patent Document 2 discloses a semiconductor device in which an electrode component is bonded to the surface and back sides of a semiconductor element, and at least a portion of the electrode component and the semiconductor element are covered by an encapsulating resin. Furthermore, in recent years, to further address loss reduction and high-temperature operation, SiC semiconductor elements made of silicon carbide (SiC) have been developed and put into practical use, and are also used in the aforementioned semiconductor devices. Patent Document 3 discloses a semiconductor device in which an insulating layer with a first and a second insulating layer stacked on top of a SiC layer is formed, a through-hole reaching the surface of the SiC layer is provided in the first insulating layer, and a protrusion is formed by embedding the second insulating layer into the through-hole, thereby improving the adhesion of the insulating layer.

[0004] Patent Document 1: Japanese Patent Application Publication No. 2004-165406

[0005] Patent Document 2: Japanese Patent Application Publication No. 2001-274177

[0006] Patent Document 3: International Publication No. 2013 / 137177

[0007] Existing semiconductor devices suffer from the following problems: due to stress caused by temperature cycling, the semiconductor element experiences stress from the encapsulating resin, leading to the peeling of the protective film on the semiconductor element surface and reduced reliability. Regarding the semiconductor device with the structure disclosed in Patent Document 2, it is believed that the increased stress applied to the semiconductor element further increases the likelihood of protective film peeling. If the peeling progresses, for example, to the area covering the gate wiring that is inside the end region compared to the end region, it can sometimes damage the gate wiring, ultimately resulting in poor performance. In particular, for semiconductor devices equipped with SiC semiconductor elements, since SiC has a higher Young's modulus than Si, the increased stress applied to the protective film makes peeling more likely to develop further. Furthermore, even with a structure that improves the adhesion of the insulating layer, as disclosed in Patent Document 3, if peeling cannot be completely suppressed, the end region of the SiC semiconductor element, which becomes a strong electric field, may be exposed, causing discharge from the peeling location and reducing the withstand voltage. Summary of the Invention

[0008] The present invention was proposed to solve the aforementioned problems, and its object is to provide a semiconductor device that suppresses the peeling of the protective film on the surface of the semiconductor element even when the semiconductor element is subjected to stress from the encapsulation resin due to stress caused by temperature cycling.

[0009] The semiconductor device of the present invention comprises: a substrate; a semiconductor element bonded to the substrate; and an encapsulating resin encapsulating at least a portion of the substrate and the semiconductor element, the semiconductor element having: an active region through which a main current flows in an on state of the semiconductor element; an end region surrounding the active region; an anchoring film disposed on an insulating film of the end region; and a protective film covering at least the end region containing the anchoring film, the anchoring film being made of a material different from the insulating film and having a plurality of dispersed openings.

[0010] The effects of the invention

[0011] According to the semiconductor device of the present invention, by providing an anchoring film on the insulating film at the end region of the semiconductor element, even when the semiconductor element is subjected to stress from the encapsulating resin due to stress caused by temperature cycling, the protective film will hook onto the opening of the anchoring film. Thus, the protective film shares the stress from the encapsulating resin as tensile stress, thereby reducing the compressive stress at the peeling tip and suppressing the peeling of the protective film. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view illustrating the structure of the semiconductor device according to Embodiment 1 of the present invention.

[0013] Figure 2 This is a top view showing the structure of the semiconductor element mounted on the semiconductor device according to Embodiment 1 of the present invention.

[0014] Figure 3 This is a partial cross-sectional view showing the structure of the semiconductor element mounted on the semiconductor device according to Embodiment 1 of the present invention.

[0015] Figure 4 This is a partial top view showing the structure of the semiconductor element mounted on the semiconductor device according to Embodiment 1 of the present invention.

[0016] Figure 5 This is a partial top view showing the structure of the semiconductor element mounted on the semiconductor device according to Embodiment 1 of the present invention.

[0017] Figure 6 This is a partial top view showing the structure of the semiconductor element mounted on the semiconductor device according to Embodiment 1 of the present invention.

[0018] Figure 7 It is a contour plot representing the simulation results of the stress generated at the interface between the protective film and the semiconductor element under the stress caused by temperature cycling.

[0019] Figure 8 It is a contour plot representing the simulation results of the stress generated at the interface between the protective film and the semiconductor element under the stress caused by temperature cycling.

[0020] Figure 9 It is a contour plot representing the simulation results of the stress generated at the interface between the protective film and the semiconductor element under the stress caused by temperature cycling.

[0021] Explanation of the label

[0022] 1 Semiconductor device, 11 Semiconductor element, 11a Terminal region, 12 Interlayer insulating film, 13 Anchoring film, 14 Protective film. Detailed Implementation

[0023] <Introduction>

[0024] In the following description, "active region" refers to the region through which the main current flows when the semiconductor element is switched on. Additionally, below, "outer side" refers to the direction towards the outer periphery of the semiconductor element, and "inner side" is the opposite direction. Furthermore, in the following description, regarding the conductivity type of impurities, n-type is generally defined as "first conductivity type," and p-type, which is the opposite conductivity type of n-type, is defined as "second conductivity type," but the opposite definitions are also possible.

[0025] Furthermore, the accompanying drawings are schematic, and the dimensions and positions of the images shown in different drawings may not be accurately depicted and can be appropriately modified. Additionally, in the following description, the same structural elements are illustrated with the same reference numerals, and their names and functions are identical. Therefore, detailed descriptions of them may sometimes be omitted. Furthermore, in this specification, the use of terms such as "above" and "covering" does not exclude the presence of inclusions between structural elements. For example, the description "B is provided above A" or "A covers B" may mean that other structural element C is provided between A and B, or that no other structural element C is provided. Additionally, in the following description, terms such as "above," "below," "side," "bottom," "top," or "back," which indicate specific positions and directions, are sometimes used. These terms are used for convenience only to facilitate understanding of the embodiments and are not related to the actual direction during implementation.

[0026] Furthermore, the term "MOS" was previously used for the junction structure of metal-oxide-semiconductor, using the first letters of Metal-Oxide-Semiconductor. However, specifically regarding field-effect transistors with a MOS structure (hereinafter referred to as "MOS transistors"), from the perspective of recent improvements in integration and manufacturing processes, the materials of the gate insulating film and gate electrode are being improved.

[0027] For example, in the case of MOS transistors, from the viewpoint of self-aligned formation of the source and drain, polysilicon can be used as the gate electrode material instead of metal. Furthermore, from the viewpoint of improving electrical characteristics, a material with a high dielectric constant is used as the gate insulating film material, but this material is not necessarily limited to oxides.

[0028] Therefore, the term "MOS" is not necessarily limited to metal-oxide-semiconductor stacked structures, and this specification does not impose such a limitation. That is, based on common technical knowledge, "MOS" here is not only an abbreviation derived from its etymology, but also has a broad meaning that includes conductor-insulator-semiconductor stacked structures.

[0029] <Implementation Method 1>

[0030] <Device Structure>

[0031] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device 1 according to Embodiment 1. Figure 2 This is a top view showing the structure of the semiconductor element 11 mounted on the semiconductor device 1.

[0032] like Figure 1As shown, the semiconductor device 1 has a plurality of semiconductor elements 11 bonded to a main surface (upper surface) of a conductor substrate 21 via a bonding material 31 such as solder. A lead frame 22 is bonded to the upper surface of each semiconductor element 11 via a bonding material 32 such as solder on the side opposite to the lower surface bonded by the bonding material 31. The lead frame 22 is electrically connected to a source electrode (not shown) on the upper surface of the semiconductor element 11, and one end of the lead frame 22 protrudes to the outside of the semiconductor device 1.

[0033] One end of the external terminal 23 is connected to the edge of the upper surface of the conductor substrate 21, and the other end of the external terminal 23 protrudes to the outside of the semiconductor device 1. The external terminal 23 is electrically connected to the drain electrode (not shown) on the lower surface of the semiconductor element 11.

[0034] Additionally, one end of the wire WR is connected to the upper surface of the semiconductor device 11 via wire bonding, and the other end of the wire WR is connected to one end of the control terminal 24 via wire bonding. The other end of the control terminal 24 protrudes to the outside of the semiconductor device 1. The wire WR is bonded to the gate pad 11d of the semiconductor device 11. Figure 2 The control signal is input from the outside of the semiconductor device 1 via the control terminal 24.

[0035] At least a portion of the lead frame 22, external terminal 23, and control terminal 24, the wire WR, the conductor substrate 21, and the semiconductor element 11 are encapsulated by encapsulating resin 41. The other end of each of the lead frame 22, external terminal 23, and control terminal 24 protrudes from the side of the encapsulating resin 41 to the outside. The lower surface of the conductor substrate 21 is not covered by the encapsulating resin 41 and is exposed to the outside. Furthermore, Figure 1 The structure of the semiconductor device 1 shown is an example and is not limited to this structure.

[0036] like Figure 2 As shown, the semiconductor element 11 has a rectangular shape, with its central portion forming the active region AR. The active region AR, viewed from above, is a rectangle with curved corners. One side has a rectangular indentation at its center, extending inwards to form a gate pad 11d that extends into the indentation of the active region AR. Furthermore, a source electrode 11c, having approximately the same size and shape as the active region AR, is disposed on top of the active region AR.

[0037] Furthermore, the gate wiring 11b connected to one side of the gate pad 11d is disposed along the outer periphery of the active region AR, and the active region AR is surrounded by the gate wiring 11b. Moreover, the arrangement and top view shape of the active region AR, source electrode 11c, and gate pad 11d are not limited to the above-described cases.

[0038] An anchoring film 13 is provided along the outer periphery of the gate wiring 11b. The region including the anchoring film 13 from the outer edge of the gate wiring 11b to the outer edge of the semiconductor element 11 is defined as the end region 11a.

[0039] exist Figure 3 The middle shows Figure 2 The axial section view of the area indicated by line AA in the figure. Figure 4 Is with Figure 3 A partial top view of the corresponding area.

[0040] like Figure 3 As shown, in the terminal region 11a, an anchoring film 13 is provided on the interlayer insulating film 12, and a protective film 14 is formed covering at least a portion of the interlayer insulating film 12, the gate wiring 11b, and the source electrode 11c. Furthermore, the protective film 14 is made of a different material than the interlayer insulating film 12. Additionally, although not shown in the figure, impurity regions for maintaining withstand voltage may also be provided in the terminal region.

[0041] Semiconductor element 11 is a SiC semiconductor element (silicon carbide semiconductor element) made of silicon carbide (SiC). It has a semiconductor layer epitaxially grown on a semiconductor substrate, i.e., a SiC wafer. After multiple semiconductor element structures are formed on the SiC wafer through various wafer fabrication processes, an anchoring film 13 is formed at the end region 11a of each semiconductor element structure, and a protective film 14 covers the end region 11a. Then, the SiC wafer is ground to a thickness of about 100 μm, and for example, the multiple semiconductor element structures are cut along the dicing line by a dicing method to form a single wafer, thereby becoming semiconductor element 11.

[0042] Furthermore, although the illustration and explanation of the semiconductor element structure of semiconductor element 11 are omitted, a MOS transistor is envisioned in this embodiment. However, semiconductor element 11 is not limited to a MOS transistor, and may also be an insulated gate bipolar transistor (IGBT), a pn junction diode, a Schottky diode, etc.

[0043] For example, polyimide or polyamide can be used as the main material to form the protective film 14. Regarding the protective film 14, in the wafer fabrication process, a precursor solution of the protective film 14 is applied onto a SiC wafer using spin coating, and then a photolithography process is performed to form the desired pattern. An example of such a pattern is a pattern where the area outside the openings above the source electrode 11c and gate pad 11d of a MOS transistor, including the end region 11a and the area where the gate wiring 11b is formed, is covered by the protective film 14.

[0044] To elaborate further, when using a disc-shaped whetstone to cut semiconductor wafers, if the protective film 14 covers the dicing line, breakage or other issues may occur during cutting, potentially reducing the yield. Therefore, it is preferable that the outer end face of the protective film 14 is positioned recessed inwards from the dicing line, so that it does not contact the whetstone during cutting, creating a pattern with an opening above the dicing line. Thus, as... Figure 3 As shown, the outer end face of the protective film 14 is positioned behind the end face of the semiconductor element 11. Furthermore, this receding distance varies depending on cutting conditions such as the blade width of the whetstone, and is, for example, 20–100 μm.

[0045] The interlayer insulating film 12 is made of silicon oxide as the main material, and can be formed to any thickness by thermal oxidation or by depositing a TEOS oxide film using TEOS (tetraethoxysilane).

[0046] The end region 11a of the semiconductor element 11 is also a voltage holding region for maintaining the withstand voltage. Since it becomes a high electric field, the interlayer insulating film 12 covering the end region 11a is set in thickness and formed in such a way that the end region 11a is not exposed. In addition, the interlayer insulating film 12 is set to a thickness that will not reduce the withstand voltage due to leakage current generated by the high electric field.

[0047] Anchoring film 13, for example, is composed primarily of silicon nitride. Figure 2 As shown, the anchoring membrane 13, when viewed from above, is arranged in a ring shape along the end region 11a. Additionally, as... Figure 4 As shown, multiple openings 13a are provided in a dispersed manner throughout the anchoring membrane 13.

[0048] The anchoring film 13 is formed in a ring shape to surround the gate wiring 11b and the active region AR on the outside of the gate wiring 11b, thereby suppressing the peeling development of the protective film 14 and preventing peeling from reaching the gate wiring 11b and the active region AR.

[0049] Regarding the anchor film 13, after a silicon nitride film is formed on the entire SiC wafer using chemical vapor deposition (CVD) during the wafer fabrication process, a resist film is formed on the silicon nitride film. Following a photolithography process, the resist film remains circumferentially along the end region 11a, and multiple openings 13a are formed in a dispersed manner to pattern the resist film. Subsequently, the silicon nitride film is etched using the patterned resist film as an etching mask to obtain the desired pattern.

[0050] Here, the interlayer insulating film 12 is made of silicon oxide and the anchoring film 13 is made of silicon nitride. Therefore, the etching process is selective, so the removal of the interlayer insulating film 12 during the patterning process of the anchoring film 13 can be suppressed.

[0051] Figure 4 The top view of the opening 13a of the anchoring membrane 13 shown is circular, and the minimum interval between the openings 13a is set to be greater than or equal to 5 μm and less than or equal to 20 μm.

[0052] Furthermore, by setting the top view shape of the opening 13a to be circular, the tensile stress generated when the protective film 14 is hooked onto the opening 13a after peeling can be evenly borne.

[0053] Furthermore, the top view shape of the opening 13a is not limited to a circle, for example, Figure 5 As shown, it can also be set to a shape close to a semicircle (semicircular), such as... Figure 6 As shown, it can also be set to a shape close to a crescent shape (crescent shape). The inner side (the side that forms the active region AR and the gate wiring 11b) is in the shape of an arc, and the minimum spacing between the openings 13a can be greater than or equal to 5μm and less than or equal to 20μm.

[0054] By setting the openings to a semi-circular or crescent shape, the number of openings 13a per unit area can be increased, thereby enhancing the anchoring effect of the protective film 14 provided by the openings 13a. The anchoring effect refers to the effect of the protective film 14 resisting horizontal stress by using the elasticity of the surface to hook onto the openings 13a.

[0055] <Manufacturing Method>

[0056] In order to mount the semiconductor element 11 having such a structure onto the semiconductor device 1, such as Figure 1 As shown, when the semiconductor element 11 is a MOS transistor, a bonding material 31, such as a solder material with tin as the main material or a sintering material with silver and copper as the main materials, will become the drain electrode of the lower surface bonded to the conductor substrate 21.

[0057] The conductor substrate 21 is a substrate on which an insulating substrate (not shown) is mounted on a heat sink (not shown) made of a material with good thermal conductivity such as copper. A circuit pattern is formed on the upper surface of the insulating substrate. The drain electrode of the semiconductor element 11 is thermally and electrically connected to the circuit pattern through a bonding material 31.

[0058] The source electrode 11c, which forms the upper surface of the semiconductor element 11, is bonded to the lead frame 22, which is made primarily of copper, using a solder material 32, or a sintered material, which is made primarily of silver and copper, as the bonding material 32. Alternatively, the source electrode 11c can be configured such that wires with a diameter of several hundred μm, made primarily of aluminum or copper, are mechanically bonded together by wire bonding or the like, with the other end of the wires connected to an external terminal.

[0059] After the semiconductor element 11 is mounted on the conductor substrate 21, for example, in the state where the semiconductor element 11 is mounted on the conductor substrate 21 and the lead frame 22 in a molding die, the encapsulation resin 41 is molded by a transfer molding encapsulation technique in which molding resin is injected into the molding die under pressure and then heated, thereby completing the semiconductor device 1.

[0060] By using epoxy resins for encapsulating resin 41, reliability such as moisture resistance and temperature cycling resistance can be improved compared to using gels for encapsulating materials.

[0061] When a thermosetting resin is used as the encapsulating resin 41, if the semiconductor device 1 is subjected to stress caused by temperature cycling, stress is generated on the semiconductor element 11 due to the stress from the encapsulating resin 41, and the protective film 14 on the surface of the semiconductor element 11 may peel off.

[0062] Therefore, use Figures 7-9 The stress contour plot shown illustrates the results of stress simulation obtained from the stress generated at the interface between the protective film 14 and the semiconductor element 11 under the condition that the semiconductor device 1 is subjected to stress caused by temperature cycling.

[0063] Figure 7 This is a stress contour plot showing the stress simulation results for a semiconductor element 111 that does not have an anchoring film 13 on the outer periphery of the gate wiring 11b.

[0064] exist Figure 7 The image shows, from top to bottom, the changes in the position of the peeling front end 14E as the peeling of the protective film 14 begins at the end of the semiconductor element 111 and progresses to the inner side (source electrode 11c side).

[0065] exist Figure 7 In the uppermost stress contour map, peak tensile stress is generated at the ends of semiconductor element 111 and protective film 14, and peak compressive stress is generated at the pre-peel end 14E. Furthermore, in Figures 7-9 In the diagram, the darker the color, the higher the stress.

[0066] As shown in the second stress contour map from the top, if the stress increases further, the peeling front end 14E moves inward, and the peeling area 14O expands. The same situation is observed in the third, fourth, and fifth stress contour maps from the top, showing that the peeling front end 14E moves inward and the peeling area 14O expands.

[0067] In addition, such as Figure 7As shown, it can be seen that with the development of peeling, the range of the peak value of tensile stress at the peeling start point of the semiconductor element 111 and the protective film 14 increases.

[0068] Regarding semiconductor element 111, when peeling progresses inward over the end region 11a, the peak value of compressive stress at the peeling tip 14E remains unchanged, maintaining a high value. This demonstrates that once peeling of the protective film 14 occurs, its progression cannot be suppressed. If the peeling of the protective film 14 progresses further inward, for example, reaching the gate wiring 11b, it causes a short circuit between the gate electrode and the source electrode, and a decrease in the discharge initiation voltage between the gate electrode and the drain electrode, thus reducing the reliability of the semiconductor device.

[0069] Figure 8 This is a stress contour plot showing the stress simulation results of a semiconductor element 11 with an anchoring film 13 disposed on the outer periphery of the gate wiring 11b. It is the stress simulation result when the arrangement interval of the openings 13a of the anchoring film 13 is set to 10 μm.

[0070] exist Figure 8 Nakaya and Figure 7 Similarly, from top to bottom, we show the changes in the position of the peeling front end 14E as the peeling of the protective film 14 begins from the end of the semiconductor element 11 and progresses to the inner side (source electrode 11c side).

[0071] exist Figure 8 In the uppermost part of the stress contour map, the peak value of tensile stress is generated at the end of semiconductor element 11 and protective film 14, and the peak value of compressive stress is generated at the peeling end 14E.

[0072] As shown in the second stress contour plot from the top, if the stress increases further, the peeling tip 14E moves inward, and the peeling region 14O expands. The same situation is observed in the third, fourth, and fifth stress contour plots from the top. It can be seen that the peeling tip 14E moves inward, and the peeling region 14O expands, which is the same as the semiconductor element 111. However, when the peeling develops inward above the end region 11a, in the peeling region 14O which is further outward than the peeling tip 14E, the protective film 14 hooks onto the anchoring film 13, and the tensile stress is dispersed in the peeling region 14O.

[0073] That is, in the second stress contour map from the top and below, there are multiple peak points of tensile stress in the peeling region 14O. In this part, the protective film 14 is hooked onto the opening 13a of the anchoring film 13, so the protective film 14 shares the stress from the encapsulating resin 41 as tensile stress. As a result, the peak value of the compressive stress at the peeling front end 14E is smaller than that of the semiconductor element 111. It can be understood that the reason is that, with Figure 7 In contrast, even with the peeling process, the range of the peak tensile stress at the peeling start point at the ends of the semiconductor element 11 and the protective film 14 did not increase.

[0074] If the peak value of the compressive stress at the peeling front end 14E is reduced, the development of peeling can be suppressed. If the development of peeling can be suppressed, the rate at which peeling develops further inward can be reduced, thereby extending the lifespan of the semiconductor device 1.

[0075] Furthermore, even if the protective film 14 peels off from the outermost periphery of the semiconductor element 11 and extends to the middle of the end region 11a, the opening 13a of the anchor film 13 does not penetrate the interlayer insulating film 12 and exists only in the anchor film 13. Therefore, the silicon carbide layer in the end region 11a remains covered by the interlayer insulating film 12. Thus, no degradation phenomena that cause discharge or the like occur in the end region 11a, and the breakdown voltage of the semiconductor element 11 can be prevented from decreasing.

[0076] Figure 9 This is a stress contour plot showing the stress simulation results of a semiconductor element 11 with an anchoring film 13 disposed on the outer periphery of the gate wiring 11b. It is the stress simulation result when the arrangement interval of the openings 13a of the anchoring film 13 is set to 50 μm.

[0077] exist Figure 9 Nakaya and Figure 8 Similarly, from top to bottom, we show the changes in the position of the peeling front end 14E as the peeling of the protective film 14 begins from the end of the semiconductor element 11 and progresses to the inner side (source electrode 11c side).

[0078] exist Figure 9 The uppermost part of the stress contour map and Figure 8The similarity is that a peak of tensile stress is generated at the end of the semiconductor element 11 and the protective film 14, and a peak of compressive stress is generated at the peeling end 14E. According to the stress contour plot from the second to the top, the protective film 14 at the peeling region 14O, which is further outward than the peeling end 14E, has fewer hook points towards the opening 13a. Therefore, the anchoring film 13 cannot adequately bear the compressive stress of the peeling end 14E. This is believed to be because the protective film 14 itself stretches, thus the hooking of the anchoring film 13 towards the opening 13a is insufficient to adequately maintain the compressive stress generated at the peeling end 14E.

[0079] Therefore, the spacing of the openings 13a in the anchoring film 13 needs to be designed in accordance with the Young's modulus and breakdown strength of the protective film 14. When the protective film 14 is formed of polyimide, if the changes in pattern size, such as shrinkage after polyimide firing, are taken into account, it is preferable to set the spacing of the openings 13a to be greater than or equal to 5 μm and less than or equal to 20 μm, so as to balance stress reduction effect and pattern accuracy.

[0080] For example, by forming the interlayer insulating film 12 from silicon oxide, the anchoring film 13 from silicon nitride, and the protective film 14 from polyimide, the interlayer insulating film 12 and the anchoring film 13 can be made of materials harder than the protective film 14. When the protective film 14 peels off, the protective film 14 deforms, thereby distributing stress and preventing the anchoring film 13 from peeling off or the interlayer insulating film 12 from cracking. Furthermore, if each of these materials is used, they can be easily formed using existing wafer fabrication processes, thus suppressing increases in manufacturing costs.

[0081] In addition, by making the inner side of the opening 13a of the anchoring film 13 (the side where the active region AR and the gate wiring 11b are formed) rounded, the tensile stress generated when the protective film 14 is stuck after being peeled off can be dispersed, and the anchoring film 13 can be prevented from peeling off.

[0082] Furthermore, by dispersing the openings 13a, when the protective film 14 peels off, the compressive stress can be dispersed planarly within the plane of the end region 11a, thus preventing the peeling from developing locally.

[0083] In the case of the semiconductor device 1 of Embodiment 1 described above, the semiconductor element 11 is a SiC semiconductor element, but it may also be a Si semiconductor element made of silicon.

[0084] SiC has an insulation breaking strength that is about 10 times that of Si, and can reduce the thickness of the semiconductor layer to about 1 / 10 of that of Si. Therefore, SiC semiconductor devices can achieve low on-state voltage. In addition, they can also operate at high temperatures. Thus, compared with Si semiconductor devices, SiC semiconductor devices can achieve miniaturization and high efficiency.

[0085] Furthermore, semiconductor element 11 is not limited to... Figure 1 The semiconductor device 1 shown can achieve the same effect as described above by mounting the semiconductor element 11, as long as the semiconductor element is encapsulated in resin.

[0086] Furthermore, the present invention may make appropriate modifications or omissions to the embodiments within the scope of its invention.

Claims

1. A semiconductor device comprising: substrate; A semiconductor element, which is bonded to the substrate; as well as An encapsulating resin that encapsulates at least a portion of the substrate and the semiconductor element. The semiconductor element has: An active region through which the main current flows when the semiconductor element is switched on; The terminal region surrounding the active region; An anchoring film is disposed only on the insulating film in the end region; as well as A protective film that at least covers the end region containing the anchoring film. The anchoring membrane is made of a different material than the insulating membrane and has a plurality of dispersed openings. The anchoring film is entirely separated from the insulating film and the semiconductor layer of the end region. The minimum spacing between the plurality of openings is set to be greater than or equal to 5 μm and less than or equal to 20 μm.

2. The semiconductor device according to claim 1, wherein, The anchoring membrane, when viewed from above, is arranged along the end region in a ring shape.

3. The semiconductor device according to claim 1, wherein, The plurality of openings have a top view shape in which at least the edge on the active region side is arc-shaped.

4. The semiconductor device according to claim 3, wherein, The top view of the plurality of openings is circular.

5. The semiconductor device according to claim 3, wherein, The top view of the plurality of openings is semi-circular.

6. The semiconductor device according to claim 3, wherein, The top view of the plurality of openings is crescent-shaped.

7. The semiconductor device according to claim 1, wherein, The semiconductor element is a silicon carbide semiconductor element.

8. The semiconductor device according to claim 1, wherein, The protective film is a film made primarily of polyimide or polyamide.

9. The semiconductor device according to claim 1, wherein, The anchoring membrane is a membrane made primarily of silicon nitride.

10. A semiconductor element having: The active region, in which the main current flows when the circuit is on; The terminal region surrounding the active region; An anchoring film is disposed only on the insulating film in the end region; as well as A protective film that at least covers the end region containing the anchoring film. The anchoring film is made of a different material from the insulating film and has a plurality of openings that are dispersed throughout the anchoring film. The anchoring film is entirely separated from the insulating film and the semiconductor layer of the end region. The minimum spacing between the plurality of openings is set to be greater than or equal to 5 μm and less than or equal to 20 μm.

Images