Common-mode voltage generation circuit and successive approximation analog-to-digital converter

Abstract

The invention provides a common-mode voltage generation circuit and a successive approximation type analog-to-digital converter comprising the same, the common-mode voltage generation circuit is connected with a capacitor array in the successive approximation type analog-to-digital converter, and under the control of an externally input control signal, according to a first voltage and a second voltage which are externally input, the common-mode voltage generation circuit generates a common-mode voltage according to the first voltage and the second voltage which are externally input. The common-mode voltage generation circuit generates different common-mode voltages, and the common-mode voltages can enable node voltages output by the capacitor array not to generate negative voltages when the differential input signals with different input voltage common-mode values are subjected to analog-to-digital conversion, and the output differential output signals are always within a voltage threshold range. Different common-mode voltages are provided for the capacitor array through the common-mode voltage generation circuit, so that the successive approximation type analog-to-digital converter can be suitable for input signals in different input ranges, and the application range is wide; and the common-mode voltage generation circuit adopts a conventional electrical element, so that the circuit structure is simple, and the circuit has the advantages of low cost and high reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-to-digital converter, and particularly relates to a common-mode voltage generation circuit and a successive approximation register (SAR) analog-to-digital converter (ADC). BACKGROUND

[0002] Analog-to-digital converter is an important bridge connecting analog system and digital signal processing system. With the wide application of ADC in the field of digital signal processing technology and wireless communication, especially the successive approximation register (SAR) analog-to-digital converter (ADC) has great influence in the field of wireless sensor devices and high-speed communication standards due to its inherent low power consumption.

[0003] Commonly used SAR ADC based on common-mode switching is widely used for detecting various parameters of a chip, including power supply voltage, temperature sensor voltage, current sensor output, etc. In the existing processing method of the common-mode voltage of the SAR ADC, a high-precision bandgap voltage is usually generated by using a bandgap reference voltage generation circuit, and the bandgap voltage is used as the reference voltage Vref of the SAR ADC. At this time, the differential input range of the SAR ADC is between-Vref and Vref, and Vref may be less than the power supply voltage VDD. That is, the input range of the differential SAR ADC is doubled, so the dynamic range is larger. In order to use the maximum signal range, generally, the common-mode voltage Vcm in the SAR ADC is set to Vref / 2.

[0004] However, when the input voltage common-mode value of the differential input signal of the SAR ADC is greater than VDD / 2 or less than VDD / 2, the MOS switch in the SAR ADC circuit will be misdirected, which will cause the charge conservation of the top plate of the capacitor in the capacitor array, and the analog-to-digital conversion result of the SAR ADC will be incorrect.

[0005] Therefore, due to the fixed value of the common-mode voltage Vcm, when the SAR ADC needs to face different input common-mode voltage values Vcmi of the differential input, there is a possibility that the top plate voltage of the capacitor in the capacitor array of the SAR ADC exceeds the range of [GND, VDD], so that the charge of the node is no longer conserved, and the conversion result of the SAR ADC is incorrect. SUMMARY

[0006] The present application provides a common-mode voltage generation circuit and a successive approximation register (SAR) analog-to-digital converter, which can solve the technical problem that the differential output signal after digital-to-analog conversion exceeds the range of [0, VDD] when the successive approximation register (SAR) analog-to-digital converter based on common-mode switching faces different input common-mode voltages, resulting in incorrect conversion results.

[0007] In a first aspect, the embodiments of the present application provide a common-mode voltage generation circuit applied to a successive approximation analog-to-digital converter, the common-mode voltage generation circuit comprising:

[0008] an input end comprising a first input end and a second input end, configured to acquire a first voltage and a second voltage inputted from outside, wherein the first voltage is not equal to the second voltage;

[0009] an output end configured to output a common-mode voltage;

[0010] a common-mode voltage adjustment module arranged between the first input end and the second input end, configured to generate different common-mode voltages according to the first voltage and the second voltage under the control of an external control signal;

[0011] The common-mode voltage outputted by the common-mode voltage adjustment module can make the successive approximation analog-to-digital converter output a differential output signal within a voltage threshold range when performing analog-to-digital conversion on a differential input signal with different common-mode values of input voltage, wherein the voltage threshold range is [0, VDD], and VDD is a power voltage.

[0012] In some embodiments, when the common-mode value of input voltage of the differential input signal is greater than a threshold voltage, the common-mode voltage outputted by the common-mode voltage adjustment module is greater than the threshold voltage.

[0013] When the common-mode value of input voltage of the differential input signal is less than a threshold voltage, the common-mode voltage outputted by the common-mode voltage adjustment module is less than the threshold voltage.

[0014] In some embodiments, the threshold voltage VQ∈[0, VDD].

[0015] In some embodiments, the common-mode voltage adjustment module comprises a voltage division adjustment unit and a switch unit.

[0016] The voltage division adjustment unit comprises N series-connected voltage division resistors, and the voltage division resistors are connected between the first voltage and the second voltage.

[0017] The switch unit comprises N-1 analog switches, a first end of the analog switch is connected between every two voltage division resistors, a second end of the analog switch is commonly connected and connected with the output end, and a control end of the analog switch is commonly connected and configured to acquire the external control signal.

[0018] The switch unit is configured to turn on or turn off one or more analog switches under the control of the external control signal, so as to adjust the voltage value of the common-mode voltage through one or more voltage division resistors.

[0019] In some embodiments, the common-mode voltage adjusting module further comprises a filter capacitor; a first end of the filter capacitor is connected to the second end of the analog switch, and a second end of the filter capacitor is grounded.

[0020] In a second aspect, the embodiments of the present application provide a successive approximation type analog-to-digital converter, comprising:

[0021] a digital-to-analog converter comprising an in-phase end capacitor array and an anti-phase end capacitor array; the digital-to-analog converter is configured to, in a sampling phase, perform corresponding switch switching according to a sampling control signal, sample a differential input signal through the in-phase end capacitor array and the anti-phase end capacitor array; in a conversion phase, perform corresponding switch switching according to a conversion control signal, and generate an in-phase end node voltage and an anti-phase end node voltage based on an externally input reference voltage and / or a common-mode voltage;

[0022] a comparison module connected to the in-phase end capacitor array and the anti-phase end capacitor array, configured to generate a comparison signal according to the in-phase end node voltage and the anti-phase end node voltage;

[0023] a successive approximation logic control module connected to the in-phase end capacitor array, the anti-phase end capacitor array and the comparison module, configured to generate and output a differential output signal after analog-to-digital conversion according to the comparison signal;

[0024] a common-mode voltage generation circuit connected to the in-phase end capacitor array and the anti-phase end capacitor array, configured to generate different common-mode voltages according to an externally input first voltage and a second voltage; the common-mode voltage output by the common-mode voltage adjusting module can enable the successive approximation type analog-to-digital converter to output a differential output signal within a voltage threshold range when performing analog-to-digital conversion on a differential input signal with different common-mode values of input voltage; wherein the first voltage is not equal to the second voltage; the voltage threshold range is [0, VDD], and VDD is a power voltage.

[0025] In some embodiments, when the input common-mode voltage of the differential input signal is greater than a threshold voltage, the common-mode voltage output by the common-mode voltage adjusting module output by the common-mode voltage generation circuit is greater than the threshold voltage.

[0026] When the input common-mode voltage of the differential input signal is less than a threshold voltage, the common-mode voltage output by the common-mode voltage adjusting module output by the common-mode voltage generation circuit is less than the threshold voltage.

[0027] In some embodiments, the threshold voltage VQ∈[0, VDD].

[0028] In some embodiments, the common-mode voltage generation circuit comprises a voltage division adjusting unit and a switch unit.

[0029] The voltage divider adjustment unit includes N voltage divider resistors connected in series; the voltage divider resistors are connected between the first voltage and the second voltage;

[0030] The switching unit includes N-1 analog switches. The first terminal of each analog switch is connected between every two voltage divider resistors. The second terminals of each analog switch are connected together and connected to the output terminal of the common-mode voltage generating circuit. The control terminals of the analog switches are connected together to acquire the external control signal.

[0031] The switching unit is used to turn one or more analog switches on or off under the control of the external control signal, so as to adjust the voltage value of the common mode voltage through one or more voltage divider resistors.

[0032] In some embodiments, the common-mode voltage regulation module further includes a filter capacitor; the first terminal of the filter capacitor is connected to the second terminal of the analog switch, and the second terminal of the filter capacitor is grounded.

[0033] The common-mode voltage generation circuit and the successive approximation analog-to-digital converter (ADC) including the common-mode voltage generation circuit provided in this application embodiment are connected to the capacitor array in the successive approximation ADC. Under the control of an externally input control signal, different common-mode voltages are generated according to the first and second externally input voltages. These common-mode voltages ensure that when performing analog-to-digital conversion on differential input signals with different common-mode values, the node voltages output by the capacitor array will not be negative, and the output differential signal will always be within the voltage threshold range. This application provides different common-mode voltages to the capacitor array through the common-mode voltage generation circuit, enabling the successive approximation ADC to be applicable to input signals with different input ranges, thus having a wide range of applications. Furthermore, the common-mode voltage generation circuit uses conventional electrical components, has a simple circuit structure, and offers advantages such as low cost and high reliability. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0035] Figure 1 This is a schematic diagram of an existing analog-to-digital converter based on common-mode switching;

[0036] Figure 2 The circuit diagram for an existing capacitor unit;

[0037] Figure 3 This is a schematic diagram of the structure of a successive approximation analog-to-digital converter provided in one embodiment of this application;

[0038] Figure 4This is a schematic diagram of the common-mode voltage generation circuit provided in one embodiment of this application;

[0039] Figure 5 This is a circuit diagram of a common-mode voltage regulation module provided in one embodiment of this application.

[0040] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0041] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0042] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0043] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages).

[0044] Figure 1 This is a schematic diagram of an existing analog-to-digital converter based on common-mode switching. (Example:) Figure 1 As shown, existing SAR ADCs based on common-mode switching include a DAC (Digital-to-Analog Converter) module, a Comp (Comparison) module, and a SAR-Logic register-type logic control module. The DAC module includes capacitor arrays CDAC, consisting of a non-inverting capacitor array CDACP and an inverting capacitor array CDACN. Each array contains eight small capacitor units, each including a capacitor and a switching switch. The top plate of the capacitor is connected to the differential common-mode signal Vcm, while the bottom plate, under the control of the switching control signal and the successive comparison control signal, is connected to the differential input signal (Vin and Vip), the reference voltage (Vrefn and Vrefp), and the common-mode voltage Vcm via the switching switch. The outputs of the non-inverting capacitor array CDACP and the inverting capacitor array CDACN are connected to the non-inverting and inverting inputs of the comparison module, respectively. The comparison module transmits the comparison result of the two node voltages to the SAR-Logic register-type logic control module, which performs logical operations to obtain the converted differential output value. After each bit of analog-to-digital conversion, the SAR ADC feeds back the digital result to the internal DAC to obtain the conversion voltage for the next bit. This process is repeated n times to obtain the complete analog-to-digital conversion result from the most significant bit to the least significant bit, thus achieving multi-bit analog-to-digital conversion.

[0045] Figure 2 The diagrams show the circuit diagrams of capacitor units in an existing capacitor array; (a) is the circuit diagram of a capacitor unit in the non-inverting capacitor array; and (b) is the circuit diagram of a capacitor unit in the inverting capacitor array. (Combined with...) Figure 1 and Figure 2 In (a) and (b), the conventional common-mode switching-based SAR ADC has its capacitors in the CDAC array connected together on their top plates and connected to the input of the comparator module. The bottom plates of the CDAC capacitors are connected to the differential input signal, and bottom-plate sampling is used. Its specific operation is as follows:

[0046] During the sampling phase, the top plate of the CDAC capacitor is connected to its internal common-mode voltage Vcm under the control of the sampling control signal, while each bottom plate of the CDAC capacitor is connected to the input signal Vin (Vip) for sampling. At the switching moment from sampling to quantization (i.e., the charge-splitting phase), the switch between the top plate of the CDAC capacitor and the common-mode voltage Vcm is disconnected. At this time, the node is in a floating state, and its voltage is determined by the bottom plate of the CDAC capacitor. The bottom plate of the CDAC capacitor switches from Vin (Vip) to Vcm. At this time, the voltage of the top plate of the CDAC capacitor is Vtop = Vcm + (Vcm - Vin) = 2 * Vcm - Vin (Vip).

[0047] In the initial stage of SAR ADC conversion, the common-mode value of the output voltage of capacitor array CDAC is 2*Vcm-Vcmi, which shows that it is inversely proportional to the common-mode value of input voltage Vcmi.

[0048] It is understandable that when the input common-mode voltage Vcmi is greater than VDD / 2 and the common-mode voltage Vcm is too low, the output common-mode voltage of the capacitor array CDAC will be lower than VDD / 2. Furthermore, the larger the input common-mode voltage Vcmi, the lower the output common-mode voltage of the capacitor array CDAC. In this case, given a fixed common-mode voltage Vcmi, the value of the common-mode voltage Vcm may cause the differential output voltage of the capacitor array CDAC to fall below GND. At this point, the NMOS switch between the capacitor top plate and the common-mode voltage Vcm in the CDAC may still be turned on even when its gate voltage is GND, thus disrupting the charge conservation of the CDAC top plate and causing errors in the conversion results of the SAR ADC.

[0049] Similarly, when the input common-mode voltage Vcmi is less than VDD / 2 and the common-mode voltage Vcm is too high, the output common-mode voltage of the capacitor array CDAC will be higher than VDD / 2. Furthermore, the smaller the input common-mode voltage Vcmi, the higher the output common-mode voltage of the capacitor array CDAC. In this case, given a fixed common-mode voltage Vcmi, the value of the common-mode voltage Vcm may cause the differential output voltage of the capacitor array CDAC to be higher than VDD. At this point, the PMOS switch between the DAC capacitor top plate and Vcm may also be turned on even when its gate voltage is VDD, thus disrupting the charge conservation of the CDAC top plate and causing errors in the SAR ADC conversion results.

[0050] For traditional SAR ADCs based on common-mode switching, the CDAC common-mode voltage Vcm is generally VDD / 2. If the differential input voltage common-mode value Vcmi is also VDD / 2, then the differential voltage output by the CDAC during the conversion stage will always be symmetrical based on Vcm = VDD / 2.

[0051] Therefore, in traditional common-mode switching-based SAR ADCs, since the CDAC common-mode voltage Vcm is a fixed value, when the SAR ADC needs to deal with differential inputs with different input voltage common-mode values ​​Vcmi, there is a possibility that the CDAC top plate voltage may exceed the range of [GND, VDD], which will cause the node charge to no longer be conserved, resulting in errors in the conversion results of the SAR ADC.

[0052] Therefore, this application proposes a common-mode voltage generation circuit and a successive approximation analog-to-digital converter to address the technical problem that existing successive approximation analog-to-digital converters based on common-mode switching have differential output signals that exceed the range [0, VDD] when faced with differential inputs of different input common-mode voltages, resulting in incorrect conversion results.

[0053] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0054] Figure 3 Figure 3 is a schematic diagram of the structure of a successive approximation analog-to-digital converter provided in one embodiment of this application. As shown in Figure 3, the successive approximation analog-to-digital converter provided in this embodiment includes a digital-to-analog converter 310, a comparison module 320, a successive approximation logic control module 330, and a common-mode voltage generation circuit 340.

[0055] In this embodiment, the digital-to-analog converter 310 includes a non-inverting capacitor array 3101 and an inverting capacitor array 3102. The non-inverting capacitor array 3101 and the inverting capacitor array 3102 each include a plurality of capacitor units. Each capacitor unit includes a capacitor and a capacitor switch. The first input terminal of the non-inverting capacitor array 3101 is used to acquire a first input signal Vip, and the first input terminal of the inverting capacitor array 3102 is used to acquire a second input signal Vin.

[0056] During the sampling phase, the digital-to-analog converter 310 is used to switch each capacitor switch in the in-phase capacitor array 3101 and the in-phase capacitor array 3102 according to the sampling control signal PHS, and to sample the first input signal and the second input signal analog input signal through the in-phase capacitor array 3101 and the in-phase capacitor array 3102.

[0057] During the conversion phase, the digital-to-analog converter 310 is also used to switch each capacitor switch in the in-phase capacitor array 3101 and the in-phase capacitor array 3102 according to the conversion control signal PHC, and generate the in-phase node voltage DACP and the in-phase node voltage DACN based on the reference voltage and / or common-mode voltage Vcm.

[0058] The comparison module 320 is connected to the in-phase capacitor array 3101 and the in-phase capacitor array 3102 respectively. The comparison module 320 is used to receive the in-phase node voltage DACP and the in-phase node voltage DACN output by the two, and generate a comparison signal based on the in-phase node voltage DACP and the in-phase node voltage DACN.

[0059] The successive approximation logic control module 330 is connected to the non-inverting capacitor array 3101, the inverting capacitor array 3102, and the comparator module 320, respectively. The successive approximation logic control module 330 is used to generate and output a digital output signal ADCOUT, which is a digital signal after analog-to-digital conversion, corresponding to the first input signal and the second input signal, based on the comparison signal obtained from the comparator module 320.

[0060] The common-mode voltage generation circuit 340 is connected to the non-inverting capacitor array 3101 and the inverting capacitor array 3102, and is used to generate different common-mode voltages Vcm based on the first and second externally input voltages. This common-mode voltage Vcm ensures that when differential input signals with different common-mode values ​​of the input voltage are converted from analog to digital, the output differential output signal is always within the voltage threshold range; where the voltage threshold range is [0, VDD], and VDD is the power supply voltage.

[0061] The following describes the specific process by which the common-mode voltage generation circuit 340 generates different common-mode voltages.

[0062] As mentioned above, in traditional SAR ADCs based on common-mode switching, since the CDAC common-mode voltage Vcm is a fixed value, such as VDD / 2, when the SAR ADC needs to deal with differential inputs with different input voltage common-mode values ​​Vcmi, there is a possibility that the CDAC top plate voltage may exceed the range of [GND, VDD], which will cause the node charge to no longer be conserved, resulting in errors in the conversion results of the SAR ADC.

[0063] Figure 4 This is a schematic diagram of a common-mode voltage generation circuit provided in one embodiment of this application. Figure 4 As shown, the common-mode voltage generation circuit provided in this application embodiment includes an input terminal, an output terminal, and a common-mode voltage regulation module.

[0064] The system includes a first input terminal and a second input terminal, used to acquire a first voltage and a second voltage from external inputs, respectively; wherein the first voltage is not equal to the second voltage. The output terminal outputs a common-mode voltage Vcm. A common-mode voltage regulation module is positioned between the first and second input terminals. Under the control of an external control signal Vcm_SEL, the common-mode voltage regulation module generates different common-mode voltages Vcm based on the first and second voltages, and outputs these voltages to the non-inverting capacitor array 3101 and the inverting capacitor array 3102 via the output terminal.

[0065] It should be noted that the common-mode voltage Vcm output by the common-mode voltage regulation module provided in this embodiment enables the successive approximation analog-to-digital converter to always output a differential output signal within the voltage threshold range when performing analog-to-digital conversion on differential input signals with different common-mode input voltage values; wherein, the voltage threshold range is [0, VDD], and VDD is the power supply voltage.

[0066] As analyzed above, in the initial stage of conversion by the SAR ADC, the common-mode output voltage of the capacitor array CDAC is 2*Vcm-Vcmi, which is inversely proportional to the input common-mode voltage Vcmi. When the input common-mode voltage Vcmi is greater than VDD / 2 and the common-mode voltage Vcm is too low, the output common-mode voltage of the capacitor array CDAC will be lower than VDD / 2. Furthermore, the larger the input common-mode voltage Vcmi, the lower the output common-mode voltage of the capacitor array CDAC. Similarly, when the input common-mode voltage Vcmi is less than VDD / 2 and the common-mode voltage Vcm is too high, the output common-mode voltage of the capacitor array CDAC will be higher than VDD / 2. Furthermore, the smaller the input common-mode voltage Vcmi, the higher the output common-mode voltage of the capacitor array CDAC.

[0067] Therefore, for a successive approximation analog-to-digital converter to perform analog-to-digital conversion on differential input signals with different common-mode input voltage values, the output differential output signal is always within the range [0, VDD]. The common-mode voltage regulation module provided in this application, when adjusting its output common-mode voltage Vcm:

[0068] When the common-mode value of the input voltage of the differential input signal is greater than the threshold voltage, the common-mode voltage Vcm output by the common-mode voltage regulation module is greater than the threshold voltage.

[0069] When the common-mode value of the input voltage of the differential input signal is less than the threshold voltage, the common-mode voltage Vcm output by the common-mode voltage regulation module is less than the threshold voltage.

[0070] It should be noted that when the common-mode value of the input voltage of the differential input signal is equal to the threshold voltage, the common-mode voltage Vcm output by the common-mode voltage regulation module provided in this embodiment can be greater than or less than the threshold voltage, or it can be equal to the threshold voltage.

[0071] In some embodiments, the threshold voltage VQ ∈ [0, VDD], and in general, the threshold voltage VQ = VDD / 2.

[0072] Specifically, assuming the threshold voltage VQ = VDD / 2, when the common-mode value of the differential input signal is greater than VDD / 2, the common-mode voltage Vcm output by the common-mode voltage regulation module is also greater than VDD / 2. Since the common-mode value of the capacitor array CDAC output voltage is 2*Vcm-Vcmi, the situation where the common-mode value of the capacitor array CDAC output voltage is lower than GND can be avoided when the common-mode value of the input voltage Vcmi is greater than VDD / 2 and the common-mode voltage Vcm is too low.

[0073] Meanwhile, when the common-mode value of the differential input signal is less than VDD / 2, the common-mode voltage Vcm output by the common-mode voltage regulation module is also less than VDD / 2. Since the common-mode value of the capacitor array CDAC output voltage is 2*Vcm-Vcmi, the situation where the common-mode value of the capacitor array CDAC output voltage is higher than VDD can be avoided when the common-mode value of the input voltage Vcmi is less than VDD / 2 and the common-mode voltage Vcm is too high.

[0074] Figure 5 This is a circuit diagram of a common-mode voltage regulation module provided in one embodiment of this application. Figure 5 As shown, the common-mode voltage regulation module provided in this application embodiment includes a voltage divider regulation unit and a switching unit.

[0075] The voltage divider adjustment unit includes N voltage divider resistors connected in series. Multiple voltage divider resistors are connected between the first input terminal and the second input terminal. The first end of the first voltage divider resistor is used to obtain the first voltage, and the second end of the Nth voltage divider resistor is used to obtain the second voltage.

[0076] In some embodiments, the first voltage is the power supply voltage VDD, and the second voltage is the grounding voltage GND.

[0077] The switching unit comprises N-1 analog switches, each positioned between two series-connected voltage divider resistors. The first terminal of each analog switch is connected to the common terminal of its corresponding two voltage divider resistors. The second terminals of all N-1 analog switches are connected together and to the output of the common-mode voltage generation circuit, outputting different common-mode voltages Vcm. The control terminals of all N-1 analog switches are also connected together to acquire an external control signal Vcm_SEL. Under the control of the external control signal Vcm_SEL, the switching unit turns one or more analog switches on or off, connecting one or more voltage divider resistors in the common-mode voltage regulation module to the circuit, thereby adjusting the output common-mode voltage Vcm to different values.

[0078] In some embodiments, the common-mode voltage regulation module further includes a filter capacitor; the first terminal of the filter capacitor is connected to the common connection terminal of the second terminals of all analog switches, and the second terminal of the filter capacitor is grounded.

[0079] In summary, the common-mode voltage generation circuit and the successive approximation analog-to-digital converter (ADC) including the common-mode voltage generation circuit provided in this application embodiment are connected to the capacitor array in the successive approximation ADC. Under the control of an externally input control signal, different common-mode voltages are generated according to the first and second externally input voltages. These common-mode voltages ensure that when performing analog-to-digital conversion on differential input signals with different common-mode values, the node voltages output by the capacitor array will not be negative, and the output differential signal will always be within the voltage threshold range. This application provides different common-mode voltages to the capacitor array through the common-mode voltage generation circuit, enabling the successive approximation ADC to be applicable to input signals with different input ranges, thus having a wide range of applications. Furthermore, the common-mode voltage generation circuit uses conventional electrical components, has a simple circuit structure, and offers advantages such as low cost and high reliability.

[0080] In a specific example, for a successive approximation analog-to-digital converter, assuming its VDD = 5.0V, VREF = 2.5V, Vcmi = 4.0V, Vip = 4.2V, and Vin = 2.8V, Vcmi = 4.0V is greater than VDD / 2 = 2.5V. Therefore, the common-mode voltage Vcm generated by the common-mode voltage generation circuit provided in this application embodiment needs to be greater than VDD / 2.

[0081] Assume that the common-mode voltage generation circuit outputs Vcm = 3.5V at this point. According to the working principle of a successive approximation analog-to-digital converter based on common-mode switching, the capacitor array CDAC outputs at the initial stage of conversion are: CDACP = 2*Vcm - Vinp = 7.0 - 4.2 = 2.8V, CDACN = 2*Vcm - Vin = 7.0 - 2.8 = 3.2V. After quantization of the first bit, the capacitor array outputs become: CDACP = 2.8 + (VREF - Vcm) / 2 = 2.3V, CDACN = 3.2 + (0 - Vcm) / 2 = 1.45V.

[0082] Further assuming that the common-mode voltage Vcm output by the common-mode voltage generation circuit is less than VDD / 2, for example, Vcm = 1.5V, and based on the working principle of the successive approximation analog-to-digital converter with common-mode switching, the capacitor array CDAC outputs at the initial stage of conversion are: CDACP = 2*Vcm - Vinp = 3.0 - 4.2 = -1.2V, CDACN = 2*Vcm - Vin = 3.0 - 2.8 = -0.2V. After the first bit of quantization, the voltage output by the capacitor array will be lower than 0V (i.e., GND), which exceeds the operating range of [0, VDD]. This will cause errors in the conversion result of the successive approximation analog-to-digital converter.

[0083] In another specific example, for a successive approximation analog-to-digital converter, assuming its VDD = 5.0V, VREF = 2.5V, Vcmi = 1.0V, Vip = 1.2V, and Vin = 0.8V, Vcmi = 1.0V is less than VDD / 2 = 2.5V. In this case, the common-mode voltage Vcm generated by the common-mode voltage generation circuit provided in this application embodiment needs to be less than VDD / 2.

[0084] Let's assume the common-mode voltage Vcm is greater than VDD / 2, for example, Vcm = 4V. According to the working principle of a successive approximation analog-to-digital converter (ADC) with common-mode switching, the capacitor array CDAC outputs at the initial stage of conversion are: CDACP = 2*Vcm - Vip = 8.0 - 1.2 = 6.8V, CDACN = 2*Vcm - Vin = 8.0 - 0.8 = 7.2V. After the first bit of quantization, the voltage output of the capacitor array will be higher than 5V (i.e., VDD), which exceeds the operating range of [0, VDD]. This will cause errors in the conversion result of the successive approximation ADC.

[0085] Therefore, if the common-mode voltage Vcm = 2V generated by the common-mode voltage generation circuit provided in this application embodiment, according to the working principle of the successive approximation analog-to-digital converter based on common-mode switching, the outputs of the capacitor array CDAC in the initial stage of conversion are: CDACP = 2*Vcm - Vinp = 4.0 - 1.2 = 2.8V, CDACN = 2*Vcm - Vin = 4.0 - 0.8 = 3.2V. After the first bit quantization, the output of the capacitor array will become: CDACP = 2.8 + (VREF - Vcm) / 2 = 2.3V, CDACN = 3.2 + (0 - Vcm) / 2 = 1.45V, effectively solving the problem that the output voltage of the capacitor array CDAC is greater than VDD.

[0086] In summary, the common-mode voltage generation circuit provided in this application can provide different common-mode voltages for successive approximation analog-to-digital conversion based on common-mode switching, ensuring that the differential output signal after digital-to-analog conversion does not exceed the range of [0, VDD] when facing differential inputs with different input common-mode voltages, thus further guaranteeing the accuracy of the conversion result.

[0087] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art, under the guidance of this application, can make several simple deductions, modifications or substitutions based on the spirit of this application and the scope of protection of the claims without departing from the spirit of this application and the claims. All of these are within the protection scope of this application.

Claims

1. A common-mode voltage generation circuit, applied to a successive approximation analog-to-digital converter, characterized in that, include: The input terminal includes a first input terminal and a second input terminal, which are used to acquire a first voltage and a second voltage from external input, respectively; wherein the first voltage is not equal to the second voltage; The output terminal is used to output common-mode voltage. A common-mode voltage regulation module is disposed between the first input terminal and the second input terminal, and is used to generate different common-mode voltages according to the first voltage and the second voltage under the control of an external control signal; The common-mode voltage output by the common-mode voltage regulation module enables the successive approximation analog-to-digital converter to always output a differential output signal within the voltage threshold range when performing analog-to-digital conversion on differential input signals with different common-mode values ​​of the input voltage; wherein the voltage threshold range is [0, VDD], and VDD is the power supply voltage.

2. The common-mode voltage generating circuit according to claim 1, characterized in that: When the common-mode value of the input voltage of the differential input signal is greater than the threshold voltage, the common-mode voltage output by the common-mode voltage adjustment module is greater than the threshold voltage. When the common-mode value of the input voltage of the differential input signal is less than the threshold voltage, the common-mode voltage output by the common-mode voltage adjustment module is less than the threshold voltage.

3. The common-mode voltage generating circuit according to claim 1, characterized in that: The threshold voltage VQ ∈ [0, VDD].

4. The common-mode voltage generating circuit according to claim 1, characterized in that: The common-mode voltage regulation module includes a voltage divider regulation unit and a switching unit; The voltage divider adjustment unit includes N voltage divider resistors connected in series; the voltage divider resistors are connected between the first voltage and the second voltage; The switching unit includes N-1 analog switches. The first terminal of each analog switch is connected between every two voltage divider resistors. The second terminals of each analog switch are connected together and connected to the output terminal. The control terminals of each analog switch are connected together to acquire the external control signal. The switching unit is used to turn one or more analog switches on or off under the control of the external control signal, so as to adjust the voltage value of the common mode voltage through one or more voltage divider resistors.

5. The common-mode voltage generating circuit according to claim 4, characterized in that: The common-mode voltage regulation module also includes a filter capacitor; the first end of the filter capacitor is connected to the second end of the analog switch, and the second end of the filter capacitor is grounded.

6. A successive approximation analog-to-digital converter, characterized in that, include: A digital-to-analog converter (DAC) includes a non-inverting capacitor array and an inverting capacitor array; the DAC is used to switch accordingly based on a sampling control signal during the sampling phase, and to sample the differential input signal through the non-inverting capacitor array and the inverting capacitor array. During the conversion phase, corresponding switching is performed according to the conversion control signal, and the in-phase terminal voltage and the out-of-phase terminal voltage are generated based on the externally input reference voltage and / or common-mode voltage. A comparison module, connected to the non-inverting capacitor array and the inverting capacitor array, is used to generate a comparison signal based on the non-inverting node voltage and the inverting node voltage. The successive approximation logic control module, connected to the non-inverting capacitor array, the inverting capacitor array, and the comparison module, is used to generate and output the differential output signal after analog-to-digital conversion based on the comparison signal. A common-mode voltage generation circuit, connected to the non-inverting capacitor array and the inverting capacitor array, is used to generate different common-mode voltages based on the first and second externally input voltages. The common-mode voltage output by the common-mode voltage regulation module enables the successive approximation analog-to-digital converter to ensure that the differential output signal is always within the voltage threshold range when performing analog-to-digital conversion on differential input signals with different common-mode values ​​of the input voltage. The first voltage is not equal to the second voltage. The voltage threshold range is [0, VDD], where VDD is the power supply voltage.

7. The successive approximation analog-to-digital converter according to claim 6, characterized in that, When the input common-mode voltage of the differential input signal is greater than the threshold voltage, the common-mode voltage output by the common-mode voltage generation circuit and the common-mode voltage adjustment module is greater than the threshold voltage. When the input common-mode voltage of the differential input signal is less than the threshold voltage, the common-mode voltage output by the common-mode voltage generation circuit and the common-mode voltage adjustment module is less than the threshold voltage.

8. The successive approximation analog-to-digital converter according to claim 6, characterized in that, The threshold voltage VQ ∈ [0, VDD].

9. The successive approximation analog-to-digital converter according to claim 6, characterized in that, The common-mode voltage generation circuit includes a voltage divider adjustment unit and a switching unit; The voltage divider adjustment unit includes N voltage divider resistors connected in series; the voltage divider resistors are connected between the first voltage and the second voltage; The switching unit includes N-1 analog switches. The first terminal of each analog switch is connected between every two voltage divider resistors. The second terminals of each analog switch are connected together and connected to the output terminal of the common-mode voltage generating circuit. The control terminals of the analog switches are connected together to acquire the external control signal. The switching unit is used to turn one or more analog switches on or off under the control of the external control signal, so as to adjust the voltage value of the common mode voltage through one or more voltage divider resistors.

10. The successive approximation analog-to-digital converter according to claim 9, characterized in that: The common-mode voltage regulation module also includes a filter capacitor; the first end of the filter capacitor is connected to the second end of the analog switch, and the second end of the filter capacitor is grounded.

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