Uci e-based data transmission method, storage medium and artificial intelligence chip

Abstract

The application provides a data transmission method based on UCIe, a storage medium and an artificial intelligence chip. The data transmission method comprises the following steps: receiving, by a receiving module of a second core, bypass-received data signals and bypass-received clock signals from a sending module of a first core; transmitting, by the receiving module, the bypass-received data signals and the bypass-received clock signals to a serial-parallel conversion module of the second core; counting, by a receiving clock counter of the serial-parallel conversion module, the bypass-received clock signals to obtain a bypass-received frame count value; generating, by the serial-parallel conversion module, a gray code count according to the bypass-received clock signals, and generating a gray code count synchronization signal and a gray code count delay signal in a bypass-constant-on clock domain; comparing, by the serial-parallel conversion module, the gray code count synchronization signal and the gray code count delay signal to determine whether to asynchronously reset the bypass-received frame count value; and sampling, by the serial-parallel conversion module, the bypass-received data signals according to the bypass-received frame count value.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chips, in particular to a data transmission method based on UCIe, a computer readable storage medium and an artificial intelligence chip. BACKGROUND

[0002] In the communication process between the dies, since the bypass receiving data and the bypass receiving clock received by the receiving end are one-to-one corresponding, the type of the bypass data packet needs to be judged according to the data packet type code (opcode), and the serial-parallel conversion also needs to be completed according to the counting of the bypass receiving clock signal. However, if the clock on the receiving link has glitches, the receiving end will have data mis-sampling, which may cause data packet type code judgment error and serial-parallel conversion error, and finally lead to bypass data packet parsing error. SUMMARY

[0003] The present application is a data transmission method based on UCIe, a computer readable storage medium and an artificial intelligence chip, which can effectively ensure the data transmission reliability and data correctness of the sideband (or auxiliary channel) between the dies (Die-to-Die).

[0004] According to the embodiment of the present application, the data transmission method based on UCIe communicates between the first die and the second die. The data transmission method comprises the following steps: receiving, by a receiving module of the second die, a bypass receiving data signal and a bypass receiving clock signal from a sending module of the first die; transmitting, by the receiving module, the bypass receiving data signal and the bypass receiving clock signal to a serial-parallel conversion module of the second die; counting, by a receiving clock counter of the serial-parallel conversion module, the bypass receiving clock signal to obtain a bypass receiving frame count value; generating, by the serial-parallel conversion module, a Gray code count synchronization signal and a Gray code count delay signal according to the bypass receiving clock signal; comparing, by the serial-parallel conversion module, the Gray code count, and generating the Gray code count synchronization signal and the Gray code count delay signal in the bypass always-on clock domain to determine whether to asynchronously reset the bypass receiving frame count value; and sampling, by the serial-parallel conversion module, the bypass receiving data signal according to the bypass receiving frame count value.

[0005] In the data transmission method according to the embodiment of the present application, the step of generating the Gray code count synchronization signal comprises: counting, by a Gray code counter, the bypass receiving clock signal to obtain a Gray code count value; and synchronizing, by a two-stage synchronizer, the Gray code count value to the clock domain of the bypass always-on clock signal to generate the Gray code count synchronization signal.

[0006] In the data transmission method according to the embodiment of the present application, the step of generating the Gray code count delay signal comprises: delaying the Gray code count synchronization signal by one tick in the bypass always-on clock domain through the bypass reception idle detection circuit to generate the Gray code count delay signal.

[0007] In the data transmission method according to the embodiment of the present application, the step of comparing the Gray code count synchronization signal and the Gray code count delay signal to determine whether to asynchronously reset the bypass reception frame count value comprises: comparing whether the Gray code count synchronization signal and the Gray code count delay signal are the same through the bypass reception idle detection circuit to generate a reception valid indication signal.

[0008] In the data transmission method according to the embodiment of the present application, the reception valid indication signal is high when the Gray code count synchronization signal and the Gray code count delay signal are different; and the reception valid indication signal is low when the Gray code count synchronization signal and the Gray code count delay signal are the same.

[0009] In the data transmission method according to the embodiment of the present application, the step of asynchronously resetting the bypass reception frame count value comprises: generating a bypass reception frame count clear pulse signal through the bypass reception idle detection circuit after detecting the falling edge of the reception valid indication signal for a plurality of clock cycles; and asynchronously resetting the bypass reception frame count value through the reception clock counter according to the bypass reception frame count clear pulse signal.

[0010] In the data transmission method according to the embodiment of the present application, the plurality of clock cycles is three clock cycles.

[0011] In the data transmission method according to the embodiment of the present application, the step of asynchronously resetting the bypass reception frame count value comprises: resetting the last 6 bits of the bypass reception frame count value through the reception clock counter.

[0012] In the data transmission method according to the embodiment of the present application, the step of resetting the last 6 bits of the bypass reception frame count value comprises: judging the bypass data packet type code of the bypass reception data signal through the data packet type code judgment circuit; judging whether the bypass data packet length of the bypass reception data signal is a first length according to the bypass data packet type code through the reception clock counter; and resetting the last 6 bits of the bypass reception frame count value to a first reset value through the reception clock counter when the bypass data packet length of the bypass reception data signal is the first length.

[0013] In the data transmission method according to the embodiment of the present application, the first length is 64 bits, and the first reset value is 0.

[0014] In the data transmission method according to the embodiment of the present application, the step of resetting the last 6 bits of the bypass-received frame count value further comprises: when the bypass data packet length is not the first length, determining, by the receiving clock counter, whether the bypass-received frame count value is greater than or equal to a first threshold value and less than a second threshold value, and resetting the last 6 bits of the bypass-received frame count value to a second reset value, wherein the second threshold value is greater than the first threshold value.

[0015] In the data transmission method according to the embodiment of the present application, the second reset value is 64, the first threshold value is 64, and the second threshold value is 127.

[0016] In the data transmission method according to the embodiment of the present application, the step of resetting the last 6 bits of the bypass-received frame count value further comprises: when the bypass-received frame count value is greater than or equal to the first threshold value and less than the second threshold value, resetting, by the receiving clock counter, the last 6 bits of the bypass-received frame count value to the second reset value; and when the bypass-received frame count value is less than the first threshold value or greater than or equal to the second threshold value, resetting, by the receiving clock counter, the last 6 bits of the bypass-received frame count value to a third reset value.

[0017] In the data transmission method according to the embodiment of the present application, the third reset value is 0.

[0018] According to the embodiment of the present application, the computer readable storage medium of the present application is used to store a computer program. The computer program is executed by a processor to implement the steps of the UCIe-based data transmission method described above.

[0019] According to the embodiment of the present application, the artificial intelligence chip of the present application comprises a first core particle and a second core particle. The second core particle is coupled to the first core particle and is used to communicate with the first core particle. A receiving module of the second core particle receives a bypass-received data signal and a bypass-received clock signal from a transmitting module of the first core particle, and the receiving module transmits the bypass-received data signal and the bypass-received clock signal to a serial-parallel conversion module of the second core particle. A receiving clock counter of the serial-parallel conversion module counts the bypass-received clock signal to obtain a bypass-received frame count value, and the serial-parallel conversion module generates a Gray code count synchronization signal and a Gray code count delay signal according to the bypass-received clock signal. The serial-parallel conversion module compares the Gray code count synchronization signal and the Gray code count delay signal to determine whether to asynchronously reset the bypass-received frame count value. The serial-parallel conversion module samples the bypass-received data signal according to the bypass-received frame count value.

[0020] Based on the above, the UCIe-based data transmission method, the computer readable storage medium, and the artificial intelligence chip of the present application can correctly sample the bypass data packet during the bypass communication process, thereby effectively ensuring the quality of data transmission between the core particles.

[0021] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a data transmission system according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of the data transmission path of the physical layer of UCIe according to an embodiment of the present invention;

[0024] Figure 3 This is a flowchart of a data transmission method according to an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the architecture of the serial-to-parallel conversion module according to an embodiment of the present invention;

[0026] Figure 5 This is a flowchart illustrating the reset bypass receive frame count value according to an embodiment of the present invention;

[0027] Figure 6 This is a data timing diagram of multiple signals according to an embodiment of the present invention;

[0028] Figure 7 This is a data timing diagram of multiple signals according to another embodiment of the present invention;

[0029] Figure 8 This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present invention.

[0030] Explanation of icon numbers

[0031] 100: Data transmission system;

[0032] 110: First chip;

[0033] 111: First physical layer architecture;

[0034] 112: Encoding module;

[0035] 113: Parallel-to-serial conversion module;

[0036] 114: Sending module;

[0037] 120: Second core;

[0038] 121: Second physical layer architecture;

[0039] 122: Receiver module;

[0040] 123: Serial-to-parallel conversion module;

[0041] 1231: Receive clock counter;

[0042] 1232: Gray code counter;

[0043] 1233: Two-stage synchronizer;

[0044] 1234: Bypass receiver idle detection circuit;

[0045] 1235: Series-to-Parallel conversion circuit;

[0046] 1236: Data packet type code determination circuit;

[0047] 1237: Bypass data packet sampling circuit;

[0048] 124: Decoding module;

[0049] 201: Encoded signal;

[0050] 202: Serial data signal;

[0051] 203: First bypass receives data signal;

[0052] 204: First bypass receives clock signal;

[0053] 205: First sampled data signal;

[0054] 800: Artificial intelligence chip;

[0055] B[0]~B

[127] : Bypass data;

[0056] D0~D127: Sampling data;

[0057] SRD: Second bypass data reception signal;

[0058] SRC: Second bypass receives clock signal;

[0059] SD: Second sampled data signal;

[0060] SCA: Bypass normally open clock signal;

[0061] SRV: Valid Indicator Signal;

[0062] SG: Gray code count value;

[0063] SGS: Gray code counting synchronization signal;

[0064] SFCC: Bypass Receive Frame Count Clear Pulse Signal;

[0065] SC: Bypass Receive Frame Count;

[0066] OPC: Bypass Data Packet Type Code;

[0067] RB: Bypass data packet signal;

[0068] RBV: Bypass data packet valid signal;

[0069] lclk: Local clock signal. Detailed Implementation

[0070] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0071] Figure 1 This is a schematic diagram of a data transmission system according to an embodiment of the present invention. (See reference) Figure 1 The data transmission system 100 includes a first chiplet 110 and a second chiplet 120. The first chiplet 110 and the second chiplet 120 are used to implement inter-chiplet communication based on the Universal Chiplet Interconnect Express (UCIe) protocol. The first chiplet 110 can be coupled to the second chiplet 120, for example, via multiple bump lanes.

[0072] In this embodiment, bypass communication can be established between the first chip 110 and the second chip 120, wherein the bypass is independent of the main data channel between the first chip 110 and the second chip 120. In this embodiment, the bypass can be composed of a clock channel (i.e., a clock signal line) and a data channel (i.e., a data signal line). In this embodiment, the first chip 110 and the second chip 120 can transmit information through sideband messages to, for example, implement link initialization and link training between the first chip 110 and the second chip 120.

[0073] In this embodiment, the bypass is used to transmit control signals or management information and to ensure efficient collaboration between the cores. For example, the first core 110 and the second core 120 can transmit control commands through the bypass to help coordinate the operation of the main data channel. The first core 110 and the second core 120 can also transmit core status information, such as error detection or performance monitoring, through the bypass.

[0074] In one embodiment of the present invention, the data transmission system 100 may be implemented in an electronic device, and the electronic device includes a storage unit and a processor. The storage unit is used to store a computer program. The processor is coupled to the storage unit and is used to execute the computer program stored in the storage unit to cause the electronic device to perform the UCIe-based data transmission method as described in the embodiments of the present invention.

[0075] Processors may include, for example, a central processing unit (CPU) or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), other similar processing devices, or combinations thereof.

[0076] Storage units may include, for example, random access memory (RAM), non-volatile memory, hard disk drive (HDD), or solid state drive (SSD). Random access memory may include, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). Non-volatile memory may include, for example, flash memory or read-only memory (ROM).

[0077] Figure 2 This is a schematic diagram of the data transmission path of the physical layer of UCIe according to an embodiment of the present invention. (Reference) Figure 2 , Figure 1 The first core 110 may have the following characteristics: Figure 2 The circuit configuration of the first physical layer architecture 111 shown, and the second chip 120 may have, as Figure 2 The circuit configuration of the second physical layer architecture 121 is shown. In this embodiment, the first physical layer architecture 111 of the first chip 110 includes an encoding module 112, a parallel-to-serial conversion module 113, and a transmitting module 114. The second physical layer architecture 121 of the second chip 120 includes a receiving module 122, a serial-to-parallel conversion module 123, and a decoding module 124. In this embodiment, the parallel-to-serial conversion module 113 is coupled to the encoding module 112 and the transmitting module 114. The serial-to-parallel conversion module 123 is coupled to the receiving module 122 and the decoding module 124. The transmitting module 114 is coupled to the receiving module 122.

[0078] In this embodiment, the encoding module 112 can receive the RDI (Raw Die-to-Die Interface) bypass configuration signal and the RDI bypass configuration valid signal, and generate the corresponding encoded signal 201. The encoding module 112 can encode the sideband packet to generate the encoded signal 201, and transmit the encoded signal 201 to the parallel-to-serial conversion module 113. The parallel-to-serial conversion module 113 performs parallel-to-serial conversion on the encoded signal 201 and outputs a serial data signal 202 to the transmitting module 114. The transmitting module 114 can transmit the serial data signal to the receiving module 122. The serial data signal includes a first bypass received data signal 203 and an accompanying first bypass received clock signal 204. The receiving module 122 can transmit the first bypass received data signal 203 and the first bypass received clock signal 204 to the serial-to-parallel conversion module 123.

[0079] In this embodiment, the serial-to-parallel conversion module 123 performs serial-to-parallel conversion on the first bypass received data signal 203, and samples the first bypass received data signal 203, which has been converted into a parallel data signal, according to the first bypass received clock signal 204, to generate a first sampled data signal 205. The serial-to-parallel conversion module 123 outputs the first sampled data signal 205 to the decoding module 124. The decoding module 124 decodes the first sampled data signal 205, performs related parsing operations on the bypass data packets, and outputs the corresponding RDI bypass configuration signal and RDI bypass configuration valid signal to the subsequent circuit.

[0080] Figure 3 This is a flowchart of a data transmission method according to an embodiment of the present invention. (See reference...) Figure 2 as well as Figure 3The first chip 110 and the second chip 120 can perform data transmission as described in steps S310 to S360. In step S310, the receiving module 122 of the second chip 120 receives a first bypass received data signal 203 and a first bypass received clock signal 204 from the transmitting module 114 of the first chip 110. In step S320, the receiving module 122 transmits the first bypass received data signal 203 and the first bypass received clock signal 204 to the serial-to-parallel conversion module 123 of the second chip 120. In step S330, the serial-to-parallel conversion module 123 counts the first bypass received clock signal 204 to obtain a bypass received frame count value. In step S340, the serial-to-parallel conversion module 123 generates a Gray code count based on the first bypass received clock signal 204, and generates a Gray code count synchronization signal and a Gray code count delay signal in the bypass normally open clock domain. In step S350, the serial-to-parallel conversion module 123 compares the Gray code count synchronization signal and the Gray code count delay signal to determine whether to asynchronously reset the bypass receive frame count value. In step S360, the serial-to-parallel conversion module 123 samples the bypass receive data signal based on the bypass receive frame count value.

[0081] In this embodiment, the first bypass receiving clock signal 204 is a clock strobe signal. The data edges of the first bypass receiving data signal 203 are aligned with the edges of each pulse of the first bypass receiving clock signal 204. When the serial-to-parallel conversion module 123 detects a pulse of the first bypass receiving clock signal 204, the serial-to-parallel conversion module 123 counts the bypass receiving frame count value and records the data sampling result of the first bypass receiving data signal 203. When the bypass receiving frame count value is counted to a specific value, the serial-to-parallel conversion module 123 can sample at the corresponding parallel data sampling position to generate parallel data.

[0082] In this embodiment, the serial-to-parallel conversion module 123 performs Gray code counting based on the first bypass receiving clock signal 204. The synchronizer synchronizes the Gray code count to the bypass normally open clock domain to generate a Gray code counting synchronization signal, and the bypass receiving idle detection module timestamps the Gray code synchronization signal to generate a Gray code counting delay signal. The Gray code counting delay signal can be a signal that is one time delayed from the Gray code counting synchronization signal. The Gray code counting synchronization signal and the Gray code counting delay signal are used to determine whether the level of the first bypass receiving clock signal 204 has switched (i.e., whether bypass data is being received), and then to determine whether the bypass receiving frame count value can be asynchronously reset during the receiving idle period.

[0083] In this regard, if a glitch occurs in the first bypass receive clock signal 204 during the idle interval between two bypass data packets, the bypass receive frame count caused by the glitch can be reset without causing data sampling errors. Furthermore, if a glitch occurs in the first bypass receive clock signal 204 during the idle interval between two sub-packets of a bypass data packet, the bypass receive frame count caused by the glitch can also be properly reset without causing data sampling errors.

[0084] Figure 4 This is a schematic diagram of the serial-to-parallel conversion module according to an embodiment of the present invention. (See reference) Figure 4 In one embodiment, Figure 1 The serial-to-parallel conversion module 123 may have the following functions: Figure 4 The architecture of the serial-to-parallel conversion module 123 includes a receive clock counter 1231, a Gray code counter 1232, a two-stage synchronizer 1233, a bypass receive idle detection circuit 1234, a serial-to-parallel conversion circuit 1235, a data packet type code judgment circuit 1236, and a bypass data packet sampling circuit 1237. The receive clock counter 1231 is coupled to the Gray code counter 1232, the bypass receive idle detection circuit 1234, the data packet type code judgment circuit 1236, and the bypass data packet sampling circuit 1237. The two-stage synchronizer 1233 is coupled to the Gray code counter 1232 and the bypass receive idle detection circuit 1234. The serial-to-parallel conversion circuit 1235 is coupled to the data packet type code judgment circuit 1236.

[0085] Figure 5 This is a flowchart illustrating the reset bypass receive frame count value according to an embodiment of the present invention. (See reference) Figure 4 as well as Figure 5 The serial-to-parallel conversion module 123 can execute steps S501 to S510 to reset the bypass received frame count value. In this embodiment, the Gray code counter 1232 receives the second bypass received clock signal SRC. In step S501, the Gray code counter 1232 counts the second bypass received clock signal SRC to obtain the Gray code count value SG. The Gray code counter 1232 outputs the Gray code count value SG to the two-stage synchronizer 1233. The two-stage synchronizer 1233 uses the bypass normally open clock signal SCA. In step S502, the two-stage synchronizer 1233 synchronizes the Gray code count value SG to the clock domain of the bypass normally open clock signal SCA to generate the Gray code count synchronization signal SGS. The two-stage synchronizer 1233 outputs the Gray code count synchronization signal SGS to the bypass received idle detection circuit 1234. The bypass received idle detection circuit 1234 uses the bypass normally open clock signal SCA.

[0086] In step S503, the bypass receive idle detection circuit 1234 delays the Gray code counting synchronization signal SGS by one clock cycle in the clock domain of the bypass normally open clock signal SCA to generate a Gray code counting delay signal. In step S504, the bypass receive idle detection circuit 1234 compares the Gray code counting synchronization signal SGS with the Gray code counting delay signal to generate a valid receive indication signal. Specifically, if the Gray code counting synchronization signal SGS and the Gray code counting delay signal are different, the valid receive indication signal can be high. If the Gray code counting synchronization signal SGS and the Gray code counting delay signal are the same, the valid receive indication signal can be low.

[0087] In step S505, after the bypass receive idle detection circuit 1234 detects the falling edge of the valid indication signal for multiple clock cycles, it generates a bypass receive frame count clear pulse signal SFCC. The aforementioned multiple clock cycles are, for example, three clock cycles. The bypass receive idle detection circuit 1234 outputs the bypass receive frame count clear pulse signal SFCC to the receive clock counter 1231.

[0088] The serial-to-parallel converter 1235 receives the second bypass receive clock signal SRC and the second bypass receive data signal SRD, and converts the second bypass receive data signal SRD into a parallel second sampled data signal SD based on the second bypass receive clock signal SRC. The data packet type code determination circuit 1236 receives the second sampled data signal SD and the second bypass receive clock signal SRC. Based on the count of the bypass receive clock signal SRC, the data packet type code determination circuit 1236 extracts the bypass data packet type code OPC (opcode) from the second sampled data signal SD. The data packet type code determination circuit 1236 outputs the bypass data packet type code OPC to the receive clock counter 1231.

[0089] In step S506, the receive clock counter 1231 determines whether the length of the bypass data packet of the second bypass received data signal SRD is equal to the first length based on the bypass data packet type code OPC. If yes, in step S507, the receive clock counter 1231 resets the last 6 bits of the bypass received frame count value to the first reset value. If the length of the bypass data packet of the second bypass received data signal SRD is not equal to the first length, then in step S508, the receive clock counter 1231 determines whether the bypass received frame count value is greater than or equal to the first threshold and less than the second threshold. The aforementioned second threshold is greater than the aforementioned first threshold.

[0090] If the bypass received frame count is greater than or equal to the first threshold and less than the second threshold, then in step S509, the receive clock counter 1231 resets the last 6 bits of the bypass received frame count to the second reset value. If not (i.e., the bypass received frame count is less than the first threshold, or the bypass received frame count is greater than or equal to the second threshold), then in step S510, the receive clock counter 1231 resets the last 6 bits of the bypass received frame count to the third reset value.

[0091] Taking a bypass data packet with a packet length of 64 bits as an example, the aforementioned first length can be, for example, 64 bits, and the aforementioned first reset value can be, for example, 0. In this case, in the scenario of step S508, if the second bypass receive clock signal SRC glitches during the idle interval between two bypass data packets, the next bypass data packet can be correctly sampled without data sampling errors because the bypass receive frame count value can be properly reset to 0.

[0092] Taking a bypass data packet with a length of 128 bits as an example, the aforementioned second reset value is, for example, 64, and the aforementioned third reset value is, for example, 0. The aforementioned first threshold is, for example, 64, and the aforementioned second threshold is, for example, 127. Therefore, in the scenario of step S509, if the second bypass receive clock signal SRC glitches during the idle interval between bypass data packets of a bypass data packet, the bypass receive frame count value can also be appropriately reset to 64, so the other part of the bypass data packet can still be correctly sampled without data sampling errors. Furthermore, in the scenario of step S510, if the second bypass receive clock signal SRC glitches during the idle interval between two bypass data packets, the bypass receive frame count value can be appropriately reset to 0, so the next bypass data packet can be correctly sampled without data sampling errors.

[0093] Therefore, the receive clock counter 1231 can output the correct bypass receive frame count value SC to the bypass data packet sampling circuit 1237, so that the bypass data packet sampling circuit 1237 can concatenate the second sampled data signal SD into a bypass data packet of the corresponding number of bits according to the bypass receive frame count value SC. The bypass data packet sampling circuit 1237 uses the local clock signal lclk and synchronizes the bypass data packet to the clock domain of the local clock signal lclk through an asynchronous first-in / first-out (FIFO) data buffer, so as to output the bypass data packet signal RB and the corresponding bypass data packet valid signal RBV to the decoding module 124 for subsequent data packet content parsing operations.

[0094] It should be understood that the second bypass received data signal SRD and the first bypass received data signal 203 are different representations of bypass received data signals in different figures and embodiments, and both are bypass received data signals; the second bypass received clock signal SRC and the first bypass received clock signal 204 are different representations of bypass received clock signals in different figures and embodiments, and both are bypass received clock signals; the second sampled data signal SD and the first sampled data signal 205 are different representations of sampled data signals in different figures and embodiments, and both are sampled data signals.

[0095] Figure 6 This is a data timing diagram of multiple signals according to an embodiment of the present invention. (Reference) Figure 4 as well as Figure 6 For example, the receiving module 122 of the second chip 120 can receive data from the transmitting module 114 of the first chip 110, such as... Figure 6 The second bypass receive data signal SRD and the second bypass receive clock signal SRC are shown. The second bypass receive data signal SRD is used to transmit two 64-bit bypass data packets during the period from time t0 to time t4. During the period from time t0 to time t1 (64 UIs), the second bypass receive data signal SRD may transmit, for example, a bypass data packet, which may include, for example, bypass data B[0] to B

[63] . During the period from time t2 to time t3 (64 UIs), the second bypass receive data signal SRD may transmit, for example, another bypass data packet, which may include, for example, bypass data B[0] to B

[63] . During the idle interval from time t1 to time t2 (greater than or equal to 32 UIs), the second bypass receive data signal SRD may operate at a low level, and the second bypass receive clock signal SRC may also operate at a low level. The receiving module 122 provides the second bypass receive data signal SRD and the second bypass receive clock signal SRC to the serial-to-parallel conversion module 123.

[0096] In this embodiment, the receive clock counter 1231 can count the second bypass receive clock signal SRC to obtain the bypass receive frame count value SC, and the serial-to-parallel circuit 1235 samples the second bypass receive data signal SRD to generate a 64-bit parallel second sampled data signal SD.

[0097] During the period from time t0 to time t1, the data packet type code determination circuit 1236 determines that the data packet of the second sampled data signal SD is 64 bits. Therefore, when the bypass receive frame count value SC counts to 64, the bypass data packet sampling circuit 1237 resets it to zero and takes the sampled data D63 of the second sampled data signal SD during the period from time t0 to time t1 (i.e., the correctly sampled bypass data B[0] to B

[63] ) as the corresponding bypass data packet data and outputs the corresponding bypass data packet signal RB. Then, since the second bypass receive clock signal SRC glitches during the idle interval from time t1 to time t2, the receive clock counter 1231 incorrectly counts the bypass receive frame count value SC as 1 during the idle interval from time t1 to time t2.

[0098] To avoid data sampling errors, the bypass receive idle detection circuit 1234 can generate a valid indication signal SRV based on the bypass normally open clock signal SCA, as described in the above embodiment. The valid indication signal SRV can switch from low to high during the idle interval from time t1 to time t2, corresponding to the time point when the second bypass receive clock signal SRC glitches, and then switch from high to low after a one-beat delay. Next, the bypass receive idle detection circuit 1234 can detect that the valid indication signal SRV has not been pulled up after several clock cycles of its falling edge, and then generate a bypass receive frame count clear pulse signal SFCC. The receive clock counter 1231 can determine that the length of the bypass data packet type currently transmitted by the second bypass receive data signal SRD is 64 bits based on the bypass data packet type code OPC, and reset the bypass receive frame count value SC to 0 according to the bypass receive frame count clear pulse signal SFCC.

[0099] In this way, the bypass data packet sampling circuit 1237 can use the sampled data D63 of the second sampled data signal SD during the period from time t0 to time t1 (i.e., the next set of bypass data B[0] to B

[63] that was sampled correctly) as the corresponding bypass data packet data and output the corresponding bypass data packet signal RB, without recording the data that was missampled due to glitches during the idle interval from time t1 to time t2. Furthermore, the same operation can be performed during the next idle interval from time t3 to time t4.

[0100] Figure 7 This is a data timing diagram of multiple signals according to another embodiment of the present invention. (See reference) Figure 4 as well as Figure 7 For example, the receiving module 122 of the second chip 120 can receive data from the transmitting module 114 of the first chip 110, such as... Figure 7The second bypass receive data signal SRD and the second bypass receive clock signal SRC are shown. The second bypass receive data signal SRD is used to transmit a 128-bit bypass data packet during the period from time t0 to time t3. During the period from time t0 to time t1 (64 UIs), the second bypass receive data signal SRD may transmit, for example, a first portion of a 128-bit bypass data packet, wherein the first portion of the 128-bit bypass data packet may include, for example, bypass data B[0] to B

[63] . During the period from time t2 to time t3 (64 UIs), the second bypass receive data signal SRD may transmit, for example, a second portion of a 128-bit bypass data packet, wherein the second portion of the 128-bit bypass data packet may include, for example, bypass data B

[64] to B

[127] . During the idle interval from time t1 to time t2 (greater than or equal to 32 UIs), the second bypass receive data signal SRD may operate at a low level, and the second bypass receive clock signal SRC may also operate at a low level. The receiving module 122 provides the second bypass receive data signal SRD and the second bypass receive clock signal SRC to the serial-to-parallel conversion module 123.

[0101] In this embodiment, the receive clock counter 1231 can count the second bypass receive clock signal SRC to obtain the bypass receive frame count value SC, and the serial-to-parallel circuit 1235 samples the second bypass receive data signal SRD to generate a 64-bit parallel second sampled data signal SD.

[0102] During the period from time t0 to time t1, the data packet type code determination circuit 1236 determines that the data packet of the second sampled data signal SD is 128 bits. Therefore, when the bypass receive frame count value SC reaches 64, the bypass data packet sampling circuit 1237 will maintain the bypass receive frame count value SC at 64 until the second part of the bypass data packet is sampled. Then, due to a glitch in the second bypass receive clock signal SRC during the idle interval from time t1 to time t2, the receive clock counter 1231 incorrectly counts the bypass receive frame count value SC as 65 during the idle interval from time t1 to time t2.

[0103] To avoid data sampling errors, the bypass receive idle detection circuit 1234 can generate a valid indication signal SRV based on the bypass normally open clock signal SCA, as described in the above embodiment. The valid indication signal SRV can switch from low to high during the idle interval from time t1 to time t2, corresponding to the time point when the second bypass receive clock signal SRC glitches, and then switch from high to low after a one-beat delay. Next, the bypass receive idle detection circuit 1234 can detect that the valid indication signal SRV has not been pulled up after several clock cycles of its falling edge, and then generate a bypass receive frame count clear pulse signal SFCC. The receive clock counter 1231 can determine, based on the bypass data packet type code OPC, that the length of the currently transmitted bypass data packet in the second bypass receive data signal SRD is 128 bits, and determine that the bypass receive frame count value SC is greater than 64 bits and less than 127 bits, and reset the bypass receive frame count value SC to 64 based on the bypass receive frame count clear pulse signal SFCC.

[0104] In this way, the bypass data packet sampling circuit 1237 can use the sampled data D63 of the second sampled data signal SD during the period from time t0 to time t1 and the sampled data D127 of the second sampled data signal SD during the period from time t2 to time t3 (i.e., the next set of bypass data B[0] to B

[127] that are sampled correctly) as the corresponding bypass data packet data, and output the corresponding bypass data packet signal RB, without recording the data that is missampled due to glitches during the idle interval from time t1 to time t2. Furthermore, the above can be performed during the next idle interval from time t3 to time t4. Figure 6 Perform the example operation to reset the bypass receive frame count value SC to 0.

[0105] Figure 8 This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present invention. (See reference) Figure 8 In one embodiment, the artificial intelligence chip 800 may include a first chip 110 and a second chip 120. The first chip 110 and the second chip 120 are used to realize inter-chip communication based on general chip interconnect technology. The first chip 110 and the second chip 120 can form a data transmission system. For relevant implementation methods and technical details regarding the first chip 110 and the second chip 120, please refer to the descriptions of the above embodiments. Furthermore, the data transmission method between the first chip 110 and the second chip 120 can also refer to the flow of the above embodiments, thus obtaining sufficient illustrations, suggestions, and implementation descriptions. In addition, in another embodiment, the number of chips in the artificial intelligence chip 800 is not limited to... Figure 8 The first core 110 and the second core 120 are shown.

[0106] In one embodiment, the artificial intelligence chip 800 may be a system-on-chip (SoC) and includes multiple small chips or modules with specific functions. In another embodiment, the artificial intelligence chip 800 may be any one of a central processing unit, a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU).

[0107] In summary, the UCIe-based data transmission method, computer-readable storage medium, and artificial intelligence chip of this invention reset the bypass receive frame count during the idle interval between two bypass data packets during bypass communication. Alternatively, the bypass receive frame count is reset during the idle interval between bypass data packets of a single bypass data packet, ensuring accurate sampling of bypass data packets. This effectively improves the stability and reliability of data transmission in bypass communication between chips, thereby ensuring the system's data transmission performance. The UCIe-based data transmission method, computer-readable storage medium, and artificial intelligence chip of this invention effectively avoid data sampling errors caused by glitches in the bypass receive clock signal during the idle interval between two bypass data packets or between two sub-data packets of a single bypass data packet.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A UCIe-based data transmission method, wherein a first core communicates with a second core, characterized in that, The data transmission method includes: The receiving module of the second chip receives the bypass reception data signal and the bypass reception clock signal from the transmitting module of the first chip. The bypass received data signal and the bypass received clock signal are transmitted by the receiving module to the serial-to-parallel conversion module of the second chip. The bypass receiving clock signal is counted by the receiving clock counter of the serial-to-parallel conversion module to obtain the bypass receiving frame count value; The serial-to-parallel conversion module generates Gray code counting based on the bypass received clock signal, and generates Gray code counting synchronization signal and Gray code counting delay signal in the bypass normally open clock domain. The serial-to-parallel conversion module compares the Gray code counting synchronization signal and the Gray code counting delay signal to determine whether to asynchronously reset the bypass received frame count value; and The bypass received data signal is sampled by the serial-to-parallel conversion module according to the bypass received frame count value; in, The step of generating the Gray code counting synchronization signal includes: The bypass received clock signal is counted using a Gray code counter to obtain a Gray code count value; and The Gray code count value is synchronized to the clock domain of the bypass normally open clock signal through a two-stage synchronizer to generate the Gray code count synchronization signal. The step of comparing the Gray code count synchronization signal and the Gray code count delay signal to determine whether to asynchronously reset the bypass receive frame count value includes: The bypass receive idle detection circuit compares the Gray code count synchronization signal and the Gray code count delay signal to generate a valid receive indication signal. The step of asynchronously resetting the bypass received frame count value includes: After detecting the falling edge of the valid indication signal for multiple clock cycles via the bypass receive idle detection circuit, a bypass receive frame count clear pulse signal is generated; and The bypass receive frame count value is asynchronously reset by the receive clock counter according to the bypass receive frame count clear pulse signal.

2. The data transmission method based on UCIe according to claim 1, characterized in that, The step of generating the Gray code counting delay signal includes: The Gray code counting synchronization signal is delayed by one clock cycle in the bypass normally open clock domain by a bypass receiver idle detection circuit to generate the Gray code counting delay signal.

3. The data transmission method based on UCIe according to claim 1, characterized in that, When the Gray code count synchronization signal and the Gray code count delay signal are different, the valid reception indication signal is high; and when the Gray code count synchronization signal and the Gray code count delay signal are the same, the valid reception indication signal is low.

4. The UCIe-based data transmission method according to claim 3, characterized in that, The multiple clock cycles are three clock cycles.

5. The data transmission method based on UCIe according to claim 1, characterized in that, The step of asynchronously resetting the bypass received frame count value includes: The last 6 bits of the bypass receive frame count value are reset by the receive clock counter.

6. The UCIe-based data transmission method according to claim 5, characterized in that, The step of resetting the last 6 bits of the bypass received frame count value includes: The bypass data packet type code of the bypass received data signal is determined by the data packet type code determination circuit; The receiver clock counter determines whether the length of the bypass data packet in the bypass received data signal is the first length based on the bypass data packet type code; and When the length of the bypass data packet of the bypass received data signal is the first length, the last 6 bits of the bypass received frame count value are reset to the first reset value by the receive clock counter.

7. The UCIe-based data transmission method according to claim 6, characterized in that, The first length is 64 bits, and the first reset value is 0.

8. The UCIe-based data transmission method according to claim 6, characterized in that, The step of resetting the last 6 bits of the bypass receive frame count value further includes: When the length of the bypass data packet is not the first length, the bypass received frame count value is determined by the receive clock counter to be greater than or equal to a first threshold and less than a second threshold, so that the last 6 bits of the bypass received frame count value are reset to the second reset value. The second threshold is greater than the first threshold.

9. The UCIe-based data transmission method according to claim 8, characterized in that, The second reset value is 64, the first threshold is 64, and the second threshold is 127.

10. The UCIe-based data transmission method according to claim 8, characterized in that, The step of resetting the last 6 bits of the bypass receive frame count value further includes: When the bypass received frame count value is greater than or equal to the first threshold and less than the second threshold, the last 6 bits of the bypass received frame count value are reset to the second reset value using the receive clock counter; and When the bypass received frame count value is less than the first threshold, or greater than or equal to the second threshold, the last 6 bits of the bypass received frame count value are reset to the third reset value by the receive clock counter.

11. The UCIe-based data transmission method according to claim 10, characterized in that, The third reset value is 0.

12. A computer-readable storage medium for storing a computer program, characterized in that, The computer program is executed by a processor to implement the steps of the UCIe-based data transmission method according to any one of claims 1 to 11.

13. An artificial intelligence chip, characterized in that, include: First core; as well as The second core is coupled to the first core and is used to communicate with the first core. The receiving module of the second chip receives a bypass reception data signal and a bypass reception clock signal from the transmitting module of the first chip, and the receiving module transmits the bypass reception data signal and the bypass reception clock signal to the serial-to-parallel conversion module of the second chip. The serial-to-parallel conversion module's receive clock counter counts the bypass receive clock signal to obtain a bypass receive frame count value. Furthermore, the serial-to-parallel conversion module generates Gray code counting based on the bypass receive clock signal and generates a Gray code counting synchronization signal and a Gray code counting delay signal in the bypass normally open clock domain. The serial-to-parallel conversion module compares the Gray code count synchronization signal and the Gray code count delay signal to determine whether to asynchronously reset the bypass receive frame count value, and the serial-to-parallel conversion module samples the bypass receive data signal according to the bypass receive frame count value; The Gray code counting synchronization signal is generated in the following manner: The bypass received clock signal is counted using a Gray code counter to obtain a Gray code count value; and The Gray code count value is synchronized to the clock domain of the bypass normally open clock signal through a two-stage synchronizer to generate the Gray code count synchronization signal. The comparison of the Gray code count synchronization signal and the Gray code count delay signal to determine whether to asynchronously reset the bypass receive frame count value includes: The bypass receive idle detection circuit compares the Gray code count synchronization signal and the Gray code count delay signal to generate a valid receive indication signal. The asynchronous reset of the bypass received frame count value includes: After detecting the falling edge of the valid indication signal for multiple clock cycles via the bypass receive idle detection circuit, a bypass receive frame count clear pulse signal is generated; and The bypass receive frame count value is asynchronously reset by the receive clock counter according to the bypass receive frame count clear pulse signal.

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