High-voltage super junction device structure and manufacturing method thereof

Abstract

The invention provides a high-voltage super junction device structure and a manufacturing method thereof. The method comprises the following steps: providing a first device wafer with a first P-type column, flattening the front surface of the first device wafer, and temporarily bonding the first device wafer with a carrier wafer; thinning the back of the first device wafer to expose the back of the first P-type column; providing a second device wafer with a second P-type column; carrying out permanent bonding on the back surface of the thinned first device wafer and the front surface of the second device wafer, so that the first P-type column and the second P-type column are aligned and connected to form an extended P-type column; and finally, releasing the temporary bonding between the first device wafer and the carrier wafer. The two P-type columns are in butt joint through the wafer bonding technology, the process limit of a single wafer is effectively broken through, the high-voltage super junction device with the deeper junction depth and the higher withstand voltage level can be manufactured, and the process reliability is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a high-voltage super junction device structure and a manufacturing method thereof. BACKGROUND

[0002] The super junction device constructs a charge compensation structure by alternately arranging fine N-type and P-type semiconductor pillars (i.e., N-type pillars and P-type pillars) in the drift region. In the off state of the device, the space charges in the N-type pillars and the P-type pillars can be depleted to each other, so that the electric field distribution in the drift region is more uniform, thereby enabling a very high breakdown voltage in a thinner and higher doping concentration drift region. At the same time, thanks to the higher doping concentration of the drift region (N-type pillars), the device has very low on-resistance in the on state. This feature successfully breaks the "silicon limit" of traditional power devices, making it possible to simultaneously achieve high breakdown voltage and low on-resistance.

[0003] With the increasing demand for voltage level of power devices in application fields, such as new energy vehicles, industrial power supplies, smart grids, etc., high-voltage super junction devices capable of withstanding thousands of volts or even higher voltages need to be developed. To achieve higher breakdown voltage, the key is to have longer P-type pillars and N-type pillars, i.e., a deeper super junction structure.

[0004] However, the existing mainstream high-voltage super junction manufacturing processes, such as multiple epitaxial growth stacking or deep trench etching and filling technology, face great challenges in preparing a super deep junction structure. The multiple epitaxial growth process is complicated, has a high thermal budget, and the alignment accuracy between layers is difficult to control, which is costly. The deep trench etching technology is limited by the capability of the etching equipment. When the depth-to-width ratio of the trench reaches the limit, the etching rate will drop sharply, and it is difficult to ensure the morphology and etching uniformity at the bottom of the trench, which directly limits the effective length of the P-type pillars.

[0005] Therefore, due to the limitations of existing process capabilities, the manufacture of high-voltage super junction devices with a super deep junction structure has problems such as great process difficulty, complex process flow, high cost, and difficulty in breaking through physical limits. Therefore, there is an urgent need in the art for a new type of high-voltage super junction device structure and a manufacturing method thereof that can effectively increase the length of the super junction P-type pillars to break through the current process limit. SUMMARY

[0006] The technical problem solved by the present application is that the method for manufacturing high-voltage super junction (HV SJ) devices in the prior art, such as deep trench etching and filling technology, is limited by the aspect ratio capability of the etching equipment, resulting in process limits of the depth and length of the P-type column, which directly restricts the further improvement of the voltage grade of the device. Therefore, the existing process faces the problems of great process difficulty, complex process flow and difficulty in breaking through the physical bottleneck when preparing HV SJ devices of an ultra-high voltage grade.

[0007] To achieve the above object and other related objects, the present application provides a high-voltage super junction device structure, comprising:

[0008] a first device wafer and a second device wafer, the first device wafer and the second device wafer are bonded together through a bonding interface; and

[0009] an extended P-type column, the extended P-type column penetrates through the bonding interface;

[0010] wherein the extended P-type column comprises a first P-type column located in the first device wafer and a second P-type column located in the second device wafer, the first P-type column and the second P-type column are aligned and connected at the bonding interface.

[0011] Preferably, the bonding interface is formed by silicon-silicon direct bonding.

[0012] Preferably, further comprising: a first N-type column arranged in the first device wafer and alternating with the first P-type column; and a second N-type column arranged in the second device wafer and alternating with the second P-type column.

[0013] Preferably, the first device wafer has a front surface and a back surface, and the second device wafer has a front surface, wherein the bonding interface is located between the back surface of the first device wafer and the front surface of the second device wafer.

[0014] Preferably, a metal structure and an insulating layer are formed on the front surface of the first device wafer.

[0015] According to another aspect of the present application, a manufacturing method of a high-voltage super junction device is provided, comprising:

[0016] Step one, providing a first device wafer, the first device wafer has a first P-type column formed on its front surface, and the front surface of the first device wafer is subjected to a planarization treatment to form a first bonding surface, then the first bonding surface of the first device wafer is temporarily bonded with a carrier wafer;

[0017] Step two, backside thinning the first device wafer temporarily bonded with the carrier wafer until the back of the first P-type pillar is exposed;

[0018] Step three, providing a second device wafer having a second P-type pillar formed on its front side;

[0019] Step four, bonding the back of the backside-thinned first device wafer with the front side of the second device wafer so that the first P-type pillar is connected with the second P-type pillar in alignment, thereby forming an extended P-type pillar; and

[0020] Step five, releasing the temporary bonding between the first device wafer and the carrier wafer.

[0021] Preferably, in step one, the planarization of the front side of the first device wafer includes depositing an insulating layer on the front side of the first device wafer, and chemically mechanically polishing the insulating layer to planarize the first bonding surface.

[0022] Preferably, in step one, before depositing the insulating layer, the front side of the first device wafer is pre-formed with a field oxide layer and a polysilicon layer, thereby forming a step difference on the front side; the chemically mechanically polishing of the insulating layer eliminates the step difference.

[0023] Preferably, in step one, before the chemically mechanically polishing, further including forming a metal structure on the first device wafer, and metal chemically mechanically polishing the metal structure.

[0024] Preferably, the metal chemically mechanically polishing is tungsten chemically mechanically polishing.

[0025] Preferably, the insulating layer is a silicon oxide layer formed by tetraethoxysilane plasma-enhanced chemical vapor deposition.

[0026] Preferably, in step four, the bonding is silicon-silicon direct bonding.

[0027] Preferably, in step four, after the bonding, further including annealing the bonded first device wafer and the second device wafer.

[0028] Preferably, the first P-type pillar and / or the second P-type pillar is formed by etching a deep trench in an N-type semiconductor layer, and filling the deep trench with P-type semiconductor material.

[0029] As described above, the high-voltage super-junction device structure and the manufacturing method thereof have the following beneficial effects:

[0030] The present application uses wafer bonding to butt joint two device wafers with P-type pillars, so that the total length of the extended P-type pillars is equal to the sum of the lengths of the two independent P-type pillars, which can be several times the limit of the existing single wafer process. This "splicing" method fundamentally bypasses the limitation of the deep trench etching aspect ratio, thereby enabling the manufacture of super-junction structures with deeper junction depths, significantly improving the breakdown voltage of the device and making it possible to prepare high-voltage super-junction devices of ultra-high voltage levels. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 A schematic diagram showing the deposition of an insulating layer on the front surface of the first device wafer according to the present application;

[0032] Figure 2 A schematic diagram showing the chemical mechanical polishing of the insulating layer according to the present application;

[0033] Figure 3 A schematic diagram showing the temporary bonding of the first bonding surface of the first device wafer to a carrier wafer according to the present application;

[0034] Figure 4 A schematic diagram showing the back-thinning of the first device wafer temporarily bonded to the carrier wafer according to the present application;

[0035] Figure 5 A schematic diagram showing the permanent bonding of the back surface of the back-thinned first device wafer to the front surface of the second device wafer according to the present application;

[0036] Figure 6 A schematic diagram showing the release of the temporary bonding of the first device wafer to the carrier wafer according to the present application;

[0037] Figure 7 A schematic diagram showing the process flow according to the present application. DETAILED DESCRIPTION

[0038] The embodiments of the present application will be described in detail with specific reference felt to the drawings. Those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in the specification. The present application can also be implemented or applied in other different embodiments, and the details in the specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0039] In order to overcome the problem that the manufacturing of the HV SJ device in the prior art is limited by the process capability such as deep trench etching, and it is difficult to further improve the junction depth and voltage grade, an embodiment of the present application provides a high-voltage super junction (HV SJ) device structure and a manufacturing method thereof. The present application adopts wafer bonding technology to butt joint two device wafers each having a P-type column, so as to "splice" an extended P-type column with a total length far exceeding the process limit of a single wafer, and realize the improvement of the voltage performance of the device.

[0040] Please refer to Figure 6 A high-voltage super junction device structure comprises:

[0041] A first device wafer 101 and a second device wafer 108 are permanently bonded together through a bonding interface; and

[0042] An extended P-type column penetrates through the bonding interface; wherein the extended P-type column comprises a first P-type column 102 in the first device wafer 101 and a second P-type column 109 in the second device wafer 108, and the first P-type column 102 and the second P-type column 109 are aligned and connected at the bonding interface. By bonding two pieces of device wafers which have been processed respectively, the P-type columns are connected into a longer whole, and the device structure provided in the embodiment can effectively increase the total depth of the super junction structure. This structure breaks through the depth limit that can be reached by single deep trench etching or multiple epitaxial growth processes, so as to significantly improve the breakdown voltage of the device.

[0043] In some embodiments, the bonding interface is formed by silicon-silicon (Si-Si) direct bonding.

[0044] In some embodiments, it further comprises a first N-type column arranged in the first device wafer 101 and alternating with the first P-type column 102, and a second N-type column arranged in the second device wafer 108 and alternating with the second P-type column 109. In this way, the extended P-type column and the also extended N-type column jointly constitute a complete super junction charge compensation structure, which can be mutually depleted when the device is turned off, so as to form a uniform electric field distribution, which is the key basis for realizing high breakdown voltage.

[0045] In some embodiments, the first device wafer 101 has a front surface and a back surface, and the second device wafer 108 has a front surface, wherein the bonding interface is located between the back surface of the first device wafer 101 and the front surface of the second device wafer 108. This bonding method can protect the front surface of the first device wafer 101 which has completed the complex process such as metal wiring, while the back surface thereof is used for bonding with the second device wafer 108, so as to optimize the overall process flow.

[0046] In some embodiments, the front side of the first device wafer 101 is formed with metal structures and an insulating layer 105. That is, the front side of the first device wafer 101 is a device surface that has completed a front-end-of-line (FEOL) or a partial back-end-of-line (BEOL) process.

[0047] Referring to Figure 7 Corresponding to the above device structure, the present application also provides a method for manufacturing a high-voltage super-junction device, comprising the following steps:

[0048] Step one, providing a first device wafer 101, the first device wafer 101 has a first P-type pillar 102 formed on its front side, and the front side of the first device wafer 101 is subjected to a planarization process to form a first bonding surface, and then the first bonding surface of the first device wafer 101 is temporarily bonded with a carrier wafer 107 to form a structure as shown in Figure 3 This step provides a solid mechanical support for the subsequent processing (such as thinning) of the back side of the first device wafer 101 through the temporary bonding technology, and at the same time protects the precise device structures such as gate structures and metal interconnections on the front side of the first device wafer 101, which have been completed, from being damaged in subsequent processes.

[0049] In some embodiments, in step one, the planarization process on the front side of the first device wafer 101 comprises: depositing an insulating layer 105 on the front side of the first device wafer 101 to form a structure as shown in Figure 1 ; and subjecting the insulating layer 105 to chemical mechanical polishing to planarize the first bonding surface to form a structure as shown in Figure 2 More specifically, since the device structures such as field oxide layer 103 and polysilicon layer 104 are formed on the front side of the first device wafer 101 in advance, these structures will form a step difference with the surface of the first device wafer 101. Therefore, this planarization process can effectively fill and eliminate this step difference by depositing the insulating layer 105 and subjecting it to chemical mechanical polishing, which is the key to achieving high-quality temporary bonding. By obtaining a highly planar first bonding surface, it can be ensured that a tight and void-free temporary bonding interface is formed between the first device wafer 101 and the carrier wafer 107, thereby improving the yield of subsequent processes.

[0050] In some embodiments, in step one, before the chemical mechanical polishing, it further comprises: forming a metal structure on the first device wafer 101, and subjecting the metal structure to metal chemical mechanical polishing, such as tungsten (W) chemical mechanical polishing. This corresponds to a specific front-end-of-line process flow, that is, after the process of filling tungsten in the contact hole 106 is completed, the tungsten CMP and the subsequent interlayer dielectric (ILD) CMP are used to achieve the high planarity of the front side of the wafer, creating ideal surface conditions for temporary bonding.

[0051] In some embodiments, in step one, the insulating layer 105 is a silicon oxide layer formed by plasma-enhanced chemical vapor deposition of tetraethoxysilane (TEOS). TEOS silicon oxide is chosen as the insulating layer 105 because of its good filling property and electrical insulation property, and precise control of the removal thickness of CMP can ensure that the final surface reaches the required flatness for bonding.

[0052] In step two, backside thinning is performed on the first device wafer 101 temporarily bonded to the carrier wafer 107 until the back of the first P-type pillar 102 is exposed, forming a structure as shown in FIG. 2B. This step exposes the end of the P-type pillar originally buried in the wafer, creating conditions for subsequent butt joint with the P-type pillar of the second device wafer 108. Figure 4

[0053] In step three, a second device wafer 108 is provided, which has a second P-type pillar 109 formed on its front side. The second device wafer 108 can be independently manufactured using similar processes as the first device wafer 101, which allows the entire manufacturing process to be processed in parallel, improving production efficiency.

[0054] In step four, the back of the backside-thinned first device wafer 101 is permanently bonded to the front side of the second device wafer 108 to align and connect the first P-type pillar 102 with the second P-type pillar 109, forming an extended P-type pillar, forming a structure as shown in FIG. 2D. This step'stitches' two independent P-type pillars into an extended P-type pillar with a length that can reach several times the existing process limit through permanent wafer-to-wafer bonding, directly and effectively breaking through the process bottleneck of deep trench etching on a single wafer, and is a core technical means to realize a super-junction structure with ultra-high voltage. Figure 5

[0055] In some embodiments, in step four, the permanent bonding is silicon-silicon (Si-Si) direct bonding. Silicon-silicon direct bonding does not require any intermediate adhesive and can form a high-quality single-crystal interface, ensuring the continuity of the extended P-type pillar in physical structure and electrical properties. After permanent bonding, annealing is performed on the bonded first device wafer 101 and second device wafer 108, which can enhance the atomic bonding strength of the bonding interface and repair interface defects that may have been generated during the bonding process, further improving the bonding quality and long-term reliability of the device.

[0056] In step five, the temporary bonding of the first device wafer 101 to the carrier wafer 107 is released, forming a structure as shown in FIG. 2E. Figure 6 ​​The permanent bonding is removed by a debonding process after the stable bi-wafer structure is formed, and the front device structure of the first device wafer 101 is exposed, and the subsequent flow process such as electrode lead-out can be continued, so as to complete the manufacturing of the whole high-voltage super-junction device.

[0057] In some embodiments, the first P-type pillar 102 and / or the second P-type pillar 109 are formed by etching deep grooves in the N-type semiconductor layer and filling the deep grooves with P-type semiconductor material.

[0058] It is to be noted that the drawings provided in the embodiments only schematically illustrate the basic concepts of the present application, and only the components related to the present application are shown in the drawings, rather than the number, shape and size of the components in actual implementation. The shapes, number and proportions of the components in actual implementation can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0059] The above embodiments only illustratively explain the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the present application should be covered by the claims of the present application.

Claims

1. A high-voltage superjunction device structure, characterized in that, include: A first device wafer and a second device wafer are bonded together via a bonding interface; as well as An extended P-shaped post extends through the bonding interface; The extended P-type pillar includes a first P-type pillar located in the first device wafer and a second P-type pillar located in the second device wafer, wherein the first P-type pillar and the second P-type pillar are aligned and connected at the bonding interface.

2. The high-voltage superjunction device structure according to claim 1, characterized in that: The bonding interface is formed by direct silicon-silicon bonding.

3. The high-voltage superjunction device structure according to claim 1, characterized in that: Also includes: The first N-type pillar is disposed in the first device wafer and is arranged alternately with the first P-type pillar; and a second N-type pillar disposed in the second device wafer and arranged alternately with the second P-type pillar.

4. The high-voltage superjunction device structure according to claim 1, characterized in that: The first device wafer has a front side and a back side, and the second device wafer has a front side, wherein the bonding interface is located between the back side of the first device wafer and the front side of the second device wafer.

5. The high-voltage superjunction device structure according to claim 4, characterized in that: A metal structure and an insulating layer are formed on the front side of the first device wafer.

6. A method for manufacturing a high-voltage superjunction device structure, characterized in that, include: Step 1: Provide a first device wafer, the first device wafer having a first P-type pillar formed on its front side, and planarize the front side of the first device wafer to form a first bonding surface, and then temporarily bond the first bonding surface of the first device wafer to a carrier wafer. Step 2: Perform back-side thinning on the first device wafer temporarily bonded to the carrier wafer until the back side of the first P-type pillar is exposed; Step 3: Provide a second device wafer, the second device wafer having a second P-type pillar formed on its front side; Step 4: Bond the back side of the first device wafer, which has undergone back-side thinning, to the front side of the second device wafer so that the first P-pillar and the second P-pillar are aligned and connected, thereby forming an extended P-pillar. as well as Step 5: Release the temporary bond between the first device wafer and the carrier wafer.

7. The method for manufacturing the high-voltage superjunction device structure according to claim 6, characterized in that: In step one, the planarization process on the front side of the first device wafer includes: depositing an insulating layer on the front side of the first device wafer; and performing chemical mechanical polishing on the insulating layer to planarize the first bonding surface.

8. The method for manufacturing the high-voltage superjunction device structure according to claim 7, characterized in that: In step one, before depositing the insulating layer, a field oxide layer and a polysilicon layer are pre-formed on the front side of the first device wafer, thereby forming a step difference on the front side; the insulating layer is then chemically and mechanically polished to eliminate the step difference.

9. The method for manufacturing the high-voltage superjunction device structure according to claim 7, characterized in that: In step one, prior to performing chemical mechanical polishing, the method further includes: forming a metal structure on the first device wafer and performing metal chemical mechanical polishing on the metal structure.

10. The method for manufacturing the high-voltage superjunction device structure according to claim 9, characterized in that: The metal chemical mechanical polishing is tungsten chemical mechanical polishing.

11. The method for manufacturing the high-voltage superjunction device structure according to claim 7, characterized in that: The insulating layer is a silicon oxide layer formed by tetraethoxysilane plasma-enhanced chemical vapor deposition.

12. The method for manufacturing the high-voltage superjunction device structure according to claim 6, characterized in that: In step four, the bonding is a silicon-silicon direct bonding.

13. The method for manufacturing the high-voltage superjunction device structure according to claim 12, characterized in that: In step four, after bonding, the first device wafer and the second device wafer after bonding are further subjected to annealing.

14. The method for manufacturing the high-voltage superjunction device structure according to claim 6, characterized in that: The first P-type pillar and / or the second P-type pillar are formed by etching deep trenches in an N-type semiconductor layer and filling the deep trenches with P-type semiconductor material.

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