A method for reducing warpage of LED wafer bonding

Abstract

The application relates to a LED wafer bonding method for reducing warping, which comprises the following steps: (1) roughening a P-type layer of an epitaxial wafer; (2) preparing a film on the surface; (3) preparing a metal layer; (4) applying photoresist on the surface of a substrate; (5) evaporating metal material on the substrate; (6) removing the photoresist; (7) preparing silicon oxide on the substrate; (8) using CMP to planarize the surface of the silicon oxide and expose the metal material; (9) bonding the epitaxial wafer and the substrate; (10) removing the GaAs substrate of the epitaxial wafer and etching a stop layer; (11) removing part of an N-type ohmic contact layer and performing roughening treatment; (12) etching the current epitaxial layer through and removing the film in the step (2) to form a cutting path; and (13) preparing an N electrode in the N-type ohmic contact layer region, cutting along the cutting path, and obtaining independent chips. The application reduces the contact area, optimizes the bonding contact area on the basis of meeting the use, and reduces the stress.

Description

TECHNICAL FIELD

[0001] The application relates to a LED wafer bonding method for reducing warping, and belongs to the technical field of optoelectronics. BACKGROUND

[0002] At present, the reverse polarity AlGaInP quaternary LED chip is widely applied to the field of high-power red LED display screens, and the reverse polarity refers to substrate replacement, that is, replacing the GaAs substrate with large light absorption into a single-crystal conductive Si substrate or a sapphire substrate, so that the light efficiency can be improved by more than 20%. In the substrate replacement process, the original wafer needs to be transferred to a support substrate through a bonding process. The bonding material used in this step can be metal, oxide, organic adhesive and the like. In the bonding process, the bonding strength can be improved by applying temperature, pressure and electric field, that is, the firmness between wafers is increased. Since the thermal expansion coefficients of different materials are different, when the temperature and pressure decrease to room temperature or the use temperature, the stress difference between the wafers will cause the wafers to warp. The whole process flow is relatively long, the wafer warps greatly after the substrate replacement process, and the wafer is extremely prone to breakage in the subsequent wafer flow process, thereby affecting the wafer flow efficiency. The production, sales and profits of the reverse polarity chip are greatly affected. At present, how to effectively reduce the warping and the breakage rate and improve the output of the reverse polarity chip has become the main research direction.

[0003] Chinese patent document CN104518056A discloses a preparation method of a reverse polarity AlGaInP red LED chip, which comprises the following steps: (1) bonding the wafer of a GaAs substrate light emitting diode and a silicon wafer together; (2) etching the GaAs substrate, rotating the wafer by 180 degrees in the vertical direction and continuing etching; (3) scraping off the metal film layer remaining at the edge of the wafer after the GaAs substrate is etched completely; (4) rinsing the surface of the wafer; etching the barrier layer on the surface of the wafer by using a sulfuric acid solution; (5) pasting a high-temperature-resistant adhesive tape with an area larger than the over-etching alignment mark on the over-etching alignment mark of the wafer; and (6) then performing evaporation of an N-type metal electrode and etching a window by using a window etching solution. The clear over-etching alignment mark pattern is obtained after etching. In the method, the relevant dimensions are confirmed first and then the operation is performed. Since the manufacturing process of the reverse polarity AlGaInP quaternary LED chip is relatively long, the possibility of unstable process is greater, and the yield of the final output is low. SUMMARY

[0004] In view of the deficiencies of the prior art, the application provides a LED wafer bonding method for reducing warping. The bonding is performed by using a patterned material of metal and oxide, that is, part of the area has metal and part of the area has no metal, so that the contact area is reduced. On the basis of meeting the use, the bonding contact area is optimized, the stress is reduced, and the metal has a linear thermal expansion coefficient of part of the material, which is 10^-6 / ℃.

[0005] The technical scheme of the present application is as follows:

[0006] A LED wafer bonding method for reducing warping, comprising the following steps:

[0007] (1) roughening the P-type layer of the epitaxial wafer;

[0008] (2) preparing a thin film on the surface of the roughened P-type layer;

[0009] (3) preparing a metal layer on the surface of the thin film;

[0010] (4) coating photoresist on the surface of the substrate to form a periodic photoresist pattern;

[0011] (5) evaporating metal material on the substrate with the pattern;

[0012] (6) removing the photoresist by lift off process to complete the preparation of the periodic metal pattern;

[0013] (7) preparing silicon oxide on the substrate with the metal pattern;

[0014] (8) planarizing the surface of the silicon oxide by CMP to expose the metal material and thinning the metal material;

[0015] (9) bonding the P surface of the epitaxial wafer of step (3) with the metal side of the substrate of step (8);

[0016] (10) removing the GaAs substrate of the epitaxial wafer and etching the stop layer;

[0017] (11) removing part of the N-type ohmic contact layer and roughening the removed part of the ohmic contact layer;

[0018] (12) etching through the current epitaxial layer and removing the thin film in step (2) to form a cutting path;

[0019] (13) preparing an N electrode in the N-type ohmic contact layer region;

[0020] (14) cutting according to the cutting path formed in step (12) by laser cutting or cutter wheel cutting to obtain independent chips.

[0021] According to the present application, preferably, in step (1), the roughening uses a mixed solution of HF, HNO3 and CH3COOH, the volume ratio of HF, HNO3 and CH3COOH is 3:2:4, the temperature of the mixed solution is 25-35℃, and the soaking time is 30-120 seconds.

[0022] According to the present application, preferably, in step (2), the thin film is a transparent conductive thin film ITO, a transparent conductive thin film ZNO or a SiO2\TCF composite thin film, and the thickness of the thin film is 300-1200 angstroms.

[0023] According to the application, preferably, in step (3), the metal layer material is gold, silver or copper, the manufacturing method is electron beam evaporation or sputtering, and the thickness of the metal layer is 0.1 μm.

[0024] According to the application, preferably, in step (4), the substrate is a silicon wafer, sapphire or ceramic.

[0025] According to the application, preferably, in step (5), the metal material is gold, silver or copper, and the thickness is 0.5-1 μm.

[0026] According to the application, preferably, in step (7), the thickness of the silicon oxide is 1-2 μm.

[0027] According to the application, preferably, in step (8), the metal material is thinned to 0.8-0.9 μm.

[0028] According to the application, preferably, in step (10), the removing method is etching, and the etching solution used is a mixture of ammonia, hydrogen peroxide and water, with a volume ratio of 1:2:6.

[0029] According to the application, preferably, in step (12), the etching of the epitaxial layer utilizes wet etching or dry etching process.

[0030] The application has the following advantages:

[0031] The application uses patterned metal and oxide materials for bonding, which is equivalent to having metal in part of the area and no metal in part of the area, thereby reducing the contact area, optimizing the bonding contact area and reducing stress on the basis of meeting the use. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 Fig. 1 is a sectional view of a quad chip made in step (1) of the application;

[0033] Figure 2 Fig. 2 is a sectional view of a quad chip made in step (2) of the application;

[0034] Figure 3 Fig. 3 is a sectional view of a quad chip made in step (3) of the application;

[0035] Figure 4 Fig. 4 is a sectional view of a quad chip made in step (6) of the application;

[0036] Figure 5 Fig. 5 is a sectional view of a quad chip made in step (7) of the application;

[0037] Figure 6 Fig. 6 is a sectional view of a quad chip made in step (8) of the application;

[0038] Figure 7 This is a cross-sectional view of the quaternary chip produced in step (9) of the present invention;

[0039] Figure 8 This is a cross-sectional view of a single chip produced in step (11) of the present invention;

[0040] Figure 9 This is a cross-sectional view of a single chip produced in step (12) of the present invention;

[0041] Figure 10 This is a cross-sectional view of a single chip produced in step (13) of the present invention;

[0042] Figure 11 This is a cross-sectional view of a single chip produced in step (14) of the present invention;

[0043] In the figure, 1 is the GaAs substrate; 2 is the etching stop layer; 3 is the ohmic contact layer; 4 is the P-type layer; 5 is the metal layer; 6 is the thin film; 7 is the metal material; 8 is silicon oxide; 9 is the substrate; 10 is the roughened region; and 11 is the N-electrode. Detailed Implementation

[0044] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0045] Example 1:

[0046] This embodiment provides a method for fabricating an AlGaInP quaternary vertical LED chip, the steps of which are as follows:

[0047] (1) Roughening of the P-type layer 4 of the epitaxial wafer: The roughening was carried out using a mixture of HF, HNO3 and CH3COOH, with a volume ratio of HF, HNO3 and CH3COOH of 3:2:4, a temperature of 25°C, and a soaking time of 30 seconds;

[0048] (2) An ITO film was prepared on the roughened P-type layer surface, with a film thickness of 300 angstroms;

[0049] (3) A metal layer 5 with a thickness of 0.1 μm was fabricated on the surface of the ITO thin film by electron beam evaporation;

[0050] (4) Photoresist is applied to the surface of the silicon wafer substrate 9 to form a periodic photoresist pattern;

[0051] (5) Deposit metal material 7 onto the substrate with the completed pattern, using the same process as step (3), with a thickness of 1 μm;

[0052] (6) The photoresist is removed using a lift-off process to complete the fabrication of periodic metal patterns, such as... Figure 4 As shown, multiple columnar metals are arranged side by side to form a periodic metal pattern;

[0053] (7) The substrate surface with the metal pattern prepared in step (6) is prepared with silicon oxide 8, and the thickness of the silicon oxide is 1.5 μm;

[0054] (8) The silicon oxide surface is planarized by using CMP, and the metal is exposed after planarization, and the thickness of the metal is reduced from 1 μm in step (5) to 0.9 μm;

[0055] (9) The P surface of the epitaxial wafer in step (3) is bonded to the metal side of the substrate in step (8);

[0056] (10) The GaAs substrate 1 and the etching stop layer 2 are removed by using an etching solution, and the etching solution is a mixture of ammonia, hydrogen peroxide and water, and the volume ratio of ammonia, hydrogen peroxide and water in the mixture is 1:2:6;

[0057] (11) The N-type ohmic contact layer 3 is selectively etched (only part of the ohmic contact is retained, and the specific value is not limited) by using a wet etching or dry etching process in combination with a photoresist mask, and the removed part is roughened, and the roughening solution is composed of 96% phosphoric acid, 36.5% hydrochloric acid and pure water in a volume ratio of 1:3:5 or 2:5:10, and the roughening time is 30 seconds;

[0058] (12) The current epitaxial layer is etched through by using a wet etching or dry etching process, and the thin film in step (2) is removed to form a chip cutting path;

[0059] (13) The electrode pattern is prepared on the N-type surface by using a photoetching process, and the N electrode 11 is prepared by using electron beam evaporation, sputtering and the like;

[0060] (14) The surface is cut along the cutting path in step (12) by using a 355 nm laser, and independent chips are obtained by breaking the wafer.

[0061] Embodiment 2:

[0062] The embodiment provides a preparation method of an AlGaInP quaternary vertical LED chip, comprising:

[0063] (1) The P-type layer of the epitaxial wafer is roughened: a mixed solution of HF, HNO3 and CH3COOH is used for roughening, the volume ratio of HF, HNO3 and CH3COOH is 3:2:4, the temperature of the mixed solution is 35°C, and the immersion time is 120 seconds;

[0064] (2) An ITO thin film is prepared on the roughened P-type layer surface, and the thickness of the thin film is 1200 angstroms;

[0065] (3) A metal layer is prepared on the ITO thin film surface by using electron beam evaporation, and the thickness is 0.1 μm;

[0066] (4) Coating photoresist on the sapphire surface to form a periodic photoresist pattern;

[0067] (5) Evaporating metal material on the substrate with completed pattern, the process being consistent with step (3), and the thickness being 1 μm;

[0068] (6) Removing the photoresist by lift off process to complete the fabrication of periodic metal pattern, as shown in FIG. 6, a plurality of columnar metals are arranged side by side to form the periodic metal pattern; Figure 4

[0069] (7) Fabricating silicon oxide on the surface of the substrate with metal pattern fabricated in step (6), and the thickness of the silicon oxide being 1.5 μm;

[0070] (8) Planarizing the surface of the silicon oxide by CMP, and exposing the metal after planarization, and reducing the thickness of the metal from 1 μm in step (5) to 0.9 μm;

[0071] (9) Bonding the P surface of the epitaxial wafer in step (3) with the metal side of the substrate in step (8);

[0072] (10) Removing the GaAs substrate by etching solution, and etching the stop layer, and the etching solution being a mixture of ammonia, hydrogen peroxide and water, and the volume ratio of the ammonia, the hydrogen peroxide and the water being 1:2:6;

[0073] (11) Selectively etching the N-type ohmic contact layer by wet etching or dry etching process in combination with photoresist mask, and roughening the removed part, and the roughening solution being configured according to the volume ratio of 96% phosphoric acid, 36.5% hydrochloric acid and pure water being 1:3:5 or 2:5:10, and the roughening time being 60 seconds;

[0074] (12) Etching the current epitaxial layer to penetrate the metal layer in step (3) by wet etching or dry etching process;

[0075] (13) Continuing to etch to the sapphire surface by wet etching or dry etching process again to form a cutting path;

[0076] (14) Preparing electrode pattern on the surface in step (14) by photolithography process, and preparing P\N electrode by electron beam evaporation, sputtering and the like, and here the sapphire is used as the bonding substrate, and the sapphire is not conductive, and thus it is necessary to etch from the epitaxial layer to the bonding metal layer to realize the conduction of P electrode, and here the P\N electrode can be prepared at the same time;

[0077] (15) Cutting the surface along the cutting path in step (13) by 355 nm laser, and obtaining independent chips by the way of splitting.​

Claims

1. A method of reducing warpage in LED wafer bonding, comprising: The steps are as follows: (1) roughen the P-type layer of the epitaxial wafer; (2) prepare a thin film on the surface of the roughened P-type layer; (3) prepare a metal layer on the surface of the thin film; (4) coat photoresist on the surface of the substrate to form a periodic photoresist pattern; (5) evaporate metal material on the substrate with the pattern; (6) remove the photoresist by lift off process to complete the preparation of the periodic metal pattern; (7) prepare silicon oxide on the substrate with the metal pattern; (8) planarize the surface of the silicon oxide by CMP to expose the metal material and thin the metal material; (9) bond the P surface of the epitaxial wafer in step (3) with the metal side of the substrate in step (8); (10) remove the GaAs substrate of the epitaxial wafer and etch the stop layer; (11) remove part of the N-type ohmic contact layer and roughen the removed part of the ohmic contact layer; (12) etch through the current epitaxial layer and remove the thin film in step (2) to form a cutting path; (13) prepare an N electrode in the N-type ohmic contact layer region; (14) cut according to the cutting path formed in step (12) to obtain independent chips.

2. The reduced warp LED wafer bonding method of claim 1, wherein, In step (1), the roughening uses a mixed solution of HF, HNO3 and CH3COOH, the volume ratio of HF, HNO3 and CH3COOH is 3:2:4, the temperature of the mixed solution is 25-35℃, and the soaking time is 30-120 seconds.

3. The method of claim 2, wherein the LED wafer bonding method is reduced warpage, characterized in that, In step (2), the thin film is a transparent conductive thin film ITO, a transparent conductive thin film ZNO or a SiO2\TCF composite thin film, and the thickness of the thin film is 300-1200 angstroms.

4. The method of claim 3, wherein the LED wafer bonding method is reduced warpage, characterized in that, In step (3), the metal layer material is gold, silver or copper, and the preparation method is electron beam evaporation or sputtering, and the thickness of the metal layer is 0.1μm.

5. The LED wafer bonding method for reducing warpage as described in claim 4, characterized in that, In step (4), the substrate is a silicon wafer, sapphire or ceramic.

6. The method of claim 5, wherein the LED wafer bonding method is reduced warpage, and In step (5), the metal material is gold, silver or copper, and the thickness is 0.5-1μm.

7. The LED wafer bonding method for reducing warpage as described in claim 6, characterized in that, In step (7), the thickness of the silicon oxide is 1-2um.

8. The reduced warp LED wafer bonding method of claim 7, wherein, In step (8), the metal material is thinned to 0.8-0.9um.

9. The LED wafer bonding method for reducing warpage as described in claim 8, characterized in that, In step (10), the removal method is etching, and the etching solution used is a mixed solution of ammonia, hydrogen peroxide and water, and the volume ratio of ammonia, hydrogen peroxide and water in the mixed solution is 1:2:

6.

10. The LED wafer bonding method for reducing warpage as described in claim 9, characterized in that, In step (12), the epitaxial layer etching utilizes wet etching or dry etching process.

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