Method for preventing Al diffusion of metal gate

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a method for preventing Al diffusion of a metal gate. The method comprises the steps that a substrate is provided, and a gate trench is formed in the substrate; sequentially forming a TiN work function metal layer, a TiAl work function layer and a graphene barrier layer in the gate trench; and an Al metal layer is formed on the graphene barrier layer, and the lattice spacing of the graphene barrier layer is smaller than the atom diameter of the Al metal layer, so that diffusion of Al atoms of the Al metal layer to the TiAl work function layer is inhibited. According to the invention, diffusion of Al atoms of the Al metal layer to the TiAl work function layer is effectively inhibited, the stability of the work function of the metal gate can be maintained, and increase of interface resistance is inhibited; and meanwhile, the graphene barrier layer has excellent bonding strength with the TiAl work function layer and the Al metal layer, the adhesion is good, the intrinsic conductivity is high, and the problems of electrode stripping and contact resistance increase can be avoided.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method for preventing Al diffusion in a metal gate. Background Technology

[0002] Metal gates are key electrode structures in metal-oxide-semiconductor field-effect transistors (MOSFETs). Located above the gate dielectric layer, they control the conduction and turn-off of the channel by applying voltage. For example, a work function (WF) metal layer can be used to replace the traditional polysilicon gate, thereby solving the problems of low device efficiency and performance degradation caused by the boron penetration effect of traditional polysilicon gates. Existing metal gates have lower resistance and better electrical stability, thus improving device performance.

[0003] Existing metal gates mainly adopt composite structures, which are usually formed in gate trenches. The gate trenches are formed in the interlayer film on the surface of the semiconductor substrate. The gate trenches are formed by removing the dummy gate structure and include the substrate, a work function metal layer (such as TiN, TaN) for adjusting the threshold voltage of the MOSFET, and a low resistance metal layer (such as Al, Cu, W) for reducing the gate series resistance.

[0004] A related technology discloses a MOS transistor with HKMG and its manufacturing method. The structure includes an NMOS transistor, with a first gate structure formed in a first gate groove. This first gate structure comprises a gate dielectric layer, a first barrier layer, an N-type work function metal layer, and a metal conductive material layer stacked together. The first barrier layer is composed of ALD-TiAl, which also contains C atoms. The N-type work function metal layer is grown using a PVD process. The general structural principle of the MOS transistor and its manufacturing method in this scheme is as follows: ALD-TiAl is used instead of TaN as the barrier layer at the bottom of the N-type work function metal layer. The flatness of ALD-TiAl is superior to that of the N-type work function metal layer grown by the PVD process, and the structural characteristic of ALD-TiAl containing C atoms enables the first barrier layer to prevent the downward diffusion of the metal conductive material layer.

[0005] However, the MOS transistor and its manufacturing method still have at least the following shortcomings in actual use, which are the technical problems to be solved by this application: During high-temperature annealing or deposition, Al atoms are prone to diffuse and react with ALD-TiAl to form stable intermetallic compounds such as TiAl3, which leads to a shift in the work function of the metal gate, an increase in the interface resistance, and affects the circuit stability and device performance.

[0006] Therefore, in summary, there is an urgent need for a method to prevent Al diffusion in metal gates. Summary of the Invention

[0007] This application provides a method for preventing Al diffusion in a metal gate. This method involves sequentially forming a TiN work function layer, a TiAl work function layer, and a graphene barrier layer in the gate trench. This allows the graphene barrier layer to block the Al metal layer, effectively inhibiting the diffusion of Al atoms from the Al metal layer into the TiAl work function layer and maintaining the stability of the metal gate's work function, thus suppressing the increase in interface resistance. Simultaneously, the graphene barrier layer exhibits excellent bonding strength and adhesion with both the TiAl work function layer and the Al metal layer, and possesses high intrinsic conductivity, thus avoiding electrode peeling and increased contact resistance.

[0008] The technical solution adopted by this application to solve the above problems is: a method for preventing Al diffusion in a metal gate, comprising: providing a substrate, forming a gate trench on the substrate; sequentially forming a TiN work function layer, a TiAl work function layer and a graphene barrier layer in the gate trench; forming an Al metal layer on the graphene barrier layer, wherein the lattice spacing of the graphene barrier layer is smaller than the atomic diameter of the Al metal layer, so as to suppress the diffusion of Al atoms from the Al metal layer to the TiAl work function layer.

[0009] The graphene barrier layer not only effectively inhibits the diffusion of Al atoms from the Al metal layer to the TiAl work function layer, but also maintains the stability of the metal gate work function and suppresses the growth of interface resistance. At the same time, the graphene barrier layer has excellent bonding strength and good adhesion with the TiAl work function layer and the Al metal layer, and has high intrinsic conductivity, which can avoid problems such as electrode peeling and increased contact resistance.

[0010] The graphene barrier layer is a single layer with a thickness of 4-8 Å. The work function of the graphene barrier layer (~4.3 eV) is close to that of the TiAl work function layer (~4.2 eV), which can minimize the impact on the work function of the metal gate.

[0011] The graphene barrier layer is formed using atomic layer deposition (ALD). Controlling the deposition thickness of the graphene barrier layer based on the number of ALD cycles helps improve the quality of the graphene and reduce defects.

[0012] The atomic layer deposition temperature of the graphene barrier layer is 300-350℃, which promotes the growth of graphene on the surface of the TiAl work function layer.

[0013] Before forming the TiN work function layer, a TaN transition layer is formed within the gate trench to prevent metal atoms from the TiN work function layer from diffusing to the substrate. Effectively blocking the diffusion of work function metal atoms reduces defects caused by direct contact between the metal and semiconductor materials, thus optimizing the threshold voltage and lowering the overall gate resistance.

[0014] Before forming the TaN transition layer, a low-dielectric-constant material layer is formed within the gate trench to isolate the TiN work function layer and the substrate. This reduces signal delay and power consumption, improving device performance.

[0015] The low dielectric constant material layer is made of one or more combinations of porous SiO2, SiCOH, polyimide, lanthanum fluoride, and fluorosilicone glass. It meets the requirements of a dielectric constant K less than 3.0, reliable mechanical strength (able to withstand chemical mechanical polishing, encapsulation stress, etc.), thermal stability greater than 400℃, and adhesion to the work function metal layer.

[0016] The low dielectric constant material layer includes a hafnium dioxide layer located beneath the TaN transition layer. This layer increases the adhesion between the TaN transition layer and the low dielectric constant material layer, while further enhancing the isolation and protective effect of the low dielectric constant material layer.

[0017] The TiN work function layer is the work function layer of the PMOS. It can effectively adjust the threshold voltage of the PMOS to a reasonable range (so that the PMOS turns on under an appropriate negative gate voltage), while reducing gate leakage current and improving device stability.

[0018] The TiAl work function layer is the work function layer of the NMOS. It allows the threshold voltage of the NMOS to be adjusted to a suitable positive value (so that the NMOS turns on at an appropriate positive gate voltage), ensuring that electrons can be effectively injected into the channel and improving the device's switching performance. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of the method for preventing Al diffusion in a metal gate according to this application.

[0021] Figure 2 This is a schematic diagram of the intermetallic combination structure after a graphene barrier layer is deposited on the surface of the TiAl layer in this application.

[0022] Figure 3 This is a schematic diagram showing the location of the gate trench in this application.

[0023] Figure label:

[0024] 1. Substrate; 2. Gate trench; 3. TiN work function layer; 4. TiAl work function layer; 5. Graphene barrier layer; 6. Al metal layer; 7. TaN transition layer; 8. Low dielectric constant material layer.

[0025] 11. Silicon substrate, 12. Source / drain region, 13. Zero-layer interlayer film. Detailed Implementation

[0026] The embodiments of this application will be described in detail below with reference to the accompanying drawings. The following description is only a preferred embodiment of this application and is not intended to limit the scope of this application. The directional terms such as up, down, left, right, front, back, front, back, top, bottom, etc., mentioned or possibly mentioned in this specification are defined relative to the structure shown in the accompanying drawings. The terms "inner" and "outer" refer to the direction toward or away from the geometric center of a specific component, respectively. These are relative concepts and may therefore vary depending on their different positions and usage states. Therefore, these or other directional terms should not be interpreted as restrictive terms.

[0027] like Figures 1-3 As shown in the embodiment of this application, a method for preventing Al diffusion in a metal gate includes: providing a substrate 1, forming a gate trench 2 on the substrate 1; sequentially forming a TiN work function layer 3, a TiAl work function layer 4, and a graphene barrier layer 5 in the gate trench 2; forming an Al metal layer 6 on the graphene barrier layer 5, wherein the lattice spacing of the graphene barrier layer 5 is smaller than the atomic diameter of the Al metal layer 6, so as to suppress the diffusion of Al atoms from the Al metal layer 6 to the TiAl work function layer 4.

[0028] In this embodiment, the substrate 1 includes the silicon substrate 11, the source / drain regions 12, and the zeroth interlayer film 13. The structure is formed as follows: a pseudo-gate structure is formed on the surface of the silicon substrate 11. The pseudo-gate structure is typically formed by stacking a pseudo-gate dielectric layer and a polysilicon pseudo-gate. Then, sidewalls are formed by self-alignment on the side of the pseudo-gate structure, and the source / drain regions 12 are formed by self-alignment on the sidewalls of the pseudo-gate structure. Then, the zeroth interlayer film 13 is formed, and the zeroth interlayer film 13 is etched and chemically mechanically polished so that the top surface of the zeroth interlayer film 13 is flush with the top surface of the pseudo-gate structure. Then, the pseudo-gate structure is removed to form the gate trench 2.

[0029] Furthermore, the TiN work function layer 3 and the TiAl work function layer 4 are used to adjust the threshold voltage of the MOSFET. The graphene barrier layer 5 is used to prevent the diffusion of Al atoms from the Al metal layer 6 and their migration through the TiN work function layer 3 and the TiAl work function layer 4 towards the zeroth interlayer film 13 or the silicon substrate 11, thereby disrupting the work function stability of the metal gate. During the annealing and high-temperature deposition processes, the Al atoms in the Al metal layer 6 are affected by high temperatures and will rapidly diffuse along grain boundaries or defects, reacting with the TiAl work function layer 4 to form TiAl3. Since the work function of TiAl3 (~4.3 eV) is different from that of TiAl (~4.1 eV), the work function shifts, the interface resistance increases (RTiAl3 > RTiAl > RAl), and the consumption of Al makes the TiAl work function layer more Ti-rich (e.g., transforming into Ti3Al), with an even higher work function (~4.5 eV), further aggravating the gate threshold voltage (Vt) drift and leading to device contact failure. Therefore, to avoid interfacial reactions between the Al atoms of the Al metal layer 6 and the TiAl work function layer 4, the graphene barrier layer 5 is deposited after the TiAl work function layer 4 is formed. Since the hexagonal lattice spacing (~0.246 nm) of the graphene barrier layer 5 is smaller than the diameter of the Al atoms in the Al metal layer 6 (~0.286 nm), the graphene barrier layer 5 can block the diffusion of Al atoms from the Al metal layer 6, thereby maintaining the stability of the gate work function.

[0030] The graphene barrier layer 5 exhibits excellent interfacial bonding strength with the TiAl work function layer 4 and the Al metal layer 6, preventing electrode delamination between Al-graphene-TiAl. Firstly, regarding chemical bonding characteristics, the 3d orbital electrons of Ti form partial covalent bonds (Ti-C bonds) with the π electron cloud of graphene. At the interface, Ti in TiAl forms local carbides (TiC) with the carbon atoms of graphene, enhancing the adhesion strength between the two without requiring additional plasma treatment. While the 3p electrons of Al form metallic bonds with the π electrons of graphene, although weaker than Ti-C bonds, Al's high ductility allows for increased contact area through plastic deformation, improving the actual bonding force. Secondly, regarding electron coupling and charge transfer, when graphene contacts TiAl, the Fermi level of TiAl (~4.1 eV) is lower than the Dirac point of graphene (~4.5 eV), causing electrons to transfer from graphene to TiAl, reducing its work function to near that of TiAl. This reduces the interface barrier, forming an ohmic contact, lowering contact resistance, and promoting electron transport. Furthermore, a small number of electrons from Ti / Al atoms in graphene can be electrostatically adsorbed at the interface, further increasing the bonding strength. Thirdly, in terms of structural matching, the six-membered ring structure of TiAl and graphene exhibits local matching, reducing interface strain. Additionally, Ti / Al atoms can fill dangling bonds (such as vacancies and grain boundaries) at the edges of graphene, lowering the interface energy and passivating defects. Therefore, the interface bonding between the graphene barrier layer 5, the TiAl work function layer 4, and the Al metal layer 6 provides a stable interface for the metal gate structure. Combined with the high intrinsic conductivity of graphene ensuring signal transmission efficiency, this makes it suitable for high-frequency, high-power devices.

[0031] Finally, the metal gate structure is formed using a gate-last process. First, a substrate 1 is provided, and a gate trench 2 is formed on the substrate 1. The TiN work function layer 3, the TiAl work function layer 4, and the graphene barrier layer 5 are sequentially formed in the gate trench 2. Then, Al metal conductive material is completely filled on the graphene barrier layer 5 and in the gate trench 2 to form the Al metal layer 6. Finally, the surface of the Al metal layer 6 is chemically and mechanically polished.

[0032] The graphene barrier layer 5 is a single layer with a thickness of 4-8 Å. The work function of the graphene barrier layer 5 (~4.3 eV) is close to that of the TiAl work function layer 4 (~4.2 eV), which can minimize the impact on the work function of the metal gate.

[0033] The graphene barrier layer 5 is formed using atomic layer deposition (ALD). The graphene barrier layer 5 is formed on the surface of the TiAl work function layer 4 using ALD, and the deposition thickness of the graphene barrier layer 5 is controlled according to the number of ALD cycles. The graphene barrier layer 5 is formed mainly through the following four steps: Step 1, benzene vapor is introduced into the reaction chamber, and the molecules of benzene vapor are adsorbed on the surface of the substrate 1; Step 2, unreacted benzene vapor and byproducts are removed using an inert gas (such as N2 or Ar); Step 3, formic acid is introduced as an auxiliary source, reacting with benzene derivatives on the surface to generate the graphene barrier layer 5 and release CO2 / H2O; Step 4, inert gas is introduced again to purge residual gas, completing a single cycle. Benzene derivatives or methane (CH4) are selected as carbon sources as precursors. These carbon sources can be effectively cracked under the action of plasma, providing the carbon atoms required for graphene deposition. Furthermore, using oxygen-containing organic compounds such as formic acid (HCOOH) as an auxiliary source helps improve the quality of graphene and reduce defects.

[0034] The atomic layer deposition temperature of the graphene barrier layer 6 is 300-350℃. In this embodiment, when the graphene barrier layer 6 is generated using the atomic layer deposition method, the deposition temperature is 300-350℃. Based on this, using plasma enhancement technology with a radio frequency power of 100-200W can promote the cracking and dehydrogenation of the carbon source, reduce the film porosity of the graphene barrier layer 6, and thus promote the growth of graphene on the surface of the TiAl work function layer 4.

[0035] Before forming the TiN work function layer 3, a TaN transition layer 7 is formed within the gate trench 2 to prevent the metal atoms of the TiN work function layer 3 from diffusing to the substrate 1. The function of the TaN transition layer 7 is to prevent the metal atoms of the TiN work function layer 3 from contacting the substrate 1. By depositing the TaN transition layer 7 first and then the TiN work function layer 3, the high chemical stability of TaN effectively blocks the diffusion of work function metal atoms, reducing defects caused by direct contact between the metal and semiconductor materials, thus optimizing the threshold voltage and reducing the overall gate resistance. Furthermore, in the back-gate process, the bilayer structure of the TaN transition layer 7 + the TiN work function layer 3 maintains stability during high-temperature annealing or deposition.

[0036] Before forming the TaN transition layer 7, a low-dielectric-constant material layer 8 is formed within the gate trench 2 to isolate the TiN work function layer 3 and the substrate 1. The low-dielectric-constant material layer 8 isolates the TiN work function layer 3 and the substrate 1, reducing signal delay and power consumption, and improving device performance.

[0037] The low dielectric constant material layer 8 is made of one or more combinations of porous SiO2, SiCOH, polyimide, lanthanum fluoride, and fluorosilicone glass. The material of the low dielectric constant material layer 8 needs to meet the following requirements: dielectric constant K < 3.0, reliable mechanical strength (able to withstand chemical mechanical polishing, encapsulation stress, etc.), thermal stability > 400℃, and the ability to adhere to the TiN work function layer 3. Therefore, the material can be selected from one or more combinations of porous SiO2, SiCOH, polyimide, lanthanum fluoride, and fluorosilicone glass.

[0038] The low dielectric constant material layer 8 includes a hafnium dioxide layer located below the TaN transition layer 7. The hafnium dioxide layer is located between the low dielectric constant material layer 8 and the TaN transition layer 7, and is deposited before the TaN transition layer 7. It is used to increase the adhesion between the TaN transition layer 7 and the low dielectric constant material layer 8, and at the same time further enhance the isolation and protection effect of the low dielectric constant material layer 8.

[0039] The TiN work function layer 3 is the work function layer of the PMOS. The work function of the TiN work function layer 3 is in the range of ~4.6-4.8 eV. Its work function characteristics can form a good bandgap match with the P-type substrate, which can effectively adjust the threshold voltage of the PMOS to a reasonable range (so that the PMOS can be turned on under an appropriate negative gate voltage), while reducing the gate leakage current and improving the device stability.

[0040] The TiAl4 work function layer 4 is the work function layer of the NMOS. The work function of the TiAl4 work function layer is in the range of ~4.1-4.3 eV. Its work function characteristics can form a good bandgap match with the N-type substrate, which can adjust the threshold voltage of the NMOS to a suitable positive value (so that the NMOS can be turned on under an appropriate positive gate voltage), ensuring that electrons can be effectively injected into the channel and improving the switching performance of the device.

[0041] It should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application, and all such modifications and substitutions should be covered within the scope of this application.

Claims

1. A method for preventing Al diffusion in a metal gate, characterized in that, include: A substrate is provided, on which gate trenches are formed; A TiN work function metal layer, a TiAl work function metal layer, and a graphene barrier layer are sequentially formed in the gate trench; An Al metal layer is formed on the graphene barrier layer, wherein the lattice spacing of the graphene barrier layer is smaller than the atomic diameter of the Al metal layer, so as to suppress the diffusion of Al atoms from the Al metal layer to the TiAl work function metal layer.

2. The method for preventing Al diffusion in a metal gate according to claim 1, characterized in that, The graphene barrier layer is a single layer with a thickness of 4-8 Å.

3. The method for preventing Al diffusion in a metal gate according to claim 2, characterized in that, The graphene barrier layer was formed using atomic layer deposition.

4. The method for preventing Al diffusion in a metal gate according to claim 3, characterized in that, The atomic layer deposition temperature of the graphene barrier layer is 300-350℃.

5. The method for preventing Al diffusion in a metal gate according to claim 1, characterized in that, Before forming the TiN work function metal layer, a TaN transition layer is formed in the gate trench to prevent metal atoms from the TiN work function layer from diffusing to the substrate.

6. The method for preventing Al diffusion in a metal gate according to claim 5, characterized in that, Prior to forming the TaN transition layer, a low dielectric constant material layer is formed within the gate trench to isolate the TiN work function layer and the substrate.

7. The method for preventing Al diffusion in a metal gate according to claim 6, characterized in that, The material of the low dielectric constant material layer includes at least one of porous SiO2, SiCOH, polyimide, lanthanum fluoride, and fluorosilicone glass.

8. The method for preventing Al diffusion in a metal gate according to claim 6, characterized in that, The low dielectric constant material layer includes a hafnium dioxide layer located below the TaN transition layer.

9. The method for preventing Al diffusion in a metal gate according to claim 1, characterized in that, The TiN work function layer is the work function layer of PMOS.

10. The method for preventing Al diffusion in a metal gate according to claim 1, characterized in that, The TiAl work function layer is the work function layer of NMOS.

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