A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, the substrate comprising a first region and a second region, a gate structure being formed on the substrate in the first region and the second region, a stress layer, a polysilicon layer and a patterned photoresist layer being sequentially formed on the substrate, and the patterned photoresist layer exposing the second region; taking the patterned photoresist layer as a mask, performing a first ion implantation process to form an NOMS source-drain structure and to dope boron in the polysilicon layer; removing the photoresist layer and removing the polysilicon layer and the stress layer in the first region without a mask; performing a second ion implantation process without a mask to form a POMS source-drain structure on both sides of the gate structure in the first region; removing the polysilicon layer in the second region and performing an SMT process. The application only needs one mask plate and one independent photoetching process step, reduces the complexity and time cost of the process, and greatly reduces the overall manufacturing cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In the field of semiconductor device manufacturing, especially in the manufacturing process of metal-oxide-semiconductor field-effect transistors (MOSFETs), the formation of the source and drain (S / D) and stress engineering techniques to improve device performance are crucial steps.

[0003] The source and drain regions typically require precise implantation of high concentrations of impurity ions to form the desired conductivity type (N-type or P-type). This implantation process (i.e., S / D implantation) demands extremely strict control over impurity distribution and junction depth. Meanwhile, to improve transistor performance, particularly carrier mobility in NMOS devices, stress memory technology (SMT) is widely employed. This technology improves device electrical characteristics by introducing beneficial stress into the channel region. However, the effects of SMT on NMOS and PMOS transistors differ significantly; for example, it may positively improve the performance of NMOS transistors but adversely affect the performance of PMOS transistors. Therefore, after applying the SMT stress layer, selective processing is necessary to ensure that it only affects the region where the NMOS transistor is located.

[0004] Currently, in the manufacturing process of forming high-performance transistors, achieving precise N-type and P-type source / drain injection and selective application of SMT stress requires multiple independent photolithography steps. Each photolithography step involves a series of complex and expensive processes such as mask preparation, alignment, exposure, and development. These additional photolithography steps not only significantly increase the complexity and time cost of the process but also greatly increase the overall manufacturing cost. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and its fabrication method, which can reduce the number of masks to reduce photolithography steps, thereby reducing process complexity and cost.

[0006] To address the above technical problems, this invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0007] A substrate is provided, the substrate including a first region and a second region, a gate structure is formed on the substrate in both the first region and the second region, and a stress layer, a polysilicon layer and a patterned photoresist layer are sequentially formed on the substrate, the patterned photoresist layer exposing the second region;

[0008] Using the patterned photoresist layer as a mask, a first ion implantation process is performed to form NOMS source / drain structures on both sides of the gate structure in the second region, and boron is doped into the polysilicon layer in the second region.

[0009] Remove the photoresist layer, and remove the polysilicon layer and stress layer in the first region without a mask;

[0010] A second ion implantation process is performed without a mask to form POMS source / drain structures on both sides of the gate structure in the first region.

[0011] Remove the polysilicon layer in the second region and perform the SMT process.

[0012] Optionally, NOMS source / drain structures are formed on both sides of the gate structure in the second region, and boron is doped in the polysilicon layer of the second region using the following specific method:

[0013] Using the patterned photoresist layer as a mask, N-type ions are implanted into the substrates on both sides of the second gate structure and the second gap wall to form a second highly doped region, thereby forming a NOMS source / drain structure.

[0014] Using the patterned photoresist layer as a mask, boron ions are doped into the polycrystalline silicon layer.

[0015] Furthermore, the N-type ions include phosphorus and arsenic.

[0016] Optionally, the implantation energy of the N-type ions is 20 keV to 30 keV, and the implantation concentration is 1.5E15 atoms / cm³. 2 ~2.5E15 atoms / cm 2 ;

[0017] The boron ion implantation energy is less than 10 keV, and the implantation concentration is 1E15 atoms / cm². 2 ~2E15 atoms / cm 2 .

[0018] Optionally, the specific method for removing the polysilicon layer and stress layer in the first region without a mask is as follows:

[0019] The polysilicon layer in the first region was removed using a wet method with TMAH solution.

[0020] The stress layer in the first region was removed using a wet method with a phosphoric acid solution.

[0021] Optionally, when performing the second ion implantation process under the maskless condition, the boron-doped polysilicon layer and the stress layer retained on the second region together serve as a barrier layer to prevent P-type ions from implanting into the substrate of the second region.

[0022] Optionally, P-type ions are implanted in the second ion implantation process, and the implantation energy of the P-type ions is 8 keV to 12 keV.

[0023] Optionally, the specific method for removing the polysilicon layer in the second region is as follows:

[0024] The polysilicon layer in the second region is selectively etched using a dry etching process, thereby exposing the stress layer in the second region.

[0025] In the dry etching process, the reaction gas introduced into the reaction chamber is hydrogen.

[0026] Optionally, the specific method for performing the SMT process is as follows:

[0027] Perform the annealing process;

[0028] The stress layer in the second region was removed using a wet method with a phosphoric acid solution.

[0029] On the other hand, the present invention also provides a semiconductor device, which is prepared by the semiconductor device preparation method described above.

[0030] Compared with the prior art, the present invention has the following unexpected technical effects:

[0031] This invention provides a semiconductor device and its fabrication method. The fabrication method includes the following steps: providing a substrate, the substrate comprising a first region and a second region, wherein a gate structure is formed on both the first and second regions of the substrate; sequentially forming a stress layer, a polysilicon layer, and a patterned photoresist layer on the substrate, the patterned photoresist layer exposing the second region; using the patterned photoresist layer as a mask, performing a first ion implantation process to form NOMS source / drain structures on both sides of the gate structure in the second region, and doping boron in the polysilicon layer of the second region; removing the photoresist layer, and removing the polysilicon layer and stress layer of the first region without a mask; performing a second ion implantation process without a mask to form POMS source / drain structures on both sides of the gate structure in the first region; removing the polysilicon layer of the second region and performing an SMT process. This invention requires only one photomask and one independent photolithography step, greatly reducing the complexity and time cost of the process, and also significantly reducing the overall manufacturing cost. Attached Figure Description

[0032] Figure 1This is a schematic diagram of a traditional source / drain structure with a gate structure formed on the substrate.

[0033] Figure 2 This is a schematic diagram of the traditional source-drain structure when forming the source-drain structure of an NMOS.

[0034] Figure 3 This is a schematic diagram of the traditional source-drain structure when forming the source-drain structure of a PMOS.

[0035] Figure 4 This is a schematic diagram of the traditional source / drain structure during the formation of the stress layer.

[0036] Figure 5 This is a schematic diagram of the traditional source / drain structure when the stress layer in the PMOS region is removed.

[0037] Figure 6 This is a schematic diagram of the traditional source-drain structure during annealing.

[0038] Figure 7 This is a schematic diagram of the traditional source / drain structure when the stress layer in the NMOS region is removed.

[0039] Figure 8 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0040] Figure 9 This is a schematic diagram of the structure of a substrate provided in an embodiment of the present invention.

[0041] Figure 10 This is a schematic diagram of the structure after a polycrystalline silicon layer is formed according to an embodiment of the present invention.

[0042] Figure 11 This is a schematic diagram of the structure during the first ion implantation process according to an embodiment of the present invention.

[0043] Figure 12 This is a schematic diagram of the structure after removing the remaining photoresist layer according to an embodiment of the present invention.

[0044] Figure 13 This is a schematic diagram of the structure after removing the stress layer in the first region according to an embodiment of the present invention.

[0045] Figure 14 This is a schematic diagram of the structure during the second ion implantation process according to an embodiment of the present invention.

[0046] Figure 15 This is a schematic diagram of the structure after removing the polysilicon layer in the second region according to an embodiment of the present invention.

[0047] Figure 16 This is a schematic diagram of the structure after removing the stress layer in the second region according to an embodiment of the present invention.

[0048] Explanation of reference numerals in the attached figures:

[0049] Figures 1-7 In the middle: i-POMS region; ii-NOMS region; 10-substrate; 11-P-type lightly doped region; 12-N-type lightly doped region; 13-N-type heavily doped region; 14-P-type source / drain structure heavily doped region; 21-first photoresist layer; 22-second photoresist layer; 23-third photoresist layer; 30-stress layer;

[0050] Figures 9-16 middle:

[0051] I - First region; II - Second region; 100 - Substrate; 101 - First well region; 102 - Second well region; 103 - First low-doped region; 104 - First pocket doped region; 106 - Second low-doped region; 107 - Second pocket doped region; 108 - Silicon-germanium epitaxial layer; 109 - Second high-doped region; 110 - First high-doped region; 120 - Bottom oxide layer; 210 - First gate structure; 220 - Second gate structure; 230 - First spacer wall; 240 - Second spacer wall; 310 - Stress layer; 320 - Polysilicon layer; 400 - Photoresist layer. Detailed Implementation

[0052] The following will provide a more detailed description of a semiconductor device and its fabrication method according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0053] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0054] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0055] The traditional method for fabricating source / drain structures is as follows:

[0056] First, such as Figure 1 As shown, a substrate 10 is provided, which includes an NMOS region ii and a PMOS region i. Gate structures G1 and G2 are formed on both the NMOS region ii and the PMOS region i. The gate structure G1 has a P-type lightly doped region 11 on both sides, and the gate structure G2 has an N-type lightly doped region 12 on both sides.

[0057] Next, as Figure 2 As shown, a patterned first photoresist layer 21 is formed, and using the patterned first photoresist layer 21 as a mask, N-type ions are highly doped in the NOMS region ii to form an N-type ion highly doped region 13 and form the source and drain structure of NMOS, and then the first photoresist layer 21 is removed.

[0058] Next, as Figure 3 As shown, a patterned second photoresist layer 22 is formed, and using the patterned second photoresist layer 22 as a mask, highly doped P-type ions are implanted in the POMS region i to form a highly doped P-type ion region 14 and to form the source and drain structure of PMOS, and then the second photoresist layer 22 is removed.

[0059] Next, as Figure 4 As shown, stress layers 30 are formed on the substrate 10 of NMOS region ii and PMOS region i and on the surface of gate structures G1 and G2.

[0060] Next, as Figure 5 As shown, a patterned third photoresist layer 23 is formed, and the stress layer 30 of the PMOS region i is etched away using the patterned third photoresist layer 23 as a mask, and then the third photoresist layer 23 is removed.

[0061] Next, as Figures 6-7 As shown, annealing is performed to positively improve the performance of NMOS transistors, and then the remaining stress layer 30 is removed.

[0062] It is known that traditional source-drain structures require two photomasks and three independent photolithography steps in their fabrication. Each photolithography step involves a series of complex and expensive processes, including mask fabrication, alignment, exposure, and development. These additional photolithography steps not only significantly increase the complexity and time cost of the process but also greatly increase the overall manufacturing cost.

[0063] To address the above technical problems, the core of this embodiment lies in providing a method for fabricating a semiconductor device, comprising the following steps:

[0064] Step S10: Provide a substrate, the substrate including a first region and a second region, a gate structure is formed on the substrate in both the first region and the second region, a stress layer, a polysilicon layer and a patterned photoresist layer are sequentially formed on the substrate, the patterned photoresist layer exposing the second region;

[0065] Step S20: Using the patterned photoresist layer as a mask, perform the first ion implantation process to form NOMS source / drain structures on both sides of the gate structure in the second region, and dope boron in the polysilicon layer of the second region.

[0066] Step S30: Remove the photoresist layer, and remove the polysilicon layer and stress layer of the first region without a mask;

[0067] Step S40: Perform a second ion implantation process without a mask to form POMS source / drain structures on both sides of the gate structure in the first region;

[0068] Step S50: Remove the polysilicon layer in the second region and perform the SMT process.

[0069] This embodiment provides a method for fabricating a semiconductor device that greatly reduces the complexity and time cost of the process by requiring only one photomask and one independent photolithography step, and also significantly reduces the overall manufacturing cost.

[0070] The following combination Figures 9-16 This embodiment provides a detailed description of a method for fabricating a semiconductor device. First, step S10 is performed, in which a substrate is provided. The substrate includes a first region I and a second region II. Gate structures are formed on both the first region I and the second region II. A stress layer 310, a polysilicon layer 320, and a patterned photoresist layer 400 are sequentially formed on the substrate. The patterned photoresist layer 400 exposes the second region II.

[0071] This step specifically includes:

[0072] Please see Figures 9-11 First, a substrate is provided, the substrate including a first region I and a second region II, on which gate structures are formed respectively. A stress layer 310, a polysilicon layer 320 and a patterned photoresist layer 400 are sequentially formed on the substrate, the patterned photoresist layer 400 exposing the second region II.

[0073] First, such as Figure 9As shown, a substrate is provided, the substrate including a first region I and a second region II, a first well region 101 and a second well region 102 are disposed in the substrate, the first well region 101 is disposed in the first region I and the second well region 102 is disposed in the second region II.

[0074] The first well region 101 can be N-type doped or P-type doped, while the second well region 102 can be either P-type doped or N-type doped. In the following embodiments, the first well region 101 is an N-well region and the second well region 102 is a P-well region, meaning that in the following embodiments, a PMOS transistor will eventually be formed on the first well region 101, and an NMOS transistor will eventually be formed on the second well region 102. Furthermore, a shallow trench isolation (STI) surrounds the first well region 101 and the second well region 102 with the surrounding substrate.

[0075] A first gate structure 210 is disposed on the first well region 101, and a second gate structure 220 is disposed on the second well region 102. The first gate structure 210, from bottom to top, includes a first dielectric layer, a first conductive layer, and a first capping layer. The first gate structure 210 also includes a first spacer wall 230 located on the sidewalls of the first dielectric layer, the first conductive layer, and the first capping layer. The second gate structure 220, from bottom to top, includes a second dielectric layer, a second conductive layer, and a second capping layer. The second gate structure 220 also includes a second spacer wall 240 located on the sidewalls of the second dielectric layer, the second conductive layer, and the second capping layer.

[0076] In one embodiment, the first dielectric layer and the second dielectric layer may be composed of silicon oxide layers formed by processes such as thermal oxidation or deposition, or high dielectric constant material layers with a dielectric constant greater than 4. The first conductive layer and the second conductive layer may be conductive materials such as polycrystalline silicon, or metal materials with a specific work function. The first capping layer and the second capping layer may be composed of silicon nitride layers, and the first capping layer and the second capping layer may be selectively formed.

[0077] A first low-doped region 103 is formed in the first well region 101 located on both sides of the first gate structure 210. A first pocket doped region 104 is provided on the side of each first low-doped region 103 near the other first low-doped region 103. A portion of the first low-doped region 103 is located below the first spacer wall 230 and overlaps with the projection of the first spacer wall 230. The first low-doped region 103 is P-type doped, and the doping type of the first pocket doped region 104 is the same as that of the first well region 101, for example, both are N-type doped.

[0078] A second low-doped region 106 is formed in the second well region 102 located on both sides of the second gate structure 220. A second pocket doped region 107 is provided on the side of each second low-doped region 106 adjacent to the other second low-doped region 106. A portion of the second low-doped region 106 is located below the second spacer wall 240 and overlaps with the projection of the second spacer wall 240. The second low-doped region 106 is N-type doped, and the second pocket doped region 107 and the second well region 102 have the same doping type, for example, both are P-type doped.

[0079] A silicon-germanium epitaxial layer 108 is embedded in the substrate outside the first spacer wall 230. A bottom oxide layer 120 is formed on the substrate surface of the first well region 101 and the second well region 102. The bottom oxide layer 120 covers the silicon-germanium epitaxial layer 108 and the first low-doped region 103.

[0080] Next, as Figures 10-11 As shown, a stress layer 310, a polysilicon layer 320, and a patterned photoresist layer 400 are sequentially formed on the substrate, the patterned photoresist layer 400 exposing the second region II.

[0081] Detailed, such as Figure 10 As shown, a stress layer 310 is first formed on the substrate surface using a deposition process. The stress layer 310 covers the surfaces of the first capping layer and the first spacer wall 230, as well as the surfaces of the second capping layer and the second spacer wall 240. The stress layer 310 is a silicon nitride layer with a thickness of 100 Å to 150 Å. Then, a polycrystalline silicon layer 320 with a thickness of 100 Å is formed on the stress layer 310 using a deposition process. Figure 11 As shown, a patterned photoresist layer 400 is then formed, the patterned photoresist layer 400 having an opening that exposes the substrate surface of the second region II.

[0082] Please see Figure 11 Next, step S20 is executed, using the patterned photoresist layer 400 as a mask, to perform the first ion implantation process to form NOMS source / drain structures on both sides of the gate structure in the second region II, and to dope boron in the polysilicon layer 320 in the second region II.

[0083] This step specifically includes:

[0084] In the first step, at the opening, using the patterned photoresist layer 400 as a mask, N-type ions are implanted into the substrates on both sides of the second gate structure 220 and the second spacer wall 240 to form a second highly doped region 109, thereby forming a NOMS source / drain structure.

[0085] The implantation energy of the N-type ions is 20 keV to 30 keV, allowing the implanted ions to penetrate the polysilicon layer 320, stress layer 310, and bottom oxide layer 120 to reach a predetermined position on the substrate, thereby forming a second highly doped region 109. The N-type ions include, but are not limited to, phosphorus and arsenic. The implantation concentration of the N-type ions is 1.5E15 atoms / cm³. 2 ~2.5E15 atoms / cm 2 In this embodiment, the second highly doped region 109 extends downward from the substrate surface of the second well region 102 to below the second low-doped region 106, such that the second highly doped region 109 partially overlaps with the second low-doped region 106, and the lower part of the second highly doped region 109 extends below the second low-doped region 106.

[0086] The second step is to use the patterned photoresist layer 400 as a mask at the opening to dope boron ions in the polysilicon layer 320, so that the doping type in the polysilicon layer 320 of the second region II changes, that is, from N-type ions to P-type boron ions, and the etching rate of the boron-doped polysilicon layer 320 decreases, or even decreases to 0.

[0087] The implantation energy of the boron ions is less than 10 keV, preferably 2 keV to 5 keV, so as to dope boron ions only in the polysilicon layer 320 at a very shallow location. The implantation concentration of the boron ions is 1E15 atoms / cm². 2 ~2E15 atoms / cm 2 .

[0088] Please see Figures 12-13 Next, step S30 is performed to remove the photoresist layer 400, and the polysilicon layer 320 and stress layer 310 of the first region I are removed without a mask.

[0089] This step specifically includes:

[0090] First, such as Figure 12 As shown, the remaining photoresist layer 400 is removed.

[0091] Next, as Figure 13 As shown, the polysilicon layer 320 in the first region I is wet-etched using TMAH solution until the stress layer 310 in the first region I is exposed. In this step, the etch rate of the polysilicon layer 320 in the first region I is greater than 3000 Å / min during the wet etching process, while the polysilicon layer 320 in the second region II is doped with boron ions. Since the etch rate in the second region II is close to 0 during the wet etching process, the polysilicon layer 320 in the second region II is not consumed and remains.

[0092] Next, the stress layer 310 of the first region I is wet-etched using a phosphoric acid solution until the bottom oxide layer 120 of the first region I is exposed. In this step, the stress layer 310 of the second region II is protected by the polysilicon layer 320 of that region, and the polysilicon layer 320 of the second region II is not etched. Therefore, both the stress layer 310 and the polysilicon layer 320 of the second region II are preserved.

[0093] Please see Figure 14 Then, step S40 is executed to perform a second ion implantation process without a mask, so as to form POMS source and drain structures on both sides of the gate structure of the first region I.

[0094] In detail, without a mask, P-type ions are implanted into the substrate to form a first highly doped region 110 in the substrate on both sides of the first gate structure 210 and the first spacer wall 230, thereby forming a POMS source / drain structure.

[0095] The implantation energy of the P-type ions is 8 keV to 12 keV, so that the implanted ions can penetrate the bottom oxide layer 120 on the surface and reach the preset position of the substrate, thereby forming the first highly doped region 110.

[0096] In this embodiment, the first highly doped region 110 extends downward from the substrate surface to below the first low-doped region 103 in the first region I, such that the first highly doped region 110 partially overlaps with the second low-doped region 106, and the lower part of the first highly doped region 110 extends below the first low-doped region 103.

[0097] In this step, the boron-doped polysilicon layer 320 and stress layer 310 retained on the second region II together act as a barrier layer to prevent P-type ions from implanting into the substrate of the second region. Furthermore, the second source / drain structure of the second region II, protected by the upper boron-doped polysilicon layer 320, stress layer 310, and second capping layer, prevents P-type ions from implanting into the second source / drain structure of the second region II, thereby ensuring that P-type ions are only implanted into the substrates on both sides of the first gate structure 210 of the first region I.

[0098] Please see Figures 15-16 Next, step S50 is executed to remove the polysilicon layer 320 of the second region II and perform the SMT process.

[0099] This step specifically includes:

[0100] First, such as Figure 15As shown, a dry etching process is used to selectively etch the polysilicon layer 320 in the second region II, exposing the stress layer 310 in the second region II. In this step, hydrogen gas is introduced into the reaction chamber during the dry etching process, and the selective etching in this step only removes the polysilicon layer 320 in the first region I.

[0101] Next, an annealing process is performed, which can maintain the channel tensile stress after the stress layer 310 is removed, thereby increasing the electron mobility of the NMOS transistor by 20%-30% and the drive current by 10%-20%. The process temperature during annealing is 900℃~1050℃.

[0102] Next, as Figure 16 As shown, the stress layer 310 of the second region II is etched using a phosphoric acid solution wet etching process until the bottom oxide layer 120 of the second region II is exposed.

[0103] Please continue reading. Figure 16 This embodiment also provides a semiconductor device, including a substrate, the substrate including a first region I and a second region II, a gate structure is formed on the substrate of both the first region I and the second region II, a POMS source-drain structure is formed on both sides of the gate structure of the first region I, and a NOMS source-drain structure is formed on both sides of the gate structure of the second region II.

[0104] In summary, this invention provides a semiconductor device and its fabrication method. The fabrication method includes the following steps: providing a substrate, the substrate comprising a first region and a second region, wherein a gate structure is formed on both the first and second regions of the substrate; sequentially forming a stress layer, a polysilicon layer, and a patterned photoresist layer on the substrate, the patterned photoresist layer exposing the second region; using the patterned photoresist layer as a mask, performing a first ion implantation process to form NOMS source / drain structures on both sides of the gate structure in the second region, and doping boron in the polysilicon layer of the second region; removing the photoresist layer, and removing the polysilicon layer and stress layer of the first region without a mask; performing a second ion implantation process without a mask to form POMS source / drain structures on both sides of the gate structure in the first region; removing the polysilicon layer of the second region and performing an SMT process. This invention requires only one photomask and one independent photolithography step, greatly reducing the complexity and time cost of the process, and also significantly reducing the overall manufacturing cost.

[0105] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0106] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, the substrate including a first region and a second region, a gate structure is formed on the substrate in both the first region and the second region, and a stress layer, a polysilicon layer and a patterned photoresist layer are sequentially formed on the substrate, the patterned photoresist layer exposing the second region; Using the patterned photoresist layer as a mask, a first ion implantation process is performed to form NOMS source / drain structures on both sides of the gate structure in the second region, and boron is doped into the polysilicon layer in the second region. Remove the photoresist layer, and remove the polysilicon layer and stress layer in the first region without a mask; A second ion implantation process is performed without a mask to form POMS source / drain structures on both sides of the gate structure in the first region. Remove the polysilicon layer in the second region and perform the SMT process.

2. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The specific method for forming NOMS source / drain structures on both sides of the gate structure in the second region and doping boron in the polysilicon layer of the second region is as follows: Using the patterned photoresist layer as a mask, N-type ions are implanted into the substrate on both sides of the gate structure and the second gap wall in the second region to form a second highly doped region, thereby forming a NOMS source-drain structure. Using the patterned photoresist layer as a mask, boron ions are doped into the polycrystalline silicon layer.

3. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The N-type ions include phosphorus and arsenic.

4. The method for fabricating a semiconductor device as described in claim 2, characterized in that, The implantation energy of the N-type ions is 20 keV ~ 30 keV, and the implantation concentration is 1.5E15 atoms / cm³. 2 ~2.5E15 atoms / cm 2 ; The boron ion implantation energy is less than 10 keV, and the implantation concentration is 1E15 atoms / cm². 2 ~2E15 atoms / cm 2 .

5. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The specific method for removing the polysilicon layer and stress layer in the first region without a mask is as follows: The polysilicon layer in the first region was removed using a wet method with TMAH solution. The stress layer in the first region was removed using a wet method with a phosphoric acid solution.

6. The method for fabricating a semiconductor device as described in claim 1, characterized in that, When the second ion implantation process is performed under the maskless condition, the boron-doped polysilicon layer and the stress layer retained on the second region together serve as a barrier layer to prevent P-type ions from implanting into the substrate of the second region.

7. The method for fabricating a semiconductor device as described in claim 1, characterized in that, In the second ion implantation process, P-type ions were implanted, and the implantation energy of the P-type ions was 8 keV to 12 keV.

8. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The specific method for removing the polysilicon layer in the second region is as follows: The polysilicon layer in the second region is selectively etched using a dry etching process, thereby exposing the stress layer in the second region. In the dry etching process, the reaction gas introduced into the reaction chamber is hydrogen.

9. The method for fabricating a semiconductor device as described in claim 1, characterized in that, The specific method for performing SMT (Surface Mount Technology) is as follows: Perform the annealing process; The stress layer in the second region was removed using a wet method with a phosphoric acid solution.

10. A semiconductor device, characterized in that, It is prepared by the method of preparing a semiconductor device as described in any one of claims 1 to 9.

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