Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a lower transistor including a lower channel structure and a lower source / drain structure connected to the lower channel structure; and an upper transistor over the lower transistor, the upper transistor including an upper channel structure and an upper source / drain structure connected to the upper channel structure, in which a portion of the upper channel structure overlaps the lower channel structure in the vertical direction and another portion of the upper channel structure does not overlap the lower channel structure in the vertical direction.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device in which the lower channel structure and the upper channel structure are offset from each other, and a method for manufacturing the semiconductor device. Background Technology

[0002] There is a need for transistors with reduced size to increase the density of logic devices in integrated circuits. To increase transistor density within a limited space on a substrate, semiconductor devices with multi-stack structures are being developed, in which transistors are formed in both a lower stack and an upper stack. The above information is presented as related technology to aid in understanding this disclosure. Summary of the Invention

[0003] An exemplary embodiment of this disclosure provides a semiconductor device and a method for manufacturing the same, in which the lower channel structure of a lower transistor and the upper channel structure of an upper transistor are horizontally offset, thereby providing space in a high-density footprint for contact structures connected to the upper portion of the lower source / drain structure of the lower transistor and the lower portion of the upper source / drain structure of the upper transistor.

[0004] However, the improvements achieved through the exemplary embodiments of this disclosure are not limited to those described above, and additional improvements not mentioned above may also be achieved.

[0005] According to one aspect of this disclosure, a semiconductor device is provided, the semiconductor device comprising: a lower transistor including a lower channel structure and a lower source / drain structure connected to the lower channel structure; and an upper transistor above the lower transistor, the upper transistor including an upper channel structure and an upper source / drain structure connected to the upper channel structure, wherein a portion of the upper channel structure overlaps with the lower channel structure in a vertical direction, and another portion of the upper channel structure does not overlap with the lower channel structure in a vertical direction.

[0006] According to one aspect of this disclosure, a semiconductor device is provided, which may include: a lower transistor including a lower channel structure and a lower source / drain structure connected to the lower channel structure; and an upper transistor above the lower transistor, the upper transistor including an upper channel structure and an upper source / drain structure connected to the upper channel structure, wherein the side surfaces of the lower channel structure and the vertically corresponding side surfaces of the upper channel structure are offset from each other in the horizontal direction.

[0007] According to another aspect of this disclosure, a method for manufacturing a semiconductor device is provided. The method may include: forming a lower transistor such that the lower transistor includes a lower channel structure and a lower source / drain structure connected to the lower channel structure; and forming an upper transistor above the lower transistor such that the upper transistor includes an upper channel structure and an upper source / drain structure connected to the upper channel structure, wherein the lower channel structure and the upper channel structure are formed such that a portion of the upper channel structure overlaps with the lower channel structure in a vertical direction, and another portion of the upper channel structure does not overlap with the lower channel structure in a vertical direction. Attached Figure Description

[0008] These and / or other aspects, features, and advantages of certain embodiments of this disclosure will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 It is a front perspective view showing a portion of a semiconductor device according to one or more embodiments;

[0010] Figure 2 This illustrates one or more embodiments. Figure 1 A rear perspective view of a portion of a semiconductor device;

[0011] Figure 3 It is according to one or more embodiments along Figure 1 A sectional view taken by line A-A';

[0012] Figure 4 It is according to one or more embodiments along Figure 2 A sectional view taken by line B-B';

[0013] Figure 5 It is according to one or more embodiments along Figure 2 A sectional view taken by line C-C';

[0014] Figure 6 It is a schematic diagram of an inverter circuit formed of semiconductor devices according to one or more embodiments;

[0015] Figure 7 It is a cross-sectional view showing a portion of a semiconductor device according to one or more embodiments;

[0016] Figure 8 It is a cross-sectional view showing a portion of a semiconductor device according to one or more embodiments;

[0017] Figure 9 It is a flowchart of a method for manufacturing a semiconductor device according to one or more embodiments; and

[0018] Figures 10 to 18 These are sequential cross-sectional views of a stacked die structure, illustrating the process of manufacturing a semiconductor device according to one or more embodiments. Detailed Implementation

[0019] In the following, embodiments will be described in detail with reference to the accompanying drawings. The embodiments described herein are non-limiting exemplary embodiments, and therefore, this disclosure is not limited thereto and may be implemented in various other forms. When describing embodiments with reference to the accompanying drawings, the same reference numerals refer to the same parts, and any repetitive descriptions associated with them will be omitted.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. It will also be understood that the terms “comprising / including…” and / or “including / including…” as used herein specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments pertain. Terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant art and the context of this disclosure, and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined herein.

[0022] When describing embodiments with reference to the accompanying drawings, the same reference numerals refer to the same parts, and redundant descriptions related to them will be omitted. In the description of embodiments, detailed descriptions of well-known related structures or functions will be omitted when such descriptions are thought to lead to a vague interpretation of this disclosure.

[0023] Furthermore, in the description of components, when describing components of this disclosure, terms such as first, second, A, B, (a), (b), etc., may be used herein. These terms are used only to distinguish one component from another, and the nature, order, or sequence of the components is not limited by these terms. It should be noted that if a component is described as "connected," "joined," or "joined" to another component, the former may be directly "connected," "joined," or "joined" to the latter, or may be "connected," "joined," or "joined" to the latter via another component.

[0024] The same names can be used to describe the elements included in the above embodiments and elements with common functions. Unless otherwise stated, the description of the examples is applicable to the following examples, therefore, for the sake of brevity, redundant descriptions will be omitted.

[0025] Figure 1 It is a front perspective view showing a portion of a semiconductor device according to one or more embodiments. Figure 2 This illustrates one or more embodiments. Figure 1 A rear perspective view of a portion of a semiconductor device.

[0026] Reference Figure 1 and Figure 2 The semiconductor device 10 according to one or more embodiments may include one or more transistor stacks ST formed on a substrate 100. The transistor stack ST may be formed as a structure in which a pair of transistors (e.g., lower transistor 200 and upper transistor 300) are stacked in a vertical direction D3. In the following description... Figure 1 and Figure 2 For ease of description, a transistor stack ST will be used as an example to describe the semiconductor device 10. In the illustrated embodiment, the first horizontal direction D1 and the second horizontal direction D2 are horizontal directions parallel to and perpendicular to each other on the top surface of the substrate 100. The vertical direction D3 is a direction perpendicular to the first horizontal direction D1 and the second horizontal direction D2. Furthermore, it will be apparent to those skilled in the art that in... Figure 1 and Figure 2 The areas shown as empty spaces can be filled with insulators, air gaps, or other structures that can be positioned within them.

[0027] The semiconductor device 10 according to one or more embodiments may include a substrate 100, a transistor stack ST formed on the substrate 100, a lower wiring 110, an upper wiring 500, and a plurality of contact structures (e.g., Figure 3 First contact structure 610 Figure 3 The second contact structure 620 Figure 5 The third contact structure 630 and Figure 4 The fourth contact structure 640). The substrate 100 can be a bulk substrate formed of a semiconductor material, such as silicon (Si), silicon germanium (SiGe), or silicon-on-insulator (SOI) substrate. Optionally, the substrate 100 can be an insulating substrate comprising an insulating material. For example, the insulating substrate may include at least one of silicon oxide, silicon nitride, silicon oxide nitride, silicon carbide, and any other low-k dielectric material. However, this is an example, and the type of substrate 100 is not limited thereto.

[0028] A transistor stack ST may include a lower transistor 200, an intermediate insulating layer 400, and an upper transistor 300. The lower transistor 200 may be positioned on a substrate 100. The upper transistor 300 may be positioned above the lower transistor 200. The intermediate insulating layer 400 may be positioned between the lower transistor 200 and the upper transistor 300. In one example transistor stack ST, the lower transistor 200 may be an n-type field-effect transistor (nFET), and the upper transistor 300 may be a p-type field-effect transistor (pFET). In another example transistor stack ST, the lower transistor 200 may be a pFET, and the upper transistor 300 may be an nFET. In yet another example transistor stack ST, the lower transistor 200 and the upper transistor 300 may each be either a pFET or an nFET.

[0029] The lower wiring 110 can be positioned below the lower transistor 200. Multiple lower wirings 110 can be provided. These multiple lower wirings 110 can extend in a first horizontal direction D1 and can be spaced apart from each other in a second horizontal direction D2. The number of lower wirings 110 shown in the figures is an example, and the number of lower wirings 110 is not limited thereto. For example, the multiple lower wirings 110 may include at least a first lower wiring (e.g., ...). Figure 3 111) and the second wiring (e.g. Figure 3 (112).

[0030] For example, the lower wiring 110 can be a wire for transmitting power. For example, the lower wiring 110 can be a power line 110, which may include a first power line (e.g., Figure 3 111) and the second power line (e.g. Figure 3 (112). As another example, one of the plurality of lower wirings 110 may be a signal line connected to another circuit element for transmitting signals (rather than to a voltage source), while the other lower wirings are power lines connected to the respective voltage sources. As yet another example, all of the plurality of lower wirings 110 may be signal lines. In the following description, the lower wirings 110 (which are power lines 110) will be used as the basis.

[0031] The power lines 110 can be formed as a back-side power transmission network (BSPDN) structure. For example, the power lines 110 can be formed in the substrate 100. For example, the substrate 100 may include a first lower insulating layer 101 and a second lower insulating layer 102 stacked on the first lower insulating layer 101, and multiple power lines 110 can be formed in the first lower insulating layer 101. However, this is just an example, and the structure of the substrate 100 is not limited to this.

[0032] The upper wiring 500 can be positioned on the opposite side of the substrate 100 in the vertical direction D3 based on the transistor stack ST. The upper wiring 500 can be positioned above the upper transistor 300. Multiple upper wirings 500 can be provided. Multiple upper wirings 500 can extend in a first horizontal direction D1 and can be spaced apart from each other in a second horizontal direction D2. The number of upper wirings 500 shown in the figures is an example, and the number of upper wirings 500 is not limited thereto. For example, the multiple upper wirings 500 can include at least a first upper wiring (e.g., Figure 5 510) and the second wiring (e.g. Figure 4 (520).

[0033] For example, the upper wiring 500 can be a line used for transmitting signals. For example, the upper wiring 500 can be a signal line 500, which may include a first signal line (e.g., Figure 5 510) and the second signal line (e.g. Figure 4 (520). However, as another example, at least one of the upper wirings 500 may be a power line. As yet another example, all of the plurality of upper wirings 500 may be power lines. In the following description, the upper wirings 500 (which are signal lines 500) will be provided.

[0034] Power lines 110 and signal lines 500 can be positioned opposite each other in the vertical direction D3, with a transistor stack ST between them. For example, power line 110 can be positioned below the transistor stack ST, and signal line 500 can be formed above the transistor stack ST in the vertical direction D3. By separating the positions of power lines 110 and signal lines 500 connected to a transistor stack ST in the vertical direction D3, the area required in the horizontal direction (e.g., a second horizontal direction D2) for connecting power lines 110 and signal lines 500 to the transistor stack ST can be reduced.

[0035] Figure 3 It is according to one or more embodiments along Figure 1 A sectional view taken by line A-A'. Figure 4 It is according to one or more embodiments along Figure 2 The sectional view taken by line B-B'. Figure 5 It is according to one or more embodiments along Figure 2 A sectional view taken by line C-C'.

[0036] In the following text, reference will be made to Figures 1 to 5 Components of a semiconductor device 10 according to one or more embodiments are described.

[0037] The lower transistor 200 may include a plurality of lower channel layers 210 as a channel structure, a plurality of lower gate insulating layers 220, a lower gate structure 230, a first lower source / drain structure 240 and a second lower source / drain structure 250.

[0038] The plurality of lower channel layers 210 can serve as current flow channels for the lower transistor 200. For example, the plurality of lower channel layers 210 may comprise silicon (Si). For example, the lower channel layers 210 may be formed as nanosheets. The plurality of lower channel layers 210 may be spaced apart from each other in the vertical direction D3. For example, the plurality of lower channel layers 210 may have substantially the same width (e.g., width in the second horizontal direction D2). For example, the plurality of lower channel layers 210 may be aligned with each other in the vertical direction D3. The number and / or width of the lower channel layers 210 shown in the figures are examples, and the number and / or width of the lower channel layers 210 are not limited thereto.

[0039] Each lower channel layer 210 may be surrounded by a lower gate insulating layer 220. The lower gate insulating layer 220 may be formed on the bottom surface, top surface, and two side surfaces of each lower channel layer 210. The lower gate insulating layer 220 may include an insulating material. For example, the lower gate insulating layer 220 may include silicon oxide (SiO), silicon nitride (SiN), silicon nitride oxide (SiON), and / or a high-k material with a higher dielectric constant than silicon oxide, but is not limited thereto. The high-k material may include one or more of, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, and zirconium silicon oxide.

[0040] The lower gate structure 230 may surround the plurality of lower channel layers 210. The lower gate structure 230 may extend in a first horizontal direction D1 and a second horizontal direction D2. The lower gate structure 230 may include a conductive material. For example, the lower gate structure 230 may be formed of a plurality of films including a work function metal film and a gate electrode film. For example, the work function metal film may include titanium (Ti), tantalum (Ta), or compounds thereof, and the gate electrode film may include copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), ruthenium (Ru), or compounds thereof. However, this is an example, and the materials included in the lower gate structure 230 are not limited thereto.

[0041] The first lower source / drain structure 240 and the second lower source / drain structure 250 can be respectively connected to two ends of the plurality of lower channel layers 210 in the first horizontal direction D1. For example, the first lower source / drain structure 240 can be connected to one lateral portion of the plurality of lower channel layers 210 in the first horizontal direction D1 (e.g., the portion in the +D1 direction), and the second lower source / drain structure 250 can be connected to another lateral portion of the plurality of lower channel layers 210 in the first horizontal direction D1 (e.g., the portion in the -D1 direction). The plurality of lower channel layers 210 can extend in the first horizontal direction D1 between the first lower source / drain structure 240 and the second lower source / drain structure 250. The first lower source / drain structure 240 and the second lower source / drain structure 250 can be obtained by epitaxial growth from the plurality of lower channel layers 210. When the semiconductor device 10 is observed in the first horizontal direction D1, the first lower source / drain structure 240 and the second lower source / drain structure 250 can be formed at positions corresponding to the plurality of lower channel layers 210. The first lower source / drain structure 240 and the second lower source / drain structure 250 can each be connected to the power line 110 or the signal line 500.

[0042] The upper transistor 300 may include a plurality of upper channel layers 310 as a channel structure, a plurality of upper gate insulating layers 320, an upper gate structure 330, a first upper source / drain structure 340 and a second upper source / drain structure 350.

[0043] The plurality of upper channel layers 310 can serve as current flow channels for the upper transistor 300. For example, the plurality of upper channel layers 310 may comprise silicon (Si). For example, the upper channel layers 310 may be formed as nanosheets. The plurality of upper channel layers 310 may be spaced apart from each other in the vertical direction D3. For example, the plurality of upper channel layers 310 may have substantially the same width (e.g., width in the second horizontal direction D2). For example, the plurality of upper channel layers 310 may be aligned with each other in the vertical direction D3. The number of upper channel layers 310 and the number of lower channel layers 210 may be the same or different. For example, the upper channel layers 310 may be formed to have a narrower width in the second horizontal direction D2 than the lower channel layers 210, while the number of upper channel layers 310 is greater than the number of lower channel layers 210, and the lower channel layers 210 and the upper channel layers 310 have the same height. This structure of the lower channel layer 210 and the upper channel layer 310 can be implemented to achieve the same effective channel width (i.e., the sum of the channel widths) in each of the lower transistor 200 and the upper transistor 300, such that the two transistors can have the same device performance in terms of the amount of current flowing per unit time. However, this is just an example; the upper channel layer 310 and the lower channel layer 210 can have substantially the same width or similar widths in the second horizontal direction D2 to realize semiconductor devices in which the lower transistor 200 and the upper transistor 300 have different channel performances. The number and / or width of the upper channel layer 310 shown in the figures are illustrative, and the number and / or width of the upper channel layer 310 are not limited thereto.

[0044] Each upper channel layer 310 may be surrounded by an upper gate insulating layer 320. The upper gate insulating layer 320 may be formed on the bottom surface, top surface, and two side surfaces of each upper channel layer 310. The upper gate insulating layer 320 may include an insulating material. For example, the upper gate insulating layer 320 may include silicon oxide (SiO), silicon nitride (SiN), silicon nitride oxide (SiON), and / or a high-k material having a higher dielectric constant than silicon oxide, but is not limited thereto. The high-k material may include one or more of, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, and zirconium silicon oxide.

[0045] The upper gate structure 330 may surround the plurality of upper channel layers 310. The upper gate structure 330 may extend in a first horizontal direction D1 and a second horizontal direction D2. The upper gate structure 330 may include a conductive material. For example, the upper gate structure 330 may be formed of a plurality of films including a work function metal film and a gate electrode film. For example, the work function metal film may include titanium (Ti), tantalum (Ta), or compounds thereof, and the gate electrode film may include copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), ruthenium (Ru), or compounds thereof. However, this is an example, and the materials included in the upper gate structure 330 are not limited thereto. The upper gate structure 330 and the lower gate structure 230 may include different materials depending on the work function.

[0046] The upper gate structure 330 may be stacked above the lower gate structure 230. An intermediate insulating layer 400 may be positioned between the upper gate structure 330 and the lower gate structure 230. For example, the upper gate structure 330 and the lower gate structure 230 may be separated by the intermediate insulating layer 400. The intermediate insulating layer 400 may include an insulating material. For example, the intermediate insulating layer 400 may be formed of silicon oxide (SiO), silicon nitride (SiN), and / or silicon oxide nitride (SiON), but is not limited thereto. The upper gate structure 330 and the lower gate structure 230 may be electrically connected to each other via a separate structure (e.g., an interconnect) not shown.

[0047] The first source / drain structure 340 and the second source / drain structure 350 can be respectively connected to two ends of the plurality of upper channel layers 310 in the first horizontal direction D1. For example, the first source / drain structure 340 can be connected to one lateral portion of the plurality of upper channel layers 310 in the first horizontal direction D1 (e.g., the portion in the +D1 direction), and the second source / drain structure 350 can be connected to another lateral portion of the plurality of upper channel layers 310 in the first horizontal direction D1 (e.g., the portion in the -D1 direction). The plurality of upper channel layers 310 can extend in the first horizontal direction D1 between the first source / drain structure 340 and the second source / drain structure 350. The first source / drain structure 340 and the second source / drain structure 350 can be obtained by epitaxial growth from the plurality of upper channel layers 310. When the semiconductor device 10 is observed in the first horizontal direction D1, the first upper source / drain structure 340 and the second upper source / drain structure 350 can be formed at positions corresponding to the plurality of upper channel layers 310. The first upper source / drain structure 340 and the second upper source / drain structure 350 can each be connected to the power line 110 or the signal line 500.

[0048] In a transistor stack ST, such as Figure 4As shown, the plurality of lower channel layers 210 and the plurality of upper channel layers 310 can be positioned offset from each other in a second horizontal direction D2. Here, offset can refer to a misaligned and skewed state. For example, as Figure 4 As shown, the plurality of lower channel layers 210 may be offset relative to the plurality of upper channel layers 310 in the -D2 direction. Alternatively, as another example, the plurality of lower channel layers 210 may be offset relative to the plurality of upper channel layers 310 in the +D2 direction.

[0049] The virtual vertical centerlines of the plurality of lower channel layers 210 and the plurality of upper channel layers 310 may be misaligned with each other in the vertical direction D3. The plurality of lower channel layers 210 and the plurality of upper channel layers 310 may only partially overlap in the vertical direction D3. For example, a portion of the plurality of upper channel layers 310 (e.g., a portion in the -D2 direction) may overlap with the plurality of lower channel layers 210 in the vertical direction D3, while another portion of the plurality of upper channel layers 310 (e.g., a portion in the +D2 direction) may not overlap with the plurality of lower channel layers 210 in the vertical direction D3. As another example, a portion of the plurality of lower channel layers 210 (e.g., a portion in the +D2 direction) may overlap with the plurality of upper channel layers 310 in the vertical direction D3, while another portion of the plurality of lower channel layers 210 (e.g., a portion in the -D2 direction) may not overlap with the plurality of upper channel layers 310 in the vertical direction D3.

[0050] A lateral end (e.g., an end in the +D2 direction) of the plurality of lower channel layers 210 in the second horizontal direction D2 and a lateral end (e.g., an end in the +D2 direction) of the plurality of upper channel layers 310 in the second horizontal direction D2 may be misaligned with each other in the vertical direction D3. For example, the lateral end (e.g., an end in the +D2 direction) of the plurality of upper channel layers 310 in the second horizontal direction D2 may be positioned to protrude more in the +D2 direction than the lateral end (e.g., an end in the +D2 direction) of the plurality of lower channel layers 210 in the second horizontal direction D2. The lateral end (e.g., an end in the +D2 direction) of the plurality of lower channel layers 210 in the second horizontal direction D2 may overlap with the plurality of upper channel layers 310 in the vertical direction D3.

[0051] The other lateral ends of the plurality of lower channel layers 210 in the second horizontal direction D2 (e.g., the ends in the -D2 direction) and the other lateral ends of the plurality of upper channel layers 310 in the second horizontal direction D2 (e.g., the ends in the -D2 direction) may be misaligned with each other in the vertical direction D3. For example, the other lateral ends of the plurality of lower channel layers 210 in the second horizontal direction D2 (e.g., the ends in the -D2 direction) may be positioned to protrude more in the -D2 direction than the other lateral ends of the plurality of upper channel layers 310 in the second horizontal direction D2 (e.g., the ends in the -D2 direction). The other lateral ends of the plurality of upper channel layers 310 in the second horizontal direction D2 (e.g., the ends in the -D2 direction) may overlap with the plurality of lower channel layers 210 in the vertical direction D3.

[0052] When the plurality of lower channel layers 210 and the plurality of upper channel layers 310 in a transistor stack ST are positioned offset from each other in the second horizontal direction D2, the first lower source / drain structure 240 and the first upper source / drain structure 340 can also be positioned offset from each other in the second horizontal direction D2 (see...). Figure 3 The second lower source / drain structure 250 and the second upper source / drain structure 350 can also be positioned offset from each other in the second horizontal direction D2 (see...). Figure 5 For example, such as Figure 3 As shown, the first lower source / drain structure 240 (e.g., its left edge or surface and right edge or surface) can be offset relative to the first upper source / drain structure 340 (e.g., its left edge or surface and right edge or surface) in the -D2 direction. As another example, such as... Figure 5 As shown, the second lower source / drain structure 250 (e.g., its left edge or surface and right edge or surface) can be offset relative to the second upper source / drain structure 350 (e.g., its left edge or surface and right edge or surface) in the -D2 direction. Additionally, as yet another example, the first lower source / drain structure 240 can be offset relative to the first upper source / drain structure 340 in the +D2 direction, and the second lower source / drain structure 250 can be offset relative to the second upper source / drain structure 350 in the +D2 direction.

[0053] The plurality of contact structures (610, 620, 630, and 640) can connect the lower transistor 200 and / or the upper transistor 300 to the power line 110 and / or the signal line 500. Each of the plurality of contact structures (610, 620, 630, and 640) may include a conductive material. For example, each of the plurality of contact structures (610, 620, 630, and 640) may be formed of a metallic material (such as cobalt (Co), tungsten (W), ruthenium (Ru), or combinations thereof), but is not limited thereto.

[0054] The plurality of contact structures (610, 620, 630 and 640) may include a first contact structure 610, a second contact structure 620, a third contact structure 630 and a fourth contact structure 640.

[0055] Reference Figure 3 The first contact structure 610 can connect the first upper source / drain structure 340 to the first power line 111. The first contact structure 610 can extend in the vertical direction D3 between the first upper source / drain structure 340 and the first power line 111. The first contact structure 610 can extend from the first power line 111 in the vertical direction D3 and directly contact the first upper source / drain structure 340. For example, the first contact structure 610 may include a first through-path 611 and a first contact pad 612. Each of the first through-path 611 and the first contact pad 612 may include a conductive material. For example, the conductive material may include aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), or combinations thereof. However, the conductive material is not limited to these. For example, the first through-path 611 and the first contact pad 612 may include different materials. The first through-path 611 can be formed in the vertical direction D3 and connected to the first power line 111. For example, the width of the first through-path 611 may decrease from bottom to top (e.g., in the +D3 direction). A first contact pad 612 may connect the first through-path 611 to the first upper source / drain structure 340. The first contact pad 612 may be formed to directly contact the first upper source / drain structure 340. For example, the first contact pad 612 may be connected to the lower portion of the first upper source / drain structure 340. As another example, the first contact pad 612 may be formed by extending the upper end of the first through-path 611 in the width direction. However, these are examples, and the structure of the first contact structure 610 is not limited thereto. For example, the first contact structure 610 may simply include a first through-path 611 extending from the first power line 111 in the vertical direction D3, and the first through-path 611 may directly contact the lower portion of the first upper source / drain structure 340. For example, the first contact pad 612 may contact the side surface of the first upper source / drain structure 340. Optionally, the first contact pad 612 may contact both the bottom surface and the side surface of the first upper source / drain structure 340. For example, the maximum length of the first contact pad 612 in the vertical direction D3 may be greater than the maximum length of the first contact pad 612 in the second horizontal direction D2.

[0056] Since the first upper source / drain structure 340 is positioned offset relative to the first lower source / drain structure 240 in the second horizontal direction D2, the first upper source / drain structure 340 can be directly connected to the first power line 111 via the first contact structure 610 formed in the vertical direction D3. For example, as Figure 3 As shown, when the first upper source / drain structure 340 is positioned offset relative to the first lower source / drain structure 240 in the +D2 direction, the space for forming the first contact structure 610 can be provided below the first upper source / drain structure 340. The first contact structure 610 formed in the vertical direction D3 can be formed in the lower space of the first upper source / drain structure 340 in the +D2 direction, and the first upper source / drain structure 340 can be directly connected to the first power line 111 through the first contact structure 610 having only the structure in the vertical direction D3. According to this structure, the first contact structure 610 can connect the first upper source / drain structure 340 and the first power line 111 to each other in the vertical direction D3 without requiring a separate bypass structure included in the horizontal direction (e.g., the second horizontal direction D2), and without interfering with other structures (e.g., the first lower source / drain structure 240). Since the first contact structure 610 may not be included in a separate bypass structure in the horizontal direction (e.g., the second horizontal direction D2), the pitch of the semiconductor device 10 in the horizontal direction (e.g., the second horizontal direction D2) can be further reduced, and the integration density of the semiconductor device 10 can be improved.

[0057] Reference Figure 3 The second contact structure 620 can connect the first lower source / drain structure 240 to the second power line 112. The second contact structure 620 may include a conductive material. For example, the conductive material may include aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), or combinations thereof. However, the conductive material is not limited to these. For example, the second contact structure 620 may extend from the first lower source / drain structure 240 toward the second power line 112 in the vertical direction D3. For example, the second contact structure 620 may penetrate the second lower insulating layer 102 in the vertical direction D3. For example, the width of the second contact structure 620 may decrease from top to bottom (e.g., in the -D3 direction). However, this is just an example, and the structure of the second contact structure 620 is not limited to this. For example, the second contact structure 620 may be formed as a structure including a through-path and a contact pad. For example, the width of the second contact structure 620 may increase from top to bottom (e.g., in the -D3 direction).

[0058] Reference Figure 5 The third contact structure 630 can connect the second lower source / drain structure 250 and the second upper source / drain structure 350 to the first signal line 510 positioned above the transistor stack ST. The third contact structure 630 can be positioned so that it is not connected to the first contact structure in the first horizontal direction D1. Figure 3The second contact structure 630 may include a second through-path 631, a second contact pad 632, a third contact pad 633, and a fourth contact pad 634. The second through-path 631, second contact pad 632, third contact pad 633, and fourth contact pad 634 may include conductive materials. For example, conductive materials may include aluminum (Al), tungsten (W), titanium (Ti), copper (Cu), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), or combinations thereof. However, the conductive materials are not limited to these. For example, the second through-path 631 and the second contact pad 632, third contact pad 633, or fourth contact pad 634 may include different materials. The second contact pad 632 may be formed to directly contact the second lower source / drain structure 250. The third contact pad 633 may be formed to directly contact the second upper source / drain structure 350. The fourth contact pad 634 may be formed to directly contact the first signal line 510. The second through-path 631 can be formed in the vertical direction D3 to connect to all of the second contact pad 632, the third contact pad 633, and the fourth contact pad 634. For example, the lower end of the second through-path 631 can be connected to the second contact pad 632, the lateral portion of the second through-path 631 can be connected to the third contact pad 633, and the upper end of the second through-path 631 can be connected to the fourth contact pad 634. However, this is just an example, and the structure of the third contact structure 630 is not limited to this. For example, the second through-path 631 can be formed such that the lateral portion of the second through-path 631 can directly contact the second upper source / drain structure 350 without the use of a contact pad (e.g., the third contact pad 633). For example, the second through-path 631 can be formed such that the lower end of the second through-path 631 can directly contact the second lower source / drain structure 250 without the use of a contact pad (e.g., the second contact pad 632). For example, the second through-path 631 can be configured such that the upper end of the second through-path 631 can directly contact the first signal line 510 without the use of a contact pad (e.g., the fourth contact pad 634).

[0059] Reference Figure 4The fourth contact structure 640 can connect the upper gate structure 330 to the second signal line 520 positioned above the transistor stack ST. For example, the fourth contact structure 640 can extend from the second signal line 520 toward the upper gate structure 330 in the vertical direction D3. For example, the fourth contact structure 640 can connect the second signal line 520 and the upper gate structure 330 in the vertical direction D3. For example, the width of the fourth contact structure 640 can decrease from top to bottom (e.g., in the -D3 direction). However, this is an example, and the structure of the fourth contact structure 640 is not limited to this. For example, the fourth contact structure 640 can be formed as a structure including a through-path and a contact pad. In another embodiment, the fourth contact structure 640 can be configured to connect the lower gate structure 230 to the second signal line 520. In addition, since the upper gate structure 330 and the lower gate structure 230 can be electrically connected to each other, the upper gate structure 330 and the lower gate structure 230 can be directly or indirectly electrically connected to the second signal line 520 through the fourth contact structure 640.

[0060] Figure 6 It is a schematic diagram of an inverter circuit formed of semiconductor devices according to one or more embodiments.

[0061] Reference Figure 6 Semiconductor devices according to one or more embodiments (e.g.) Figures 1 to 5 The semiconductor device 10) can form an inverter circuit. Figure 6 An inverter circuit may include a pFET and an nFET connected in series. To connect the inverter circuit to a power supply and other circuit elements, the source nodes of the pFET and nFET can be connected to a positive voltage source Vdd and a negative voltage source Vss, respectively, and the drain nodes of the pFET and nFET can be combined to connect to other circuit elements based on a common gate input signal.

[0062] Figure 6 The pFET and nFET shown can be derived from... Figures 1 to 5 The upper transistor 300 and lower transistor 200 shown are formed. For example, in Figures 1 to 5In this example, the upper transistor 300 and the lower transistor 200 can be configured as a pFET and an nFET, respectively. In this case, the first power line 111, the second power line 112, the first signal line 510, and the second signal line 520 can be understood as a positive voltage source Vdd, a negative voltage source Vss, an output line Vout, and an input line Vin, respectively. However, this is just an example; the upper transistor 300 and the lower transistor 200 can also be configured as an nFET and a pFET, respectively. In this case, the first power line 111, the second power line 112, the first signal line 510, and the second signal line 520 can be understood as a negative voltage source Vss, a positive voltage source Vdd, an output line Vout, and an input line Vin, respectively.

[0063] in addition, Figure 6 The inverter circuit shown can be a semiconductor device available according to one or more embodiments (e.g., Figures 1 to 5 Examples of various logic circuits implemented by the semiconductor device 10. For example, the semiconductor device 10 can be configured with multiple contact structures in different connections (e.g., Figure 3 First contact structure 610 Figure 3 The second contact structure 620 Figure 5 The third contact structure 630 and Figure 4 The fourth contact structure (640) is used to implement various logic circuits.

[0064] Figure 7 It is a cross-sectional view of a portion of a semiconductor device according to one or more embodiments. Figure 7 It can be in the corresponding Figure 4 A sectional view of the location.

[0065] Reference Figure 7 The semiconductor device 10 according to one or more embodiments may include a plurality of transistor stacks ST1, ST2, and ST3. Each of the plurality of transistor stacks ST1, ST2, and ST3 may include a lower transistor (e.g., Figure 4 The lower transistor 200), the intermediate insulating layer (e.g. Figure 4 The intermediate insulating layer 400) and the upper transistor (e.g. Figure 4 The plurality of transistor stacks ST1, ST2, and ST3 may be arranged side-by-side in a continuous manner along a second horizontal direction D2. A gate dicing structure 700 may be positioned between each pair of transistor stacks in the plurality of transistor stacks ST1, ST2, and ST3. The gate dicing structure 700 may isolate the plurality of transistor stacks ST1, ST2, and ST3 from each other. The gate dicing structure 700 may be formed of silicon nitride, silicon oxide, or a composite thereof, and is not limited thereto.

[0066] The plurality of transistor stacks ST1, ST2, and ST3 may, for example, have the same structural dimensions (including width in the second horizontal direction D2). However, as another example, the plurality of transistor stacks ST1, ST2, and ST3 may have different structural dimensions (including width in the second horizontal direction D2). Furthermore, the plurality of gate cut structures 700 may, for example, have the same structural dimensions (including width in the second horizontal direction D2). However, as another example, the plurality of gate cut structures 700 may have different structural dimensions (including width in the second horizontal direction D2).

[0067] like Figure 7 As shown, the plurality of transistor stacks ST1, ST2 and ST3 may, for example, include at least a first transistor stack ST1, a second transistor stack ST2 and a third transistor stack ST3. The first transistor stack ST1, the second transistor stack ST2 and the third transistor stack ST3 may be arranged side by side in a continuous manner adjacent to each other in the second horizontal direction D2.

[0068] In the plurality of transistor stacks ST1, ST2, and ST3, the transistor stacks positioned adjacent to each other can be formed symmetrically about the vertical direction D3. For example, in the plurality of transistor stacks ST1, ST2, and ST3, the transistor stacks positioned adjacent to each other can be formed symmetrically based on the gate dicing structure 700 located therebetween. For example, the first transistor stack ST1 and the second transistor stack ST2 can be formed symmetrically about the vertical direction D3. For example, the second transistor stack ST2 and the third transistor stack ST3 can be formed symmetrically about the vertical direction D3.

[0069] In the first transistor stack ST1, the directions in which the plurality of lower channel layers 210-1 and the plurality of upper channel layers 310-1 are offset from each other can be opposite to the directions in which the plurality of lower channel layers 210-2 and the plurality of upper channel layers 310-2 are offset from each other in the second transistor stack ST2. For example, as Figure 7 As shown, when the plurality of lower channel layers 210-2 in the second transistor stack ST2 are offset relative to the plurality of upper channel layers 310-2 in the +D2 direction, the plurality of lower channel layers 210-1 in the first transistor stack ST1 can be offset relative to the plurality of upper channel layers 310-1 in the -D2 direction.

[0070] Similarly, in the third transistor stack ST3, the directions in which the plurality of lower channel layers 210-3 and the plurality of upper channel layers 310-3 are offset from each other can be opposite to the directions in which the plurality of lower channel layers 210-2 and the plurality of upper channel layers 310-2 are offset from each other in the second transistor stack ST2. For example, as Figure 7As shown, when the plurality of lower channel layers 210-2 in the second transistor stack ST2 are offset relative to the plurality of upper channel layers 310-2 in the +D2 direction, the plurality of lower channel layers 210-3 in the third transistor stack ST3 can be offset relative to the plurality of upper channel layers 310-3 in the -D2 direction.

[0071] For example, the separation distance DS3 in the second horizontal direction D2 between the plurality of lower channel layers 210-1 of the first transistor stack ST1 and the plurality of lower channel layers 210-2 of the second transistor stack ST2 can be smaller than the separation distance DS1 in the second horizontal direction D2 between the plurality of upper channel layers 310-1 of the first transistor stack ST1 and the plurality of upper channel layers 310-2 of the second transistor stack ST2. For example, the separation distance DS4 in the second horizontal direction D2 between the plurality of lower channel layers 210-2 of the second transistor stack ST2 and the plurality of lower channel layers 210-3 of the third transistor stack ST3 can be greater than the separation distance DS2 in the second horizontal direction D2 between the plurality of upper channel layers 310-2 of the second transistor stack ST2 and the plurality of upper channel layers 310-3 of the third transistor stack ST3. For example, the separation distance DS1 in the second horizontal direction D2 between the plurality of upper channel layers 310-1 of the first transistor stack ST1 and the plurality of upper channel layers 310-2 of the second transistor stack ST2 can be greater than the separation distance DS2 in the second horizontal direction D2 between the plurality of upper channel layers 310-2 of the second transistor stack ST2 and the plurality of upper channel layers 310-3 of the third transistor stack ST3. For example, the separation distance DS3 in the second horizontal direction D2 between the plurality of lower channel layers 210-1 of the first transistor stack ST1 and the plurality of lower channel layers 210-2 of the second transistor stack ST2 can be less than the separation distance DS4 in the second horizontal direction D2 between the plurality of lower channel layers 210-2 of the second transistor stack ST2 and the plurality of lower channel layers 210-3 of the third transistor stack ST3. For example, the separation distance DS1 in the second horizontal direction D2 between the plurality of upper channel layers 310-1 of the first transistor stack ST1 and the plurality of upper channel layers 310-2 of the second transistor stack ST2 can be greater than or substantially the same as the separation distance DS4 in the second horizontal direction D2 between the plurality of lower channel layers 210-2 of the second transistor stack ST2 and the plurality of lower channel layers 210-3 of the third transistor stack ST3. Similarly, the separation distance DS2 in the second horizontal direction D2 between the plurality of upper channel layers 310-2 of the second transistor stack ST2 and the plurality of upper channel layers 310-3 of the third transistor stack ST3 can be greater than or substantially the same as the separation distance DS3 in the second horizontal direction D2 between the plurality of lower channel layers 210-1 of the first transistor stack ST1 and the plurality of lower channel layers 210-2 of the second transistor stack ST2. However, this is just an example, and the respective distances between components are not limited to this.

[0072] For example, such as Figure 7As shown, a first type of transistor stack (e.g., ST1 or ST3) and a second type of transistor stack (e.g., ST2) with opposite channel layer offset directions can be alternately arranged in the second horizontal direction D2.

[0073] Here, the separation distance can refer to the horizontal distance between the right surface (or edge) of a channel layer in a transistor stack and the left surface (or edge) of a channel layer at the same horizontal level in the vertical direction in an adjacent transistor stack in the second horizontal direction. For example, the separation distance DS1 can refer to the horizontal distance between the right surface (or edge) of the uppermost channel layer in the plurality of upper channel layers 310-1 in the first transistor stack ST1 and the left surface (or edge) of the uppermost channel layer in the plurality of upper channel layers 310-2 in the second transistor stack ST2.

[0074] In the accompanying drawings, for ease of description, three transistor stacks ST1, ST2, and ST3 are shown as an example; however, those skilled in the art will readily understand that the semiconductor device 10 may include four or more transistor stacks arranged side by side in the second horizontal direction D2, and a pair of transistor stacks (e.g., ST1 and ST2 or ST2 and ST3) arranged adjacent to each other in the second horizontal direction D2 may be formed symmetrically about the vertical direction D3.

[0075] Figure 8 It is a cross-sectional view showing a portion of a semiconductor device according to one or more embodiments. Figure 8 It can be in the corresponding Figure 4 A sectional view of the location.

[0076] Reference Figure 8 In one or more embodiments, the two side surfaces of the intermediate insulating layer 400 positioned between the lower transistor 200 and the upper transistor 300, facing the second horizontal direction D2, can be formed as inclined surfaces. For example, the two side surfaces of the intermediate insulating layer 400 facing the second horizontal direction D2 can be formed to be inclined from the vertical direction or downward from the plurality of upper channel layers 310 toward the plurality of lower channel layers 210. For example, the two side surfaces of the intermediate insulating layer 400 facing the second horizontal direction D2 can be formed to be inclined downward in a direction in which the plurality of lower channel layers 210 are offset relative to the plurality of upper channel layers 310 in the second horizontal direction D2 (e.g., the -D2 direction). For example, as... Figure 8 As shown, when the plurality of lower channel layers 210 are offset relative to the plurality of upper channel layers 310 in the -D2 direction, the two side surfaces of the intermediate insulating layer 400 facing the second horizontal direction D2 can be formed to be inclined downwards. This can be understood as the intermediate insulating layer 400 (or Figure 18The two side surfaces of the intermediate insulating layer 830 in the second horizontal direction D2 are cut into inclined surfaces at an angle because the plurality of lower channel layers 210 and the plurality of upper channel layers 310 are offset from each other in the second horizontal direction D2 during the manufacturing process of the lower transistor 200, the intermediate insulating layer 400 and the upper transistor 300.

[0077] Figure 9 This is a flowchart of a method for manufacturing a semiconductor device according to one or more embodiments. Figures 10 to 18 These are sequential cross-sectional views of a stacked die structure, illustrating the process of manufacturing a semiconductor device according to one or more embodiments.

[0078] The method 90 for manufacturing a semiconductor device according to one or more embodiments can be interpreted as manufacturing a reference device. Figures 1 to 5 The method described for the semiconductor device 10.

[0079] Reference Figure 9 The method 90 for manufacturing a semiconductor device may include operations 91 of forming a stacked mold structure, 92 of forming a first through-hole region, 93 of widening the lower portion of the first through-hole region, 94 of forming a second through-hole region, and 95 of widening the upper portion of the second through-hole region. Additionally, Figure 9 This is an example, and the order of the method 90 for manufacturing a semiconductor device is not limited thereto. In one or more embodiments, the method 90 for manufacturing a semiconductor device can be in conjunction with... Figure 9 The order of operations in the examples shown may differ. At least one operation of the method 90 for manufacturing a semiconductor device may be omitted. At least two operations of the method 90 for manufacturing a semiconductor device may be performed simultaneously. At least one operation of the method 90 for manufacturing a semiconductor device may be performed repeatedly.

[0080] In the following text, reference will be made to Figures 9 to 18 Methods for manufacturing semiconductor devices are described 90.

[0081] Operation 91 can be the operation that forms the stacked module structure 800 (see...) Figure 10 ).like Figure 10 As shown, the stacked structure 800 may include a lower stacked structure 810, an intermediate sacrificial layer 830, and an upper stacked structure 820. For example, the lower stacked structure 810, the intermediate sacrificial layer 830, and the upper stacked structure 820 may be stacked sequentially in the vertical direction D3. The lower stacked structure 810 may include a plurality of lower sacrificial layers 811 and a plurality of lower channel layers 812 alternately stacked on top of each other. The upper stacked structure 820 may include a plurality of upper sacrificial layers 821 and a plurality of upper channel layers 822 alternately stacked on top of each other. The intermediate sacrificial layer 830 may be positioned between the lower stacked structure 810 and the upper stacked structure 820.

[0082] For example, the plurality of lower channel layers 812 and the plurality of upper channel layers 822 may comprise silicon (Si) material. For example, the plurality of lower sacrificial layers 811 and the plurality of upper sacrificial layers 821 may comprise silicon-germanium (SiGe) material. For example, the intermediate sacrificial layer 830 may comprise silicon-germanium (SiGe) material having a different germanium concentration than that of the plurality of lower sacrificial layers 811 and the plurality of upper sacrificial layers 821. For example, the intermediate sacrificial layer 830 may have a higher germanium concentration than the plurality of lower sacrificial layers 811 and the plurality of upper sacrificial layers 821. This difference in germanium concentration allows for selective etching of the intermediate sacrificial layer 830 relative to the lower sacrificial layers 811 and the upper sacrificial layers 821.

[0083] Operation 92 can be an operation of forming multiple first penetration regions PA1 of the penetrating stacked mold structure 800 at multiple first locations (see...). Figures 11 to 13 For example, the plurality of first positions may be spaced apart at a specified interval in the second horizontal direction D2. Figure 11 As shown, a protective insulating layer 801 and a first protective pad 802 can be formed on the stacked mold structure 800, and a plurality of first penetration regions PA1 penetrating the stacked mold structure 800 in the vertical direction D3 can be formed at the plurality of first locations by an etching process. The first penetration regions PA1 may include a first lower penetration region LPA1, a first intermediate penetration region MPA1, and a first upper penetration region UPA1. The first lower penetration region LPA1 can be understood as the region penetrating the lower stacked structure 810, the first intermediate penetration region MPA1 can be understood as the region penetrating the intermediate sacrificial layer 830, and the first upper penetration region UPA1 can be understood as the region penetrating the upper stacked structure 820. The open first penetration regions PA1 can be filled with an insulating material. Thereafter, as... Figure 12 As shown, the insulating material in the first intermediate penetration region MPA1 and the first upper penetration region UPA1 can be removed by a partial etching process. A second protective gasket 803 can then be formed on the inner walls of the first intermediate penetration region MPA1 and the first upper penetration region UPA1. Afterwards, as... Figure 13 As shown, the insulating material in the bottom of the second protective pad 803 and the first lower penetration area LPA1 can be removed by etching and / or pull-back processes.

[0084] Operation 93 could be an operation of etching the stacked structure 810 in a horizontal direction (e.g., a second horizontal direction D2) to increase the width of the lower region (e.g., the first lower penetration region LPA1) of each of the plurality of first penetration regions PA1 (see [link to relevant documentation]). Figure 14 ).like Figure 14 As shown, a portion of the lower stacked structure 810 can be removed in the horizontal direction using a horizontal etching process, thereby increasing the width of the first under-penetration region LPA1. Subsequently, as... Figure 15As shown, the second protective pad 803 can be removed, and the open first penetration area PA1 can be filled with insulating material.

[0085] Operation 94 may be an operation of forming multiple second penetration regions PA2 of the penetrating stacked mold structure 800 at multiple second positions between pairs of first positions respectively inserted in the plurality of first positions (see...). Figure 15 and Figure 16 For example, each of the plurality of second positions can be interposed between two adjacent first positions. For example, the plurality of second positions can be spaced apart at a specified interval in the second horizontal direction D2. Figure 15 As shown, the plurality of second penetration regions PA2 penetrating the stacked mold structure 800 in the vertical direction D3 can be formed at the plurality of second locations by an etching process. Each of the plurality of second penetration regions PA2 can be formed between two adjacent first penetration regions PA1. The second penetration region PA2 may include a second lower penetration region LPA2, a second intermediate penetration region MPA2, and a second upper penetration region UPA2. The second lower penetration region LPA2 can be understood as the region penetrating the lower stacked structure 810, the second intermediate penetration region MPA2 can be understood as the region penetrating the intermediate sacrificial layer 830, and the second upper penetration region UPA2 can be understood as the region penetrating the upper stacked structure 820. The open second penetration regions PA2 can be filled with insulating material. Then, as Figure 16 As shown, the insulating material in the second upper penetration region UPA2 can be removed by a partial etching process.

[0086] Operation 95 could be an operation of etching a stacked structure 820 in a horizontal direction (e.g., a second horizontal direction D2) to increase the width of the upper region (e.g., a second upper penetration region UPA2) of each of the plurality of second penetration regions PA2 (see [link to relevant documentation]). Figure 17 ).like Figure 17 As shown, a portion of the upper stacked structure 820 can be removed in the horizontal direction using a horizontal etching process, thereby increasing the width of the second upper penetration region UPA2. Then, as... Figure 18 As shown, the insulating material in the first penetration region PA1 and the second penetration region PA2 can both be removed.

[0087] Reference Figure 18 The stacked module structure 800 can be divided into multiple unit structures 840 spaced apart from each other by the first penetrating region PA1 and the second penetrating region PA2. For example, as Figure 18As shown, the plurality of unit structures 840 may be spaced apart from each other in the second horizontal direction D2. Adjacent unit structures 840 may be symmetrical about the vertical direction D3. In each of the plurality of unit structures 840, the lower stack structure 810 and the upper stack structure 820 may be positioned offset from each other in the second horizontal direction D2 based on the intermediate sacrificial layer 830. In each of the plurality of unit structures 840, the plurality of lower channel layers 812 and the plurality of upper channel layers 822 may be positioned offset from each other in the second horizontal direction D2.

[0088] Through subsequent processes, a single cell structure 840 can be formed into a transistor stack (e.g. Figure 4 (Transistor stacking ST). For example, the lower stacking structure 810 of the cell structure 840 can be formed Figure 4 The lower transistor 200 and the upper stacked structure 820 of the unit structure 840 can be formed Figure 4 The upper transistor 300. For example, the intermediate sacrificial layer 830 can be removed and then replaced to form Figure 4 The intermediate insulating layer 400. For example, the plurality of lower channel layers 812 and the plurality of upper channel layers 822 can be respectively formed Figure 4 The plurality of lower channel layers 210 and the plurality of upper channel layers 310. For example, the plurality of lower sacrificial layers 811 and the plurality of upper sacrificial layers 821 can be removed and then replaced to form, respectively. Figure 4 The lower gate structure 230 and the upper gate structure 330. For example, processes for forming source / drain structures, contact structures, power lines and / or signal lines can be further performed. For example, the separation distances DS1, DS2, DS3 and DS4 in the second horizontal direction D2 between the upper channel layer 310 and the lower channel layer 210 of the cell structure 840 can satisfy the reference. Figure 7 The dimensional relationships between the separation distances DS1, DS2, DS3 and DS4 are described.

[0089] Several implementation methods have been described above. However, it should be understood that various modifications and variations can be made to these implementation methods. For example, suitable results can be achieved if the techniques are performed in a different order, and / or if the components in the system, architecture, device, or circuit are combined in different ways and / or replaced or supplemented with other components or their equivalents.

[0090] In the above embodiments, the structural differences between the lower channel structure and the upper channel structure, as well as between the lower source / drain structure and the upper source / drain structure of the nanosheet transistor, have been described. However, this disclosure is not limited thereto, and therefore, these structural differences can be applied to other types of transistors, such as FinFETs, forksheet transistors, etc., and are not limited thereto.

[0091] Therefore, other implementations, other embodiments, and / or equivalents of the claims are within the scope of the appended claims.

[0092] This application is based on and claims priority to Korean Patent Application No. 10-2024-0076817, filed on June 13, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A lower transistor includes a lower channel structure and a lower source / drain structure connected to the lower channel structure; and An upper transistor, located above the lower transistor, includes an upper channel structure and an upper source / drain structure connected to the upper channel structure. A portion of the upper channel structure overlaps with the lower channel structure in the vertical direction, while another portion of the upper channel structure does not overlap with the lower channel structure in the vertical direction.

2. The semiconductor device of claim 1, wherein the side edges of the lower source / drain structure and the vertically corresponding side edges of the upper source / drain structure are offset from each other in the horizontal direction.

3. The semiconductor device according to claim 2, further comprising: Substrate, below the lower transistor; The lower wiring is located in the substrate; as well as The contact structure connects the upper source / drain structure to the lower wiring.

4. The semiconductor device of claim 3, wherein the contact structure extends from the lower wiring in the vertical direction and directly contacts the upper source / drain structure.

5. The semiconductor device according to claim 4, wherein the contact structure comprises: A through-path extends in the vertical direction and connects to the lower wiring; and The contact pad connects the through-path to the upper source / drain structure. The contact pad is connected to the lower part of the upper source / drain structure.

6. The semiconductor device of claim 1, wherein the semiconductor device comprises a first transistor stack, a second transistor stack, and a third transistor stack, each transistor stack comprising the lower transistor and the upper transistor. The first transistor stack, the second transistor stack, and the third transistor stack are arranged continuously in the horizontal direction.

7. The semiconductor device according to claim 6, wherein: In the first transistor stack, the lower channel structure and the upper channel structure are offset from each other in the opposite direction to the offset direction of the lower channel structure and the upper channel structure in the second transistor stack. In the third transistor stack, the lower channel structure and the upper channel structure are offset from each other in the opposite direction to the offset from each other in the second transistor stack.

8. The semiconductor device of claim 7, wherein the horizontal separation distance between the upper channel structure of the first transistor stack and the upper channel structure of the second transistor stack is greater than the horizontal separation distance between the upper channel structure of the second transistor stack and the upper channel structure of the third transistor stack.

9. The semiconductor device of claim 7, wherein the separation distance in the horizontal direction between the lower channel structure of the first transistor stack and the lower channel structure of the second transistor stack is less than the separation distance in the horizontal direction between the lower channel structure of the second transistor stack and the lower channel structure of the third transistor stack.

10. The semiconductor device of claim 7, wherein the separation distance in the horizontal direction between the lower channel structure of the first transistor stack and the lower channel structure of the second transistor stack is less than the separation distance in the horizontal direction between the upper channel structure of the second transistor stack and the upper channel structure of the third transistor stack.

11. The semiconductor device according to claim 7, wherein: The first transistor stack and the second transistor stack are symmetrical about the vertical direction, and The second transistor stack and the third transistor stack are symmetrical about the vertical direction.

12. The semiconductor device according to claim 1, further comprising: An intermediate insulating layer is located between the lower channel structure and the upper channel structure. The side surface of the intermediate insulating layer is inclined from the vertical direction.

13. A semiconductor device, comprising: A lower transistor includes a lower channel structure and a lower source / drain structure connected to the lower channel structure; and An upper transistor, located above the lower transistor, includes an upper channel structure and an upper source / drain structure connected to the upper channel structure. The side surfaces of the lower channel structure and the vertically corresponding side surfaces of the upper channel structure are offset from each other in the horizontal direction.

14. The semiconductor device according to claim 13, wherein: The lower channel structure includes multiple lower channel layers, and the upper channel structure includes multiple upper channel layers. The number of lower channel layers is less than the number of upper channel layers.

15. The semiconductor device of claim 13, wherein the width of the lower channel structure is greater than the width of the upper channel structure.

16. A method for manufacturing a semiconductor device, comprising: A lower transistor is formed such that the lower transistor includes a lower channel structure and a lower source / drain structure connected to the lower channel structure; as well as An upper transistor is formed above the lower transistor, such that the upper transistor includes an upper channel structure and an upper source / drain structure connected to the upper channel structure. The lower channel structure and the upper channel structure are configured such that a portion of the upper channel structure overlaps with the lower channel structure in the vertical direction, while another portion of the upper channel structure does not overlap with the lower channel structure in the vertical direction.

17. The method of claim 16, wherein the lower source / drain structure and the upper source / drain structure are formed such that the side edges of the lower source / drain structure and the vertically corresponding side edges of the upper source / drain structure are offset from each other in the horizontal direction.

18. The method of claim 16, further comprising: A substrate is formed, and the lower transistor is formed on the substrate; as well as A contact structure is formed that connects to the lower part of the upper channel structure.

19. The method of claim 16, further comprising: Forming a first transistor stack, a second transistor stack, and a third transistor stack, such that: Each of the first transistor stack, the second transistor stack, and the third transistor stack includes the lower transistor and the upper transistor. The first transistor stack, the second transistor stack, and the third transistor stack are arranged continuously in the horizontal direction, and The first transistor stack and the second transistor stack are symmetrical about the vertical direction, and The second transistor stack and the third transistor stack are symmetrical about the vertical direction.

20. The method of claim 16, wherein: The width of the lower channel structure is greater than the width of the upper channel structure. The lower channel structure includes multiple lower channel layers, and the upper channel structure includes multiple upper channel layers. The number of lower channel layers is less than the number of upper channel layers.

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