Semiconductor device with interconnects formed by atomic layer deposition

Abstract

The invention provides a semiconductor device assembly. The semiconductor device assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die has a first dielectric material layer and a first conductive pad disposed in a first opening of the first dielectric material layer. The second semiconductor die has a second dielectric material layer facing the first dielectric material layer, and a second conductive pad disposed in a second opening of the second dielectric material layer and corresponding to the first conductive pad. A spacer extends between the first layer of dielectric material and the second layer of dielectric material. A conductive material (e.g., by atomic layer deposition (ALD)) is disposed between the first conductive pad and the second conductive pad to implement an interconnect that electrically couples the first semiconductor die and the second semiconductor die.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor device assemblies, and more particularly to a stacked semiconductor device having interconnects formed by atomic layer deposition (ALD). BACKGROUND

[0002] Microelectronic devices generally have a die (e.g., a chip) that includes integrated circuitry with a high density of very small components. Typically, the die includes an array of bond pads that are electrically coupled to the integrated circuitry. The bond pads are external electrical contacts through which voltages, signals, etc. are transmitted to and from the integrated circuitry. After the die is formed, it is “packaged” to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to various power supply lines, signal lines, and ground lines. Conventional processes for packaging a die include electrically coupling the bond pads on the die to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the die to protect it from environmental factors (e.g., moisture, particulates, static electricity, and physical shock). BRIEF DESCRIPTION OF DRAWINGS

[0003] Figure 1 A simplified schematic cross-sectional view of a semiconductor device assembly according to embodiments of the present technology is illustrated.

[0004] Figures 2 to 6 A simplified schematic plan and cross-sectional view of a series of steps for manufacturing a semiconductor device assembly according to embodiments of the present technology is illustrated.

[0005] Figure 7 A simplified schematic cross-sectional view of a semiconductor device assembly according to embodiments of the present technology is illustrated.

[0006] Figure 8 A schematic diagram of a system including a semiconductor device assembly configured according to embodiments of the present technology is illustrated.

[0007] Figure 9 A method of manufacturing a semiconductor device assembly according to embodiments of the present technology is illustrated. DETAILED DESCRIPTION

[0008] Computing devices often include semiconductor devices to implement processors, memory, or other functional features. Semiconductor devices can be stacked to increase the number of circuit elements implemented within a device without increasing the device footprint. Many stacked semiconductor devices utilize hybrid bonding to form vertical interconnects. Hybrid bonding utilizes the volume expansion of a conductive material, such as copper, to form a vertical interconnect through an opening in a layer of bonded dielectric material. For example, two semiconductor dies can be aligned such that a conductive pad in an opening of a layer of dielectric material positioned on one of the semiconductor dies is aligned with a conductive pad in an opening of a layer of dielectric material positioned on the other semiconductor die. The layers of dielectric material at each of the semiconductor dies can be bonded, and the conductive pads can be heated, thereby causing them to expand toward each other.

[0009] Ideally, the conductive pads expand and a metal-metal interconnect is formed within the bonded layer of dielectric material through diffusion. However, in other cases, the spacing between the conductive pads, which can result from a difficult to control chemical-mechanical planarization (CMP) process, can result in under-expanded or over-expanded interconnects, which limit the reliability of the semiconductor device. For example, the conductive pads can be spaced too far apart, which can leave a gap between the interconnects that can short the semiconductor device. Alternatively, the conductive pads can be spaced too close together, which can cause the interconnects to separate the bond between the layers of dielectric material and thereby reduce the mechanical strength of the semiconductor device assembly.

[0010] To address these and other issues, the technology discloses a semiconductor device having an interconnect formed through atomic layer deposition (ALD). The semiconductor device includes a first semiconductor die and a second semiconductor die. The first semiconductor die has a first layer of dielectric material and a first conductive pad disposed in a first opening of the first layer of dielectric material. The second semiconductor die has a second layer of dielectric material facing the first layer of dielectric material, and a second conductive pad disposed in a second opening of the second layer of dielectric material and corresponding to the first conductive pad. A spacer extends between the first layer of dielectric material and the second layer of dielectric material. A conductive material (e.g., through ALD) is disposed between the first conductive pad and the second conductive pad to implement an interconnect electrically coupling the first semiconductor die and the second semiconductor die. In this way, a reliable semiconductor device can be assembled, Figure 1 Examples of the reliable semiconductor device are described in the detailed description.

[0011] Figure 1This illustration shows a simplified schematic cross-sectional view of a semiconductor device assembly 100 comprising semiconductor dies 102 and 104 electrically coupled to each other. Semiconductor die 102 may be implemented on a substrate 106, which may be a wafer-level substrate on which multiple semiconductor dies are implemented or a die-level substrate on which single-cut semiconductor dies are implemented. Semiconductor die 104 may similarly be implemented on a substrate 108, which may be a wafer-level or die-level substrate. Therefore, the semiconductor device assembly 100 may be formed via wafer-to-wafer bonding, chip-to-wafer bonding, or chip-to-chip bonding. Semiconductor dies 102 and 104 may be front-to-front, front-to-back, or back-to-back coupled. In this manner, semiconductor die 102 or semiconductor die 104 may include through-silicon vias (TSVs) (not shown) extending through substrate 106 or substrate 108, respectively, to provide electrical connections to circuitry on the front side via exposed TSVs on the back side.

[0012] A dielectric material layer 110 (e.g., silicon oxide, silicon nitride, silicon carbide, silicon carbonitride) may be disposed on a semiconductor die 102 to implement a passivation layer. The dielectric material layer 110 may have one or more openings through which contact pads 112 (e.g., copper pads) disposed on the semiconductor die 102 are exposed. For example, the contact pads 112 may be recessed from the dielectric material layer 110 (e.g., between 5 nm and 10 nm) due to CMP (concave-mass perforation). The contact pads 112 may be connected to a circuit system (e.g., traces, wires, vias) to enable additional circuit components to be electrically coupled to and provide functionality (e.g., power, ground, input / output (I / O) signaling) to the semiconductor die 102. A dielectric material layer 114 may be disposed on a semiconductor die 104 such that the dielectric material layer 114 faces the dielectric material layer 110. The dielectric material layer 114 may have an opening that exposes a contact pad 116, which corresponds to a contact pad 112 disposed on a semiconductor die 102.

[0013] Unlike other semiconductor devices, dielectric layers 114 and 110 do not necessarily contact each other. Instead, spacer 118 may be disposed between dielectric layers 110 and 114 to maintain a specific spacing between semiconductor dies 102 and 104. This allows for control over the specifications of the semiconductor device assembly 100. Spacer 118 may be disposed at and extend from dielectric layers 110 or 114. In some cases, spacer 118 does not need to cover the entire dielectric layer 110 or 114. Alternatively, spacer 118 may be a separate structure covering only a portion of dielectric layers 110 or 114. In several aspects, spacer 118 may comprise a dielectric material (e.g., the same or different from the dielectric material of dielectric layer 110 or 114) or a polymer. The spacer 118 may have a thickness 120 of less than 100 nanometers, less than 200 nanometers, less than 500 nanometers, etc. (e.g., measured perpendicularly from the surface on which the spacer 118 is disposed). In some cases, a bond may be formed between the spacer 118 and a dielectric material layer opposite to the dielectric material layer on which the spacer 118 is disposed. For example, if the spacer 118 is disposed at a dielectric material layer 110, then the distal end of the spacer 118 may be bonded to the dielectric material layer 114 (e.g., fusion bond).

[0014] Conductive material 122 (e.g., tin-free, lead-free, or solder-free material) can be disposed between contact pads 112 and 116 to implement interconnects electrically coupling semiconductor dies 102 and 104. Conductive material 122 can be disposed via an ALD (Alternating Discharge Deposition). In several aspects, an ALD is a process by which material is deposited at a fine-grained scale (e.g., sub-nanometer precision). However, due to this precision, an ALD may take substantially longer than other material deposition techniques (e.g., deposition rates of 100 nm / h to 300 nm / h). Therefore, an ALD can be used for highly controlled deposition in small spaces. In the illustrated example, an ALD is used to deposit conductive material 122 between contact pads 112 and 116. Therefore, conductive material 122 can implement interconnects having sizes less than 100 nm, less than 200 nm, less than 500 nm, etc. Any number of conductive materials can be used to implement the interconnects. For example, conductive material 122 may particularly comprise copper, aluminum, silver, or gold. In some cases, the conductive material 122 may contain cobalt due to the favorable material properties of cobalt relative to ALD.

[0015] Interconnects formed using the techniques described herein may differ from interconnects formed using other bonding techniques, such as hybrid bonding. For example, hybrid bonding can utilize the thermal expansion properties of conductive pads to form metal-to-metal interconnects from a single conductive material. In the hybrid bonding process, a connection between conductive pad 112 and contact pad 116 is formed by a high-temperature annealing process, wherein contact pads 112 and 116 expand toward each other. Once in contact, metal atoms from contact pads 112 and 116 diffuse into each other and form a bond. In this context, the indentation of contact pads 112 and 116 (e.g., erosion at one part of the contact pad relative to another part of the contact pad or dielectric material) must be precisely controlled to prevent over-expansion or under-expansion.

[0016] Compared to these embodiments, the technology disclosed herein utilizes separate deposition processes to form interconnects between contact pads 112 and 116. The ALD process, or additive process, involves selectively adding conductive material 122 to the tops of contact pads 112 and 116 until the gap between them is filled. This allows for a larger recess margin in contact pads 112 and 116, and this recess can remain even after the conductive material 122 has been deposited. In this way, the risk of under- or over-expanding interconnects is reduced, thereby improving the robustness of the semiconductor device assembly 100. Furthermore, the conductive material 122 can accommodate misalignments in contact pads 112 and 116 due to its selective addition capability.

[0017] In another aspect, the conductive material 122 and contact pads 112 or 116 may comprise different conductive materials. For example, contact pads 112 or 116 may comprise copper, and the conductive material 122 may comprise cobalt, gold, silver, or any other conductive material. In some embodiments, the conductive material 122 may be continuous (e.g., seamless) and lack metal-to-metal bonding, such as metal-to-metal bonding formed by hybrid bonding, because no diffusion occurs between contact pads 112 and 116 to form an interconnect. Furthermore, given that the ALD may deposit the conductive material 122 slowly, the conductive material 122 may be deposited not only vertically but also radially on the deposited conductive material 122, causing the conductive material 122 to expand into the gap between the dielectric material layer 110 and the dielectric material layer 114. In this way, the conductive material 122 may be wider than contact pads 112 or 116 in some portions.

[0018] As discussed above, spacer 118 does not need to cover the entire surface of dielectric layer 110 or dielectric layer 114. Therefore, gaps may exist between dielectric layer 110, dielectric layer 114, spacer 118, and conductive material 122. In some cases, gap filler 124 may be used to fill these gaps. Doing so further supports the semiconductor device assembly 100. Gap filler 124 may comprise a dielectric material or a polymer. If gap filler 124 comprises a dielectric material, the dielectric material may be the same as or different from the dielectric material used for spacer 118. Similarly, if gap filler 124 comprises a polymer, the polymer may be the same as or different from the polymer used for spacer 118. In some cases, gap filler 124 may comprise a dielectric material disposed via an ALD.

[0019] This disclosure now turns to a series of steps for manufacturing a semiconductor device assembly according to embodiments of the present technology. Specifically, Figures 2 to 6 Simplified schematic plan views and cross-sectional views illustrate a series of steps for manufacturing a semiconductor device assembly according to embodiments of the present technology. For ease of description, the steps are described with respect to specific embodiments. However, the steps may be performed with respect to… Figures 2 to 6 The steps described are for manufacturing a semiconductor device assembly according to other embodiments.

[0020] Figure 2 This illustration shows a simplified schematic cross-sectional view of a semiconductor device assembly 200 including a substrate 202 (e.g., a wafer-level substrate, a die-level substrate). In several aspects, the semiconductor device assembly 200 may include a wafer of semiconductor dies or a single-cut semiconductor die. A dielectric layer 204 is disposed on a side (e.g., a front or back side) of the substrate 202. Contact pads 206 are disposed on a side of the substrate 202 to allow additional circuit components (e.g., semiconductor dies) to be coupled thereto. The dielectric layer 204 includes openings through which the contact pads 206 are exposed. For example, the contact pads 206 may be recessed from the dielectric layer 204 (e.g., 5 nm to 10 nm) due to CMP (concave-mass permeation). In several aspects, the dielectric layer 204 does not need to be planarized because the dielectric layer 204 does not contact the dielectric layer at the additional die location and therefore a planar surface is not required to improve adhesion.

[0021] Figure 3A A simplified schematic cross-sectional view illustrating a semiconductor device assembly 300a after at least one spacer 302 has been placed on a dielectric material layer 204. Figure 3B A simplified schematic plan view illustrating the upper surface of the semiconductor device assembly 300b. At least one spacer 302 may be disposed on the upper surface of the dielectric material layer 204. The at least one spacer 302 may comprise a plurality of independent islands separated from each other.Figure 3B As described, at least one spacer 302 does not cover the entire upper surface of the dielectric material layer 204. In this way, at least one spacer 302 can have a connection with the upper surface (…). Figure 3B The cross-sectional area of ​​the surfaces described herein is coplanar and is smaller than the area of ​​the upper surface of the dielectric material layer 204. At least one spacer 302 may extend above the upper surface of the dielectric material layer 204 by a uniform amount (e.g., less than 100 nanometers, less than 200 nanometers, less than 500 nanometers).

[0022] At least one spacer 302 can be positioned using any suitable technique. For example, photolithography can be used to deposit at least one spacer 302. At least one spacer 302 may comprise a dielectric material or a polymer. In some cases, CMP can be used to planarize the upper surface of at least one spacer 302. In doing so, the upper surface of at least one spacer 302 provides a planar contact surface at which additional semiconductor dies can be coupled.

[0023] Figure 4 A simplified schematic cross-sectional view of a semiconductor device assembly 400 is shown. The semiconductor device assembly 400 includes a substrate 402 on which semiconductor dies are implemented. In some embodiments, the substrate 402 is a wafer-level substrate on which multiple semiconductor dies are implemented or a die-level substrate on which a single, monocut semiconductor die is implemented. In this manner, the semiconductor device assembly 400 can be formed by wafer-to-wafer bonding, chip-to-wafer bonding, or chip-to-chip bonding. A dielectric layer 404 is disposed on the side of the substrate 402. The dielectric layer 404 has an opening through which contact pads 406 are exposed. Contact pads 406 correspond to contact pads 206. The dielectric layer 404 faces the dielectric layer 204. The dielectric layer 404 is in contact with the coupling surface of a spacer 302. In this manner, the spacer 302 maintains the gap between semiconductor dies. In some cases, the dielectric layer 404 is directly bonded to the spacer 302. For example, spacer 302 may comprise a dielectric material, and spacer 302 and dielectric material layer 404 may be fused together. Alternatively, spacer 302 may comprise a polymer, and spacer 302 may be bonded to dielectric material layer 404 by heating or by an adhesive.

[0024] Figure 5This is a simplified schematic cross-sectional view illustrating a semiconductor device assembly 500 after conductive material 502 has been disposed between contact pads 206 and 406. In several aspects, conductive material 502 is disposed by an ALD (Alternating Discharge Machining). In some cases, the ALD allows for selective deposition at specific locations. In this way, conductive material 502 can be selectively deposited in the narrow gap between contact pads 206 and 406, but outside the lateral positions of contact pads 206 and 406. For example, conductive material 502 can be deposited in gaps smaller than 100 nanometers, smaller than 200 nanometers, smaller than 500 nanometers, etc. Conductive material 502 can comprise any number of conductive materials. For example, conductive material 502 can be a different material than the material used to implement contact pads 206 or 406. As a specific example, conductive material 502 can comprise cobalt.

[0025] Figure 6 This is a simplified schematic cross-sectional view illustrating the semiconductor device assembly 600 after the spacer filler 602 has been placed. Since the spacer 302 does not necessarily cover the entire surface of the dielectric layer 204 and the conductive material 502 is selectively deposited between contact pads 206 and 406, gaps may exist between the dielectric layer 204, the dielectric layer 404, the spacer 302, and the conductive material 502. The spacer filler 602 may be placed within these gaps. For example, an ALD (Alternating Current Deposition) may be used to deposit the spacer filler 602. In some cases, the spacer filler 602 may comprise a dielectric material or a polymer. Placing the spacer filler 602 improves the mechanical strength of the semiconductor device assembly 600 and prevents electrical contact with the conductive material 502.

[0026] Figure 7 This illustration shows a simplified schematic cross-sectional view of a semiconductor device assembly 700 comprising a stack of semiconductor dies 702 packaged into a semiconductor device (e.g., diced from two coupled semiconductor wafers). The semiconductor dies 702 may be coupled front-to-front, front-to-back, or back-to-back. One or more of the semiconductor dies 702 may include TSVs 704 to couple contact pads on the back side to a metallization layer on the front side (e.g., with traces, lines, vias, or other connection structures). In several aspects, interconnects 706 electrically coupling the semiconductor dies 702 may be formed using techniques disclosed herein (e.g., using spacers via ALD deposition).

[0027] Semiconductor die 702 may be coupled to package-grade substrate 708 (e.g., printed circuit board (PCB), interposer, another semiconductor die). Interconnect structures 710 (e.g., solder balls, solder bumps, conductive pillars) may be disposed between contact pads on the underside of the bottom semiconductor die 702 and contact pads (not shown) on the upper side of the package-grade substrate 708 to implement interconnects electrically coupling the semiconductor die 702 and the package-grade substrate 708. Underfill material 712 (e.g., capillary underfill) may be provided between the bottom die of semiconductor die 702 and the package-grade substrate 708 to provide electrical insulation for the interconnect structures 710 and structurally support the semiconductor device assembly 700. The package-grade substrate 708 may include internal wiring circuitry (e.g., traces, wires, vias, and other connection structures) connecting the upper contact pads to the lower contact pads. The connection structure 714 may provide external connectivity to other devices (e.g., on a motherboard) via a contact pad disposed on the underside. The semiconductor device assembly 700 may further include an encapsulating material 716 (e.g., a molding resin compound or the like) that at least partially encapsulates the semiconductor die 702 stack and the package-level substrate 708 to prevent electrical contact therewith or to provide mechanical strength to the semiconductor device assembly 700.

[0028] Although the semiconductor device assembly has been described and depicted in the foregoing exemplary embodiments as having a specific configuration including semiconductor dies, in other embodiments, the assembly may have different configurations of semiconductor dies. For example, with appropriate modifications, the semiconductor device assembly described in any of the foregoing examples may be implemented using, for example, a vertical stack of semiconductor dies or multiple semiconductor dies.

[0029] According to one aspect of this disclosure, in Figures 1 to 7 The semiconductor device described in the assembly may include memory dies, such as dynamic random access memory (DRAM) dies, NAND memory dies, NOR memory dies, magnetic random access memory (MRAM) dies, phase-change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, or the like. In embodiments in which multiple dies are provided in a single assembly, the semiconductor device may include the same type of memory dies (e.g., both are NAND, both are DRAM) or different types of memory dies (e.g., one DRAM and one NAND). According to another aspect of this disclosure, the semiconductor dies of the assemblies described above may be logic dies (e.g., controller dies, processor dies), or a mixture of logic dies and memory dies (e.g., memory controller dies and memory dies controlled by them).

[0030] The above text is about Figures 1 to 7 Any of the described semiconductor devices and semiconductor device assemblies can be incorporated into any of a multitude of larger or more complex systems, a representative example of which is... Figure 8 The system 800 is schematically shown in the diagram. System 800 may include a semiconductor device assembly 802 (e.g., a discrete semiconductor device), a power supply 804, a driver 806, a processor 808, and / or other subsystems or components 810. The semiconductor device assembly 802 may include components related to those described above. Figures 1 to 7 The described semiconductor device assemblies are characterized by generally similar features. The resulting system 800 can perform any of a wide variety of functions, such as memory storage, data processing, or other suitable functions. Therefore, a representative system 800 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, or other products. The components of system 800 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). The components of system 800 may also include remote devices and any of a wide variety of computer-readable media.

[0031] Figure 9 An example method 900 for manufacturing a semiconductor device assembly according to embodiments of the present technology is described. Although described with a particular configuration, one or more operations of method 900 may be omitted, repeated, or rearranged. Additionally, method 900 may include... Figure 9 Additional operations not described herein, for example, operations detailed in one or more other methods described herein.

[0032] At 902, a first semiconductor die is provided. The first semiconductor die includes a first dielectric material layer and a first conductive pad disposed in a first opening in the first dielectric material layer. At 904, a second semiconductor die is provided. The second semiconductor die includes a second dielectric material layer and a second conductive pad disposed in a second opening in the second dielectric material layer. At 906, a spacer is disposed at the first dielectric material layer. The spacer extends from the first dielectric material layer. At 908, the first and second semiconductor dies are aligned such that the first dielectric material layer faces the second dielectric material layer, the second dielectric material layer contacts the spacer, and the first conductive pad corresponds to the second conductive pad. At 910, a conductive material (e.g., using ALD) is deposited between the first and second conductive pads to implement an interconnect that electrically couples the first and second semiconductor dies. This allows for the assembly of a reliable semiconductor device.

[0033] The foregoing describes specific details of several embodiments of semiconductor devices and associated systems and methods. Depending on the context in which the term "substrate" is used, it may refer to a wafer-level substrate or a single-cut die-level substrate. Furthermore, unless the context otherwise indicates, the structures disclosed herein can be formed using conventional semiconductor manufacturing techniques. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, ALD, or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, CMP, or other suitable techniques.

[0034] The technologies disclosed herein relate to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term "semiconductor device" can refer to a solid-state device comprising one or more semiconductor materials. Examples of semiconductor devices include, in particular, logic devices, memory devices, and diodes. Additionally, the term "semiconductor device" can refer to a finished device or an assembly or other structure at various processing stages prior to becoming a finished device. Depending on the context in which the term "substrate" is used, it can refer to a structure supporting electronic components (e.g., a die), such as a PCB or wafer-level substrate, a die-level substrate, or another die used for die stacking or three-dimensional interface (3DI) applications.

[0035] The devices discussed herein (including memory devices) can be formed on a semiconductor substrate or die (e.g., silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0036] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functions may also be physically located in various locations, including portions distributed such that the functions are implemented at different physical locations.

[0037] As used herein, the word "or," as included in the claims, or as used in a list of items (for example, a list of items beginning with phrases such as "at least one of..." or "one or more of..."), indicates a comprehensive list such that a list of at least one of, for example, A, B, or C, implies A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0038] As used herein, the terms “vertical,” “horizontal,” “up,” “down,” “above,” and “below” can refer to the relative orientation or position of a feature in a semiconductor device given the orientation shown in the figures. For example, “up” or “top” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be interpreted broadly to include semiconductor devices with other orientations (e.g., inverted or tilted orientations), where top / bottom, above / below, above / below, up / down, and left / right can be interchanged depending on the orientation.

[0039] As will be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details have been set forth in the foregoing description to provide a thorough and illustrative description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of these specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail to avoid obscuring other aspects of the present technology. Generally, it should be understood that various other devices, systems, and methods besides those specific embodiments disclosed herein are also within the scope of the present technology.

Claims

1. A method for manufacturing a semiconductor device assembly, comprising: A first semiconductor die is provided, the first semiconductor die comprising: First dielectric material layer; and A first conductive pad is disposed in a first opening of the first dielectric material layer; A second semiconductor die is provided, the second semiconductor die comprising: Second dielectric material layer; and A second conductive pad is disposed in a second opening of the second dielectric material layer; A spacer disposed on and extending therefrom the first dielectric material layer; Align the first semiconductor die and the second semiconductor die such that the first dielectric material layer faces the second dielectric material layer, the second dielectric material layer contacts the spacer, and the first conductive pad corresponds to the second conductive pad; and Atomic layer deposition is used to deposit conductive material between the first conductive pad and the second conductive pad.

2. The method of claim 1, further comprising depositing a polymer or dielectric material between the first dielectric material layer, the second dielectric material layer, the conductive material, and the spacer using atomic layer deposition.

3. The method of claim 1, wherein the spacer is disposed only on a portion of the exposed surface of the first dielectric material layer.

4. The method of claim 1, further comprising forming a direct bond between the spacer and the second dielectric material layer.

5. The method of claim 1, wherein the spacer comprises a dielectric material or a polymer.

6. The method of claim 1, wherein the first conductive pad comprises copper and the conductive material comprises cobalt.

7. The method of claim 1, further comprising using chemical-mechanical planarization to thin the spacer.

8. A semiconductor device assembly comprising: The first semiconductor die includes: First dielectric material layer; and A first conductive pad is disposed in a first opening of the first dielectric material layer; The second semiconductor die includes: A second dielectric material layer, which faces the first dielectric layer; and The second conductive pad is disposed in the second opening of the second dielectric material layer and corresponds to the first conductive pad; A spacer, disposed at the first dielectric layer and extending from the first dielectric layer to the second dielectric layer; and A conductive material is disposed between the first conductive pad and the second conductive pad to implement an interconnect for electrically coupling the first semiconductor die and the second semiconductor die, the conductive material extending at least partially into the gap between the first dielectric material layer and the second dielectric material layer.

9. The semiconductor device assembly of claim 8, wherein the first conductive pad is recessed from the first dielectric material layer.

10. The semiconductor device assembly of claim 9, wherein the first conductive pad is recessed from the first dielectric material layer by more than 5 nanometers.

11. The semiconductor device assembly of claim 8, wherein the first conductive pad and the conductive material comprise different conductive materials.

12. The semiconductor device assembly of claim 11, wherein the first conductive pad comprises copper and the conductive material comprises cobalt.

13. The semiconductor device assembly of claim 8, wherein the spacer is disposed only on a portion of the surface of the first dielectric layer toward the second dielectric layer.

14. The semiconductor device assembly of claim 8, further comprising a polymer or dielectric material disposed between the first dielectric layer, the second dielectric layer, the conductive material and the spacer.

15. The semiconductor device assembly of claim 8, wherein the spacer comprises a polymer or a dielectric material.

16. The semiconductor device assembly of claim 8, wherein the spacer has a thickness of less than 0.5 micrometers.

17. The semiconductor device assembly of claim 8, wherein the conductive material is formed using an atomic layer deposition process.

18. The semiconductor device assembly of claim 8, wherein the interconnect is continuous between the first conductive pad and the second conductive pad and lacks metal-to-metal bonding.

19. The semiconductor device assembly of claim 8, wherein the conductive material is tin-free and lead-free.

20. A method for manufacturing a semiconductor device assembly, comprising: A first semiconductor die is provided, the first semiconductor die comprising: First dielectric material layer; and A first conductive pad is disposed in a first opening of the first dielectric material layer; A second semiconductor die is provided, the second semiconductor die comprising: Second dielectric material layer; and A second conductive pad is disposed in a second opening of the second dielectric material layer; A spacer disposed on and extending therefrom the first dielectric material layer; The spacer is coupled to the second dielectric material layer such that the first dielectric material layer faces the second dielectric material layer and the first conductive pad corresponds to the second conductive pad; A conductive material is deposited between the first conductive pad and the second conductive pad using atomic layer deposition; and Atomic layer deposition is used to deposit at least partially a polymer or dielectric material between the first dielectric material layer and the second dielectric material layer.

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