Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device occupying a small area. The semiconductor device includes a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first conductive layer, a second conductive layer, and a first semiconductor layer. The second transistor includes a third conductive layer, a third insulating layer and a second semiconductor layer. The first insulating layer is on the first conductive layer and has a first opening portion reaching the first conductive layer. The second conductive layer is on the first insulating layer and has a second opening portion in a region overlapping the first opening portion. The first semiconductor layer has a region in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a side surface of the second conductive layer. The second insulating layer is located on the first insulating layer. The third conductive layer is located on the second insulating layer. The third insulating layer is located on the third conductive layer. The second semiconductor layer has a region overlapping the third conductive layer with the third insulating layer interposed therebetween.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. A third aspect of the present invention relates to a display device including a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving or manufacturing methods for the aforementioned devices.

[0003] Note that in this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips incorporating integrated circuits, and electronic components that house chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes all include semiconductor devices. Background Technology

[0004] Semiconductor devices, including transistors, are widely used in electronic devices. In recent years, the applications of display devices have become increasingly diverse, including portable information terminals, television sets (also known as television receivers), digital signage, and public information displays (PIDs). Examples of display devices include those using organic EL (Electroluminescence) elements or light-emitting diodes (LEDs), displays including liquid crystal elements, and electronic paper that uses electrophoretic display.

[0005] In display devices, pixel size can be reduced by shrinking the area occupied by transistors, thus improving resolution. Furthermore, reducing the area occupied by transistors allows for an increase in aperture ratio. Therefore, miniaturized transistors are required.

[0006] The development of devices that require high-definition display devices, such as those for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), is very active.

[0007] Patent document 1 discloses a high-definition display device using organic EL elements.

[0008] [Preliminary Technology Documents]

[0009] [Patent Literature]

[0010] [Patent Document 1] International Patent Application Publication No. 2016 / 038508 Summary of the Invention

[0011] The technical problem that the invention aims to solve

[0012] One objective of this invention is to provide a semiconductor device including micro-transistors. Another objective of this invention is to provide a semiconductor device including transistors with short channel lengths. Another objective of this invention is to provide a semiconductor device including transistors with large on-state current. Another objective of this invention is to provide a semiconductor device including both short-channel-length and long-channel-length transistors. Another objective of this invention is to provide a semiconductor device including transistors with good electrical characteristics. Another objective of this invention is to provide a semiconductor device with a small footprint. Another objective of this invention is to provide a semiconductor device with low wiring resistance. Another objective of this invention is to provide a semiconductor device or display device with low power consumption. Another objective of this invention is to provide a semiconductor device or display device including highly reliable transistors. Another objective of this invention is to provide a display device with high resolution. Another objective of this invention is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another objective of this invention is to provide a semiconductor device, display device, or method for manufacturing the same, including novel transistors.

[0013] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims.

[0014] means of solving technical problems

[0015] One aspect of the present invention is a semiconductor device including a first transistor, a second transistor, a first insulating layer, and a second insulating layer. The first transistor includes a first conductive layer, a second conductive layer, and a first semiconductor layer. The second transistor includes a third conductive layer, a third insulating layer, and a second semiconductor layer. The first insulating layer is located on the first conductive layer. The first insulating layer has a first opening extending to the first conductive layer. The second conductive layer is located on the first insulating layer. The second conductive layer has a second opening in a region overlapping with the first opening. The first semiconductor layer has a region in the first opening that contacts the top surface of the first conductive layer and the side surface of the first insulating layer. The first semiconductor layer has a region in the second opening that contacts the side surface of the second conductive layer. The second insulating layer is located on the first insulating layer. The third conductive layer is located on the second insulating layer. The third insulating layer is located on the third conductive layer. The second semiconductor layer has a region overlapping with the third conductive layer across the third insulating layer.

[0016] In the above-described semiconductor device, the end of the third insulating layer is preferably the same as or substantially the same as the end of the second insulating layer.

[0017] In the above-described semiconductor device, the end of the second insulating layer is preferably in contact with the top surface of the first insulating layer.

[0018] In the above-described semiconductor device, the end of the second insulating layer is preferably in contact with the top surface of the second conductive layer.

[0019] In the above-described semiconductor device, the first semiconductor layer preferably has a region that contacts the top surface of the second conductive layer.

[0020] In the above-described semiconductor device, the first semiconductor layer preferably does not contact the second insulating layer.

[0021] In the above-described semiconductor device, the first semiconductor layer and the second semiconductor layer preferably each comprise a metal oxide.

[0022] In the aforementioned semiconductor device, the first insulating layer preferably includes a fourth insulating layer and a fifth insulating layer thereon. The fourth insulating layer preferably comprises silicon and oxygen. The fifth insulating layer preferably comprises silicon and nitrogen.

[0023] In the aforementioned semiconductor device, the first insulating layer preferably includes a fourth insulating layer and a fifth insulating layer on the fourth insulating layer. The fourth insulating layer preferably comprises silicon and oxygen. The fifth insulating layer preferably comprises one or both of aluminum and hafnium, as well as oxygen.

[0024] In the aforementioned semiconductor device, the first insulating layer preferably includes a sixth insulating layer. The sixth insulating layer is preferably located between the first conductive layer and the fourth insulating layer. The sixth insulating layer preferably comprises silicon and nitrogen.

[0025] In the aforementioned semiconductor device, the first insulating layer preferably includes a sixth insulating layer. The sixth insulating layer is preferably located between the first conductive layer and the fourth insulating layer. The sixth insulating layer preferably comprises one or both of aluminum and hafnium, and oxygen.

[0026] In the aforementioned semiconductor device, a seventh insulating layer is preferably included. The top surface of the seventh insulating layer is preferably in contact with the bottom surface of the first conductive layer. The seventh insulating layer preferably comprises silicon and nitrogen.

[0027] The semiconductor device described above preferably includes a capacitor. The capacitor preferably includes a second conductive layer, a third conductive layer, and a second insulating layer sandwiched between the second and third conductive layers.

[0028] One aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer; forming a first insulating film on the first conductive layer; forming a second conductive layer on the first insulating film having a region overlapping with the first conductive layer; forming a second insulating film on the first insulating film and the second conductive layer; forming a third conductive layer on the second insulating film; forming a third insulating film on the second insulating film and the third conductive layer; forming a first insulating layer and a second insulating layer with consistent or substantially consistent ends by processing the second insulating film and the third insulating film; forming a fourth conductive layer having a first opening in the region overlapping with the first conductive layer by processing the second conductive layer; and so on. A third insulating layer is formed in a region overlapping with the first opening by processing a first insulating film; a first semiconductor layer is formed in the first opening having a region contacting the top surface of the first conductive layer and the side surface of the third insulating layer, and in the second opening having a region contacting the side surface of the fourth conductive layer; a second semiconductor layer having a region overlapping with the third conductive layer is formed on the second insulating layer; a fourth insulating layer is formed on the first semiconductor layer and the second semiconductor layer; and a fifth conductive layer having a region overlapping with the first semiconductor layer is formed on the fourth insulating layer, and a sixth conductive layer having a region overlapping with the second semiconductor layer is formed.

[0029] Invention Effects

[0030] According to one aspect of the present invention, a semiconductor device including micro-transistors can be provided. Additionally, a semiconductor device including transistors with short channel lengths can be provided. Additionally, a semiconductor device including transistors with large on-state currents can be provided. Additionally, a semiconductor device including both short-channel-length and long-channel-length transistors can be provided. Additionally, a semiconductor device including transistors with good electrical characteristics can be provided. Additionally, a semiconductor device with a small footprint can be provided. Additionally, a semiconductor device with low wiring resistance can be provided. Additionally, a semiconductor device or display device with low power consumption can be provided. Additionally, a semiconductor device or display device including highly reliable transistors can be provided. Additionally, a display device with high resolution can be provided. Additionally, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Additionally, a semiconductor device, display device, or method for manufacturing the same, including novel transistors, can be provided.

[0031] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims. Attached Figure Description

[0032] Figure 1A This is a top view showing an example of a semiconductor device. Figure 1B and Figure 1C This is a cross-sectional view showing an example of a semiconductor device.

[0033] Figure 2A and Figure 2B This is a perspective view showing an example of a semiconductor device.

[0034] Figure 3A This is a top view showing an example of a semiconductor device. Figure 3B This is a cross-sectional view showing an example of a semiconductor device.

[0035] Figure 4A This is a top view showing an example of a semiconductor device. Figure 4B and Figure 4C This is a cross-sectional view showing an example of a semiconductor device.

[0036] Figures 5A to 5D This is a cross-sectional view showing an example of a semiconductor device.

[0037] Figures 6A to 6D This is a cross-sectional view showing an example of a semiconductor device.

[0038] Figure 7 This is a cross-sectional view showing an example of a semiconductor device.

[0039] Figures 8A to 8C This is a cross-sectional view showing an example of a semiconductor device.

[0040] Figures 9A to 9D This is a cross-sectional view showing an example of a semiconductor device.

[0041] Figure 10A This is a top view showing an example of a semiconductor device. Figure 10B This is a cross-sectional view showing an example of a semiconductor device.

[0042] Figure 11A This is a top view showing an example of a semiconductor device. Figure 11B This is a cross-sectional view showing an example of a semiconductor device.

[0043] Figure 12A This is a top view showing an example of a semiconductor device. Figure 12B and Figure 12C This is a cross-sectional view showing an example of a semiconductor device.

[0044] Figure 13A and Figure 13B This is a cross-sectional view showing an example of a semiconductor device.

[0045] Figures 14A to 14D This is a cross-sectional view showing an example of a semiconductor device.

[0046] Figures 15A to 15C This is a cross-sectional view showing an example of a semiconductor device.

[0047] Figure 16A and Figure 16B This is a cross-sectional view showing an example of a semiconductor device.

[0048] Figures 17A to 17C This is a cross-sectional view showing an example of a semiconductor device.

[0049] Figures 18A to 18C This is a cross-sectional view showing an example of a semiconductor device.

[0050] Figure 19 This is a cross-sectional view showing an example of a semiconductor device.

[0051] Figure 20A This is a top view showing an example of a semiconductor device. Figure 20B This is a cross-sectional view showing an example of a semiconductor device.

[0052] Figure 21A and Figure 21B This is a cross-sectional view showing an example of a semiconductor device.

[0053] Figure 22AThis is a top view showing an example of a semiconductor device. Figure 22B and Figure 22C This is a cross-sectional view showing an example of a semiconductor device.

[0054] Figure 23A and Figure 23B It is the equivalent circuit diagram of a semiconductor device. Figure 23C This is a top view showing an example of a semiconductor device.

[0055] Figure 24 This is a cross-sectional view showing an example of a semiconductor device.

[0056] Figure 25 This is a perspective view showing an example of a semiconductor device.

[0057] Figures 26A to 26D This is a perspective view showing an example of a semiconductor device.

[0058] Figure 27A and Figure 27B It is the equivalent circuit diagram of a semiconductor device. Figure 27C This is a top view showing an example of a semiconductor device.

[0059] Figure 28 This is a cross-sectional view showing an example of a semiconductor device.

[0060] Figure 29 This is a perspective view showing an example of a semiconductor device.

[0061] Figures 30A to 30D This is a perspective view showing an example of a semiconductor device.

[0062] Figures 31A to 31D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0063] Figures 32A to 32C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0064] Figures 33A to 33C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0065] Figures 34A to 34C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0066] Figures 35A to 35C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0067] Figure 36A and Figure 36B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0068] Figure 37 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0069] Figure 38A This is a perspective view showing an example of a display device. Figure 38B This is a block diagram illustrating an example of a display device.

[0070] Figure 39A This is the circuit diagram of a latch circuit. Figure 39B This is the circuit diagram of an inverter circuit.

[0071] Figure 40A and Figure 40B This is a circuit diagram of a pixel circuit. Figure 40C This is a cross-sectional view showing an example of a pixel circuit.

[0072] Figure 41 This is a circuit diagram of a pixel circuit.

[0073] Figure 42A and Figure 42B This is a cross-sectional view showing an example of a display device.

[0074] Figure 43 This is a cross-sectional view showing an example of a display device.

[0075] Figures 44A to 44C This is a cross-sectional view showing an example of a display device.

[0076] Figure 45A and Figure 45B This is a cross-sectional view showing an example of a display device.

[0077] Figure 46 This is a cross-sectional view showing an example of a display device.

[0078] Figures 47A to 47D This is a diagram illustrating an example of an electronic device.

[0079] Figures 48A to 48F This is a diagram illustrating an example of an electronic device.

[0080] Figures 49A to 49G This is a diagram illustrating an example of an electronic device.

[0081] Figure 50A and Figure 50B This is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment.

[0082] Figure 51 This is a diagram illustrating the reliability of the transistor according to an embodiment.

[0083] Figures 52A to 52DThis is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment.

[0084] Figures 53A to 53D This is a diagram illustrating the Id-Vd characteristics of a transistor according to an embodiment.

[0085] Figure 54A and Figure 54B This is a diagram illustrating the drain breakdown voltage of a transistor according to an embodiment.

[0086] Figure 55 This is a diagram illustrating the electrical characteristics of a transistor according to an embodiment. Detailed Implementation

[0087] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0088] Note that in the invention structure described below, the same symbols are used in different figures to show the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when parts with the same function are indicated, the same shading lines are sometimes used without additional symbols.

[0089] Furthermore, in this specification and other documents, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as "_1", "[n]", and "[m,n]" are sometimes added to the symbol for identification. Additionally, in the accompanying drawings and other documents, when symbols such as "_1", "[n]", and "[m,n]" are added to the symbol for identification, if it is not necessary to distinguish them in this specification or other documents, sometimes these symbols are not added.

[0090] Furthermore, for ease of understanding, the positions, sizes, and extents of the components shown in the accompanying drawings do not necessarily represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0091] In this specification and other documents, ordinal numbers such as "first" and "second" are used for convenience, but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, the ordinal numbers used for constituent elements in one part of this specification may sometimes differ from those used for the same constituent element in other parts of this specification or in the claims.

[0092] Furthermore, depending on the situation or state, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be changed into a "conductive film." In addition, an "insulating film" can be changed into an "insulating layer."

[0093] A transistor is a type of semiconductor device that can amplify current or voltage, control switching operations (turning the device on or off), etc. The transistors used in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0094] In cases where transistors with different polarities are used or the direction of current changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification and other materials, the terms "source" and "drain" can be used interchangeably. Note that, depending on the situation, the source and drain of the transistor can be appropriately referred to as source terminal and drain terminal, or source electrode and drain electrode, etc.

[0095] Furthermore, the "gate" and "back gate" can be interchanged. Therefore, in this specification and other materials, the terms "gate" and "back gate" can be used interchangeably. Note that, depending on the circumstances, the gate and back gate of the transistor can be appropriately referred to as gate electrode and back gate electrode, etc.

[0096] In this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0097] In this specification, unless otherwise specified, off-state current refers to the leakage current between the source and drain of a transistor when it is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the state where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, Vgs is higher than Vth).

[0098] In this specification and the like, the top surface shape of a constituent element refers to the outline shape of the constituent element when viewed from above (also known as from a plane). Furthermore, viewing from above means looking from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0099] In this specification, "generally consistent top surface shape" means that at least a portion of the outline of each layer in the stack overlaps. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, in reality, there are cases where the outlines do not overlap; sometimes the upper layer is inside or outside the lower layer, and in these cases, it can also be said that the "top surface shape is generally consistent." Furthermore, when the top surface shape is consistent or generally consistent, it can also be said that the ends are consistent or generally consistent, or that the ends are aligned or generally aligned.

[0100] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. Additionally, the angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as the tapered angle.

[0101] In this specification, devices manufactured using metal masks or FMM (Fine Metal Mask) are sometimes referred to as devices with an MM (Metal Mask) structure. Furthermore, devices manufactured without metal masks or FMM are sometimes referred to as devices with an MML (Metal Mask Less) structure. Note that because MML structure devices can be manufactured without metal masks, the resolution can exceed the upper limit of the alignment accuracy required by metal masks. Furthermore, MML structure devices do not require the equipment needed for metal mask manufacturing or the metal mask washing process. In addition, MML structure devices can reduce manufacturing costs, making them suitable for mass production.

[0102] In this specification and other materials, the structure in which light-emitting elements (also known as light-emitting devices) with different emission wavelengths are fabricated with separate light-emitting layers is sometimes referred to as an SBS (Side By Side) structure. Because the SBS structure allows for the optimization of materials and structure for each light-emitting element, the freedom of material and structure selection is increased, and it is easy to achieve improvements in brightness and reliability.

[0103] In this specification and other materials, holes or electrons are sometimes referred to as "carriers." Specifically, the hole injection layer or electron injection layer in a light-emitting element is sometimes called a "carrier injection layer," the hole transport layer or electron transport layer is called a "carrier transport layer," and the hole blocking layer or electron blocking layer is called a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not be clearly distinguished. In addition, sometimes a single layer performs the functions of two or three of the following: carrier injection layer, carrier transport layer, and carrier blocking layer.

[0104] In this specification, the light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Examples of layers included in the EL layer (also referred to as functional layers) include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification, the light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes. In this specification, sometimes one of the pairs of electrodes is referred to as a pixel electrode, and the other as a common electrode.

[0105] In this specification, the sacrificial layer (also known as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape in the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0106] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is disconnected due to the shape of the surface to which it is formed (e.g., a step).

[0107] (Implementation Method 1)

[0108] In this embodiment, refer to Figures 1A to 30D A semiconductor device according to one aspect of the present invention is described.

[0109] One aspect of the present invention is a semiconductor device comprising a first transistor, a second transistor, a first insulating layer, and a second insulating layer.

[0110] The first transistor includes a first conductive layer, a second conductive layer, a first semiconductor layer, a gate insulating layer on the first semiconductor layer, and a first gate electrode on the gate insulating layer. The first conductive layer serves as one of the source electrode and the drain electrode of the first transistor, and the second conductive layer serves as the other of the source electrode and the drain electrode.

[0111] The second transistor includes a third conductive layer, a third insulating layer, a second semiconductor layer, a gate insulating layer on the second semiconductor layer, and a second gate electrode on the gate insulating layer. The third conductive layer serves as the back gate electrode of the second transistor, and a portion of the third insulating layer serves as the back gate insulating layer.

[0112] A first insulating layer is located on a first conductive layer. The first insulating layer has a first opening extending into the first conductive layer. A second conductive layer is located on the first insulating layer. The second conductive layer has a second opening in a region overlapping with the first opening. A first semiconductor layer has a region in the first opening that contacts the top surface of the first conductive layer and the side surface of the first insulating layer. The first semiconductor layer has a region in the second opening that contacts the side surface of the second conductive layer.

[0113] The second insulating layer is located on the first insulating layer. The third conductive layer is located on the second insulating layer. The third insulating layer is located on the third conductive layer. The second semiconductor layer has a region that overlaps with the third conductive layer through the third insulating layer. Furthermore, the end of the third insulating layer preferably coincides with or substantially coincides with the end of the second insulating layer.

[0114] The channel length of the first transistor can be controlled by the thickness of the insulating layer sandwiched between the first and second conductive layers. In other words, the channel length of the first transistor is not affected by the exposure performance of the exposure apparatus used during manufacturing. Therefore, the channel length of the first transistor can be made smaller than the minimum size that the exposure apparatus can expose (hereinafter also referred to as the minimum size). By shortening the channel length, a transistor with a large on-state current can be realized.

[0115] The second transistor has a different structure than the first transistor. The channel length of the second transistor is influenced by the performance of the exposure apparatus used in its manufacturing process and is greater than the minimum size of the exposure apparatus. Therefore, the channel length of the second transistor can be longer than that of the first transistor. By increasing the channel length, transistors with high saturation can be achieved.

[0116] A first transistor with a short channel length and a second transistor with a long channel length can share some processing steps and be formed on the same substrate. For example, the first transistor can be used as a transistor that requires a large on-state current, and the second transistor can be used as a transistor that requires high saturation, thereby obtaining a high-performance semiconductor device.

[0117] Note that in this specification, etc., the situation where the current change in the saturation region of the transistor's Id-Vd characteristics is small is sometimes described as "high saturation".

[0118] <Structure Example 1>

[0119] A semiconductor device according to one aspect of the present invention will be described. Figure 1A This is a top view (also called a plan view) of the semiconductor device 10. Figure 1B Show along Figure 1A The cross-sectional view of the section along the dotted line A1-A2 shown is shown. Figure 1C This shows a cross-sectional view along the dashed line B1-B2. Figure 2A This is a perspective view of semiconductor device 10. Note that... Figure 1A In the diagram, some components of the semiconductor device 10 (such as insulating layers) are omitted. Regarding the top view of the semiconductor device, [the diagram is incomplete]. Figure 1A Similarly, some of the constituent elements are omitted in the following figures.

[0120] Semiconductor device 10 includes transistor 100, transistor 200, insulating layer 110, and insulating layer 109. Transistor 100 and transistor 200 are disposed on substrate 102. Transistor 100 and transistor 200 have different structures from each other. Furthermore, transistor 100 and transistor 200 may share some processing steps.

[0121] Transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. In transistor 100, conductive layer 104 serves as a gate electrode, and a portion of insulating layer 106 serves as a gate insulating layer. Conductive layer 112a serves as one of the source electrode and the drain electrode, and conductive layer 112b serves as the other of the source electrode and the drain electrode. Each layer constituting transistor 100 may have a single-layer structure or a stacked structure.

[0122] Transistor 200 includes conductive layer 204, conductive layer 212a, conductive layer 212b, insulating layer 106, semiconductor layer 208, insulating layer 120, and conductive layer 202. In transistor 200, conductive layer 204 serves as a gate electrode (also called a first gate electrode), and a portion of insulating layer 106 serves as a gate insulating layer (also called a first gate insulating layer). Conductive layer 202 serves as a back gate electrode (also called a second gate electrode), and a portion of insulating layer 120 serves as a back gate insulating layer (also called a second gate insulating layer). Conductive layer 212a serves as one of the source electrode and the drain electrode, and conductive layer 212b serves as the other. Each layer constituting transistor 200 can have a single-layer structure or a stacked structure. Note that transistor 200 can also be constructed without conductive layer 202.

[0123] An insulating layer 195 is provided to cover transistors 100 and 200. The insulating layer 195 serves as a protective layer for transistors 100 and 200.

[0124] exist Figure 2A In the image, the outlines of insulating layers 110 and 106 are shown with dashed lines. Insulating layer 195 is omitted. Figure 2B The normal direction of the substrate 102 surface is staggered. Figure 2A The components shown are some of the constituent elements. Additionally, in Figure 2B In the diagram, the positional relationship of conductive layer 104, semiconductor layer 108, conductive layer 112b, and conductive layer 112a in transistor 100 is shown by dashed lines. Similarly, the positional relationship of conductive layer 204, semiconductor layer 208, and conductive layer 202 in transistor 200 is shown by dashed lines.

[0125] First, the structure of transistor 100 will be explained. Figure 3A and Figure 3B Show Figure 1A and Figure 1B An enlarged view of transistor 100 is shown.

[0126] A conductive layer 112a is disposed on a substrate 102. An insulating layer 110 is disposed on the conductive layer 112a. The insulating layer 110 has regions that contact the top surface and side surfaces of the conductive layer 112a. Alternatively, the insulating layer 110 is disposed such that it covers the top surface and side surfaces of the conductive layer 112a. The insulating layer 110 has an opening 141 that reaches the conductive layer 112a. Alternatively, the conductive layer 112a is exposed by forming the opening 141.

[0127] A conductive layer 112b is disposed on the insulating layer 110. The conductive layer 112b has a region that overlaps with the conductive layer 112a across the insulating layer 110. Alternatively, the insulating layer 110 may have a region that is sandwiched between the conductive layer 112a and the conductive layer 112b. The conductive layer 112b has an opening 143 in the region that overlaps with the conductive layer 112a. The opening 143 is disposed in the region that overlaps with the opening 141.

[0128] A semiconductor layer 108 is provided to cover openings 141 and 143. The semiconductor layer 108 has a region in opening 141 that contacts the top surface of the conductive layer 112a and the side surface of the insulating layer 110, and a region in opening 143 that contacts the side surface of the conductive layer 112b. Additionally, the semiconductor layer 108 has a region that contacts the top surface of the conductive layer 112b. The semiconductor layer 108 has a shape that extends along the top and side surfaces of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a. The semiconductor layer 108 has a region that overlaps with the conductive layer 112a, separated by the conductive layer 112b and the insulating layer 110.

[0129] The semiconductor layer 108 has a region that contacts the conductive layer 112a and a region that contacts the conductive layer 112b, and is electrically connected to the conductive layer. The region of the semiconductor layer 108 that contacts the conductive layer 112a serves as one of the source region and the drain region, and the region that contacts the conductive layer 112b serves as the other. In the semiconductor layer 108, a channel forming region is provided between the source region and the drain region.

[0130] Semiconductor layer 108 preferably has regions that contact the top and side surfaces of conductive layer 112b. By adopting a structure in which semiconductor layer 108 contacts not only the side surfaces of conductive layer 112b but also its top surface, the contact area between semiconductor layer 108 and conductive layer 112b is increased, thereby reducing the contact resistance between semiconductor layer 108 and conductive layer 112b. This, in turn, increases the on-state current of transistor 100. Note that... Figure 1BThe diagram shows a structure where the end of the semiconductor layer 108 contacts the top surface of the conductive layer 112b; however, the invention is not limited to this. The semiconductor layer 108 may also cover the end of the conductive layer 112b that does not face the opening 143. The end of the semiconductor layer 108 may contact the top surface of the insulating layer 110. Alternatively, the semiconductor layer 108 may not contact the top surface of the conductive layer 112b but only contact the side surface of the conductive layer 112b on the side of the opening 143.

[0131] An insulating layer 106 is provided to cover openings 141 and 143. The insulating layer 106 is disposed on the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110. The insulating layer 106 has regions that contact the top and side surfaces of the semiconductor layer 108, the top and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110. The insulating layer 106 has a shape that extends along the top and side surfaces of the semiconductor layer 108, the top and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110.

[0132] A conductive layer 104 is disposed on an insulating layer 106 and has a region that contacts the top surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 across the insulating layer 106. The conductive layer 104 has a shape that runs along the top and side surfaces of the insulating layer 106.

[0133] Transistor 100 is a so-called top-gate transistor having a gate electrode above semiconductor layer 108. Furthermore, since the bottom surface of semiconductor layer 108 is in contact with conductive layers 112a and 112b, which serve as source and drain electrodes, it can be considered a TGBC (Top Gate Bottom Contact) type transistor. Additionally, in transistor 100, the heights of the source and drain electrodes relative to the surface of the substrate 102 on which they are formed are different, and drain current flows in a direction perpendicular to or substantially perpendicular to the surface of substrate 102. It can also be said that in transistor 100, drain current flows in the longitudinal direction or substantially the longitudinal direction. Therefore, a transistor according to one aspect of the present invention can also be described as a longitudinal channel transistor, a longitudinal transistor, or a VFET (Vertical Field Effect Transistor).

[0134] The channel length of transistor 100 can be controlled by the thickness of the insulating layer 110 disposed between conductive layers 112a and 112b. Therefore, transistors with channel lengths smaller than the minimum exposure dimensions of the exposure apparatus used for transistor manufacturing can be manufactured with high precision. Furthermore, characteristic non-uniformity among multiple transistors 100 can be reduced. Therefore, the semiconductor device including transistors 100 operates stably, and reliability can be improved. Moreover, as characteristic non-uniformity is reduced, circuit design freedom is increased, and the operating voltage of the semiconductor device can be reduced. This, in turn, reduces the power consumption of the semiconductor device.

[0135] In transistor 100, the source electrode, the layer having the channel forming region, and the drain electrode can be stacked, so the occupied area can be greatly reduced compared to a so-called planar transistor in which the layer having the channel forming region is configured as a plane.

[0136] Conductive layers 112a, 112b, and 104 can all be used as wiring, and transistor 100 can be disposed in the area where these wirings overlap. That is, in a circuit including transistor 100 and wiring, the area occupied by transistor 100 and wiring can be reduced. Therefore, a small semiconductor device can be realized by reducing the area occupied by the circuit.

[0137] Figure 1B Examples are shown where the semiconductor layer 108, insulating layer 106, and conductive layer 104 cover the openings 141 and 143 in transistor 100, but one aspect of the invention is not limited thereto. A step is formed by the conductive layer 112b and the insulating layer 110 and the conductive layer 112a, and the semiconductor layer 108, insulating layer 106, and conductive layer 104 can be disposed along the step.

[0138] Next, the structure of transistor 200 will be explained. Figures 4A to 4B Show Figures 1A to 1C An enlarged view of transistor 200 is shown.

[0139] An insulating layer 109 is disposed on an insulating layer 110, and a conductive layer 202 is disposed on the insulating layer 109. The insulating layer 109 is disposed entirely in the area where the conductive layer 202 is disposed. In a top view, the insulating layer 109 preferably includes the conductive layer 202. The end of the conductive layer 202 contacts the top surface of the insulating layer 109.

[0140] An insulating layer 120 is disposed on the conductive layer 202. The insulating layer 120 has a region that contacts the top and side surfaces of the conductive layer 202 and the top surface of the insulating layer 109. That is, the conductive layer 202 is surrounded by the insulating layer 109 and the insulating layer 120.

[0141] Figures 5A to 5D Show Figure 1B and Figure 1CAn enlarged view of regions P1 to P4, indicated by dashed lines. (See attached image.) Figures 5A to 5D As shown, the end of insulating layer 120 preferably coincides with or substantially coincides with the end of insulating layer 109. Alternatively, the top surface shape of insulating layer 120 may coincide with or substantially coincide with the top surface shape of insulating layer 109. For example, a first insulating film is formed as insulating layer 109, a conductive layer 202 is formed on the first insulating film, and a second insulating film, which becomes insulating layer 120, is formed on the first insulating film and the conductive layer 202. Furthermore, by processing the first and second insulating films, insulating layers 120 and 109 with coincident or substantially coincident ends can be formed. By forming insulating layers 109 and 120 in the same process, the productivity of the semiconductor device 10 can be improved and manufacturing costs reduced. Here, a structure in which the first and second insulating films are processed in the same process is shown, but one aspect of the invention is not limited to this. The first and second insulating films may also be processed in different processes.

[0142] Note that, although Figure 1B Examples are shown where the thickness of insulating layer 110 is uniform in all locations, but one aspect of the invention is not limited thereto. The thickness of a region of insulating layer 110 that overlaps with one or more of insulating layers 120 and 109 may differ from the thickness of a region that does not overlap with either of insulating layers 120 and 109. For example, as... Figures 6A to 6C As shown, the insulating film processed into insulating layer 120 and insulating layer 109, by removing a portion of insulating layer 110 (here, insulating layer 110c) during the formation of insulating layers 120 and 109, sometimes the thickness of the region of insulating layer 110 that does not overlap with either insulating layer 120 or insulating layer 109 is thinner than the thickness of the region that overlaps with one or more of insulating layers 120 and 109. Furthermore, when the end of insulating layer 109 contacts the top surface of conductive layer 112b, as... Figure 6D As shown, the thickness of the region of conductive layer 112b that overlaps with one or more of insulating layers 120 and 109 may differ from the thickness of the region that does not overlap with either insulating layer 120 or 109. For example, during the formation of insulating layers 120 and 109, a portion of conductive layer 112b is removed, so sometimes the thickness of the region of conductive layer 112b that does not overlap with either insulating layer 120 or 109 is thinner than the thickness of the region that overlaps with one or more of insulating layers 120 and 109.

[0143] A semiconductor layer 208 is disposed on the insulating layer 120. The semiconductor layer 208 has a region that overlaps with the conductive layer 202 across the insulating layer 120. The semiconductor layer 208 can be made of the same material as the semiconductor layer 108. Furthermore, the semiconductor layer 208 can be formed using the same process as the semiconductor layer 108. For example, semiconductor layers 108 and 208 can be formed by forming a film that becomes semiconductor layer 108 and semiconductor layer 208 and processing that film.

[0144] The insulating layer 120 is preferably disposed at least in the region overlapping with the channel formation region of the transistor 200. Furthermore, as described above, the end of the insulating layer 120 preferably coincides with or substantially coincides with the end of the insulating layer 109. Additionally, in Figure 1B In this configuration, a portion of the end of the insulating layer 109 contacts the top surface of the insulating layer 110, while the other ends contact the top surface of the conductive layer 112b. The semiconductor layer 208 covers a portion of the sides of the insulating layer 120 and the insulating layer 109. That is, the semiconductor layer 208 has a portion protruding beyond the ends of the insulating layers 120 and 109. A portion of the end of the semiconductor layer 208 contacts the top surface of the insulating layer 110, while the other portion contacts the top surface of the insulating layer 120. Alternatively, a portion of the bottom surface of the semiconductor layer 208 contacts the top surface of the insulating layer 120, while the other portion contacts the top surface of the insulating layer 110. Alternatively, the insulating layer 120 may be disposed in the entire area where the semiconductor layer 208 is located, with the entire bottom surface of the semiconductor layer 208 contacting the top surface of the insulating layer 120.

[0145] Preferably, no other layers (especially conductive layers) are formed between the formation of the insulating layer 120 and the formation of the semiconductor layer 208. Specifically, it is preferable to form the conductive layer 112b, the insulating layer 109, the conductive layer 202, the insulating layer 120, and the semiconductor layer 208 sequentially. This prevents components contained in the conductive layer (e.g., the metal contained in the conductive layer 112b) from adhering to the interface between the insulating layer 120 and the semiconductor layer 208, thereby enabling the transistor 200 to exhibit good electrical characteristics and high reliability.

[0146] By forming an insulating layer 109 after forming a conductive layer 112b, such as Figure 1C As shown, the insulating layer 109 can be in contact with at least the side surface of the conductive layer 112b. Furthermore, the insulating layer 109 can also be in contact with the top surface of the conductive layer 112b. Note that the insulating layer 109 may also not have a region in contact with the conductive layer 112b.

[0147] like Figure 1CAs shown, insulating layers 109 and 120 preferably do not contact the semiconductor layer 108. Specifically, insulating layers 109 and 120 are preferably not disposed between the semiconductor layer 108 and the conductive layer 112b. When one or both of insulating layers 109 and 120 are disposed between the semiconductor layer 108 and the conductive layer 112b, the contact area between the semiconductor layer 108 and the conductive layer 112b may decrease, while the contact resistance between the semiconductor layer 108 and the conductive layer 112b may increase. By not disposing of insulating layers 109 and 120 between the semiconductor layer 108 and the conductive layer 112b, the on-state current can be increased. Note that a structure is shown here where the end of insulating layer 120 coincides with or substantially coincides with the end of insulating layer 109, but one aspect of the invention is not limited to this. The end of insulating layer 120 may also not coincide with the end of insulating layer 109. Note that even in this case, insulating layers 109 and 120 preferably do not contact the semiconductor layer 108.

[0148] An insulating layer 106 is disposed on the semiconductor layer 208. A portion of the insulating layer 106 serves as the gate insulating layer of the transistor 100, and another portion of the insulating layer 106 serves as the gate insulating layer of the transistor 200. The insulating layer 106 has openings 147a and 147b in the region overlapping with the semiconductor layer 208.

[0149] A conductive layer 204, a conductive layer 212a, and a conductive layer 212b are disposed on an insulating layer 106. The conductive layer 204 has a region that overlaps with the semiconductor layer 208 across the insulating layer 106. Additionally, the conductive layer 204 has a region that overlaps with the conductive layer 202 across the semiconductor layer 208. The conductive layers 212a and 212b are disposed to cover a portion of the openings 147a and 147b. The conductive layer 212a has a region that contacts the semiconductor layer 208 in the opening 147a, and the conductive layer 212b has a region that contacts the semiconductor layer 208 in the opening 147b. The semiconductor layer 208 is electrically connected to the conductive layers 212a and 212b. The conductive layers 204, 212a, and 212b can be made of the same material as the conductive layer 104. Furthermore, the conductive layers 204, 212a, and 212b can be formed using the same process as the conductive layer 104. For example, by forming a film that becomes conductive layer 104, conductive layer 204, conductive layer 212a and conductive layer 212b and processing the film, conductive layer 104, conductive layer 204, conductive layer 212a and conductive layer 212b can be formed.

[0150] The conductive layer 202, which serves as the back gate electrode of the transistor 200, preferably extends beyond the end of the region where the conductive layer 204 overlaps with the semiconductor layer 208 in the channel length direction. That is, the size of the conductive layer 202 is preferably larger than the size of the region where the conductive layer 204 overlaps with the semiconductor layer 208 in the channel length direction. Specifically, the conductive layer 202 preferably has a portion that protrudes beyond the end of the conductive layer 204 in the channel length direction.

[0151] The portion of semiconductor layer 208 that overlaps with at least one of conductive layers 204 and 202 is used as a channel formation region. Semiconductor layer 208 has a pair of regions 208L that clamp the channel formation region and a pair of regions 208D that are outside the region. Note that, for ease of explanation, the portion of semiconductor layer 208 that overlaps with conductive layer 204 is sometimes referred to as the channel formation region, but the portion that does not overlap with conductive layer 204 but overlaps with conductive layer 202 (including regions 208L and 208D) may also be used as the channel formation region.

[0152] Regions 208L and 208D contain impurity elements. These impurity elements may be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Typical examples of noble gases include helium, neon, argon, krypton, and xenon. One or more of boron, phosphorus, aluminum, magnesium, and silicon are particularly preferred as impurity elements.

[0153] Conductive layers 204, 212a, and 212b are used as masks to supply (also called add or implant) impurity elements to semiconductor layer 208. Thus, in semiconductor layer 208, region 208D is formed in a region that does not overlap with any of the conductive layers 204, 212a, 212b, and insulating layer 106, and region 208L is formed in a region that does not overlap with any of the conductive layers 204, 212a, and 212b but overlaps with insulating layer 106.

[0154] The region of semiconductor layer 208 that contacts conductive layer 212a and the region 208D adjacent to that region are used as one of the source region and the drain region. The region of semiconductor layer 208 that contacts conductive layer 212b and the region 208D adjacent to that region are used as the other of the source region and the drain region.

[0155] Transistor 200 is a planar transistor in which the semiconductor layer 208 is configured as a plane. Transistor 200 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 208. For example, by supplying impurity elements to the semiconductor layer 208 using the conductive layer 204 serving as the gate electrode as a mask, regions 208D serving as source and drain regions can be formed in a self-aligned manner. Transistor 200 can be described as a TGSA (Top Gate Self-Aligned) type transistor.

[0156] The channel length of transistor 200 can be controlled by the length of conductive layer 204. Therefore, the channel length of transistor 200 is greater than the minimum size of the exposure apparatus used to manufacture the transistor. That is, the channel length of transistor 200 can be larger than that of transistor 100. By increasing the channel length, transistors with high saturation can be achieved.

[0157] Transistors 100 with short channel lengths and transistors 200 with long channel lengths can share some processing steps and be formed on the same substrate. For example, transistor 100 can be used as a transistor that requires a large on-state current, while transistor 200 can be used as a transistor that requires high saturation, thereby obtaining a high-performance semiconductor device.

[0158] For example, when a semiconductor device according to one aspect of the present invention is used in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, thereby enabling a high-definition display device. Furthermore, for example, when a semiconductor device according to one aspect of the present invention is used in the driving circuit of a display device (e.g., one or both of a gate line driving circuit and a source line driving circuit), the occupied area of ​​the driving circuit can be reduced, thereby enabling a display device with a narrow bezel.

[0159] The detailed structures of transistors 100 and 200 are described.

[0160] There are no particular limitations on the semiconductor materials used for semiconductor layers 108 and 208. For example, semiconductors composed of a single element or compound semiconductors can be used. Examples of semiconductors composed of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. In addition, examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). These semiconductor materials may also contain impurities as dopants.

[0161] There are no particular restrictions on the crystallinity of the semiconductor materials used for semiconductor layer 108 and semiconductor layer 208; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with a portion of crystalline regions) can be used. When using single-crystal semiconductors or crystalline semiconductors, the degradation of transistor characteristics can be suppressed, so they are preferred.

[0162] Both semiconductor layer 108 and semiconductor layer 208 can use silicon. Examples of silicon include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. For example, low-temperature polycrystalline silicon (LTPS) can be used as polycrystalline silicon. Transistors using amorphous silicon as the channel formation region can be formed on large glass substrates and can be manufactured at low cost. Transistors using polycrystalline silicon in the channel formation region have high field-effect mobility and can operate at high speeds. Furthermore, compared to transistors using amorphous silicon, transistors using microcrystalline silicon in the channel formation region have higher field-effect mobility and can operate at high speeds.

[0163] Semiconductor layer 108 and semiconductor layer 208 preferably both contain metal oxides (also known as oxide semiconductors) that exhibit semiconductor properties.

[0164] The band gap of the metal oxides used in semiconductor layer 108 and semiconductor layer 208 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.

[0165] The band gap of metal oxides can be evaluated using optical methods such as spectrophotometry, spectral ellipsometrics, photoluminescence, X-ray photoelectron spectroscopy (XPS or ESCA, Electron Spectrometry for Chemical Analysis), or X-ray absorption fine structure (XAFS). Alternatively, a combination of these methods can be used. The electron affinity, or conduction band bottom, can be calculated from the ionization potential, which is the difference between the vacuum level and the valence band top energy, and the band gap. The ionization potential can be evaluated, for example, using ultraviolet photoelectron spectroscopy (UPS).

[0166] Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have a very high field-effect mobility. Furthermore, OS transistors have extremely low off-state currents, allowing them to retain the charge stored in the capacitor connected in series with the transistor for extended periods. In addition, using OS transistors can reduce the power consumption of semiconductor devices.

[0167] As the insulating layer 110, one or both of inorganic and organic insulating layers can be used. Examples of materials suitable for organic insulating layers include acrylic resin and polyimide resin. The insulating layer 110 preferably comprises one or more inorganic insulating layers. Examples of materials suitable for inorganic insulating layers include oxides, nitrides, oxynitrides, and oxynitrides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of oxynitrides include silicon oxynitride and aluminum oxynitride.

[0168] Note that in this specification, etc., oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content in their composition. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content in their composition.

[0169] The insulating layer 110 has a region that contacts the semiconductor layer 108. When a metal oxide is used as the semiconductor layer 108, at least a portion of the region of the insulating layer 110 that contacts the semiconductor layer 108 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the portion of the insulating layer 110 that contacts the channel forming region of the semiconductor layer 108 preferably contains oxygen. The portion of the insulating layer 110 that contacts the channel forming region of the semiconductor layer 108 may suitably use one or more of oxides and oxynitrides.

[0170] The insulating layer 110 preferably has a laminated structure. Figure 1B Examples are shown of insulating layer 110 including insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b. Insulating layer 110a, insulating layer 110b, and insulating layer 110c can be made of materials exemplified as insulating layer 110.

[0171] Insulating layers 110a, 110b, and 110c can be formed, for example, by sputtering or plasma-enhanced chemical vapor deposition (PECVD). Preferably, the flow rate of hydrogen-containing gas (e.g., hydrogen and ammonia) in the overall deposition gas used to form the layers is low, or the partial pressure of this gas in the processing chamber of the deposition apparatus is low. This reduces the hydrogen content of insulating layers 110a, 110b, and 110c. Furthermore, by using a method that does not use hydrogen-containing gas, the hydrogen content of the layers can be kept extremely low. The layers can be formed using sputtering. By reducing the hydrogen content of insulating layers 110a, 110b, and 110c, the supply of hydrogen to the channel formation region can be suppressed, thereby stabilizing the electrical characteristics of the transistor 100.

[0172] The region of semiconductor layer 108 that contacts insulating layer 110b serves as a channel formation region. Insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. For example, insulating layer 110b preferably contains silicon and oxygen. Specifically, insulating layer 110b may suitably use one or both of silicon oxide and silicon oxynitride.

[0173] More preferably, the insulating layer 110b is a film that releases oxygen when heated. Because the insulating layer 110b releases oxygen due to the heat applied during the manufacturing process of the transistor 100, oxygen can be supplied to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, especially to the channel formation region, oxygen vacancies (V0) are reduced. O ) are filled, thereby reducing oxygen vacancies (V) O Additionally, it can reduce V. O H. Thus, a transistor 100 exhibiting good electrical characteristics and high reliability can be realized.

[0174] For example, oxygen can be supplied to the insulating layer 110b by heating or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied by forming an oxide film on the top surface of the insulating layer 110b in an oxygen-containing atmosphere using sputtering. This oxide film can then be removed. Furthermore, the method for supplying oxygen to the insulating layer 110b will be described in Embodiment 2.

[0175] In the insulating layer 110b, it is preferable that the material (e.g., atoms, molecules, and ions) diffuses easily. In other words, the diffusion coefficient of the material in the insulating layer 110b is preferably large. In particular, it is preferable that oxygen diffuses easily in the insulating layer 110b. In other words, the oxygen diffusion coefficient in the insulating layer 110b is preferably large. Oxygen diffuses in the insulating layer 110b and is supplied to the semiconductor layer 108 through the interface between the insulating layer 110b and the semiconductor layer 108. By using the oxygen-diffuse insulating layer 110b, oxygen in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (especially the channel formation region).

[0176] In semiconductor layer 108, the region in contact with conductive layer 112a is used as one of the source and drain regions of transistor 100, and the region in contact with conductive layer 112b is used as the other. The source and drain regions are regions with lower resistance compared to the channel formation region. The source and drain regions can also be described as regions with higher carrier concentration and higher oxygen defect density compared to the channel formation region.

[0177] An insulating layer 110a is disposed between an insulating layer 110b and a conductive layer 112a. An insulating layer 110c is disposed between an insulating layer 110b and a conductive layer 112b. The amount of impurities (e.g., hydrogen and water) released from each of the insulating layers 110a and 110c is preferably minimal. Furthermore, both the insulating layers 110a and 110c are preferably impermeable to substances. In other words, the insulating layers 110a and 110c are used as barrier films. Specifically, both the insulating layers 110a and 110c are preferably impermeable to impurities. Therefore, the diffusion of impurities contained in the insulating layers 110a and 110c into the channel formation region of the semiconductor layer 108 can be suppressed. Thus, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0178] Both insulating layers 110a and 110c are preferably made of materials that are not easily permeable to oxygen. This suppresses the diffusion of oxygen contained in insulating layer 110b through insulating layer 110a to the conductive layer 112a side. Similarly, it suppresses the diffusion of oxygen contained in insulating layer 110b through insulating layer 110c to the conductive layer 112b side. Consequently, the amount of oxygen supplied from insulating layer 110b to the channel formation region of semiconductor layer 108 increases, thereby reducing the oxygen vacancies (V) in the channel formation region. O ) and hydrogen entering oxygen vacancies (V O The defect of (hereinafter also referred to as V) OH). Therefore, transistors exhibiting good electrical characteristics and high reliability can be realized. Furthermore, the increase in resistance of conductive layer 112a due to oxidation of conductive layer 112a caused by oxygen contained in insulating layer 110b can be suppressed. Similarly, the increase in resistance of conductive layer 112b due to oxidation of conductive layer 112b caused by oxygen contained in insulating layer 110b can be suppressed. Therefore, transistors with large on-state current can be realized.

[0179] Furthermore, in this specification and the like, a barrier film refers to a film that has barrier properties. Barrier properties refer to one or both of the functions of inhibiting the diffusion of a substance through the membrane (also known as low permeability) and trapping or fixing the substance (also known as gettering). For example, an insulating layer with barrier properties can be referred to as a barrier insulating layer.

[0180] The insulating layers 110a and 110c used as the barrier film can, for example, be one or more of oxides containing one or both of aluminum and hafnium, oxides containing magnesium, oxides containing gallium, nitrides containing silicon, and oxide oxynitrides containing silicon. Specifically, the insulating layers 110a and 110c can suitably be one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon oxynitride. Furthermore, the insulating layers 110a and 110c can be made of the same material. By using the same material, the apparatus used for forming can be shared, thus increasing productivity and reducing manufacturing costs. Alternatively, the insulating layers 110a and 110c can also be made of different materials.

[0181] Note that in this specification, etc., different materials refer to materials whose constituent elements are partially or completely different, or materials whose constituent elements are the same but whose composition is different.

[0182] The insulating layers 110a and 110c are more preferably formed using a method that does not use a gas containing hydrogen atoms. The insulating layers 110a and 110c can be formed, for example, by sputtering. The insulating layers 110a and 110c are particularly preferably formed using one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and zinc gallium oxide.

[0183] The insulating layer 110c disposed on the insulating layer 110b is more preferably formed in an oxygen-containing atmosphere. Therefore, oxygen can be supplied to the insulating layer 110b during the formation of the insulating layer 110c. The insulating layer 110c is particularly preferably made of an oxygen-containing material. The higher the proportion of oxygen gas flow rate in the overall deposition gas used to form the insulating layer 110c (hereinafter also referred to as the oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber of the deposition apparatus, the more efficiently oxygen can be supplied to the insulating layer 110b.

[0184] The thickness T110a of the insulating layer 110a is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, more preferably 20 nm or more and 300 nm or less, more preferably 50 nm or more and 300 nm or less, more preferably 100 nm or more and 300 nm or less, more preferably 100 nm or more and 250 nm or less, and more preferably 150 nm or more and 250 nm or less. For example... Figure 3B As shown, the thickness T110a can be the shortest distance between the surface of the insulating layer 110a that is formed (in this case, the top surface of the conductive layer 112a) and the top surface of the insulating layer 110a when viewed from the cross section.

[0185] When the thickness T110a of the insulating layer 110a is thin, oxygen contained in the insulating layer 110b may diffuse through the insulating layer 110a to the conductive layer 112a side, reducing the amount of oxygen supplied to the channel formation region. When the thickness T110a is thick, the amount of impurities released from the insulating layer 110a may increase, leading to an increase in the amount of impurities diffusing into the channel formation region. By setting the thickness T110a within the aforementioned range, the amount of oxygen supplied to the channel formation region can be increased, thereby reducing the oxygen vacancies (V) in the channel formation region. O ) and V O H. Furthermore, the increase in resistance of the conductive layer 112a due to oxidation of the conductive layer 112a caused by oxygen contained in the insulating layer 110b can be suppressed. Note that the thickness T110a is not limited to the range described above.

[0186] The thickness T110c of the insulating layer 110c is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, more preferably 20 nm or more and 300 nm or less, more preferably 20 nm or more and 200 nm or less, more preferably 30 nm or more and 200 nm or less, more preferably 50 nm or more and 200 nm or less, and more preferably 50 nm or more and 150 nm or less. Figure 3B As shown, the thickness T110c can be the shortest distance between the surface of the insulating layer 110c that is formed (in this case, the top surface of the insulating layer 110b) and the top surface of the insulating layer 110c when viewed from the cross section.

[0187] When the thickness T110c of the insulating layer 110c is relatively thick, the amount of impurities released from the insulating layer 110c may increase, leading to an increase in the amount of impurities diffusing into the channel formation region. On the other hand, when the thickness T110c is relatively thin, oxygen contained in the insulating layer 110b may diffuse through the insulating layer 110c to the conductive layer 112b side, reducing the amount of oxygen supplied to the channel formation region. By setting the thickness T110c within the aforementioned range, the oxygen vacancies (V) in the channel formation region can be reduced. O) and V O H. Furthermore, it can suppress the increase in resistance of the conductive layer 112b due to oxidation of the conductive layer 112b caused by oxygen contained in the insulating layer 110b. Note that the thickness T110c is not limited to the range described above.

[0188] The thickness T110a of the insulating layer 110a can be thicker than the thickness T110c of the insulating layer 110c. When the region of the semiconductor layer 108 in contact with the insulating layer 110a is used as a source region or a drain region, increasing the thickness T110a can make the distance from the source region or drain region to the gate electrode more uniform. This further makes the electric field applied to the gate electrode in the channel formation region more uniform. Note that there are no particular limitations on the relationship between the thicknesses T110a and T110c.

[0189] Note that when the channel length of transistor 100 is short, the influence of impurities diffusing into the channel formation region increases. Therefore, insulating layers 110a and 110c are preferably made of materials that release less impurities (especially hydrogen) from the material itself. Furthermore, it is more preferable that insulating layers 110a and 110c are thin. This reduces the amount of impurities diffusing into the channel formation region, thereby enabling transistor 100 to exhibit good electrical characteristics and high reliability even with a short channel length. For example, when the channel length is 500 nm or less, the thicknesses T110a and T110c of insulating layers 110a and 110c are preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, more preferably 3 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less, and more preferably 5 nm or more and 10 nm or less.

[0190] At least one of the regions of semiconductor layer 108 that contact insulating layer 110a and insulating layer 110c can also be regions with low resistance compared to the channel formation region (hereinafter also referred to as low resistance regions). This region can also be described as a region with high carrier concentration and high oxygen vacancy density compared to the channel formation region. As described above, there is a concern that excessive impurities may diffuse into the channel formation region when too much impurity is released from insulating layers 110a and 110c. Preferably, when impurity-releasing materials are used as insulating layers 110a and 110c, the amount of impurities released is also preferably minimal.

[0191] Here, the insulating layer 110 is shown to have a three-layer stacked structure, but the invention is not limited to this. The insulating layer 110 preferably includes at least an insulating layer 110b. Alternatively, one or more of the insulating layers 110a and 110c may not be provided. Alternatively, the insulating layer 110 may also have a single-layer structure, a two-layer structure, or a stacked structure with four or more layers.

[0192] The insulating layer 109 disposed between the conductive layer 112b and the conductive layer 202 has the function of insulating the conductive layer 112b from the conductive layer 202. The insulating layer 109 can be made of a material that can be used for the insulating layer 110.

[0193] More preferably, the insulating layer 109, which has regions in contact with both conductive layer 112b and conductive layer 202, is made of a material that releases impurities that reduce the resistance of conductive layer 112b and conductive layer 202. For example, when a metal oxide is used for conductive layer 112b, the impurity more preferably contains hydrogen atoms. Examples of such impurities include water and hydrogen. Therefore, the carrier concentration of conductive layer 112b increases, and the resistance is reduced. This allows for the realization of transistors with high on-state current. In addition, conductive layer 112b can be used as wiring, thereby enabling semiconductor devices with low wiring resistance. Similarly, when a metal oxide is used for conductive layer 202, the impurity more preferably contains hydrogen atoms. Furthermore, the impurities that reduce the resistance of conductive layer 112b and conductive layer 202 can be the same, partially different, or completely different. For example, silicon nitride or silicon oxynitride can be used for insulating layer 109.

[0194] An insulating layer 110c is disposed between insulating layer 109 and insulating layer 110b. By using insulating layer 110c as a barrier film, impurities contained in insulating layer 109 can be suppressed from diffusing through insulating layers 110c and 110b to the channel formation region of semiconductor layer 108. Insulating layer 109 preferably has a region with a higher impurity content than insulating layer 110c. Specifically, insulating layer 109 preferably has a region with a higher hydrogen content than insulating layer 110c. In analyzing the impurity content of insulating layers 109 and 110c, secondary ion mass spectrometry (SIMS) can be used, for example. Furthermore, insulating layer 120 preferably includes a barrier insulating layer. This suppresses the diffusion of impurities contained in insulating layer 109 through insulating layer 120 to the channel formation region of semiconductor layer 208.

[0195] There are no restrictions on the shape of the top surface of openings 141 and 143. For example, they can be circular, elliptical, triangular, quadrilateral (including rectangles, rhombuses, and squares), pentagonal, or other polygonal shapes with rounded corners. The polygon can also be a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). Figure 1AAs shown, the top surface shapes of both openings 141 and 143 are preferably circular. By making the top surface shape of the opening circular, the machining accuracy during the formation of the opening can be improved, and fine openings can be formed. Note that in this specification, the circular shape is not limited to a perfect circle.

[0196] In this specification, the top surface shape of the opening 141 refers to the shape of the top surface end of the opening 141 side of the insulating layer 110. Furthermore, the top surface shape of the opening 143 refers to the shape of the bottom surface end of the opening 143 side of the conductive layer 112b.

[0197] like Figure 1A As shown, the top surface shape of the opening 141 can be made the same as or substantially the same as the top surface shape of the opening 143. In this case, as... Figure 1B and Figure 1C As shown, the bottom end of the conductive layer 112b on the side of the opening 143 preferably coincides with or substantially coincides with the top end of the insulating layer 110 on the side of the opening 141. The bottom surface of the conductive layer 112b refers to the surface on the side of the insulating layer 110. The top surface of the insulating layer 110 refers to the surface on the side of the conductive layer 112b.

[0198] Furthermore, the top surface shape of opening 141 and the top surface shape of opening 143 may not be the same. Additionally, when the top surface shapes of opening 141 and opening 143 are circular, opening 141 and opening 143 may be concentric circles. Note that they may also not be concentric circles.

[0199] Reference Figure 3A and Figure 3B The channel length and channel width of transistor 100 will be explained. Here, the case where the region of semiconductor layer 108 that contacts insulating layer 110b is used as the channel formation region will be explained as an example.

[0200] exist Figure 3BIn the diagram, the channel length L100 of transistor 100 is indicated by a dashed double arrow. The channel length L100 of transistor 100 is equivalent to the length of the side surface of the opening 141 of the insulating layer 110b in cross-section. That is, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110 formed by the side surface of the insulating layer 110b (the top surface of the insulating layer 110a) with the surface on which the insulating layer 110b is formed. Therefore, the channel length L100 can be made smaller than the minimum size of the exposure apparatus, thereby enabling the realization of miniaturized transistors. Specifically, transistors with extremely small channel lengths that cannot be achieved by the exposure apparatuses used in the mass production of existing flat panel displays (e.g., with a minimum size of approximately 2 μm or 1.5 μm) can be realized. Furthermore, transistors with channel lengths less than 10 nm can be achieved without the very expensive exposure apparatuses used in state-of-the-art LSI technologies.

[0201] The channel length L100 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, less than 2.5 μm, less than 2 μm, less than 1.5 μm, less than 1.2 μm, less than 1 μm, less than 500 nm, less than 300 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 30 nm, or less than 20 nm. For example, the channel length L100 can also be set to 100 nm or more and less than 1 μm.

[0202] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. Using the transistor 100, circuits capable of high-speed operation can be manufactured. Furthermore, the circuit's footprint can be reduced. Therefore, a miniaturized semiconductor device can be realized. For example, in the case of a semiconductor device according to one aspect of the present invention used in a large display device or a high-definition display device, the signal delay of each wiring can be reduced even when the number of wirings increases, thereby suppressing display unevenness. In addition, since the circuit's footprint can be reduced, the bezel of the display device can be reduced.

[0203] The channel length L100 can be controlled by adjusting the thickness T110b of the insulating layer 110b and the angle θ110. Note that in Figure 3B In the diagram, the thickness T110b of the insulating layer 110b is indicated by a double-headed arrow with a dotted line.

[0204] The thickness T110b of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. The thickness T110b can be appropriately set to obtain the desired channel length L100.

[0205] The side of the opening 141 of the insulating layer 110 is preferably tapered. The angle θ110 is preferably less than 90 degrees. By reducing the angle θ110, the coverage of the layer (e.g., semiconductor layer 108) formed on the insulating layer 110 can be improved. In addition, the smaller the angle θ110, the longer the channel length L100 can be, and the larger the angle θ110, the shorter the channel length L100 can be.

[0206] Angle θ110 can be, for example, greater than 30 degrees, greater than 35 degrees, greater than 40 degrees, greater than 45 degrees, greater than 50 degrees, greater than 55 degrees, greater than 60 degrees, greater than 65 degrees, or greater than 70 degrees but less than 90 degrees, less than 85 degrees, or less than 80 degrees. Angle θ110 can also be less than 75 degrees, less than 70 degrees, less than 65 degrees, or less than 60 degrees. Angle θ110 can be appropriately set to obtain the desired channel length L100.

[0207] Note that in Figure 3B In the above, angle θ110 is less than 90 degrees, but one aspect of the present invention is not limited to this. For example... Figure 7 As shown, the angle θ110 can also be 90 degrees or approximately 90 degrees. This can shorten the channel length L100 of the transistor 100.

[0208] exist Figure 3B In the present invention, the side surface of the insulating layer 110 with opening 141 is straight when viewed in cross-section; however, this is not the only embodiment of the invention. The side surface of the insulating layer 110 with opening 141 can be curved when viewed in cross-section. Alternatively, it can have both a region with a straight side surface and a region with a curved side surface.

[0209] Here, the conductive layer 112b is preferably not disposed inside the opening 141. Specifically, the conductive layer 112b is preferably not in contact with the side of the insulating layer 110 at the opening 141. In particular, the conductive layer 112b is preferably not in contact with the side of the insulating layer 110b at the opening 141. When the conductive layer 112b is also disposed inside the opening 141 and the conductive layer 112b is in contact with the side of the insulating layer 110b, sometimes the channel length L100 of the transistor 100 is shorter than the length of the side of the insulating layer 110b, making it difficult to control the channel length L100. Therefore, it is preferable that the top surface shape of the opening 143 is the same as the top surface shape of the opening 141, or that the opening 143 includes the opening 141 when viewed from above.

[0210] exist Figure 3A and Figure 3B In the diagram, a double-headed solid arrow indicates the channel width W100 of transistor 100. The channel width W100 is the length of the side surface of the opening 141 of insulating layer 110b. Additionally, a double-headed double-dotted arrow indicates the width D141 of opening 141. When the top surface of opening 141 is circular, the width D141 is equivalent to the diameter of the circle, and the channel width W100 of transistor 100 is equivalent to the circumference of the circle. That is, the channel width W100 is π × D141. Thus, when the top surface of opening 141 is circular, a transistor with a smaller channel width W100 can be achieved compared to other shapes.

[0211] The width D141 of the opening 141 sometimes varies in the depth direction. For example, the width D141 of the opening 141 can be the average of the diameters of the highest, lowest, and midpoints of the insulating layer 110b (or insulating layer 110) in cross-section. Alternatively, the diameter of the opening 141 can be any one of the diameters of the highest, lowest, or midpoints of the insulating layer 110b (or insulating layer 110) in cross-section. Figure 3B In the figure, the width D141 represents the diameter of the highest position of the insulation layer 110b when viewed from the cross section.

[0212] When the opening 141 is formed using photolithography, the width D141 of the opening 141 is greater than or equal to the minimum size of the exposure apparatus. For example, the width D141 can be 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more and less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

[0213] Here, the structure described is based on the example of a channel formation region being used as the area of ​​the semiconductor layer 108 in contact with the insulating layer 110b; however, the present invention is not limited to this. The area of ​​the semiconductor layer 108 in contact with the insulating layer 110a can also be used as a channel formation region. Similarly, the area in contact with the insulating layer 110c can also be used as a channel formation region.

[0214] Figure 8A and Figure 8B A cross-sectional view of a semiconductor device 10 having a structure different from the insulating layer 110 described above is shown. For a top view of the semiconductor device 10, please refer to... Figure 1A . Figure 8A It is along Figure 1A The cross-sectional view of the section along the dotted line A1-A2 shown is shown. Figure 8B It is a cross-sectional view of the section along the dotted line B1-B2.

[0215] The semiconductor device 10 includes transistor 100, transistor 200, insulating layer 110, and insulating layer 109. Figure 8C Show Figure 8A An enlarged view of transistor 100 is shown.

[0216] Figure 8A Examples are shown where the insulating layer 110 includes an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c.

[0217] An insulating layer 110d is disposed between an insulating layer 110a and a conductive layer 112a. An insulating layer 110e is disposed between an insulating layer 110c and a conductive layer 112b. Insulating layers 110d and 110e are preferably made of materials that release impurities (e.g., water and hydrogen) that reduce the resistance of the semiconductor layer 108. Insulating layers 110d and 110e can use the materials listed in the description of insulating layers 110a and 110c. For example, silicon nitride or silicon oxynitride can be suitably used for insulating layers 110d and 110e. Note that insulating layers 110a, 110c, 110d, and 110e can use the same material. Alternatively, some or all of insulating layers 110a, 110c, 110d, and 110e can use different materials.

[0218] By using a material that releases impurities (such as water and hydrogen) as the insulating layer 110d, the region of the semiconductor layer 108 in contact with the insulating layer 110d can be used as a low-resistance region. The semiconductor layer 108 can also have a structure with a low-resistance region between the region in contact with the conductive layer 112a (one of the source and drain regions) and the channel formation region. Similarly, by using a material that releases impurities as the insulating layer 110e, the region of the semiconductor layer 108 in contact with the insulating layer 110e can be used as a low-resistance region. The semiconductor layer 108 can also have a structure with a low-resistance region between the region in contact with the conductive layer 112b (the other of the source and drain regions) and the channel formation region. The low-resistance region can serve as a buffer region to mitigate the drain electric field. Note that these low-resistance regions can also be used as either source or drain regions.

[0219] By providing a low-resistance region between the drain region and the channel formation region, a high electric field is less likely to be generated near the drain region, thus suppressing the generation of hot carriers and thereby suppressing transistor degradation. For example, when conductive layer 112a is used as the drain electrode and conductive layer 112b is used as the source electrode, by using the region of semiconductor layer 108 in contact with insulating layer 110d as a low-resistance region, a high electric field is less likely to be generated near the drain region, suppressing the generation of hot carriers and thus suppressing transistor degradation. When conductive layer 112a is used as the source electrode and conductive layer 112b is used as the drain electrode, by using the region of semiconductor layer 108 in contact with insulating layer 110e as a low-resistance region, a high electric field is less likely to be generated near the drain region, suppressing the generation of hot carriers and thus suppressing transistor degradation.

[0220] When the region of the semiconductor layer 108 that contacts the insulating layer 110d is used as a source region or a drain region, the distance from the source region to the gate electrode and the distance from the drain region to the gate electrode of the semiconductor layer 108 can be further made uniform. As a result, the electric field applied to the gate electrode in the channel formation region can be further made uniform.

[0221] The thickness T110d of insulating layer 110d and the thickness T110e of insulating layer 110e are preferably, for example, 30 nm or more and 300 nm or less, more preferably 30 nm or more and 200 nm or less, more preferably 30 nm or more and 150 nm or less, more preferably 50 nm or more and 150 nm or less, more preferably 70 nm or more and 150 nm or less, and more preferably 70 nm or more and 120 nm or less. Figure 8CAs shown, the thickness T110d can be the shortest distance between the formed surface of the insulating layer 110d (in this case, the top surface of the conductive layer 112a) and the top surface of the insulating layer 110d when viewed from a cross-section. The thickness T110e can be the shortest distance between the formed surface of the insulating layer 110e (in this case, the top surface of the insulating layer 110c) and the top surface of the insulating layer 110e when viewed from a cross-section. Note that the thicknesses T110d and T110e are not limited to the ranges described above. Furthermore, there are no particular restrictions on the relationship between the thicknesses T110d and T110e.

[0222] When the thickness T110d of the insulating layer 110d is relatively thick, sometimes the amount of impurities released from the insulating layer 110d increases, and the amount of impurities diffusing into the channel formation region also increases. On the other hand, when the thickness T110d is relatively thin, sometimes the amount of impurities diffusing into the region of the semiconductor layer 108a that contacts the insulating layer 110d decreases, and the resistance of this region increases. The same applies to the thickness T110e of the insulating layer 110e. By setting the thicknesses T110d and T110e within the aforementioned ranges, oxygen vacancies (V0) in the channel formation region can be suppressed. O ) and V O The increase of H can create a low-resistance region between the source and drain regions and the channel formation region.

[0223] The insulating layer 110d in contact with the conductive layer 112a is preferably made of a material that releases impurities that reduce the resistance of the conductive layer 112a. Similarly, the insulating layer 110e in contact with the conductive layer 112b is preferably made of a material that releases impurities that reduce the resistance of the conductive layer 112b. Examples of such impurities include water and hydrogen. This reduces the resistance of both the conductive layer 112a and the conductive layer 112b, enabling the realization of a transistor with a large on-state current. For example, when a metal oxide is used in the conductive layer 112a, the impurity more preferably contains hydrogen atoms. This increases the carrier concentration in the conductive layer 112a, reducing its resistance. The same applies to the conductive layer 112b. Furthermore, the conductive layers 112a and 112b can be used for wiring, enabling the realization of a semiconductor device with low wiring resistance. Note that the impurities that reduce the resistance of the conductive layers 112a, 112b, and semiconductor layer 108 can be the same or partially or completely different.

[0224] By providing an insulating layer 110a between insulating layers 110d and 110b, impurities released from insulating layer 110d can be suppressed from diffusing through insulating layers 110a and 110b into the channel formation region of semiconductor layer 108. This allows for the realization of a transistor 100 exhibiting good electrical characteristics and high reliability.

[0225] The insulating layer 110d preferably has regions with a higher impurity content than the insulating layer 110a. Specifically, the insulating layer 110d preferably has regions with a higher hydrogen content than the insulating layer 110a. In the analysis of the impurity content of the insulating layers 110d and 110a, secondary ion mass spectrometry (SIMS) can be used, for example.

[0226] When the same material is used for insulating layers 110d and 110a, the amount of impurities released can be adjusted by changing the deposition conditions. Specifically, one or more of the following can be varied between insulating layers 110d and 110a: deposition power (deposition power density), deposition pressure, type of deposition gas, deposition gas flow rate ratio, deposition temperature, and distance between the substrate and the electrode. For example, by making the deposition power density of insulating layer 110d lower than that of insulating layer 110a, the impurity content in insulating layer 110d can be higher than the hydrogen content in insulating layer 110a. This increases the amount of impurities released from insulating layer 110d itself due to the heat applied to it.

[0227] The flow rate of hydrogen-containing gas in the overall deposition gas used to form insulating layer 110d is preferably greater than the flow rate of hydrogen-containing gas in the overall deposition gas used to form insulating layer 110a. Specifically, it is preferable that when forming silicon nitride or silicon oxynitride films in insulating layers 110d and 110a respectively using PECVD, the proportion of ammonia gas flow rate in the overall deposition gas used to form insulating layer 110d (hereinafter also referred to as the ammonia flow rate ratio) is higher than the ammonia flow rate ratio of the deposition gas used to form insulating layer 110a. By forming insulating layer 110d under conditions of a high ammonia flow rate ratio, the hydrogen content in insulating layer 110d can be increased. Furthermore, the amount of hydrogen released from insulating layer 110d itself due to the heat applied to insulating layer 110d can be increased. For example, insulating layer 110d can be formed using ammonia gas, while insulating layer 110a can be formed without ammonia gas. In particular, when shortening the channel length L100 (e.g., to less than 100 nm) or when using a highly conductive material for the semiconductor layer 108, it is preferable not to use ammonia gas in the formation of the insulating layer 110a. In these cases, the increased amount of hydrogen released from the insulating layer 110a can sometimes have a greater impact on electrical characteristics. By not using ammonia gas in the formation of the insulating layer 110a, the amount of hydrogen in the insulating layer 110a can be further reduced, thereby enabling transistors with excellent electrical characteristics.

[0228] The film density of insulating layer 110a is preferably higher than that of insulating layer 110d. This suppresses the diffusion of impurities contained in insulating layer 110d through insulating layers 110a and 110b into the channel formation region of semiconductor layer 108. The film density can be evaluated, for example, using Rutherford backscattering spectrometry (RBS) or X-ray reflectance measurement (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observation, a higher film density results in a darker (TE) transmission electron image, while a lower film density results in a lighter (bright) TE image. Therefore, in TE images, insulating layer 110a sometimes appears darker (darker) than insulating layer 110d. Note that even if insulating layers 110d and 110a use the same material, their film densities differ, and these boundaries can sometimes be observed in cross-sectional TEM images due to differences in contrast. Note that there are no particular restrictions on the relationship between the film density of insulating layer 110a and the film density of insulating layer 110d.

[0229] By providing an insulating layer 110c between insulating layers 110e and 110b, impurities released from insulating layer 110e can be suppressed from diffusing through insulating layers 110c and 110b into the channel formation region of semiconductor layer 108. This allows for the realization of a transistor 100 exhibiting good electrical characteristics and high reliability.

[0230] The insulating layer 110e preferably has regions with a higher impurity content than the insulating layer 110c. Specifically, the insulating layer 110e preferably has regions with a higher hydrogen content than the insulating layer 110c.

[0231] The film density of insulating layer 110c is preferably higher than that of insulating layer 110e. For details regarding insulating layer 110c, please refer to the description of insulating layer 110a; for details regarding insulating layer 110e, please refer to the description of insulating layer 110d. Therefore, detailed descriptions are omitted. Note that there are no particular limitations on the relationship between the film densities of insulating layer 110c and insulating layer 110e.

[0232] Figures 9A to 9D Show Figure 8A and Figure 8B An enlarged view of regions P1 to P4, indicated by dashed lines. For example, as shown... Figures 9A to 9CAs shown, the insulating film processed into insulating layer 120 and insulating layer 109, by removing a portion of insulating layer 110 (here, insulating layer 110e) during the formation of insulating layers 120 and 109, sometimes the thickness of the region of insulating layer 110 that does not overlap with either insulating layer 120 or insulating layer 109 is thinner than the thickness of the region that overlaps with one or more of insulating layers 120 and insulating layer 109. Additionally, as... Figures 9A to 9C As shown, more preferably, insulating layer 110e remains on insulating layer 110c, and the thickness of insulating layer 110c does not become thinner. The greater the thickness of insulating layer 110c, the higher the barrier properties. Therefore, more preferably, insulating layer 110c is not removed when forming insulating layer 120 and insulating layer 109.

[0233] Next, refer to Figures 4A to 4C The channel length and channel width of transistor 200 are explained. For ease of explanation, the portion of semiconductor layer 208 that overlaps with conductive layer 204 is described as the channel formation region.

[0234] The channel length of transistor 200 is the length of the region where the semiconductor layer 208 and the conductive layer 204 overlap between a pair of regions 208D. Figure 4A and Figure 4B In the diagram, the channel length L200 of transistor 200 is indicated by a dashed double arrow. The channel length L200 of transistor 200 is determined by the length of conductive layer 204 and is greater than the minimum size of the exposure apparatus used in transistor manufacturing. For example, the channel length L200 can be 1.5 μm or more. By increasing the channel length, transistors with high saturation can be achieved.

[0235] The channel width of transistor 200 is the width of the overlapping region of semiconductor layer 208 and conductive layer 204 in a direction orthogonal to the channel length direction. Figure 4A and Figure 4C In the diagram, the double-headed arrow with a dotted line represents the channel width W200 of transistor 200.

[0236] As described above, the channel length L100 of transistor 100 can be smaller than the minimum size of the exposure apparatus, and the channel length L200 of transistor 200 can be larger than the minimum size of the exposure apparatus. For example, by using transistor 100 as a transistor requiring a large on-state current and transistor 200 as a transistor requiring high saturation, a high-performance semiconductor device that leverages the advantages of each transistor can be obtained. Furthermore, transistors 100 and 200 can be formed using shared processes. Specifically, semiconductor layer 108 and semiconductor layer 208 can be formed using the same process. A portion of insulating layer 106 serves as the gate insulating layer of transistor 100, and another portion of insulating layer 106 serves as the gate insulating layer of transistor 200. Conductive layers 104, 204, 212a, and 212b can be formed using the same process. Therefore, the productivity of the semiconductor device can be improved and manufacturing costs reduced.

[0237] like Figure 4A and Figure 4C As shown, preferably, the conductive layers 204 and 202 protrude to the outer side of the end of the semiconductor layer 208 in the channel width direction of the transistor 200. At this time, as... Figure 4C As shown, the entire channel width of semiconductor layer 208 is covered by conductive layers 204 and 202, separated by insulating layers 106 and 120. With this structure, an electric field generated by a pair of gate electrodes can be used to surround semiconductor layer 208.

[0238] Figure 4A and Figure 4C The diagram shows a structure where conductive layer 204 and conductive layer 202 are not electrically connected. Alternatively, a constant potential can be supplied to one of the pair of gate electrodes, and a signal for driving transistor 200 can be supplied to the other. In this case, the threshold voltage when transistor 200 is driven by the other gate electrode can be controlled using the potential supplied to one gate electrode.

[0239] Alternatively, a structure in which conductive layer 204 and conductive layer 202 are electrically connected can be used. By supplying the same potential to conductive layer 204 and conductive layer 202, an electric field for inducing a channel can be effectively applied to semiconductor layer 208, thereby increasing the on-state current of transistor 200. Therefore, a miniaturized transistor 200 can be realized. For example, an opening leading to conductive layer 202 can be provided in insulating layer 106 and insulating layer 120, and conductive layer 204 can be formed to cover the opening.

[0240] The conductive layer 202 may also be electrically connected to the conductive layer 212a or the conductive layer 212b. For example, an opening leading to the conductive layer 202 may be provided in the insulating layer 106 and the insulating layer 120, and the conductive layer 212a or the conductive layer 212b may be formed in such a way that the opening is covered.

[0241] The insulating layer 120 may use materials that are also suitable for the insulating layer 110.

[0242] The insulating layer 120 preferably has a laminated structure. Figure 4B The diagram shows an insulating layer 120 having a laminated structure of an insulating layer 120a and an insulating layer 120b on the insulating layer 120a. Both insulating layers 120a and 120b can be made of materials that can be used in the insulating layer 110.

[0243] The insulating layer 120b having a portion in contact with the channel formation region of the semiconductor layer 208 is more preferably a film that releases oxygen by applying heat. Since the insulating layer 120b releases oxygen due to the heat applied during the manufacturing process of the transistor 200, oxygen can be supplied to the semiconductor layer 208, especially to the channel formation region. Oxygen diffuses within the insulating layer 120b and is supplied to the semiconductor layer 208 across the interface between the insulating layer 120b and the semiconductor layer 208. By supplying oxygen from the insulating layer 120b to the semiconductor layer 208, especially to the channel formation region, oxygen vacancies (V0) are repaired. O ), can reduce oxygen vacancies (V) O Additionally, it can reduce V. O H. Therefore, a transistor 200 exhibiting good electrical characteristics and high reliability can be realized.

[0244] Preferably, the insulating layer 120a releases a small amount of impurities (e.g., hydrogen and water) and these impurities are not easily permeable. This suppresses the diffusion of impurities contained in the insulating layer 120a into the channel formation region of the semiconductor layer 208. Therefore, a transistor 200 exhibiting good electrical characteristics and high reliability can be realized.

[0245] The insulating layer 120a is preferably made of a membrane that is not easily permeable to oxygen. The insulating layer 120a can also be used as a barrier membrane. By providing the insulating layer 120a as a barrier membrane, the diffusion of oxygen contained in the insulating layer 120b through the insulating layer 120a to the conductive layer 202 side can be suppressed. This suppresses the oxidation of the conductive layer 202 and the resulting increase in resistance. Simultaneously, suppressing the diffusion of oxygen contained in the insulating layer 120b to the insulating layer 120a side increases the amount of oxygen supplied from the insulating layer 120b to the channel formation region, thereby reducing the oxygen vacancies (V) in the channel formation region. O ) and V O H.

[0246] The insulating layer 120a located on one side of the conductive layer 202 is preferably made of a material from which the metal elements contained in the conductive layer 202 do not easily diffuse. This can suppress the diffusion of the metal elements contained in the conductive layer 202 through the insulating layer 120 into the channel formation region of the semiconductor layer 208.

[0247] Insulating layer 120a may use materials suitable for insulating layers 110a and 110c. Insulating layer 120a preferably contains nitrogen, and one or more nitrides and oxynitrides may be suitably used. Specifically, insulating layer 120a may suitably use one or both of silicon oxide and silicon oxynitride, for example. Alternatively, insulating layer 120a may use any one or more oxides and oxynitrides. Insulating layer 120a may suitably use aluminum oxide, for example. Note that insulating layers 120a, 110a, and 110c may use the same material. Some or all of the aforementioned insulating layers may also use different materials.

[0248] Furthermore, both insulating layers 120a and 120b can be laminated. Although a two-layer laminated structure is shown herein, the invention is not limited to this. Insulating layer 120 can be a three- or more-layer laminated structure or a single-layer structure.

[0249] Although Figure 1B The diagram shows a structure in which the semiconductor layer 208 has a region in contact with the side of the insulating layer 120, but one aspect of the invention is not limited thereto. Figure 10A A top view of a semiconductor device 10A according to one aspect of the present invention is shown. Figure 10B Show along Figure 10A The cross-sectional view of the section along the dotted line A1-A2 is shown. Regarding the section along... Figure 10A The cross-sectional view of the section along the dotted line B1-B2 shown can be referred to... Figure 8B .

[0250] Semiconductor device 10A includes transistor 100, transistor 200A, insulating layer 110, and insulating layer 109. The main difference between transistor 200A and transistor 200 is that semiconductor layer 208 does not have a region that contacts the side surface of insulating layer 120. The end of semiconductor layer 208 contacts the top surface of insulating layer 120. The entire area where semiconductor layer 208 is disposed is covered by insulating layer 120, and the bottom surface of semiconductor layer 208 is entirely in contact with the top surface of insulating layer 120. In top view, insulating layer 120 encompasses semiconductor layer 208. Therefore, the step of the formed surface of semiconductor layer 208 is reduced, improving the coverage of semiconductor layer 208.

[0251] In semiconductor layer 208, region 208D is a region with lower resistance than the channel formation region. Region 208D can be described as a region with higher carrier concentration, higher oxygen vacancy density, or higher impurity concentration compared to the channel formation region.

[0252] Region 208L is a region with equal or lower resistivity compared to the channel formation region. Region 208L can also be described as a region with equal or higher carrier concentration, oxygen vacancy density, or impurity concentration compared to the channel formation region. Furthermore, region 208L is a region with equal or higher resistivity compared to region 208D. Region 208L can also be described as a region with equal or lower carrier concentration, oxygen vacancy density, or impurity concentration compared to region 208D.

[0253] Region 208L serves as a buffer region to mitigate the drain electric field. Since region 208L does not overlap with conductive layer 204, almost no channel is formed when a gate voltage is supplied to conductive layer 204. The carrier concentration in region 208L is preferably higher than that in the channel formation region. This allows region 208L to be used as an LDD (Lightly Doped Drain) region. By providing region 208L as an LDD region between the channel formation region and region 208D, a transistor 200 with a high drain breakdown voltage can be achieved.

[0254] The carrier concentration of the semiconductor layer 208 preferably has the following distribution: lowest in the channel formation region, and increases sequentially in the order of region 208L and region 208D. By providing region 208L between the channel formation region and region 208D, for example, even if impurities such as hydrogen diffuse from region 208D during the manufacturing process, the carrier concentration in the channel formation region can be kept extremely low.

[0255] Note that sometimes the carrier concentration in region 208L is not uniform, exhibiting a gradient that decreases towards the channel formation region from the side of region 208D. For example, region 208L may also have a high hydrogen concentration and low oxygen vacancy (V0) concentration. O The concentration gradient of one or both of them decreases as they approach the channel from the side of region 208D.

[0256] like Figure 1BAs shown, portions of conductive layers 212a and 212b are preferably located inside openings 147a and 147b. In other words, openings 147a and 147b preferably have regions where portions of conductive layers 212a and 212b contact the semiconductor layer 208. This allows the region contacting conductive layer 212a to be adjacent to one of a pair of regions 208D, and similarly, the region contacting conductive layer 212b to be adjacent to the other of the pair of regions 208D. The region contacting conductive layer 212a and one of the pair of regions 208D serve as one of the source and drain regions of transistor 200. The region contacting conductive layer 212b and the other of the pair of regions 208D serve as the other of the source and drain regions of transistor 200.

[0257] Note that there are no particular restrictions on the top surface shape of openings 147a and 147b. The top surface shape of openings 147a and 147b can be any shape that can be used for openings 141 and 143. Figure 1A The top surface shapes of openings 147a and 147b are shown to be different from those of openings 141 and 143, i.e., they are quadrangular structures with rounded corners. However, one aspect of the invention is not limited to this. The top surface shapes of openings 147a and 147b may be the same as those of openings 141 and 143.

[0258] When impurity elements are supplied to semiconductor layer 208 to form regions 208L and 208D, sometimes the impurity elements are supplied to semiconductor layer 108 through insulating layer 106 using conductive layer 104 as a mask. Thus, region 108L is formed in a region of semiconductor layer 108 that does not overlap with conductive layer 104. Note that in transistor 100, the region of semiconductor layer 108 that contacts conductive layer 112b is used as a source region or drain region. Region 108L is formed in a portion of this source region or drain region. Note that the impurity element concentration in region 108L may also be different from the impurity element concentration in region 208L. Additionally, sometimes region 108L is not formed. For example, when conductive layer 104 extends and covers the end of semiconductor layer 108, the entire semiconductor layer 108 is covered by conductive layer 104, therefore impurity elements are not supplied to semiconductor layer 108 and region 108L is not formed.

[0259] Furthermore, while the conductive layers 212a and 212b are shown here formed using the same process as conductive layer 204, this invention is not limited to this. Conductive layers 212a and 212b can be formed using a different process than conductive layer 204. For example, conductive layers 104 and 204 can be formed on insulating layer 106, and conductive layer 204 can be used as a mask to supply impurity elements to semiconductor layer 208, thereby forming source and drain regions. An insulating layer 195 can be formed on conductive layers 104 and 204, with openings leading to the source and drain regions formed in insulating layers 106 and 195, and conductive layers 212a and 212b formed to cover these openings.

[0260] Notice, Figure 1B Examples are shown where the thickness of the semiconductor layer 208 is uniform at any location, but one aspect of the invention is not limited thereto. The thickness of the semiconductor layer 208 may also differ between regions that overlap with the insulating layer 106 and regions that do not overlap with the insulating layer 106. For example, when forming openings 147a and 147b, because a portion of the semiconductor layer 208 is removed, sometimes the thickness of the region of the semiconductor layer 208 that does not overlap with the insulating layer 106 is thinner than the thickness of the region that overlaps with the insulating layer 106. Alternatively, the thickness of the semiconductor layer 208 may differ between regions that overlap with any of the insulating layer 106, conductive layers 212a, and conductive layers 212b and regions that do not overlap with any of these regions. For example, when forming conductive layers 212a and 212b, because a portion of the semiconductor layer 208 is removed, sometimes the thickness of the region of the semiconductor layer 208 that does not overlap with any of the insulating layer 106, conductive layers 212a, and conductive layers 212b is thinner than the thickness of the region that overlaps with any of these regions. Alternatively, the thickness of the semiconductor layer 208 may differ between the region overlapping with the insulating layer 106, the region overlapping with any of the insulating layer 106, conductive layers 212a and 212b, and the region not overlapping with any of these regions.

[0261] Semiconductor device 10 may include a capacitor. Figure 1A and Figure 1C The semiconductor device 10 shown includes a capacitor 150. For example... Figure 1CAs shown, capacitor 150 has a structure in which conductive layer 112b, insulating layer 109, and conductive layer 202 are sequentially stacked. Conductive layer 112b and conductive layer 202 serve as a pair of electrodes of capacitor 150. Conductive layer 112b serves as the other of the source and drain electrodes of transistor 100, and also as one of the pair of electrodes of capacitor 150. Conductive layer 202 serves as the back gate electrode of transistor 200, and also as the other of the pair of electrodes of capacitor 150. The region of insulating layer 109 sandwiched between conductive layer 112b and conductive layer 202 serves as the dielectric of capacitor 150. By forming conductive layer 112b and conductive layer 202 in different processes, capacitor 150 including these conductive layers as a pair of electrodes can be formed. In addition, by forming conductive layer 112b and conductive layer 202 in different processes, conductive layer 112b and conductive layer 202 can be made of different materials, thereby expanding the range of material choices. The thickness of the insulating layer 109 can be set according to the capacitance of the capacitor 150, the area of ​​the capacitor 150, and the relative permittivity of the material used for the insulating layer 109. Note that the area of ​​the capacitor 150 refers to the area of ​​the overlapping region of the conductive layer 112b, the conductive layer 202, and the insulating layer 109 in the capacitor 150.

[0262] Although Figure 1A The example described below shows a capacitor 150 composed of a conductive layer 112b, a conductive layer 202, and an insulating layer 109; however, the structure of the capacitor 150 is not limited to this. Furthermore, although a structure is shown in which one of the source and drain electrodes of the transistor 100 is electrically connected to one of the pairs of electrodes of the capacitor 150, and one of the source and drain electrodes of the transistor 200 is electrically connected to the other of the pairs of electrodes of the capacitor 150, there are no particular limitations on the electrical connection relationship between the transistor 100, the transistor 200, and the capacitor 150.

[0263] Furthermore, semiconductor devices may not include capacitors. Figure 11A A top view of a semiconductor device 10B according to one embodiment of the present invention is shown. Regarding the... Figure 11A The cross-sectional view of the dashed line A1-A2 shown can be referred to... Figure 8A . Figure 11B This shows a cross-sectional view along the dashed line B1-B2.

[0264] Semiconductor device 10B and Figure 8A The main difference of the semiconductor device 10 shown is that it does not include a capacitor 150. Figure 11A The diagram shows a structure where the conductive layer 202 does not have a region overlapping with the conductive layer 112b. Additionally, a structure where the insulating layer 109 does not contact the conductive layer 112b is shown. Alternatively, the insulating layer 109 may have a region contacting the conductive layer 112b.

[0265] Alternatively, capacitors may not be required in other structural examples.

[0266] Note that a structure without conductive layer 202 can also be used. Figure 12A A top view of a semiconductor device 10C according to one aspect of the present invention is shown. Figure 12B Show along Figure 12A The cross-sectional view of the section along the dotted line A1-A2 shown is shown. Figure 12C A cross-sectional view is shown along the dashed line B1-B2. Semiconductor device 10C includes transistor 100, transistor 200B, insulating layer 110, and insulating layer 109. Transistor 200B and... Figure 8A The main difference of the transistor 200 shown is that it does not include the conductive layer 202.

[0267] Transistor 200B can be described as having a structure without a conductive layer 202 serving as the back gate electrode of transistor 200. Therefore, transistors 200 and 200B can be formed on the same substrate using the same process. That is, transistors 100 with a short channel length, transistor 200 with a long channel length and a back gate electrode, and transistor 200B with a long channel length but no back gate electrode can be formed on the same substrate using some processes.

[0268] Alternatively, the conductive layer 202 may not be provided in other structural examples.

[0269] [Semiconductor layer 108 and semiconductor layer 208]

[0270] Specifically, the metal oxides that can be used in semiconductor layer 108 and semiconductor layer 208 will be described. Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium or zinc. Furthermore, the metal oxide preferably contains one or more elements selected from indium, element M, and zinc. In addition, element M is a metallic or half-metallic element with a high bonding energy with oxygen, for example, a metallic or half-metallic element with a higher bonding energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more selected from gallium, aluminum, and tin. These elements have high bonding energies with oxygen, and their ionic radii are approximately the same as those of indium or zinc, so they are more preferred. Furthermore, since tin is tetravalent, it can improve carrier mobility, making it a more preferable option. Note that in this specification, etc., metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the term "metallic element" as used in this specification, etc., sometimes includes half-metallic elements.

[0271] Semiconductor layers 108 and 208 can, for example, use indium zinc oxide (also known as In-Zn oxide or IZO (registered trademark)), indium tin oxide (also known as In-Sn oxide or ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (also known as In-W oxide or IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (also known as In-Ga-Sn oxide or IGTO), gallium zinc oxide (also known as Ga-Zn oxide or GZO), aluminum zinc oxide (also known as... These can be denoted as Al-Zn oxide or AZO, indium aluminum zinc oxide (also denoted as In-Al-Zn oxide or IAZO), indium tin zinc oxide (also denoted as In-Sn-Zn oxide or ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (also denoted as In-Ga-Zn oxide or IGZO), indium gallium tin zinc oxide (also denoted as In-Ga-Sn-Zn oxide or IGZTO), indium gallium aluminum zinc oxide (also denoted as In-Ga-Al-Zn oxide, IGAZO, IGZAO, or IAGZO), etc. Alternatively, silicon-containing indium tin oxide (also denoted as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0272] Note that metal oxides can adopt structures that replace indium or include one or more metals with high period numbers in the periodic table, in addition to indium. The greater the overlap of the metal element's orbitals, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers include those belonging to the 5th and 6th periods. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0273] Metal oxides can contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved due to increased carrier concentration or narrower band gap. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0274] Increasing the proportion of indium atoms in a metal oxide relative to the sum of the atomic numbers of all metal elements can improve the field-effect mobility of a transistor. Furthermore, it allows for the realization of transistors with high on-state currents.

[0275] In this specification, the ratio of the number of indium atoms to the total number of atoms of all contained metallic elements is sometimes described as the indium content. The same applies to other metallic elements. When multiple elements are contained as element M, the sum of the ratios of the number of atoms of element M to the total number of atoms of all contained metallic elements can be described as the content of element M.

[0276] Increasing the zinc content in metal oxides enhances their crystallinity, suppressing impurity diffusion. Consequently, variations in the electrical characteristics of transistors are inhibited, improving reliability.

[0277] Increasing the content of element M in metal oxides can result in metal oxides with large band gaps. Furthermore, suppressing the formation of oxygen vacancies (V) in metal oxides can also achieve this. O ), caused by oxygen vacancies (V O Carrier generation is suppressed, thereby suppressing threshold voltage drift in the transistor. This reduces the cutoff current, enabling normally-off transistors. Furthermore, transistors with low off-state current can be achieved. Additionally, variations in the transistor's electrical characteristics are suppressed, thus improving reliability.

[0278] The electrical characteristics and reliability of transistors vary depending on the composition of the metal oxides used in semiconductor layers 108 and 208. Therefore, by changing the composition of the metal oxides according to the required electrical characteristics and reliability of the transistor, a semiconductor device with both excellent electrical characteristics and high reliability can be realized.

[0279] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably greater than or equal to the atomic ratio of element M. Examples of such atomic ratios for the metal elements in this In-M-Zn oxide include: In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, and In:M:Zn = 5:1:8. The compositions with In:M:Zn ratios of 5:1:9, 6:1:6, 10:1:1, 10:1:3, 10:1:4, 10:1:6, 10:1:7, 10:1:8, 5:2:5, 10:1:10, 20:1:10, and 40:1:10, as well as their vicinity, are considered. Furthermore, vicinity compositions include those within ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in metal oxides can improve transistor on-state current or field-effect mobility, among other things.

[0280] In In-M-Zn oxides, the atomic ratio of In can also be less than the atomic ratio of element M. Examples of such In-M-Zn oxide atomic ratios include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these ratios. By increasing the proportion of M atoms in the metal oxide, oxygen vacancies (V0) can be suppressed. O The generation of ).

[0281] Note that when element M contains multiple elements, the sum of the atomic ratios of these elements can be set as the atomic ratio of element M.

[0282] By using materials with high indium content in semiconductor layers 108 and 208, the on-state current or field-effect mobility of transistors can be improved. Furthermore, the inclusion of element M can suppress oxygen vacancies (V0).O The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metallic elements) is preferably 0.1% or more and 25% or less, more preferably 0.1% or more and 20% or less, more preferably 0.1% or more and 10% or less, more preferably 0.1% or more and 8% or less, more preferably 0.1% or more and 6% or less, and more preferably 0.1% or more and 4% or less. This allows for the realization of transistors with excellent electrical characteristics. For example, metal oxides with In:M:Zn = 40:1:10 and its vicinity are preferably used. Element M is preferably any one or more of the above-mentioned elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides with In:Sn:Zn = 40:1:10 and its vicinity can be used appropriately. Alternatively, metal oxides with In:Al:Zn = 40:1:10 and its vicinity can be used appropriately.

[0283] Here, by using a metal oxide with a polycrystalline structure for semiconductor layers 108 and 208, grain boundaries become recombination centers, trapping charge carriers, thus sometimes reducing the on-state current of the transistor. Furthermore, when a metal oxide with a polycrystalline structure is used as semiconductor layer 108, the surface roughness of semiconductor layer 108 sometimes increases. Consequently, the steps on the formed surfaces of layers (e.g., insulating layer 106) on semiconductor layer 108 sometimes become larger, leading to problems such as breaks or voids in the layer. When using a metal oxide with a composition that easily becomes polycrystalline for semiconductor layer 108, it is preferable to include elements that inhibit crystallization. This can suppress the formation of a polycrystalline structure in semiconductor layer 108, thereby enabling the realization of transistors with high on-state current. Furthermore, the coverage of layers (e.g., insulating layer 106) formed on semiconductor layer 108 can be improved, thereby suppressing problems such as breaks or voids in the layer.

[0284] For example, compared to indium tin oxide (ITO), silicon-containing indium tin oxide (ITSO) is less likely to form a polycrystalline structure, so it can be appropriately used for semiconductor layer 108 and semiconductor layer 208. When using ITSO, the silicon content (the ratio of the number of silicon atoms to the sum of the number of atoms of all contained metal elements) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, more preferably 3% or more and 15% or less, and more preferably 5% or more and 15% or less. Specifically, In:Sn:Si = 45:5:4, In:Sn:Si = 95:5:8, and metal oxides near them can be appropriately used. When silicon-containing indium tin oxide (ITSO) is used as semiconductor layer 108, it is preferable to have crystallinity. Alternatively, semiconductor layer 108 may also have amorphous regions or adopt an amorphous structure.

[0285] Metal oxides that do not contain element M can be used for semiconductor layers 108 and 208. When the metal oxide is an In-Zn oxide, examples of the atomic ratios of the metal elements include In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions in their vicinity. Furthermore, the atomic ratio of In is more preferably greater than that of Zn. By increasing the atomic ratio of In in the metal oxide, the on-state current or field-effect mobility of the transistor can be improved.

[0286] In the analysis of the composition of semiconductor layer 108 and semiconductor layer 208, methods such as energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS or ESCA), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Furthermore, multiple methods can be combined for analysis. Peak separation of the obtained spectra is preferred to identify and quantify elements. Note that due to the influence of analytical precision, the actual content of elements with low content may sometimes differ from the content obtained from the analysis. For example, when the content of element M is low, the content of element M obtained from the analysis may sometimes be lower than the actual content, difficult to quantify, or below the detection limit.

[0287] Metal oxides can be formed using sputtering or atomic layer deposition (ALD). Note that when sputtering is used to form metal oxides, the composition of the resulting metal oxide sometimes differs from that of the sputtering target. In particular, the zinc content of the resulting metal oxide can sometimes be reduced to about 50% of the zinc content in the sputtering target.

[0288] Semiconductor layers 108 and 208 are preferably made of crystalline metal oxides. Examples of crystalline metal oxide structures include CAAC (c-axis aligned crystal) structures, polycrystalline structures, and nanocrystalline (nc: nano-crystal) structures. By using crystalline metal oxides, the defect state density in semiconductor layers 108 and 208 can be reduced, thereby enabling highly reliable semiconductor devices. Note that a CAAC structure is a crystal structure in which multiple microcrystals (typically multiple IGZO microcrystals) are c-axis aligned and connected on the ab plane in a non-oriented manner. The CAAC structure has fewer grain boundaries and grains on the ab plane than the polycrystalline structure, thus enabling highly reliable semiconductor devices.

[0289] Semiconductor layer 108 and semiconductor layer 208 preferably use CAAC-OS or nc-OS.

[0290] The CAAC-OS has multiple layered crystals. The c-axis of the crystal is oriented in the normal direction of the formed surface. Semiconductor layer 108 and semiconductor layer 208 preferably have layered crystals parallel to or substantially parallel to the formed surface. For example, semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the top surface of conductive layer 112b in the region contacting the top surface of conductive layer 112b, and layered crystals parallel to or substantially parallel to the side surface of conductive layer 112b in the region contacting the side surface of conductive layer 112b. In particular, semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the side surface of insulating layer 110, which is the formed surface, in the opening 141. By adopting this structure, the layered crystals of semiconductor layer 108 are parallel to or substantially parallel to the channel length direction of transistor 100, so a transistor with a large on-state current can be realized. Similarly, semiconductor layer 208 preferably has layered crystals parallel to or substantially parallel to the formed surface (here, the top and side surfaces of insulating layer 120 and the top surface of insulating layer 110). In particular, the semiconductor layer 208 preferably has layered crystals in the region overlapping with the conductive layer 204 that are parallel or substantially parallel to the top surface of the insulating layer 120, which is the surface to be formed.

[0291] By using highly crystalline metal oxides in the channel formation region, the defect state density in the channel formation region can be reduced. On the other hand, by using low-crystallinity metal oxides, transistors capable of carrying large currents can be realized.

[0292] The higher the substrate temperature during metal oxide formation, the more crystalline the metal oxide can be formed. The substrate temperature during formation can be adjusted, for example, according to the temperature of the stage on which the substrate is placed. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for formation or the higher the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide can be formed.

[0293] The crystallinity of semiconductor layers 108 and 208 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Furthermore, multiple of these methods can be combined for analysis.

[0294] When metal oxides are used as semiconductor layers 108 and 208, it is preferable to minimize the Vc in the channel formation region. O H is made to be a high-purity intrinsic or substantially high-purity intrinsic. Thus, in order to obtain V... O For metal oxides with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen from the metal oxide (sometimes described as dehydration or dehydrogenation); and supply oxygen to the metal oxide to fill oxygen vacancies (V). O ). By V O Metal oxides with sufficiently low levels of impurities such as hydrogen (H) used in the channel formation region of transistors can impart stable electrical characteristics. Note that sometimes oxygen is supplied to the metal oxide to repair oxygen vacancies (V0). O The treatment of ) is called oxidation treatment.

[0295] When metal oxides are used as semiconductor layers 108 and 208, the preferred carrier concentration in the channel formation region is 1 × 10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 Further optimization of less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 Further preferred is less than 1×10 12 cm -3 There is no lower limit to the carrier concentration in the channel formation region; for example, it can be set to 1 × 10⁻⁶. -9 cm -3 .

[0296] OS transistors exhibit minimal changes in electrical characteristics due to radiation exposure, meaning they possess high radiation tolerance and can therefore be appropriately used in environments where radiation exposure is possible. OS transistors can also be described as having high reliability against radiation. For example, OS transistors can be appropriately used as pixel circuits in X-ray flat panel detectors. Furthermore, OS transistors can be appropriately used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0297] Semiconductor layers 108 and 208 may also contain layered materials used as semiconductors. Layered materials are a general term for materials with layered crystal structures. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked through bonds weaker than covalent and ionic bonds, such as van der Waals bonds. Layered materials have high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material that serves as a semiconductor and has high two-dimensional conductivity in the channel formation region, transistors with large on-state currents can be provided.

[0298] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (elements belonging to Group 16). Furthermore, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as channel forming regions in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0299] Semiconductor layer 108 and semiconductor layer 208 can both employ a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers included in each of semiconductor layer 108 and semiconductor layer 208 can be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs. When the compositions of the two or more metal oxide layers included in semiconductor layer 108 and semiconductor layer 208 are the same or substantially the same, it is sometimes impossible to clearly identify the boundaries (interfaces) of these metal oxide layers.

[0300] Figure 13A and Figure 13B This shows that both semiconductor layer 108 and semiconductor layer 208 have a stacked structure. Figure 13A In the transistor 100A shown, the semiconductor layer 108 has a stacked structure of semiconductor layer 108a, semiconductor layer 108b on semiconductor layer 108a, and semiconductor layer 108c on semiconductor layer 108b. Figure 13B In the transistor 200C shown, the semiconductor layer 208 has a stacked structure of semiconductor layer 208a, semiconductor layer 208b on semiconductor layer 208a and semiconductor layer 208c on semiconductor layer 208b.

[0301] Semiconductor layer 108a and semiconductor layer 208a may have the same or substantially the same composition. Semiconductor layer 108b and semiconductor layer 208b may have the same or substantially the same composition. Semiconductor layer 108c and semiconductor layer 208c may have the same or substantially the same composition. Semiconductor layer 108a and semiconductor layer 208a may be formed using the same process, semiconductor layer 108b and semiconductor layer 208b may be formed using the same process, and semiconductor layer 108c and semiconductor layer 208c may be formed using the same process. For example, a first semiconductor film that becomes semiconductor layer 108a and semiconductor layer 208a, a second semiconductor film that becomes semiconductor layer 108b and semiconductor layer 208b, and a third semiconductor film that becomes semiconductor layer 108c and semiconductor layer 208c may be formed and processed to form semiconductor layer 108 including semiconductor layers 108a to 108c and semiconductor layer 208 including semiconductor layers 208a to 208c.

[0302] Semiconductor layers 108a, 108b, 108c, 208a, 208b, and 208c preferably comprise metal oxides exhibiting semiconductor properties. The band gap of the first metal oxide in semiconductor layers 108a and 208a, the second metal oxide in semiconductor layers 108b and 208b, and the third metal oxide in semiconductor layers 108c and 208c is preferably 2.0 eV or more, more preferably 2.5 eV or more.

[0303] The band gap of the first metal oxide is preferably different from that of the second metal oxide. The band gap of the third metal oxide is preferably different from that of the second metal oxide. Furthermore, it is more preferable that the band gap of the third metal oxide is different from that of the first metal oxide.

[0304] The band gap of the first metal oxide is preferably larger than that of the second metal oxide. The band gap of the third metal oxide is preferably larger than that of the second metal oxide. Semiconductor layer 108b is sandwiched between semiconductor layers 108a and 108c, which have larger band gaps, and can employ an embedded channel structure. Thus, in semiconductor layer 108, the main current path is semiconductor layer 108b. Similarly, in semiconductor layer 208, the main current path is semiconductor layer 208b.

[0305] The band gap of the third metal oxide is more preferably larger than that of the first metal oxide. By using a material with a large band gap for the semiconductor layer 108c, which is located on the side of the conductive layer 104 serving as the gate electrode of the transistor 100, the generation and induction of charge carriers in the semiconductor layer 108c and at the interface between the semiconductor layer 108c and the gate insulating layer (here, the insulating layer 106) can be suppressed, thereby enabling a transistor with high reliability. For example, by suppressing the generation and induction of charge carriers in the semiconductor layer 108c and at its interface due to light incident on the transistor, the variation of the transistor's electrical characteristics with respect to light can be suppressed. The same applies to the semiconductor layer 208c located on the side of the conductive layer 204 serving as the gate electrode of the transistor 200. Note that there are no particular limitations on the relationship between the size of the band gaps of the first metal oxide, the second metal oxide, and the third metal oxide.

[0306] Semiconductor layer 108a has a region that contacts conductive layers 112a and 112b, which serve as source and drain electrodes, respectively. By making the band gap of the first metal oxide included in semiconductor layer 108a smaller than the band gap of the third metal oxide, the contact resistance between semiconductor layer 108a and conductive layer 112a, and between semiconductor layer 108a and conductive layer 112b, can be reduced. Therefore, a transistor with a large on-state current can be realized.

[0307] The conduction band bottom of the first metal oxide is preferably closer to the vacuum level than the conduction band bottom of the second metal oxide. The conduction band bottom of the third metal oxide is preferably closer to the vacuum level than the conduction band bottom of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably smaller than the electron affinity of the second metal oxide. Furthermore, it is more preferable that the conduction band bottom of the third metal oxide is closer to the vacuum level than the conduction band bottom of the first metal oxide. In other words, it is more preferable that the electron affinity of the third metal oxide is smaller than the electron affinity of the first metal oxide. Note that the relative magnitudes of the electron affinity of the first, second, and third metal oxides are not particularly limited.

[0308] Here, trap levels caused by impurities or defects may form at and near the interface between the insulating layer 110 and the semiconductor layer 108. Examples of such impurities include residual components of the etchant or etching gas used when forming the opening 141, and components of the conductive layers 112a and 112b that adhere to the sides of the insulating layer 110 when forming the opening 141. By providing the semiconductor layer 108a between the semiconductor layer 108b and the insulating layer 110, the semiconductor layer 108b can be moved away from these trap levels.

[0309] During the formation of insulating layer 106, the interfaces between insulating layer 106 and semiconductor layer 108, and between insulating layer 106 and semiconductor layer 208, and their vicinity, may be damaged. Consequently, trap levels may form at the interfaces between insulating layer 106 and semiconductor layer 108, and between insulating layer 106 and semiconductor layer 208, and their vicinity. By placing semiconductor layer 108c between semiconductor layer 108b and insulating layer 106, semiconductor layer 108b can be moved away from these trap levels. Similarly, by placing semiconductor layer 208c between semiconductor layer 208b and insulating layer 106, semiconductor layer 208b can be moved away from these trap levels.

[0310] By sandwiching semiconductor layer 108b, which serves as the main current path of semiconductor layer 108, between semiconductor layers 108a and 108c, the interface and trap levels near the interface of semiconductor layer 108b can be reduced. Similarly, by sandwiching semiconductor layer 208b, which serves as the main current path of semiconductor layer 208, between semiconductor layers 208a and 208c, the interface and trap levels near the interface of semiconductor layer 208b can be reduced. This allows for the realization of transistors with high on-state current and high reliability. Consequently, a semiconductor device that simultaneously achieves low power consumption and high performance can be obtained.

[0311] Preferably, the compositions of the first, second, and third metal oxides are different. The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxides used in the semiconductor layer. Therefore, by differentiating the compositions of the first, second, and third metal oxides to correspond to the required electrical characteristics and reliability of the transistor, a semiconductor device with both excellent electrical characteristics and high reliability can be realized.

[0312] The second metal oxide used in semiconductor layers 108b and 208b preferably has a high indium atom ratio. The indium atom ratio in the second metal oxide is preferably higher than the atom ratio of element M. By using a metal oxide with a high indium atom ratio in semiconductor layers 108b and 208b, which serve as the main current path, the on-state current or field-effect mobility of the transistor can be improved. Furthermore, the indium atom ratio in the second metal oxide is preferably higher than or equal to the zn atom ratio. Increasing the indium atom ratio in the metal oxide can improve the on-state current or field-effect mobility of the transistor. Note that the indium atom ratio in the second metal oxide can be less than the zn atom ratio.

[0313] By using materials with high indium content in semiconductor layers 108b and 208b, the on-state current or field-effect mobility of transistors can be improved. Furthermore, the inclusion of element M can suppress oxygen vacancies (V0). O The formation of ). Alternatively, the second metal oxide may not contain element M.

[0314] The indium content in the second metal oxide is preferably higher than that in the first metal oxide. Furthermore, the indium content in the second metal oxide is preferably higher than that in the third metal oxide. This improves the on-state current or field-effect mobility of the transistor.

[0315] The band gap can be adjusted by changing the composition of the metal oxide. Preferably, the atomic ratio of element M in the first and third metal oxides is large. The atomic ratio of element M in the first metal oxide is preferably greater than or equal to the atomic ratio of indium. This increases the band gap of the first metal oxide. Similarly, the atomic ratio of element M in the third metal oxide is preferably greater than or equal to the atomic ratio of indium. This increases the band gap of the third metal oxide.

[0316] Furthermore, the content of element M in the first metal oxide is preferably higher than that in the second metal oxide. This allows the band gap of the first metal oxide to be larger than that of the second metal oxide. Similarly, the content of element M in the third metal oxide is preferably higher than that in the second metal oxide. This allows the band gap of the third metal oxide to be larger than that of the second metal oxide.

[0317] Furthermore, the content of element M in the third metal oxide is preferably higher than that in the first metal oxide. This allows the band gap of the third metal oxide to be larger than that of the first metal oxide.

[0318] By reducing the content of element M, which has a high bonding energy with oxygen, in the first metal oxide, oxygen can be made more permeable to semiconductor layer 108a. In other words, oxygen in insulating layer 110 can be efficiently supplied to semiconductor layer 108b through semiconductor layer 108a. This reduces oxygen vacancies (V0) in semiconductor layer 108b, which is the main circuit path. O ) and V O H. Therefore, threshold voltage drift can be suppressed, thereby enabling transistors with low cutoff current and high on-state current. This allows for the creation of semiconductor devices that simultaneously achieve low power consumption and high performance.

[0319] When the first, second, and third metal oxides are In-M-Zn oxides, for example, the composition of the first metal oxide can be set to In:M:Zn = 1:1:1 [atomic ratio] or near, the composition of the second metal oxide can be set to In:M:Zn = 40:1:10 [atomic ratio] or near, and the composition of the third metal oxide can be set to In:M:Zn = 1:3:4 [atomic ratio] or near. Alternatively, the composition of the first metal oxide can be set to In:M:Zn = 1:1:1 [atomic ratio] or near, the composition of the second metal oxide can be set to In:M:Zn = 10:1:10 [atomic ratio] or near, and the composition of the third metal oxide can be set to In:M:Zn = 1:3:4 [atomic ratio] or near.

[0320] More specifically, the composition of the first metal oxide can be set to In:Ga:Zn = 1:1:1 (atomic ratio) or near, the composition of the second metal oxide can be set to In:Sn:Zn = 40:1:10 (atomic ratio) or near, and the composition of the third metal oxide can be set to In:Ga:Zn = 1:3:4 (atomic ratio) or near. Alternatively, the composition of the first metal oxide can be set to In:Ga:Zn = 1:1:1 (atomic ratio) or near, the composition of the second metal oxide can be set to In:Sn:Zn = 10:1:10 (atomic ratio) or near, and the composition of the third metal oxide can be set to In:Ga:Zn = 1:3:4 (atomic ratio) or near.

[0321] The second metal oxide may not contain element M. For example, the second metal oxide may be an In-Zn oxide, and the first and third metal oxides may be In-M-Zn oxides. Specifically, the composition of the first metal oxide can be set to In:Ga:Zn = 1:1:1 (atomic ratio) or near, the composition of the second metal oxide can be set to In:Zn = 4:1 (atomic ratio) or near, and the composition of the third metal oxide can be set to In:Ga:Zn = 1:3:4 (atomic ratio) or near. Alternatively, the composition of the first metal oxide can be set to In:Ga:Zn = 1:1:1 (atomic ratio) or near, the composition of the second metal oxide can be set to In:Zn = 1:1 (atomic ratio) or near, and the composition of the third metal oxide can be set to In:Ga:Zn = 1:3:4 (atomic ratio) or near.

[0322] Furthermore, the composition of the third metal oxide can be the same as or substantially the same as that of the first metal oxide. By using the same composition, the manufacturing cost can be reduced because, for example, the same sputtering target can be used to form the semiconductor layer 108a and the semiconductor layer 108c.

[0323] Note that the composition of the first metal oxide, the second metal oxide, and the third metal oxide is not limited to this.

[0324] When the composition of the first metal oxide is the same as or substantially the same as the composition of the third metal oxide, it is preferable that the crystallinity of the semiconductor layer 108c is higher than that of the semiconductor layer 108a. By making the crystallinity of the semiconductor layer 108c higher than that of the semiconductor layer 108a, damage to the semiconductor layer 108 during the formation of the insulating layer 106 can be suppressed. On the other hand, by making the crystallinity of the semiconductor layer 108a lower than that of the semiconductor layer 108c, oxygen can easily permeate, thereby efficiently supplying the oxygen contained in the insulating layer 110 to the semiconductor layer 108b. Note that the crystallinity of the semiconductor layer 108c can be the same as or lower than that of the semiconductor layer 108a.

[0325] The substrate temperature for forming semiconductor layer 108c is preferably higher than the substrate temperature for forming semiconductor layer 108a. Alternatively, the oxygen flow rate ratio or oxygen partial pressure of the deposition gas used to form semiconductor layer 108c is preferably higher than the oxygen flow rate ratio or oxygen partial pressure of the deposition gas used to form semiconductor layer 108a. As a result, the crystallinity of semiconductor layer 108c can be higher than that of semiconductor layer 108a.

[0326] By increasing the thickness of semiconductor layer 108b, which forms the main circuit path, a transistor 100 with a large on-state current can be realized. Similarly, by increasing the thickness of semiconductor layer 208b, a transistor 200 with a large on-state current can be realized. The thicknesses of semiconductor layer 108b and semiconductor layer 208b are preferably thicker than the thicknesses of semiconductor layers 108a, 108c, 208a, and 208c.

[0327] The thickness of semiconductor layers 108c and 208c on the insulating layer 106 side is preferably thicker than that of semiconductor layers 108a and 208a. By forming semiconductor layers 108c and 208c to be thicker, damage to semiconductor layers 108 and 208 during the formation of insulating layer 106 can be suppressed.

[0328] The thicknesses of semiconductor layers 108a and 208a are preferably thinner than the thicknesses of semiconductor layers 108b, 108c, 208b, and 208c. Here, oxygen contained in the insulating layer 110 is supplied to the semiconductor layer 108b via semiconductor layer 108a. By making semiconductor layer 108a thinner, oxygen can easily permeate through it, thereby efficiently supplying oxygen contained in the insulating layer 110 to the semiconductor layer 108b. Similarly, oxygen contained in the insulating layer 120 (e.g., insulating layer 120b) is supplied to the semiconductor layer 208b via semiconductor layer 208a. By making semiconductor layer 208a thinner, oxygen can easily permeate through it, thereby efficiently supplying oxygen contained in the insulating layer 120 to the semiconductor layer 208b. This allows for the realization of a transistor with high on-state current and high reliability. Note that there are no particular restrictions on the relationship between the thicknesses of semiconductor layers 108a, 108b, 108c, 208a, 208b, and 208c.

[0329] Furthermore, although examples of semiconductor layers 108 and 208 each having a three-layer structure are shown herein, the invention is not limited to this. When semiconductor layers 108 and 208 have a stacked structure, it is preferable to have at least semiconductor layers 108b and 208b. For example, semiconductor layer 108 may have a two-layer structure of semiconductor layers 108a and 108b, and semiconductor layer 208 may have a two-layer structure of semiconductor layers 208a and 208b. Alternatively, semiconductor layer 108 may have a two-layer structure of semiconductor layers 108b and 108c, and semiconductor layer 208 may have a two-layer structure of semiconductor layers 208b and 208c. Alternatively, semiconductor layers 108 and 208 may each have a stacked structure of four or more layers or a single-layer structure.

[0330] Note that the structure of semiconductor layer 108 shown here can also be used for other structural examples.

[0331] [Conductive layer 112a, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a, conductive layer 212b, conductive layer 202]

[0332] Conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202 can each have a single-layer structure or a stacked structure. Examples of materials that can be used for conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202 include one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. Low-resistance conductive materials containing one or more of copper, silver, gold, and aluminum can be suitably used for conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202. In particular, copper or aluminum has advantages in mass production and is therefore preferred.

[0333] Conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202 can be made of conductive metal oxides (oxide conductors). Examples of oxide conductors (OC) include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (ITO containing silicon, also known as ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide. In particular, indium-containing oxide conductors are preferred because of their high conductivity.

[0334] For example, oxygen vacancies (V0) are formed in metal oxides with semiconductor properties. O ), for this oxygen vacancy (V O Adding hydrogen creates donor levels near the conduction band. As a result, the conductivity of the metal oxide increases, making it a conductor. Metal oxides that can become conductors are called oxide conductors.

[0335] Conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202 can all have a laminated structure comprising a conductive film containing the aforementioned oxide conductor and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, wiring resistance can be reduced.

[0336] As conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202, a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be applied. By using the Cu-X alloy film, it can be processed using a wet etching method, thereby reducing manufacturing costs.

[0337] Alternatively, conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202 may be made of the same material. Or, some or all of the above conductive layers may be made of different materials.

[0338] Conductive layers 112a and 112b have regions that contact the semiconductor layer 108. When a metal oxide is used as the semiconductor layer 108, there is a concern that if an easily oxidizable metal (e.g., aluminum) is used as the conductive layers 112a and 112b, insulating oxides (e.g., aluminum oxide) will form between the conductive layers 112a and 108, and between the conductive layers 112b and 108, hindering their conductivity. Therefore, conductive layers 112a and 112b are preferably made of conductive materials that are not easily oxidized, conductive materials that maintain low resistance even when oxidized, or oxide conductors.

[0339] As conductive layers 112a and 112b, materials such as titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. These materials are preferred because they are conductive materials that are not easily oxidized or maintain low resistance even when oxidized.

[0340] The conductive layers 112a and 112b can use the aforementioned oxide conductors. Specifically, indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, or zinc oxide with gallium added can be used.

[0341] The conductive layers 112a and 112b may also be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0342] Conductive layers 112a, 112b, and 104 can all have a stacked structure. When conductive layer 112a has a stacked structure, the layer in contact with at least semiconductor layer 108 is preferably made of a conductive material that is not easily oxidized. The same applies to conductive layer 112b.

[0343] Figures 14A to 14D The conductive layer 112a is shown to have a stacked structure.

[0344] exist Figure 14A and Figure 14B In the transistor 100B shown, the conductive layer 112a has a stacked structure of conductive layer 112a_1 and conductive layer 112a_2 on conductive layer 112a_1.

[0345] The conductive layer 112a_2, including the region in contact with the semiconductor layer 108, is preferably made of a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductor. For materials that can be used in the conductive layer 112a_2, refer to the materials exemplified in the conductive layer 112a.

[0346] Since conductive layer 112a_1 does not contact semiconductor layer 108, there are no particular restrictions on the materials used. For example, conductive layer 112a_1 is preferably made of a material with a lower resistivity than conductive layer 112a_2. This reduces the resistance of conductive layer 112a. For example, In-Sn-Si oxide (ITSO) can be suitably used for conductive layer 112a_2, and copper or tungsten can be suitably used for conductive layer 112a_1.

[0347] like Figure 14A As shown, the end of conductive layer 112a_2 can be aligned or substantially aligned with the end of conductive layer 112a_1. For example, conductive layer 112a can be formed by forming a first film as conductive layer 112a_1 and a second film as conductive layer 112a_2 and processing the first and second films. By processing the first and second films in the same manner, manufacturing costs can be reduced.

[0348] The end of conductive layer 112a_2 may not be aligned with the end of conductive layer 112a_1. For example... Figure 14BAs shown, the conductive layer 112a_2 can be provided to cover the conductive layer 112a_1. The conductive layer 112a_2 includes regions that contact the top and side surfaces of the conductive layer 112a_1. The conductive layer 112a_2 can also be described as having a portion that protrudes beyond the end of the conductive layer 112a_1. For example, the conductive layer 112a_1 can be formed, a film that becomes the conductive layer 112a_2 can be formed on the conductive layer 112a_1, and the film can be processed to form the conductive layer 112a_2. By making the conductive layer 112a_2 protrude beyond the end of the conductive layer 112a_1, the step of the formed surface of the layer (e.g., the insulating layer 110) on the conductive layer 112a is reduced, thereby improving the coverage of the layer. As a result, problems such as breaks or voids in the layer can be suppressed.

[0349] Note that in Figure 14A and Figure 14B The thicknesses of the layers constituting conductive layer 112a are generally the same or substantially the same, but this is not the limitation of the present invention. The thicknesses of the layers constituting conductive layer 112a may also differ. For example, by making the layer using a material with low resistivity thicker than the other layers, the resistance of conductive layer 112a can be reduced, which is more preferable. Specifically, conductive layer 112a_1 can be made of a material with lower resistivity than conductive layer 112a_2, and the thickness of conductive layer 112a_1 can be thicker than that of conductive layer 112a_2. This reduces the resistance of conductive layer 112a.

[0350] exist Figure 14C and Figure 14D In the transistor 100B shown, the conductive layer 112a has a three-layer structure consisting of conductive layer 112a_3, conductive layer 112a_1 on conductive layer 112a_3, and conductive layer 112a_2 on conductive layer 112a_1.

[0351] like Figure 14C As shown, the end of conductive layer 112a_2 can be aligned or substantially aligned with the end of conductive layer 112a_3. Furthermore, the end of conductive layer 112a_1 can contact the top surface of conductive layer 112a_3. Conductive layer 112a_2 has areas that contact the top and side surfaces of conductive layer 112a_1 and the top surface of conductive layer 112a_3. That is, it can also be said that conductive layers 112a_2 and 112a_3 have portions that protrude beyond the end of conductive layer 112a_1. Additionally, it can be said that the top, side, and bottom surfaces of conductive layer 112a_1 are surrounded by conductive layers 112a_2 and 112a_3. Conductive layer 112a_3 is preferably made of a material with high adhesion to the surface on which it is formed (here, the surface of substrate 102).

[0352] As described above, conductive layer 112a_1 is preferably made of a material with low resistivity. However, depending on the material, the adhesion between conductive layer 112a_1 and the surface to which it is formed (e.g., the surface of substrate 102) is low, which may lead to a decrease in the manufacturing yield of the semiconductor device. By using a material with higher adhesion to the surface to which it is formed as conductive layer 112a_3, the manufacturing yield of the semiconductor device can be improved. Note that the thickness of conductive layer 112a_3 is preferably sufficient to improve the adhesion to the surface to which it is formed, and can be smaller than the thickness of conductive layers 112a_1 and 112a_2. By reducing the thickness of conductive layer 112a_3, manufacturing costs can be reduced.

[0353] For example, conductive layer 112a_3 is suitable for using In-Sn-Si oxide (ITSO), conductive layer 112a_1 is suitable for using copper, and conductive layer 112a_2 is suitable for using In-Sn-Si oxide (ITSO). When a glass substrate is used for substrate 102, the adhesion between the glass substrate and the ITSO film is higher than that between the glass substrate and the copper film. Furthermore, by using the same material for both conductive layers 112a_2 and 112a_3, the processing of conductive layers 112a_2 and 112a_3 through the same steps becomes easier, thereby improving the manufacturing yield of semiconductor devices. For example, a first film is formed as conductive layer 112a_3, conductive layer 112a_1 is formed on the first film, and a second film as conductive layer 112a_2 is formed on the first film and conductive layer 112a_1. Furthermore, conductive layer 112a, comprising conductive layer 112a_3, conductive layer 112a_1, and conductive layer 112a_2, can be formed by processing the first and second films. By processing the first and second films using the same process, manufacturing costs can be reduced.

[0354] like Figure 14D As shown, the end of conductive layer 112a_1 can be aligned or substantially aligned with the end of conductive layer 112a_3. For example, a first film is formed to become conductive layer 112a_3, and a second film to become conductive layer 112a_1 is formed on the first film. The first film and the second film are processed to form conductive layer 112a_3 and conductive layer 112a_1. Furthermore, conductive layer 112a can be formed by forming conductive layer 112a_2. By processing the first film and the second film in the same steps, manufacturing costs can be reduced.

[0355] Each layer constituting conductive layer 112a (e.g., conductive layer 112a_1, conductive layer 112a_2 and conductive layer 112a_3) may have a single-layer structure or a stacked structure.

[0356] While examples of conductive layer 112a having a two- or three-layer stacked structure are shown herein, the invention is not limited to this. Conductive layer 112a may also have a four- or more-layered stacked structure.

[0357] Note that the structure of conductive layer 112a shown here can be used for other structural examples.

[0358] [Insulation layer 106]

[0359] The insulating layer 106 preferably comprises one or more inorganic insulating layers. The insulating layer 106 may be made of a material that can be used for the insulating layer 110.

[0360] The insulating layer 106 has a region in contact with the semiconductor layer 108, semiconductor layer 208, conductive layer 112b, conductive layer 104, conductive layer 204, conductive layer 212a, conductive layer 212b, and insulating layer 110. When metal oxides are used for semiconductor layers 108 and 208, the films constituting the insulating layer 106 that are in contact with at least semiconductor layers 108 and 208 preferably use any one of the aforementioned oxides and oxynitrides. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be appropriately used for the insulating layer 106.

[0361] Note that when the gate insulating layer is thin in a micro-transistor, leakage current sometimes increases. By using a material with a high relative permittivity (also known as a high-k material) in the gate insulating layer, it is possible to achieve low voltage operation of the transistor while maintaining the physical thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium. Furthermore, ferroelectric materials can be used as the gate insulating layer. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO. XMetal oxides such as (X is a real number greater than 0). Furthermore, materials that can exhibit ferroelectric properties include hafnium oxide with the addition of element J1 (here, element J1 is selected from one or more of zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to 1. Furthermore, materials that can exhibit ferroelectric properties include zirconium oxide with the addition of element J2 (here, element J2 is selected from one or more of hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Furthermore, the ratio of the number of zirconium atoms to the number of element J2 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to 1. Furthermore, lead titanate (PbTiO2) can be used as a material that can exhibit ferroelectric properties. X Piezoelectric ceramics with perovskite structure include barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate.

[0362] Figure 1B The diagram shows that the insulating layer 106 has a single-layer structure, but this is not the only aspect of the invention. The insulating layer 106 may also have a multilayer structure.

[0363] Figure 15A and Figure 15B A cross-sectional view of a semiconductor device 10D according to one embodiment of the present invention is shown. A top view of the semiconductor device 10D can be seen from [reference needed]. Figure 1A . Figure 15A It is along Figure 1A The cross-sectional view of the section along the dotted line A1-A2 shown is shown. Figure 15B It is a cross-sectional view of the section along the dotted line B1-B2.

[0364] The semiconductor device 10D includes transistor 100C, transistor 200D, insulating layer 110, and insulating layer 109. Figure 15C An enlarged view of transistor 100C is shown. Figure 16A and Figure 16B An enlarged view of transistor 200D is shown.

[0365] Figures 15A to 15C , Figure 16A and Figure 16B The insulating layer 106 is shown to have a two-layer structure, including an insulating layer 106a and an insulating layer 106b on the insulating layer 106a.

[0366] When the insulating layer 106 has a stacked structure, the insulating layer (here, insulating layer 106a) on one side of the semiconductor layer 108 and semiconductor layer 208 preferably contains an oxide or an oxynitride. The insulating layer 106a may, for example, suitably use one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

[0367] Preferably, a material that is not easily permeable to other substances is used in one or more of the layers constituting the insulating layer 106. This layer can also be described as acting as a barrier film. By providing a layer that acts as a barrier film, in the transistor 100C, the diffusion of metallic components contained in the conductive layer 104 and impurities (such as water and hydrogen) contained in the layers formed on the transistor 100C through the insulating layer 106 to the semiconductor layer 108 can be suppressed. Furthermore, the diffusion of oxygen contained in the semiconductor layer 108 through the insulating layer 106 to the conductive layer 104 side can be suppressed. Thus, the formation of oxygen vacancies (V0) in the semiconductor layer 108 can be suppressed. O Furthermore, the high resistance of the conductive layer 104 due to oxidation of the conductive layer 104 caused by oxygen contained in the semiconductor layer 108 can be suppressed. The same applies to the transistor 200D. As a result, transistors 100C and 200D exhibiting good electrical characteristics and high reliability can be realized. Preferably, one or more of the aforementioned nitrides and oxynitrides are used for this layer as a barrier film. Alternatively, one or more of oxides and oxynitrides can also be used as this layer; for example, aluminum oxide can be suitably used.

[0368] When the insulating layer 106 has a stacked structure, for example, silicon oxynitride can be used for insulating layer 106a and silicon nitride can be used for insulating layer 106b. Alternatively, silicon oxynitride can be used for insulating layer 106a and aluminum oxide can be used for insulating layer 106b. Alternatively, aluminum oxide can be used for insulating layer 106a and silicon oxynitride can be used for insulating layer 106b. Alternatively, aluminum oxide can be used for insulating layer 106a and silicon nitride can be used for insulating layer 106b.

[0369] An example of a two-layer laminated structure for insulating layer 106 is shown here, but the invention is not limited to this. Insulating layer 106 may also have a three-layer or higher laminated structure.

[0370] Note that the structure of insulating layer 106 shown here can also be used for other structural examples.

[0371] [Insulation layer 195]

[0372] The insulating layer 195, used as a protective layer, is preferably made of a material that does not easily allow impurities to diffuse. By providing the insulating layer 195, the diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.

[0373] The insulating layer 195 can be an insulating layer containing inorganic materials or an insulating layer containing organic materials. For example, inorganic materials such as oxides, oxynitrides, oxynitrides, or nitrides can be suitably used in the insulating layer 195. More specifically, one or more of silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of acrylic resins and polyimide resins can be used as organic materials. Photosensitive materials can be used as organic materials. Furthermore, two or more of the above-mentioned insulating films can be laminated. The insulating layer 195 can adopt a laminated structure of an insulating layer containing inorganic materials and an insulating layer containing organic materials.

[0374] [Substrate 102]

[0375] While there are no particular restrictions on the material of substrate 102, it must at least possess heat resistance capable of withstanding subsequent heat treatment. For example, substrate 102 can be a single-crystal semiconductor substrate or polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon-germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate. Furthermore, semiconductor elements can be disposed on substrate 102. Substrate 102 can also be a substrate with an insulating film formed on its surface. Note that the shapes of the semiconductor substrate and the insulating substrate can be circular or angular.

[0376] As substrate 102, a flexible substrate can be used, and transistors such as 100 can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between substrate 102 and transistors such as 100. By providing a release layer, a portion or all of a semiconductor device can be fabricated on the release layer and then separated from substrate 102 and transferred to another substrate. In this case, transistors such as 100 can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0377] The following describes structural examples that differ in some aspects from structural example 1 described above. Sometimes, descriptions of parts that overlap with structural example 1 are omitted. Furthermore, in the accompanying drawings shown below, parts having the same function as those in structural example 1 are depicted using the same shaded lines, and sometimes reference numerals are not added.

[0378] <Structure Example 2>

[0379] Figure 17A and Figure 17B A cross-sectional view of a semiconductor device 10E according to one embodiment of the present invention is shown. A top view of the semiconductor device 10E can be seen by referring to... Figure 1A . Figure 17A It is along Figure 1A The cross-sectional view of the section along the dotted line A1-A2 shown is shown. Figure 17BIt is a cross-sectional view of the section along the dotted line B1-B2.

[0380] Semiconductor device 10E includes transistor 100, transistor 200, insulating layer 110, insulating layer 109, and insulating layer 105. Semiconductor device 10E and... Figure 8A The main difference of the semiconductor device 10 shown is that it includes an insulating layer 105.

[0381] An insulating layer 105 is disposed on a substrate 102, a conductive layer 112a is disposed on the insulating layer 105, and an insulating layer 110 is disposed on the conductive layer 112a. The insulating layer 105 has a region that contacts the bottom surface of the conductive layer 112a and the bottom surface of the insulating layer 110. The conductive layer 112a has a region that is sandwiched between the insulating layers 105 and 110. The insulating layer 110 has a region that contacts the top and side surfaces of the conductive layer 112a, the top surface of the insulating layer 105, the side surface of the semiconductor layer 108, the bottom surface of the conductive layer 112b, and the bottom surface of the insulating layer 106.

[0382] The insulating layer 105 is preferably made of a material that releases impurities (e.g., water and hydrogen) that reduce the resistance of the semiconductor layer 108. The insulating layer 105 can be made of a material that can be used for both the insulating layers 110d and 110e. The insulating layer 105 is preferably made of, for example, silicon nitride or silicon oxynitride.

[0383] Impurities released from the insulating layer 105 diffuse into the region of the conductive layer 112a that contacts the insulating layer 105. Furthermore, impurities diffused into the conductive layer 112a also diffuse into the region of the semiconductor layer 108 that contacts the conductive layer 112a. This reduces the resistance of one of the source or drain regions in the region of the semiconductor layer 108 that contacts the conductive layer 112a. Therefore, transistors with high on-state current can be realized, enabling high-speed semiconductor devices.

[0384] When a metal oxide is used as the semiconductor layer 108, the impurities released from the insulating layer 105 more preferably contain hydrogen atoms. As the hydrogen diffuses from the insulating layer 105 through the conductive layer 112a to the semiconductor layer 108, the carrier concentration in the region of the semiconductor layer 108 in contact with the conductive layer 112a increases, which can reduce the resistance of one of the source and drain regions.

[0385] The insulating layer 105 is more preferably made of a material that releases impurities that reduce the resistance of the conductive layer 112a. This reduces the resistance of the conductive layer 112a. For example, when a metal oxide is used in the conductive layer 112a, the impurity more preferably contains hydrogen atoms. This increases the carrier concentration in the conductive layer 112a, thereby reducing its resistance. Furthermore, the conductive layer 112a can be used for wiring, enabling a semiconductor device with low wiring resistance. Note that the impurities reducing the resistance of the conductive layer 112a may be the same as or different from the impurities reducing the resistance of the semiconductor layer 108.

[0386] The material that can be used for the conductive layer 112a is the material described above. Furthermore, the conductive layer 112a is more preferably permeable to impurities. The conductive layer 112a is more preferably not prone to adsorbing impurities.

[0387] Figure 17A The insulating layer 110 is shown to include insulating layer 110a, insulating layer 110b, insulating layer 110c and insulating layer 110e.

[0388] The insulating layer 110a has a region that contacts the top surface of the insulating layer 105 and the top and side surfaces of the conductive layer 112a. This can suppress the diffusion of impurities contained in the insulating layer 105 and the conductive layer 112a through the insulating layer 110b into the channel formation region of the semiconductor layer 108.

[0389] The insulating layer 105 preferably includes regions with a higher hydrogen content than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 105. For details regarding the insulating layer 105, please refer to the descriptions of the insulating layers 110d and 110e.

[0390] Note that sometimes impurities released from insulating layer 105 diffuse through one of the source and drain regions of conductive layer 112a and semiconductor layer 108 to the channel formation region. However, at least the region of semiconductor layer 108 in contact with insulating layer 110b is supplied with oxygen from insulating layer 110b, thus reducing oxygen vacancies (V) in the channel formation region. O ) and V O H. Therefore, threshold voltage drift can be suppressed, enabling the realization of transistors with low cutoff current and high on-state current. This allows for the acquisition of semiconductor devices that simultaneously achieve low power consumption and high performance.

[0391] exist Figure 17A In the present invention, insulating layer 110 has a four-layer structure consisting of insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110e; however, one embodiment of the invention is not limited thereto. There are no particular limitations on the structure of insulating layer 110. For example, insulating layer 110 may have a five-layer structure consisting of insulating layers 110a to 110e.

[0392] like Figures 18A to 18C As shown, the insulating layer 110 can contact the side surface of the insulating layer 105. Furthermore, the end of the insulating layer 105 can be aligned or substantially aligned with the end of the conductive layer 112a. For example, the insulating layer 105 and the conductive layer 112a can be formed by forming an insulating film as the insulating layer 105 and a conductive film as the conductive layer 112a, and then processing them. By processing the insulating film and the conductive film in the same steps, manufacturing costs can be reduced.

[0393] A structure can be adopted in which the end of the insulating layer 105 is not aligned with the end of the conductive layer 112a. For example... Figure 19 As shown, the insulating layer 105 preferably has a portion that protrudes beyond the end of the conductive layer 112a. The end of the conductive layer 112a contacts the top surface of the insulating layer 105. By employing this structure, the steps of the surfaces on which the layers (e.g., insulating layer 110) are formed on the conductive layer 112a and the insulating layer 105 are reduced, thereby improving the coverage of the layers. This helps to suppress problems such as breaks or voids in the layers.

[0394] Alternatively, the structure of the insulating layer 105 shown in structural example 2 can be applied to other structural examples.

[0395] <Structure Example 3>

[0396] Figure 20A A top view of a semiconductor device 10F according to one embodiment of the present invention is shown. Along... Figure 20A The cross-sectional view of the dashed line A1-A2 shown can be referred to Figure 1B . Figure 20B Show along Figure 20A The cross-sectional view of the section along the dotted line B1-B2 is shown.

[0397] Semiconductor device 10F includes transistor 100, transistor 200, insulating layer 110, insulating layer 109, and capacitor 150A. Capacitor 150A and... Figure 1C The main difference of the capacitor 150 shown is that it includes a conductive layer 112a instead of a conductive layer 112b, and includes an insulating layer 110 in addition to an insulating layer 109.

[0398] The capacitor 150A includes a conductive layer 112a and a conductive layer 202 serving as a pair of electrodes, and an insulating layer 109 and an insulating layer 110 sandwiched between them. The conductive layer 112a serves as one of the source electrode and drain electrode of the transistor 100 and also serves as one of the pair of electrodes of the capacitor 150A.

[0399] Furthermore, the structure of the 150A capacitor shown in structural example 3 can also be applied to other structural examples.

[0400] <Structure Example 4>

[0401] Figure 21A This is a cross-sectional view of a transistor 100D, which can be used in one aspect of the present invention. A top view of the transistor 100D can be seen in [reference needed]. Figure 1A The transistor 100 shown. Figure 21A It is along Figure 1A The cross-sectional view of the transistor 100 along the dotted line A1-A2 is shown.

[0402] Transistor 100D and Figure 1B The main difference between the transistor 100 shown is that the thickness of the region of the conductive layer 112a that contacts the bottom surface of the semiconductor layer 108 is different from the thickness of the region that does not contact the semiconductor layer 108.

[0403] like Figure 21A As shown, the thickness of the region of conductive layer 112a that contacts the bottom surface of semiconductor layer 108 is preferably thinner than the thickness of the region that does not contact semiconductor layer 108. When conductive layer 112a has a recess, semiconductor layer 108 also contacts the side surface of conductive layer 112a, thus increasing the contact area between conductive layer 112a and semiconductor layer 108, thereby reducing their contact resistance. This, in turn, increases the on-state current of transistor 100D.

[0404] Figure 21A The height H104 is shown from the lowest point of the conductive layer 112a (here, the top surface of the substrate 102) to the bottom surface of the conductive layer 104. Furthermore, the height H112 is shown from the highest point of the conductive layer 112a in the region where it contacts the semiconductor layer 108 (here, the top surface of the substrate 102). Height H104 is preferably the same as or substantially the same as height H112. Alternatively, as... Figure 21B As shown, height H104 is preferably lower than height H112. By making height H104 the same as or lower than height H112, the electric field of the gate electrode applied to the channel formation region near the conductive layer 112a can be enhanced, thereby increasing the on-state current of transistor 100D. Furthermore, the electric field applied to the gate electrode in the channel formation region can be made more uniform.

[0405] Here, when the electric field applied to the gate electrode in the channel formation region is non-uniform, the electrical characteristics sometimes differ between the case where conductive layer 112a is used as the source electrode and conductive layer 112b is used as the drain electrode and the case where conductive layer 112a is used as the drain electrode and conductive layer 112b is used as the source electrode. When the gate electrode electric field applied to the channel formation region of transistor 100D is more uniform, the electrical characteristics can be made equal. Therefore, transistor 100D can be appropriately used in circuit structures where the source and drain electrodes are interchanged.

[0406] In addition, the thickness of the conductive layer 112a can be appropriately adjusted so that the height H104 is the same as or lower than the height H112.

[0407] Furthermore, the structure of conductive layer 112a shown in structural example 4 can also be applied to other structural examples.

[0408] <Structure Example 5>

[0409] Figure 22A A top view of a semiconductor device 10G according to one aspect of the present invention is shown. Figure 22B Show along Figure 22A The cross-sectional view of the section along the dotted line A1-A2 shown is shown. Figure 22C This shows a cross-sectional view along the dashed line B1-B2.

[0410] Semiconductor device 10G includes transistor 100E, transistor 200, insulating layer 110, and insulating layer 109. Transistor 100E and... Figure 1B The main difference of the transistor 100 shown is that it includes a conductive layer 103.

[0411] A conductive layer 103 is disposed between an insulating layer 110d and an insulating layer 110a. The conductive layer 103 is disposed on the insulating layer 110d, and the insulating layer 110a is disposed such that it covers the conductive layer 103.

[0412] The conductive layer 112a and the conductive layer 103 are electrically insulated from each other by the insulating layer 110d. The conductive layer 103 has an opening 148 in the region where it overlaps with the conductive layer 112a, which leads to the insulating layer 110d.

[0413] There are no particular restrictions on the shape of the top surface of the opening 148. The top surface shape of the opening 148 can be a shape that can be used for the opening 141. For example... Figure 22A As shown, the top surfaces of both openings 141 and 148 are preferably circular. By making the top surface of the opening circular, the machining accuracy during the formation of the opening can be improved, and fine openings can be formed.

[0414] In this specification, the top surface shape of the opening 148 refers to the shape of the top end or bottom end of the opening 148 of the conductive layer 103.

[0415] When the top surfaces of openings 141 and 148 are circular, they are preferably concentric circles. This ensures that the shortest distance between the semiconductor layer 108 and the conductive layer 103, viewed in cross-section, is the same on both the left and right sides of opening 141. However, openings 141 and 148 are sometimes not concentric circles.

[0416] In transistor 100E, semiconductor layer 108 has a region that overlaps with conductive layer 104 across insulating layer 106 and with conductive layer 103 across a portion of insulating layer 110 (especially insulating layers 110a and 110b). In other words, there is a region in semiconductor layer 108 sandwiched between conductive layer 104 and conductive layer 103, wherein insulating layer 106 is sandwiched between semiconductor layer 108 and conductive layer 104 and a portion of insulating layer 110 (especially insulating layers 110a and 110b) is sandwiched between semiconductor layer 108 and conductive layer 103.

[0417] Conductive layer 104 serves as the gate electrode (also referred to as the first gate electrode) of transistor 100E, and a portion of insulating layer 106 serves as a gate insulating layer (also referred to as the first gate insulating layer). Conductive layer 103 serves as the back gate electrode (also referred to as the second gate electrode) of transistor 100E. Furthermore, a portion of insulating layer 110 serves as the back gate insulating layer (also referred to as the second gate insulating layer) of transistor 100E. Conductive layer 103 can use materials suitable for conductive layers 112a and 104. Note that conductive layer 103 may be omitted.

[0418] By providing a back gate electrode in transistor 100E, the potential of the back gate electrode side (also known as the back channel side) of semiconductor layer 108 can be fixed, and the saturation of Id-Vd characteristics can be improved.

[0419] Because transistor 100E includes a back gate electrode, the potential on the back gate electrode side of semiconductor layer 108 can be fixed, suppressing threshold voltage drift. Here, when the threshold voltage of the transistor drifts negatively, the cutoff current sometimes increases. By suppressing threshold voltage drift, a transistor with low cutoff current can be realized. Therefore, a semiconductor device with low power consumption can be realized.

[0420] The conductive layer 103 can be electrically connected to the conductive layer 112a. For example, by providing an opening in the region of the insulating layer 110d that overlaps with the conductive layer 112a and providing the conductive layer 103 in a manner that covers the opening, the conductive layer 103 can be in contact with the conductive layer 112a. By electrically connecting the conductive layer 112a, which serves as a source electrode or drain electrode, to the conductive layer 103, which serves as a back gate electrode, the source electrode or drain electrode and the back gate electrode can be made to have the same potential. For example, when the conductive layer 112a is used as a source electrode, threshold voltage drift of the transistor 100E can be suppressed. In addition, the reliability of the transistor 100E can be improved.

[0421] Conductive layer 103 can be electrically connected to conductive layer 104. For example, by providing an opening in the region of insulating layer 106 and insulating layer 110 that overlaps with conductive layer 103 and providing conductive layer 104 in a manner that covers the opening, conductive layer 103 can be in contact with conductive layer 104. By electrically connecting conductive layer 104, which serves as a gate electrode, to conductive layer 103, which serves as a back gate electrode, the back gate electrode and the gate electrode can be made to have the same potential, thereby increasing the on-state current of transistor 100E.

[0422] The thickness of the conductive layer 103 can be greater than the thickness of the insulating layer 110. As a result, the potential on the back gate electrode side of the semiconductor layer 108 can be fixed over a large area between the source and drain regions in the semiconductor layer 108.

[0423] Transistor 100E has a region in which conductive layer 103, insulating layer 110, semiconductor layer 108, insulating layer 106, and conductive layer 104 overlap sequentially without any other layers between them. An example of this direction is a direction perpendicular to the channel length direction. By expanding this region, the potential on the back gate electrode side of semiconductor layer 108 can be controlled more reliably.

[0424] The thickness of the conductive layer 103 can be greater than the sum of the thickness of the portion inside the opening 141 of the semiconductor layer 108 that contacts the conductive layer 112a and the thickness of the insulating layer 106 that contacts that portion.

[0425] Furthermore, the structure of the conductive layer 103 shown in structural example 5 can also be applied to other structural examples.

[0426] <Structure Example 6>

[0427] Figure 23A An equivalent circuit diagram of transistor 100F in a semiconductor device that can be used in one aspect of the present invention is shown. Transistor 100F is a group of transistors including transistors 100_1 to 100_p (p being an integer greater than or equal to 2). Transistors 100_1 to 100_p are connected in parallel, and transistor 100F can be regarded as a single transistor.

[0428] The gate electrodes of transistors 100_1 to 100_p are electrically connected to each other. The source electrodes of transistors 100_1 to 100_p are electrically connected to each other. The drain electrodes of transistors 100_1 to 100_p are electrically connected to each other.

[0429] Note that in Figure 23A In this embodiment, transistors 100_1 to 100_p are n-channel transistors, but one embodiment of the invention is not limited to this. Transistors 100_1 to 100_p can also be p-channel transistors.

[0430] Let's take the case where p is 4 as an example for a specific explanation. Figure 23B An equivalent circuit diagram of a transistor 100F according to one aspect of the present invention is shown. Figure 23C A top view of transistor 100F is shown. Figure 24 Show along Figure 23C The cross-sectional view of the section between the dotted and dashed lines A3-A4 in the figure. Figure 25 A 3D view of transistor 100F is shown.

[0431] Transistor 100F includes transistors 100_1 to 100_4. Transistors 100_1 to 100_4 can all employ the structure of transistor 100 described above. Note that this description uses transistor 100 as an example, but the invention is not limited to this. Any one of transistors 100_1 to 100_4 can be used, from transistors 100A to 100G.

[0432] exist Figure 23C The diagram shows transistors 100_1 to 100_4 arranged in a 2x2 row configuration, but there are no particular restrictions on the arrangement of the individual transistors constituting transistor 100F. For example, transistors 100_1 to 100_4 can also be arranged in a 1x4 row configuration. Alternatively, the transistors can be arranged in a matrix. Or, they can be arranged without a matrix configuration.

[0433] Transistors 100_1 to 100_4 all include a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 serves as the gate electrode of transistors 100_1 to 100_4. A portion of the insulating layer 106 serves as the gate insulating layer of transistors 100_1 to 100_4. The conductive layer 112a serves as the other of the source and drain electrodes of transistors 100_1 to 100_4, and the conductive layer 112b serves as one of the source and drain electrodes.

[0434] Figure 26A This is a three-dimensional view showing the conductive layer 112a.

[0435] Figure 26B This is a perspective view summarizing the conductive layers 112a and 112b, and openings 141_1 to 141_4 and 143_1 to 143_4. Note that openings 141_1 to 141_4 provided in the insulating layer 110 are shown in dashed lines. Details of openings 141_1 to 141_4 and openings 143_1 to 143_4 can be found in the description of openings 141 and 143, so detailed descriptions are omitted.

[0436] When transistor 100F is considered as a single transistor, its channel width is the sum of the channel widths of transistors 100_1 to 100_4. For example, when the top surfaces of openings 141_1 to 141_4 are circular and the width of each opening 141_1 to 141_4 is denoted as width D141, transistor 100F can be considered as a transistor with a channel width of "D141×π×4" (see reference). Figure 3A and Figure 3B Transistor 100F, consisting of p transistors, can be considered as a transistor with a channel width of "D141×π×p". Furthermore, transistor 100F can be considered as a transistor with a channel length L100 (see reference). Figure 3B By connecting multiple transistors in parallel, the channel width is increased, thereby increasing the on-state current. Furthermore, the channel width can be varied by adjusting the number (p) of transistors connected in parallel. The number (p) of transistors connected in parallel is determined to achieve the desired on-state current.

[0437] Figure 26C This is a perspective view illustrating the conductive layer 112a and the semiconductor layer 108. The semiconductor layer 108 is disposed such that it covers openings 141_1 to 141_4 and openings 143_1 to 143_4. Note that in... Figure 26C The diagram shows the structure of transistors 100_1 to 100_4 sharing a common semiconductor layer 108, but one aspect of the invention is not limited thereto. The semiconductor layer 108 may also be separated for transistors 100_1 to 100_4.

[0438] Figure 26D This is a perspective view showing the conductive layer 112a and the conductive layer 104. The conductive layer 104 is provided such that it covers the openings 141_1 to 141_4 and the openings 143_1 to 143_4.

[0439] Furthermore, the structure of transistor 100F shown in structural example 6 can also be applied to other structural examples. For example, transistor 100F can be used as one or more of the transistors included in the semiconductor devices shown in Figures 1 to 22.

[0440] <Structure Example 7>

[0441] Figure 27A An equivalent circuit diagram of a transistor 100G in a semiconductor device that can be used in one aspect of the present invention is shown. Transistor 100G is a group of transistors including transistors 100_1 to 100_q (q being an integer greater than or equal to 2). Transistors 100_1 to 100_q are connected in series, and transistor 100G can be considered as a single transistor.

[0442] Note that in Figure 27A In this embodiment, transistors 100_1 to 100_q are n-channel transistors, but one embodiment of the invention is not limited to this. Transistors 100_1 to 100_q can also be p-channel transistors.

[0443] Let's take the case where q is 4 as an example for a specific explanation. Figure 27B An equivalent circuit diagram of a transistor 100G according to one embodiment of the present invention is shown. Figure 27C A top view of transistor 100G is shown. Figure 28 Show along Figure 27C The cross-sectional view of the section along the dotted-dash lines A5-A6 is shown. Figure 29 A 3D view of transistor 100G is shown.

[0444] Transistor 100G includes transistors 100_1 to 100_4. Transistors 100_1 to 100_4 can all adopt the structure of transistor 100 described above. Note that this description uses transistor 100 as an example, but the invention is not limited to this. Any one of transistors 100_1 to 100_4 can be used, from transistors 100A to 100G.

[0445] exist Figure 27C The diagram shows transistors 100_1 to 100_4 arranged in a 2-row, 2-column configuration, but there are no particular restrictions on the arrangement of the individual transistors constituting transistor 100G. For example, transistors 100_1 to 100_4 can also be arranged in a 1-row, 4-column configuration. Alternatively, the transistors can be arranged in a matrix. Or, they can be arranged without a matrix configuration.

[0446] Transistor 100_1 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b. Conductive layer 112a is used as one of the source electrode and the drain electrode of transistor 100_1, and conductive layer 112b is used as the other of the source electrode and the drain electrode.

[0447] Transistor 100_2 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112a, and a conductive layer 112c. Conductive layer 112a serves as one of the source and drain electrodes of transistor 100_2, and conductive layer 112c serves as the other. Transistor 100_1 and transistor 100_2 share conductive layer 112a.

[0448] Transistor 100_3 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d. Conductive layer 112c serves as one of the source and drain electrodes of transistor 100_3, and conductive layer 112d serves as the other. Transistors 100_2 and 100_3 share conductive layer 112c.

[0449] Transistor 100_4 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e. Conductive layer 112d serves as one of the source and drain electrodes of transistor 100_4, and conductive layer 112e serves as the other. Transistors 100_3 and 100_4 share conductive layer 112d.

[0450] Figure 30A This is a perspective view showing conductive layer 112a and conductive layer 112d. Conductive layer 112a and conductive layer 112d can be formed by the same process.

[0451] Figure 30B This is a perspective view illustrating conductive layers 112a, 112b, 112c, 112d, 112e, openings 141_1 to 141_4, and openings 143_1 to 143_4. Conductive layers 112a to 112e can be formed by the same process. Opening 143_1 is provided in conductive layer 112b, openings 143_2 and 143_3 are provided in conductive layer 112c, and opening 143_4 is provided in conductive layer 112e.

[0452] Figure 30C This is a perspective view illustrating conductive layer 112a, conductive layer 112d, and semiconductor layers 108_1 to 108_4. Semiconductor layers 108_1 to 108_4 can be formed by the same process.

[0453] Figure 30D This is a perspective view illustrating conductive layers 112a, 112d, and 104. Conductive layer 104 is used as the gate electrode of transistors 100_1 to 100_4.

[0454] One of the source and drain electrodes of transistor 100_1 is electrically connected to one of the source and drain electrodes of transistor 100_2. The other of the source and drain electrodes of transistor 100_2 is electrically connected to one of the source and drain electrodes of transistor 100_3. The other of the source and drain electrodes of transistor 100_3 is electrically connected to one of the source and drain electrodes of transistor 100_4.

[0455] When transistor 100G is considered as a single transistor, its channel length is the sum of the channel lengths of transistors 100_1 to 100_4. For example, when the channel lengths of transistors 100_1 to 100_4 are each denoted as channel length L100, transistor 100G can be considered as a transistor with a channel length of "L100×4" (see reference). Figure 3B Transistor 100G, consisting of q transistors, can be considered as a transistor with a channel length of "L100×q". Furthermore, transistor 100G can be considered as a transistor with a channel width W100 (see reference). Figure 3A and Figure 3B By connecting multiple transistors in series, the channel length is increased, thereby improving saturation. Furthermore, the channel length can be varied by adjusting the number (q) of transistors connected in series. The number (q) of transistors connected in series is determined in a way that achieves the desired saturation.

[0456] Furthermore, the structure of transistor 100G shown in structural example 7 can also be applied to other structural examples. For example, transistor 100G can be used as one or more of the transistors included in the semiconductor devices shown in Figures 1 to 22.

[0457] Transistor 100G can be used as the individual transistors included in transistor 100F. That is, a group of transistors connected in parallel can also be connected in series (hereinafter also referred to as series-parallel connection).

[0458] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0459] (Implementation Method 2)

[0460] In this embodiment, refer to Figures 31A to 37 This invention describes a method for manufacturing a semiconductor device according to one aspect of the present invention. Note that, regarding the materials and forming methods of each constituent element, some parts that are the same as those described in Embodiment 1 above are sometimes omitted.

[0461] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and alumina deposition (ALD). CVD methods include PECVD and thermal CVD. Furthermore, metal-organic chemical vapor deposition (MOCVD) is one type of thermal CVD method.

[0462] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0463] When processing thin films that constitute semiconductor devices, photolithography and other methods can be used. Alternatively, nanoimprint lithography, sandblasting, and lift-off methods can be used to process the thin films. In addition, island-shaped thin films can be directly formed by deposition methods that use metal masks or other masking methods.

[0464] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, processing the film by etching, and then removing the resist mask. The other method involves depositing a photosensitive thin film, exposing it to light, and then developing it to form the desired shape.

[0465] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can be employed. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferred because they allow for extremely fine processing. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0466] As a method for etching thin films, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0467] <Example of Manufacturing Method>

[0468] Here, refer to Figures 31A to 37 illustrate Figure 8A and Figure 8B An example of a method for manufacturing the semiconductor device 10 shown. Figures 31A to 37 Showing side by side along Figure 1A The cross-sectional view along the dotted-dash line A1-A2 and the cross-sectional view along the dotted-dash line B1-B2 are shown.

[0469] First, a film forming a conductive layer 112a is formed on a substrate 102, and the film is processed to form the conductive layer 112a. The film can be formed by sputtering.

[0470] Next, an insulating film 110df becoming an insulating layer 110d, an insulating film 110af becoming an insulating layer 110a, and an insulating film 110bf becoming an insulating layer 110b are formed on the conductive layer 112a. Figure 31A ).

[0471] The insulating films 110df, 110af, and 110bf can be formed using sputtering or PECVD methods. Preferably, the insulating film 110af is formed after the formation of the insulating film 110df in a manner that prevents the surface of the insulating film 110df from being exposed to the atmosphere. Similarly, it is preferable to form the insulating film 110bf after the formation of the insulating film 110af in a manner that prevents the surface of the insulating film 110af from being exposed to the atmosphere. This suppresses the adhesion of atmospheric impurities to the interfaces between the insulating films 110df and 110af, and between the insulating films 110af and 110bf. Examples of such impurities include water and organic matter. For example, it is preferable to continuously form the insulating films 110af and 110bf using the same apparatus after the formation of the insulating film 110df.

[0472] The substrate temperature during the formation of insulating films 110df, 110af, and 110bf is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. By setting the substrate temperature during the formation of insulating films 110df, 110af, and 110bf within the above range, impurities (such as water and hydrogen) released from the insulating films 110df, 110af, and 110bf themselves can be reduced, thereby suppressing impurity diffusion into the semiconductor layer 108. Therefore, transistors exhibiting good electrical characteristics and high reliability can be realized.

[0473] Note that insulating films 110df, 110af, and 110bf are formed before semiconductor layers 108 and 208 are formed, so there is no need to worry about oxygen detaching from semiconductor layers 108 and 208 due to the heat applied during the formation of insulating films 110df, 110af, and 110bf.

[0474] Oxygen can be supplied to the insulating film 110bf after its formation. Methods for supplying oxygen include, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. For plasma treatment, a device that plasma-plasmizes oxygen gas at high-frequency power can be suitably used. Examples of devices that plasma-plasmize gas at high-frequency power include PECVD devices, plasma etching devices, and plasma ashing devices. Plasma treatment is preferably performed in an oxygen-containing atmosphere. For example, plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N₂O), nitrogen dioxide (NO₂), carbon monoxide, and carbon dioxide.

[0475] Furthermore, the plasma treatment can be performed in a manner that prevents the surface of the insulating film 110bf from being exposed to the atmosphere. For example, if a PECVD apparatus is used when forming the insulating film 110bf, it is preferable to use the same PECVD apparatus for the plasma treatment. This can improve productivity. Specifically, N2O plasma treatment can be performed continuously using the same apparatus after the insulating film 110bf is formed using the PECVD apparatus.

[0476] Preferably, film 137 is formed on insulating film 110bf. Figure 31B Membrane 137 preferably contains oxygen. By forming membrane 137, oxygen can be supplied to insulating membrane 110bf.

[0477] There are no limitations on the conductivity of film 137. Film 137 can be at least one of insulating film, semiconductor film and conductive film. Film 137 can be, for example, alumina, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO) or silicon-containing indium tin oxide (ITSO).

[0478] As film 137, it is preferable to use an oxide material containing one or more elements that are the same as those in semiconductor layer 108 and semiconductor layer 208. In particular, it is preferable to use a metal oxide material that can be applied to semiconductor layer 108 and semiconductor layer 208.

[0479] When film 137 is formed, the higher the oxygen flow rate ratio of the deposition gas introduced into the processing chamber of the deposition apparatus or the higher the oxygen partial pressure in the processing chamber, the greater the amount of oxygen supplied to the insulating film 110bf. The oxygen flow rate ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% so that the oxygen partial pressure is as close as possible to 100%.

[0480] Thus, by forming film 137 using sputtering in an oxygen-containing atmosphere, oxygen can be supplied to insulating film 110bf while preventing oxygen from escaping from insulating film 110bf during film formation. As a result, more oxygen can be confined within insulating film 110bf. Furthermore, more oxygen can be supplied to semiconductor layer 108 through subsequent heat treatment. As a result, oxygen vacancies (V0) in semiconductor layer 108 can be reduced. O ) and V O H, thus enabling the realization of transistors that exhibit good electrical characteristics and high reliability.

[0481] Heat treatment can be performed after film 137 is formed. By performing heat treatment after film 137 is formed, oxygen can be effectively supplied from film 137 to insulating film 110bf.

[0482] The preferred heat treatment temperature is 150°C or higher, 200°C or higher, 230°C or higher, or 250°C or higher, and below the strain point of the substrate, 450°C or lower, 400°C or lower, 350°C or lower, or 300°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, and oxygen. Dry air (CDA) can also be used as a nitrogen-containing or oxygen-containing atmosphere. Note that the content of hydrogen or oxygen in this atmosphere is preferably as low as possible. As this atmosphere, a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, is preferred. By using an atmosphere with the lowest possible content of hydrogen, water, etc., the absorption of hydrogen, water, etc., by the insulating films 110df, 110af, and 110bf can be minimized. This heat treatment can be performed using an oven, a rapid thermal annealing (RTA) apparatus, etc. Using an RTA apparatus can shorten the heat treatment time.

[0483] Alternatively, oxygen can be supplied to the insulating film 110bf through film 137 after film 137 is formed or after the above-mentioned heat treatment. The method of oxygen supply can be referred to the above description, so detailed description is omitted.

[0484] Next, film 137 is removed. While there are no particular limitations on the method for removing film 137, wet etching can be appropriately employed. By using wet etching, etching of the insulating film 110bf during the removal of film 137 can be suppressed. Therefore, the reduction in the thickness of the insulating film 110bf can be suppressed, and the thickness of the insulating layer 110b can be made uniform.

[0485] Alternatively, oxygen can be supplied to the insulating film 110bf after the film 137 is removed. The method of supplying oxygen can be referred to the above description. For example, as... Figure 31CAs shown, a film 139 can be formed on the insulating film 110bf and oxygen can be supplied to the insulating film 110bf through the film 139. As a process for supplying oxygen, plasma treatment in an oxygen-containing atmosphere can be used. Figure 31C The arrows schematically illustrate the supply of oxygen through membrane 139 to insulating membrane 110bf.

[0486] The film 139 is preferably a conductive film or a semiconductor film. The film 139 can be a metal oxide film, a metal film, or an alloy film. When a metal oxide is used as the film 139, it is preferred because when it is formed in an oxygen-containing atmosphere by sputtering or the like, oxygen can be supplied to the insulating film 110bf during the formation of the film 139.

[0487] The thickness of film 139 is preferably thin. Specifically, the thickness of film 139 is preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less. Typically, it can be around 5 nm.

[0488] The substrate temperature during film formation 139 is preferably 350°C or lower, more preferably 340°C or lower, even more preferably 330°C or lower, and even more preferably 300°C or lower. This increases the amount of oxygen supplied to the insulating film 110bf.

[0489] By providing membrane 139, ionized oxygen is readily attracted when a bias voltage is applied between a pair of electrodes while oxygen is supplied. Therefore, the amount of oxygen supplied to insulating membrane 110bf can be increased.

[0490] As the oxygen supply processing apparatus, dry etching apparatus, ashing apparatus, PECVD apparatus, etc., can be appropriately used. In particular, an ashing apparatus is preferred. When applying a bias voltage between a pair of electrodes included in the processing apparatus, the bias voltage can be set to, for example, 10V or more and 1kV or less. Alternatively, the power density of the bias voltage can be set to, for example, 1W / cm². 2 Above and 5W / cm 2 That's all.

[0491] Next, the film 139 is removed. The removal of the film 139 can be appropriately achieved using a wet etching method.

[0492] The treatment of supplying oxygen to the insulating film 110bf is not limited to the methods described above. For example, oxygen free radicals, oxygen atoms, oxygen atom ions, or oxygen molecular ions can be supplied to the insulating film 110bf using ion doping, ion implantation, or plasma treatment. Alternatively, oxygen can be supplied to the insulating film 110bf through a film that inhibits oxygen desorption after forming the film on the insulating film 110bf. Preferably, the film is removed after oxygen supply. As the aforementioned film that inhibits oxygen desorption, conductive or semiconductor films containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used.

[0493] Preferably, more oxygen is released from the insulating layer 110b that contacts the channel formation region of the transistor 100, which has a shorter channel length, compared to the insulating layer 120b that contacts the channel formation region of the transistor 200 with a longer channel length. By supplying oxygen to the insulating film 110bf that forms the insulating layer 110b, the amount of oxygen contained in the insulating layer 110b is increased, which can increase the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108, thus exhibiting good electrical characteristics even in the transistor 100 with a shorter channel length.

[0494] Next, an insulating film 110cf, which becomes an insulating layer 110c, and an insulating film 110ef, which becomes an insulating layer 110e, are formed on the insulating film 110bf. Figure 31D The formation of insulating films 110cf and 110ef can be referred to the description of the formation of insulating films 110af and 110df, so detailed descriptions are omitted.

[0495] Next, a conductive film 112bf, which becomes a conductive layer 112b, is formed on the insulating film 110cf. Figure 32A The conductive film 112bf can be formed, for example, by sputtering.

[0496] Next, a conductive layer 112B is formed by processing the conductive film 112bf. Figure 32B The conductive layer 112B becomes the subsequent conductive layer 112b. The conductive layer 112B can be formed, for example, by a suitable wet etching method.

[0497] Next, an insulating film 109f, which becomes the insulating layer 109, is formed on the conductive layer 112B and the insulating film 110ef. Figure 32C The formation of insulating film 109f can be referred to the records concerning the formation of insulating film 110df and insulating film 110af, so detailed descriptions are omitted.

[0498] Next, a conductive film 202f, which becomes a conductive layer 202, is formed on the insulating film 109f. Figure 33A The conductive film 202f can be formed, for example, by sputtering.

[0499] Next, a conductive layer 202 is formed by processing a conductive film 202f. Figure 33B The conductive layer 202 can be formed, for example, by wet etching.

[0500] Next, an insulating film 120af, which becomes an insulating layer 120a, and an insulating film 120bf, which becomes an insulating layer 120b, are formed on the conductive layer 202 and the insulating film 109f. Figure 33C ).

[0501] When forming insulating films 120af and 120bf, sputtering or PECVD methods can be appropriately used. Preferably, insulating film 120bf is formed after insulating film 120af in a manner that prevents the surface of insulating film 120af from being exposed to the atmosphere. This suppresses the adhesion of atmospheric impurities to the interface between insulating films 120af and 120bf. Examples of such impurities include water and organic matter. For example, it is preferable to continuously form 120bf using the same apparatus after forming insulating film 120af.

[0502] The substrate temperature during the formation of insulating films 120af and 120bf is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. By keeping the substrate temperature during the formation of insulating films 120af and 120bf within the above range, the release of impurities (e.g., water and hydrogen) from the insulating films 120af and 120bf themselves can be reduced, thereby suppressing the diffusion of impurities into the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0503] Note that since insulating films 120af and 120bf are formed first, followed by semiconductor layers 108 and 208, there is no concern about oxygen detaching from semiconductor layers 108 and 208 due to the heat applied during the formation of insulating films 120af and 120bf.

[0504] After the insulating film 120bf is formed, oxygen can be supplied to the insulating film 120bf. The method for supplying oxygen can be found in the above description.

[0505] Next, while forming the insulating layer 109 by processing the insulating films 109f, 120af, and 120bf, an insulating layer 120 including the insulating layers 120a and 120b is formed. Figure 34ABy forming insulating layers 109 and 120 using the same process, their ends can be made to be consistent or substantially consistent. Furthermore, the productivity of the semiconductor device 10 can be improved and manufacturing costs reduced. Insulating layers 109 and 120 are formed at least in the region where the conductive layer 202 is disposed. Additionally, by forming insulating layers 109 and 120, a portion of the insulating layer 110 and the conductive layer 112B are exposed. The processing of insulating films 109f, 120af, and 120bf can, for example, be suitably performed using a dry etching method.

[0506] During the formation of insulating layers 109 and 120, sometimes a portion of the insulating film 110ef (the subsequent insulating layer 110e) in areas that do not overlap with both insulating layers 109 and 120 is etched, resulting in a thinner thickness of the insulating film 110ef in those areas. Similarly, sometimes a portion of the conductive layer 112B (the subsequent conductive layer 112b) in areas that do not overlap with both insulating layers 109 and 120 is etched, resulting in a thinner thickness of the conductive layer 112B in those areas. Preferably, during the etching of insulating layers 109 and 120, the selectivity ratio of the insulating film 110ef and conductive layer 112B to the insulating layers 109 and 120 is high. This suppresses the thinning of the insulating film 110ef and conductive layer 112B, which is therefore preferable.

[0507] Next, a portion of the conductive layer 112B is removed to form a conductive layer 112b having an opening 143. The conductive layer 112b can be formed, for example, by wet etching.

[0508] Next, a portion of insulating films 110df, 110af, 110bf, 110cf, and 110ef are removed to form an insulating layer 110 with an opening 141. Figure 34B An opening 141 is provided in the region overlapping with an opening 143. By forming an opening 141, a portion of the top surface of the conductive layer 112a is exposed. When forming the insulating layer 110, a dry etching method may be appropriately used, for example.

[0509] The opening 141 can be formed, for example, using the same photoresist mask used to form the opening 143. Specifically, a photoresist mask can be formed on the conductive layer 112B, and a portion of the conductive layer 112B can be removed using the photoresist mask to form the opening 143. A portion of the insulating films 110df, 110af, 110bf, 110cf, and 110ef can also be removed using the same photoresist mask to form the opening 143. The opening 141 can also be formed using a different photoresist mask than the one used to form the opening 143.

[0510] Furthermore, a portion of the conductive layer 112a overlapping with the opening 141 can be removed during or after the formation of the opening 141. By making the thickness of the region of the conductive layer 112a that contacts the bottom surface of the semiconductor layer 108 thinner than the thickness of the region that does not contact the semiconductor layer 108, the electric field applied to the gate electrode in the channel formation region near the conductive layer 112a can be enhanced, thereby increasing the on-state current of the transistor.

[0511] Next, a metal oxide film 108f is formed to cover the openings 141 and 143, thus forming the semiconductor layer 108 and the semiconductor layer 208. Figure 34C The metal oxide film 108f is disposed in contact with the top and side surfaces of the conductive layer 112b, the top and side surfaces of the insulating layer 110, the side surface of the insulating layer 110, the top surface of the conductive layer 112a, the side surface of the insulating layer 109, and the top and side surfaces of the insulating layer 120.

[0512] The metal oxide film 108f is preferably formed using a sputtering method with a metal oxide target. Alternatively, the metal oxide film 108f is preferably formed using an ALD method. Because of its high coverage, the ALD method can also be appropriately used when forming the metal oxide film 108f that is provided in a manner covering the opening 141. By using the ALD method, a metal oxide film with high coverage can also be formed on the side of the insulating layer 110. Furthermore, the ALD method makes it easy to control the deposition rate, thus allowing for the formation of thin films with a high yield.

[0513] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film, wherein impurities containing hydrogen atoms are minimized. In particular, a crystalline metal oxide film is preferably used as the metal oxide film 108f.

[0514] When forming the metal oxide film 108f, oxygen gas is preferably used. By using oxygen gas, oxygen can be suitably supplied to the insulating layers 110 and 120. For example, when an oxide or oxynitride is used in the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b. Similarly, when an oxide or oxynitride is used in the insulating layer 120b, oxygen can be suitably supplied to the insulating layer 120b.

[0515] By supplying oxygen to the insulating layer 110b, and then supplying oxygen to the channel formation region of the semiconductor layer 108 in subsequent processes, the oxygen vacancies (V) in the channel formation region can be reduced. O ) and V O H. Furthermore, by supplying oxygen to the insulating layer 120b, oxygen can be supplied to the channel formation region of the semiconductor layer 208 in subsequent processes, thereby reducing oxygen vacancies (V) in the channel formation region.O ) and V O H.

[0516] When forming the metal oxide film 108f, oxygen gas and inert gas (e.g., helium, argon, xenon, etc.) can be mixed. Note that the higher the oxygen flow rate ratio of the deposition gas or the oxygen partial pressure in the processing chamber during the formation of the metal oxide film, the higher the crystallinity of the metal oxide film can be, enabling the realization of highly reliable transistors. On the other hand, the lower the oxygen flow rate ratio or oxygen partial pressure, the more likely a metal oxide film with low crystallinity and high conductivity can be achieved, thereby enabling the realization of transistors with large on-state current.

[0517] Here, when the oxygen flow ratio or oxygen partial pressure is high, the metal oxide film sometimes exhibits a polycrystalline structure. In metal oxide films with a polycrystalline structure, grain boundaries become recombination centers, trapping charge carriers, thus sometimes reducing the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure to prevent the metal oxide film 108f from exhibiting a polycrystalline structure. Because the composition of the metal oxide film predisposes it to have a polycrystalline structure, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure according to the composition of the metal oxide film 108f.

[0518] When the substrate temperature is higher during the formation of the metal oxide film, a more crystalline and denser metal oxide film can be formed. On the other hand, when the substrate temperature is lower, a less crystalline metal oxide film with higher conductivity can be formed.

[0519] The substrate temperature for forming the metal oxide film 108f is preferably above room temperature and below 250°C, more preferably above room temperature and below 200°C, and even more preferably above room temperature and below 140°C. For example, the substrate temperature is preferably above room temperature and below 140°C, which can improve productivity. In addition, crystallinity can be reduced by setting the substrate temperature to room temperature or forming the metal oxide film 108f without heating the substrate.

[0520] At high substrate temperatures, metal oxide films sometimes exhibit a polycrystalline structure. Therefore, it is preferable to adjust the substrate temperature to prevent the metal oxide film 108f from developing a polycrystalline structure. Preferably, the substrate temperature is adjusted according to the composition applied to the metal oxide film 108f.

[0521] When using ALD methods, thermal ALD or PEALD (Plasma Enhanced ALD) deposition methods are preferred. Thermal ALD is preferred because it offers extremely high coverage. PEALD is preferred because it not only offers high coverage but also allows for low-temperature deposition.

[0522] Metal oxide films can be formed, for example, using a precursor containing a constituent metal element and an oxidant, and by the ALD method.

[0523] For example, when forming In-Ga-Zn oxide, three precursors can be used: one containing indium, one containing gallium, and one containing zinc. Alternatively, two precursors can be used: one containing indium, and one containing both gallium and zinc.

[0524] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0525] Examples of gallium-containing precursors include trimethyl gallium, triethyl gallium, gallium trichloride, tris(dimethylamide) gallium(III), gallium acetylacetonate(III), tris(2,2,6,6-tetramethyl-3,5-heptadecanoate) gallium, dimethyl gallium chloride, and diethyl gallium chloride.

[0526] As aluminum-containing precursors, aluminum chloride and trimethylaluminum can be used, for example.

[0527] Examples of tin-containing precursors include tin(IV) chloride and tetra(dimethylamide)tin.

[0528] Examples of zinc-containing precursors include dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptadecanoic acid) zinc, and zinc chloride.

[0529] Examples of oxidizing agents include ozone, oxygen, and water.

[0530] As a method for controlling the composition of the obtained membrane, one or more of the following can be adjusted: the type of source gas, the flow rate ratio of the source gas, the time the source gas flows through, and the order in which the source gas flows through. By adjusting these parameters, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these parameters, a membrane with continuously varying composition can be formed. The composition of the metal oxide film 108f can be continuously varied.

[0531] Before depositing the metal oxide film 108f, it is preferable to perform at least one of the following treatments: a treatment to remove water, hydrogen, and organic matter adsorbed on the surfaces of insulating layers 109, 110, and 120, and a treatment to supply oxygen to insulating layers 110 and 120. For example, a heating treatment can be performed at a temperature of 70°C or higher and 200°C or lower under a reduced pressure atmosphere. Alternatively, a plasma treatment in an oxygen-containing atmosphere can be performed. Alternatively, oxygen can be supplied to insulating layers 110 and 120 by performing a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N₂O). When performing a plasma treatment containing nitrous oxide gas, organic matter on the surfaces of insulating layers 109, 110, and 120 can be appropriately removed, and oxygen can be supplied to insulating layers 110 and 120. Preferably, after such treatment, the metal oxide film 108f is continuously deposited in a manner that prevents the surfaces of insulating layers 109, 110, and 120 from being exposed to the atmosphere.

[0532] Note that when semiconductor layer 108 and semiconductor layer 208 have a stacked structure, it is preferable to deposit the upper metal oxide film continuously after depositing the lower metal oxide film in a manner that does not expose its surface to the atmosphere.

[0533] When semiconductor layer 108 and semiconductor layer 208 have a stacked structure, all layers constituting semiconductor layer 108 and semiconductor layer 208 can be formed using the same deposition method (e.g., sputtering or ALD). Alternatively, each layer can be formed using a different deposition method. For example, a first metal oxide layer can be deposited using sputtering and a second metal oxide layer can be deposited using ALD.

[0534] Next, the metal oxide film 108f is processed into islands to form semiconductor layer 108 and semiconductor layer 208. Figure 35A ).

[0535] When forming semiconductor layers 108 and 208, wet etching can be appropriately used. In this case, sometimes portions of the insulating layers 110 and 120 in areas not overlapping with semiconductor layers 108 and 208 are etched, resulting in a thinning of the insulating layers. Note that in the etching of the metal oxide film 108f, using materials with high selectivity as insulating layers 110 and 120 can suppress the thinning of the insulating layers 110 and 120, which is therefore preferable.

[0536] Preferably, heat treatment is performed after depositing the metal oxide film 108f or after processing the metal oxide film 108f into semiconductor layers 108 and 208. Heat treatment can remove hydrogen and water contained in or adsorbed on the surfaces of the metal oxide film 108f, semiconductor layers 108 and 208. Furthermore, heat treatment can sometimes improve the film quality of the metal oxide film 108f, semiconductor layers 108 and 208 (e.g., reduce defects or increase crystallinity).

[0537] Oxygen can also be supplied from insulating layers 110b and 120b to the metal oxide film 108f, from insulating layer 110b to the semiconductor layer 108, or from insulating layer 120b to the semiconductor layer 208 through heat treatment. This reduces the number of oxygen vacancies (V0) in the channel formation regions of transistors 100 and 200. O More preferably, heat treatment is performed before the metal oxide film 108f is processed into semiconductor layer 108 and semiconductor layer 208. Details regarding heat treatment can be found above, so a detailed description is omitted. Furthermore, not limited to this heat treatment, oxygen is sometimes supplied to the channel formation region during heating processes after the formation of the metal oxide film 108f (e.g., the process of forming insulating layer 106).

[0538] Note that this heat treatment is not always necessary. Alternatively, a heat treatment performed in a later step can be used instead of this one. Sometimes, a heat treatment performed in a later step (e.g., a deposition step) can be used as the heat treatment for this step.

[0539] Preferably, conductive layer 112B, insulating layer 109, conductive layer 202, insulating layer 120, and semiconductor layer 208 are formed sequentially as conductive layer 112b. This suppresses the adhesion of components in the conductive layer (e.g., metals in conductive layer 112b) at the interface between insulating layer 120 and semiconductor layer 208, thereby enabling the transistor 200 to exhibit good electrical characteristics and high reliability.

[0540] Next, an insulating film 106f is formed to serve as a gate insulating layer, covering the semiconductor layer 108, the semiconductor layer 208, and the insulating layer 110. Figure 35B When forming the insulating film 106f, for example, PECVD or ALD methods can be appropriately used.

[0541] When metal oxides are used in semiconductor layers 108 and 208, insulating layer 106 is preferably used as a barrier film to suppress oxygen diffusion. By enabling insulating layer 106 to suppress oxygen diffusion, the diffusion of oxygen contained in semiconductor layers 108 and 208 to the upper side of insulating layer 106 can be suppressed, thereby suppressing oxygen vacancies (V). O This is added to semiconductor layers 108 and 208. As a result, transistors exhibiting good electrical characteristics and high reliability can be realized.

[0542] By increasing the temperature at which the insulating film 106f is formed, an insulating layer 106 with fewer defects can be formed. However, at higher temperatures when the insulating film 106f is formed, oxygen may detach from the semiconductor layers 108 and 208, and sometimes oxygen vacancies (V) in the semiconductor layers 108 and 208 may occur. O ) and V O H increases. The substrate temperature during the formation of the insulating film 106f is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, and even more preferably 300°C or higher and 400°C or lower. By keeping the substrate temperature during the formation of the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced while oxygen detachment from the semiconductor layer 108 and the semiconductor layer 208 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0543] Before forming the insulating film 106f, the surfaces of semiconductor layers 108 and 208 can be subjected to plasma treatment. This plasma treatment reduces impurities (e.g., water) adsorbed on the surfaces of semiconductor layers 108 and 208. Therefore, impurities at the interfaces between semiconductor layer 108 and insulating layer 106, and between semiconductor layer 208 and insulating layer 106, can be reduced, resulting in a transistor with high reliability. In particular, plasma treatment is preferred when the surfaces of semiconductor layers 108 and 208 are exposed to the atmosphere between the formation of semiconductor layers 108 and 208 and the formation of the insulating film 106f. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, or argon. The plasma treatment and the formation of the insulating film 106f are preferably performed continuously without exposure to the atmosphere.

[0544] Next, the insulating film 106f is processed to form the insulating layer 106. Figure 35C The insulating layer 106 is provided with openings 147a and 147b that lead to the semiconductor layer 208. Dry etching can be appropriately used when forming the insulating layer 106.

[0545] Next, a conductive film 104f is formed on the insulating layer 106 to form conductive layers 104, 204, 212a, and 212b. Figure 36A The conductive film 104f can be formed, for example, by sputtering, thermal CVD (including MOCVD) or ALD.

[0546] Next, conductive layers 104, 204, 212a, and 212b are formed by processing conductive film 104f. Figure 36B ).

[0547] Next, conductive layers 204, 212a, and 212b are used as masks to supply (also called add or implant) impurities to semiconductor layer 208. Thus, in semiconductor layer 208, region 208D is formed in regions that do not overlap with any of conductive layers 204, 212a, 212b, and insulating layer 106, and region 208L is formed in regions that do not overlap with any of conductive layers 204, 212a, and 212b but overlap with insulating layer 106. Figure 37 At this time, it is preferable to determine the impurity supply conditions based on the material and thickness of the conductive layer 204, which serves as a mask, in a manner that minimizes the supply of impurities in the region of the semiconductor layer 208 overlapping with the conductive layer 204. This allows for the formation of a channel region in the region of the semiconductor layer 208 overlapping with the conductive layer 204, where the impurity concentration is sufficiently reduced. Sometimes, the semiconductor layer 108 is also supplied with impurities using the conductive layer 104 as a mask. By supplying impurities, a region 108L is formed in the region of the semiconductor layer 108 that does not overlap with the conductive layer 104 but overlaps with the insulating layer 106.

[0548] Impurities can be supplied using plasma ion doping or ion implantation. In these methods, the concentration distribution along the depth direction can be controlled with high precision based on factors such as ion acceleration voltage and dosage. Using plasma ion doping can improve productivity. Furthermore, using ion implantation with mass separation can improve the purity of the supplied impurities.

[0549] In the supply of impurities, it is preferable to adjust the supply conditions so that the impurity concentration is highest on the surface of the semiconductor layer 208 or in a portion close to that surface.

[0550] As raw materials for supplying impurities, gases containing the aforementioned impurity elements can be used, for example. When supplying boron, one or more of B₂H₆ and BF₃ gases can typically be used. Furthermore, when supplying phosphorus, PH₃ gas can typically be used. Additionally, gases diluted with noble gases can also be used.

[0551] As raw materials for supplying impurities, for example, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and noble gases can be used. Note that the raw materials are not limited to gases; solids or liquids can also be heated to vaporize them.

[0552] By setting conditions such as accelerating voltage and dosage based on the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 208, the addition of impurities can be controlled.

[0553] When boron is added using ion implantation or plasma ion doping, the accelerating voltage can be, for example, 5 kV or higher and 100 kV or lower, preferably 7 kV or higher and 70 kV or lower, and more preferably 10 kV or higher and 50 kV or lower. Furthermore, the dose can be, for example, 1 × 10⁻⁶. 13 ions / cm 2 Above and 1×10 17 ions / cm 2 The following is preferred: 1×10 14 ions / cm 2 Above and 5×10 16 ions / cm 2 Hereinafter, 1×10 is more preferred. 15 ions / cm 2 Above and 3×10 16 ions / cm 2 the following.

[0554] When phosphorus is added using ion implantation or plasma ion doping, the accelerating voltage can be, for example, 10 kV or more and 100 kV or less, preferably 30 kV or more and 90 kV or less, and more preferably 40 kV or more and 80 kV or less. Furthermore, the dose can be, for example, 1 × 10⁻⁶ kV. 13 ions / cm 2 Above and 1×10 17 ions / cm 2 The following is preferred: 1×10 14 ions / cm 2 Above and 5×10 16 ions / cm 2 Hereinafter, 1×10 is more preferred. 15 ions / cm 2 Above and 3×10 16 ions / cm 2 the following.

[0555] Note that the method of supplying impurities is not limited to this; for example, plasma treatment or treatment utilizing thermal diffusion caused by heating can also be performed. In the case of plasma treatment, impurities can be added by first generating plasma in a gas atmosphere containing the added impurities, and then performing plasma treatment. As the apparatus for generating the aforementioned plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, or high-density plasma CVD apparatus can be used, etc.

[0556] For example, by using a plasma CVD apparatus to perform plasma processing in an atmosphere containing a gas containing hydrogen atoms, hydrogen can be supplied as an impurity to the semiconductor layer 208 in the region that does not overlap with the conductive layer 204. Furthermore, by using a plasma CVD apparatus during the supply of impurities and the formation of the insulating layer 195, the supply of impurities and the formation of the insulating layer 195 can be carried out continuously within the apparatus, thereby improving productivity.

[0557] Transistors 100 and 200 are thus formed. In addition, capacitor 150 is formed in the region where conductive layer 202, insulating layer 109 and conductive layer 112b overlap.

[0558] Next, an insulating layer 195 is formed by covering conductive layer 104, conductive layer 204, conductive layer 212a, conductive layer 212b, insulating layer 106, and semiconductor layer 208. Figure 8A and Figure 8B The insulating layer 195 can be formed using the PECVD method.

[0559] When the deposition temperature of the insulating layer 195 is too high, impurities contained in regions 108L, 208L, and 208D may diffuse to the periphery of semiconductor layers 108 and 208, including the channel formation region. Furthermore, the resistance of regions 108L, 208L, and 208D may increase. Therefore, it is preferable to determine the deposition temperature of the insulating layer 195 taking into account impurity diffusion.

[0560] The deposition temperature of the insulating layer 195 is preferably 150°C or higher and 400°C or lower, more preferably 180°C or higher and 360°C or lower, and even more preferably 200°C or higher and 250°C or lower. By depositing the insulating layer 195 at a low temperature, even transistors with short channel lengths can exhibit excellent electrical characteristics.

[0561] Heat treatment can be performed after the formation of insulating layer 195. This heat treatment can sometimes further reduce the resistance of regions 108L, 208L, and 208D. For example, by performing heat treatment, it is possible to allow impurities to diffuse appropriately, forming regions 208L and 208D with an ideal impurity concentration gradient. Details regarding heat treatment are provided above, so further explanation is omitted. Note that when the heat treatment temperature is too high (e.g., above 500°C), impurities diffuse into the channel formation region, which may lead to deterioration of the transistor's electrical characteristics and reliability.

[0562] Note that this heat treatment is not always necessary. Alternatively, a heat treatment performed in a later step can be used instead of this one. Sometimes, a heat treatment performed in a later step (e.g., deposition) can be used as the heat treatment for this step.

[0563] The semiconductor device 10 of one aspect of the present invention can be manufactured through the above-described process.

[0564] This implementation method can be appropriately combined with other implementation methods.

[0565] (Implementation Method 3)

[0566] In this embodiment, refer to Figures 38 to... Figure 46 This invention describes a display device according to one aspect of the present invention.

[0567] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used, for example, in the display section of the following devices: electronic devices with large screens such as televisions, desktop or laptop computers, monitors for computers, digital signage, large game machines such as pinball machines, etc.; digital cameras; digital video cameras; digital photo frames; mobile phones; portable game machines; portable information terminals; and sound reproduction devices.

[0568] The display device in this embodiment can be a high-definition display device. Therefore, for example, the display device in this embodiment can be used as the display unit of information terminal devices (wearable devices) such as watch-type and bracelet-type devices, as well as the display unit of wearable devices that can be worn on the head, such as head-mounted displays (HMDs) for VR devices and glasses-type AR devices.

[0569] One aspect of the semiconductor device of the present invention can be used in a display device or a module including the display device. Examples of modules including the display device include modules in which the display device is mounted with connectors such as Flexible Printed Circuit (FPC) or TCP (Tape Carrier Package), and modules in which integrated circuits (ICs) are mounted via COG (Chip On Glass) or COF (Chip On Film).

[0570] The display device of this embodiment can also have the function of a touch panel. For example, various detection elements (or sensor elements) capable of detecting the approach or contact of a detection object such as a finger can also be used in the display device.

[0571] Examples of sensor types include capacitive, resistive film, surface acoustic wave, infrared, optical, and pressure-sensitive types.

[0572] As electrostatic capacitive types, there are surface-type electrostatic capacitive types and projection-type electrostatic capacitive types. Furthermore, as projection-type electrostatic capacitive types, there are self-capacitance types and mutual-capacitance types. Mutual-capacitance types are preferred because they allow for simultaneous multi-point sensing.

[0573] Examples of touch panels include Out-Cell, On-Cell, and In-Cell types. Note that an In-Cell type touch panel refers to a structure in which electrodes constituting the detection element are provided on one or both of the substrate supporting the display element (also called the display device) and the opposing substrate.

[0574] <Example of a display device structure>

[0575] Figure 38A A perspective view of the display device 50A is shown.

[0576] The display device 50A has a structure that bonds substrate 152 and substrate 151. Figure 38A In the image, substrate 152 is represented by a dashed line.

[0577] The display device 50A includes a display section 162, a connection section 140, a circuit section 164, a conductive layer 165, etc. Figure 38A An example is shown where display device 50A is equipped with IC173 and FPC172. Therefore, it is also possible to... Figure 38A The structure shown is called a display module including display device 50A, IC and FPC.

[0578] The connecting portion 140 is disposed on the outer side of the display portion 162. The connecting portion 140 may be disposed along one or more edges of the display portion 162. There may be one or more connecting portions 140. Figure 38A An example is shown in which the connecting portions 140 are arranged around the four sides of the display portion 162. In the connecting portions 140, the common electrode of the display element is electrically connected to the conductive layer, and a potential can be supplied to the common electrode.

[0579] The circuit section 164 may include, for example, a scan line driving circuit (also known as a gate driver). Alternatively, the circuit section 164 may include both a scan line driving circuit and a signal line driving circuit (also known as a source driver).

[0580] The conductive layer 165 has the function of supplying signals and power to the display unit 162 and the circuit unit 164. The signals and power are input to the conductive layer 165 from the outside via FPC 172 or from IC 173.

[0581] Figure 38A An example is shown where IC 173 is mounted on substrate 151 using a COG or COF method. IC 173 can be, for example, an IC that includes one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module may not have an IC mounted on them. Furthermore, the IC can also be mounted on an FPC using a COF method or the like.

[0582] One aspect of the semiconductor device of the present invention can be used, for example, in one or both of the display section 162 and the circuit section 164 of the display device 50A. The channel forming region of the transistors included in the display device can suitably use oxide semiconductor (OS) transistors. By using OS transistors, a low-power display device can be realized. Alternatively, the semiconductor device of one aspect of the present invention can be used in both the display section 162 and the circuit section 164, that is, all transistors included in the display device are OS transistors. Thus, by using OS transistors as all transistors included in the display device, the effect of reducing manufacturing costs is achieved.

[0583] For example, when the semiconductor device of one aspect of the present invention is used in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, thereby enabling a high-definition display device. Furthermore, for example, when the semiconductor device of one aspect of the present invention is used in the driving circuit of a display device (e.g., one or both of a gate line driving circuit and a source line driving circuit), the occupied area of ​​the driving circuit can be reduced, thereby enabling a display device with a narrow bezel. Additionally, the semiconductor device of one aspect of the present invention has excellent electrical characteristics; by using this semiconductor device in a display device, the reliability of the display device can be improved.

[0584] Display unit 162 is an image display area in display device 50A, including a plurality of pixels 210 arranged periodically. Figure 38A The image shown is a magnified view of pixel 210.

[0585] There are no particular limitations on the arrangement of pixels in the display device of this embodiment, and various methods can be used. Examples of pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement.

[0586] Figure 38A The pixel 210 shown includes a pixel 230R that emits red light, a pixel 230G that emits green light, and a pixel 230B that emits blue light. By using pixels 230R, 230G, and 230B to form a single pixel 210, full-color display can be achieved. Pixels 230R, 230G, and 230B are all used as sub-pixels. Furthermore, in Figure 38A The display device 50A shown illustrates an example of pixels 230 arranged in a stripe pattern as subpixels. There is no particular limitation on the number of subpixels constituting a pixel 210. For example, it may include four subpixels that emit R, G, B, and white (W) light. Alternatively, it may include four subpixels that emit four colors of light: R, G, B, and Y.

[0587] Pixel 230R, Pixel 230G and Pixel 230B all include a display element and circuitry for controlling the drive of the display element.

[0588] Various components can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electro Mechanical Systems) elements using shutter-based or optical interference methods, as well as display elements employing microencapsulation, electrophoresis, electrowetting, or electronic powder fluid methods (registered trademark), can be used. Furthermore, QLED (Quantum-dot LED) technology, which utilizes a light source and employs quantum dot materials for color conversion, can also be used.

[0589] Examples of display devices using liquid crystal elements include transmissive liquid crystal displays, reflective liquid crystal displays, and transflective liquid crystal displays.

[0590] Examples of display device modes that can be used with liquid crystal elements include Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0591] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric, smectic, cubic, chiral nematic, isotropic, and blue phases, depending on the conditions. Furthermore, either positive or negative liquid crystals can be used as liquid crystal materials, and the choice can be made based on the mode or design used.

[0592] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, Mini LEDs and Micro LEDs can be used as LEDs.

[0593] Light-emitting materials contained in light-emitting elements include, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0594] The light-emitting element can emit colors such as infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, when the light-emitting element has a microcavity structure, the color purity can be improved.

[0595] In a light-emitting element, one electrode is used as the anode and the other electrode is used as the cathode.

[0596] The display device of one aspect of the present invention may also adopt any of the following structures: a top-emission type that emits light in the direction opposite to that of the substrate on which the light-emitting element is formed, a bottom-emission type that emits light in the direction of the substrate on which the light-emitting element is formed, and a dual-emission type that emits light in both directions.

[0597] In this embodiment, the example of using a light-emitting element as a display element will be used for explanation.

[0598] Figure 38B This is a block diagram illustrating the display device 50A. The display device 50A includes a display unit 162 and a circuit unit 164. The display unit 162 includes a plurality of pixels 230 arranged periodically (pixels 230[1,1] to pixels 230[m,n], where m and n are each an independent integer greater than or equal to 2). The circuit unit 164 includes a first driving circuit unit 231 and a second driving circuit unit 232.

[0599] The circuitry included in the first driving circuit section 231 is used, for example, as a scan line driving circuit. The circuitry included in the second driving circuit section 232 is used, for example, as a signal line driving circuit. Alternatively, a circuit may be provided at a position opposite to the first driving circuit section 231, separated from the display section 162. A circuit may also be provided at a position opposite to the second driving circuit section 232, separated from the display section 162.

[0600] As the circuit section 164, various circuits such as shift register circuits, level converter circuits, inverter circuits, latch circuits, analog switch circuits, demultiplexing circuits, and logic circuits can be used. Transistors and capacitors can be used in the circuit section 164. The transistors included in the circuit section 164 can be formed using the same processes as the transistors included in the pixel 230.

[0601] The display device 50A includes wiring 236 and wiring 238 arranged in generally parallel configurations. The potential of wiring 236 is controlled by a circuit included in a first driving circuit section 231, and the potential of wiring 238 is controlled by a circuit included in a second driving circuit section 232. Figure 38B The diagram shows an example of wiring 236 and wiring 238 connected to pixel 230. However, wiring 236 and wiring 238 are just examples, and wiring connected to pixel 230 is not limited to wiring 236 and wiring 238.

[0602] One aspect of the semiconductor device of the present invention can share some processes to form both vertical transistors (VFETs) with short channel lengths and high on-state currents, and TGSA-type transistors with long channel lengths and high saturation. Oxide-semiconductor (OS) transistors can be suitably used in the channel formation regions of these transistors to achieve transistors with low off-state currents. One aspect of the semiconductor device of the present invention can be suitably used in one or both of the display unit 162 and the circuit unit 164. Alternatively, one aspect of the semiconductor device of the present invention can be used in both the display unit 162 and the circuit unit 164, meaning that all transistors included in the display device are OS transistors. Thus, by using OS transistors as all transistors included in the display device, the manufacturing cost can be reduced.

[0603] <Example of a driver circuit structure>

[0604] As a circuit that can be used to drive circuits, a latching circuit is used as an example to illustrate the structure.

[0605] Figure 39A This is a circuit diagram showing an example of the structure of a latch circuit (LAT). Figure 39A The latch circuit LAT shown includes transistors Tr31, Tr33, Tr35, and Tr36, capacitor C31, and inverter circuit INV. In Figure 39A In this context, the node that electrically connects one of the source and drain terminals of transistor Tr33, the gate of transistor Tr35, and one electrode of capacitor C31 is called node N.

[0606] exist Figure 39AIn the latch circuit LAT shown, when a high-level signal is input to terminal SMP, transistor Tr33 turns on. Therefore, the potential of node N becomes the potential corresponding to the potential of terminal ROUT, and the data corresponding to the signal input from terminal ROUT to the latch circuit LAT is written to the latch circuit LAT. After writing data to the latch circuit LAT, by lowering the potential of terminal SMP, transistor Tr33 turns off. Therefore, the potential of node N is maintained, and the data written to the latch circuit LAT is retained. Specifically, for example, when the potential of node N is low, the latch circuit LAT can retain data of "0", and when the potential of node N is high, the latch circuit LAT can retain data of "1".

[0607] Transistor Tr33 is preferably a transistor with low off-state current. Transistor Tr33 can appropriately utilize an OS transistor. Therefore, the latch circuit LAT can retain data for a longer period. Consequently, the frequency of writing data back to the latch circuit LAT can be reduced.

[0608] In this specification and other materials, the phrase "writing data to the latch circuit LAT that causes the signal input from terminal SP2 to be output to terminal LIN" is sometimes abbreviated as "writing data to the latch circuit LAT". That is, for example, the phrase "writing data of "1" to the latch circuit LAT" is sometimes abbreviated as "writing data to the latch circuit LAT".

[0609] In the latch circuit (LAT), a semiconductor device according to one aspect of the invention can be suitably used. For example, one or more of transistors Tr31, Tr33, Tr35, and Tr36 can be used. Figure 1B Transistor 100 or transistor 200 as shown.

[0610] Figure 39B An example of the structure of an inverter circuit INV is shown. The inverter circuit INV includes transistors Tr41, Tr43, Tr45, and Tr47, and capacitor C41.

[0611] When the latch circuit LAT has Figure 39A The structure shown and the inverter circuit INV have Figure 39B In the structure shown, all transistors in the latch circuit LAT are transistors with the same polarity, such as n-channel transistors. Therefore, for example, besides transistor Tr33, transistors Tr31, Tr35, Tr36, Tr41, Tr43, Tr45, and Tr47 can also be OS transistors. Thus, all transistors in the latch circuit LAT can be manufactured using the same process.

[0612] In the inverter circuit INV, a semiconductor device according to one aspect of the invention can be suitably used. For example, one or more of transistors Tr41, Tr43, Tr45, and Tr47 can be used. Figure 1B Transistor 100 or transistor 200 as shown.

[0613] By using one or more of transistors 100 to 100G, the occupied area can be reduced, thereby enabling a display device with a narrow bezel. Furthermore, one or more of transistors 100 to 100G can be appropriately used as transistors requiring high on-state current. Moreover, one or more of transistors 200 to 200D can be appropriately used as transistors requiring high saturation. Thus, a high-performance display device can be achieved.

[0614] <Example 1 of pixel circuit construction>

[0615] Figure 40A An example of the structure of pixel 230 is shown. Pixel 230 includes pixel circuitry 51 and light-emitting device 61.

[0616] Figure 40A The pixel circuit 51 shown includes transistor 52A, transistor 52B, and capacitor 53. Pixel circuit 51 is a 2Tr1C type pixel circuit including two transistors and one capacitor. Note that there are no particular limitations on the pixel circuit that can be used in one aspect of the present invention.

[0617] The anode of the light-emitting device 61 is electrically connected to one of the source and drain electrodes of transistor 52B and one electrode of capacitor 53. The other of the source and drain electrodes of transistor 52B is electrically connected to wiring ANO. The gate of transistor 52B is electrically connected to one of the source and drain electrodes of transistor 52A and the other electrode of capacitor 53. The other of the source and drain electrodes of transistor 52A is electrically connected to wiring GL. The gate of transistor 52A is electrically connected to wiring GL. The cathode of the light-emitting device 61 is electrically connected to wiring VCOM.

[0618] Wiring GL is equivalent to wiring 236, and wiring SL is equivalent to wiring 238. Wiring VCOM is a wiring that supplies the potential used to supply current to the light-emitting device 61. Transistor 52A has the function of controlling the on or off state between wiring SL and the gate of transistor 52B according to the potential of wiring GL. For example, VDD is supplied to wiring ANO, and VSS is supplied to wiring VCOM.

[0619] Transistor 52B controls the amount of current flowing through light-emitting device 61. Capacitor 53 maintains the gate potential of transistor 52B. The intensity of the light emitted by light-emitting device 61 is controlled according to the image signal supplied to the gate of transistor 52B.

[0620] Some or all of the transistors included in the pixel circuit 51 may be provided with a back gate. Figure 40A The pixel circuit 51 shown illustrates a structure in which transistor 52B includes a back gate electrically connected to one of the source and drain of transistor 52B. Alternatively, the back gate of transistor 52B may also be electrically connected to the gate of transistor 52B.

[0621] The aforementioned semiconductor device can be applied to the pixel circuit 51. Preferably, the transistor 52B, which controls the current flowing through the light-emitting device 61, has higher saturation than the transistor 52A, which is used as the selection transistor to control the selection state of the pixel 230. By using one of transistors 200 to 200D with a long channel length as transistor 52B, a highly reliable display device can be provided. Furthermore, by using one of transistors 100 to 100G as transistor 52A, the area occupied by the pixel circuit 51A can be reduced, thereby enabling a high-definition display device.

[0622] Furthermore, transistor 52B can also be one of transistors 100 to 100G. By using a transistor with a short channel length as transistor 52B, a display device with high brightness can be realized. In addition, the area occupied by pixel circuit 51 can be reduced, thereby realizing a high-definition display device.

[0623] Figure 40B Showing with Figure 40A Examples of different structures for pixel 230 are shown. Pixel 230 includes pixel circuitry 51A and light-emitting device 61.

[0624] Figure 40B The pixel circuit 51A shown is Figure 40A The main difference in pixel circuit 51 shown is the inclusion of transistor 52C. Pixel circuit 51A includes transistors 52A, 52B, 52C, and capacitor 53. Pixel circuit 51A is a 3Tr1C type pixel circuit comprising three transistors and one capacitor.

[0625] One of the source and drain of transistor 52C is electrically connected to the other of the source and drain of transistor 52B. The other of the source and drain of transistor 52C is electrically connected to wiring V0. For example, wiring V0 is supplied with a reference potential. The gate of transistor 52C is electrically connected to wiring GL.

[0626] Transistor 52C has the function of controlling the on or off state of one of the source and drain terminals of transistor 52B and the wiring V0 according to the potential of wiring GL. The non-uniformity of the gate-source potential of transistor 52B can be suppressed according to the reference potential of wiring V0 supplied through transistor 52C.

[0627] Furthermore, the current value that can be used to set pixel parameters can be obtained using wiring V0. Specifically, wiring V0 can be used as a monitoring line to output the current flowing through transistor 52B or the current flowing through light-emitting device 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter or the like and output to the outside.

[0628] The aforementioned semiconductor device can be applied to pixel circuit 51A. By using one of transistors 200 to 200D with a long channel length as transistor 52B, a highly reliable display device can be provided. Furthermore, by using one or more of transistors 100 to 100G as transistors 52A and 52C, the occupied area of ​​pixel circuit 51A can be reduced, thereby realizing a high-definition display device. Additionally, transistor 52B can also use one of transistors 100 to 100G.

[0629] Figure 40C An example of the structure of pixel circuit 51 is shown. Figure 40C This is a cross-sectional view of pixel circuit 51. Figure 40C The pixel electrode included in transistor 52A, transistor 52B, capacitor 53, and light-emitting device 61 is shown in the diagram. Note that the electrical connection between transistor 52A and transistor 52B is omitted.

[0630] Transistor 52A includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. Transistor 52B includes a conductive layer 202, an insulating layer 106, a semiconductor layer 208, an insulating layer 120, a conductive layer 204, a conductive layer 212a, and a conductive layer 212b. Since transistors 52A and 52B are described above, detailed descriptions are omitted.

[0631] The capacitor 53 includes a conductive layer 212a, a conductive layer 112p, and an insulating layer 106 sandwiched between them. The conductive layer 112p is disposed on the insulating layer 120. The conductive layer 112p can be formed, for example, by the same process as the conductive layer 112b. The insulating layer 106 is disposed on the conductive layer 112p, and the conductive layer 212a is disposed on the insulating layer 106. The conductive layer 212a is used as one of the source electrode and drain electrode of the transistor 52B, and also as one electrode of the capacitor 53. Furthermore, there are no particular limitations on the structure of the capacitor 53.

[0632] An insulating layer 195 is provided to cover transistors 52A, 52B, and capacitor 53; an insulating layer 233 is provided to cover the insulating layer 195; and an insulating layer 235 is provided to cover the insulating layer 233. A light-emitting device 61 can be disposed on the insulating layer 235. Figure 40C A pixel electrode 111, serving as one electrode of the light-emitting device 61, is shown. Insulating layers 195 and 233 have a first opening reaching the conductive layer 212a, and a conductive layer 234 is disposed to cover the first opening. The conductive layer 234 is electrically connected to the conductive layer 212a through the first opening. Insulating layer 235 has a second opening reaching the conductive layer 234, and a pixel electrode 111 is disposed to cover the second opening. The pixel electrode 111 is electrically connected to the conductive layer 234 through the second opening. The insulating layer 195 can be referred to as described above, therefore a detailed description is omitted. Insulating layers 233 and 235 have the function of reducing the unevenness caused by transistors 52A, 52B, and 52C, thereby making the formed surface of the light-emitting device 61 flatter. Furthermore, in this specification, insulating layers 233 and 235 are sometimes referred to as planarization layers.

[0633] Organic insulating films are preferably used for insulating layers 233 and 235. Examples of materials suitable for organic insulating films include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimide amide resins, silicone resins, benzocyclobutene resins, phenolic resins, and precursors of these resins. Furthermore, insulating layer 235 may also have a laminated structure of organic and inorganic insulating films. Insulating layer 235 preferably has a laminated structure of an organic insulating film and an inorganic insulating film on that organic insulating film. Thus, the inorganic insulating film can be used as an etching protection layer during the formation of the light-emitting device 61. Specifically, it can prevent the etching of a portion of insulating layer 235 during the formation of pixel electrode 111, thus preventing the formation of recesses in insulating layer 235. Alternatively, recesses may sometimes be provided in insulating layer 235 during the formation of pixel electrode 111. Similarly, insulating layer 233 may have a laminated structure of organic and inorganic insulating films.

[0634] <Example 2 of pixel circuit construction>

[0635] Figure 41 A structural example different from pixel 230 described above is shown. Pixel 230 includes pixel circuitry 51B and a light-emitting device 61.

[0636] Pixel circuit 51B includes transistors M11, M12, M13, M14, M15, and M16, capacitors C11 and C12. Pixel circuit 51B is a 6Tr2C type pixel circuit comprising six transistors and two capacitors.

[0637] The anode of the light-emitting device 61 is electrically connected to one of the source and drain of transistor M15. The cathode of the light-emitting device 61 is electrically connected to wiring VCOM. The other of the source and drain of transistor M15 is electrically connected to one of the source and drain of transistor M12, one of the source and drain of transistor M13, one of the source and drain of transistor M16, one electrode of capacitor C11, and one electrode of capacitor C12. The gate of transistor M12 is electrically connected to one of the source and drain of transistor M11, the other of the source and drain of transistor M13, and the other electrode of capacitor C11. The back gate of transistor M12 is electrically connected to one of the source and drain of transistor M14 and the other electrode of capacitor C12.

[0638] The other of the source and drain of transistor M11 is electrically connected to wiring SL. The other of the source and drain of transistor M12 is electrically connected to wiring ANO. The other of the source and drain of transistor M14 is electrically connected to wiring V0. The other of the source and drain of transistor M16 is electrically connected to wiring V1. For example, wiring V1 is supplied with a constant potential. The gates of transistors M11 and M16 are electrically connected to wiring GL1. The gates of transistors M13 and M14 are electrically connected to wiring GL2. The gate of transistor M15 is electrically connected to wiring GL3.

[0639] Transistor M11 is used as a selection transistor to control the on or off state between the gate of transistor M12 and wiring SL. Transistor M12 is used as a drive transistor to control the current flowing through the light-emitting device 61. Transistor M14 has the function of supplying the potential of wiring V0 to the back gate of transistor M12. By supplying a constant potential to the back gate of transistor M12, the threshold voltage can be controlled. Capacitor C11 has the function of maintaining the gate potential of transistor M12. Capacitor C12 has the function of maintaining the back gate potential of transistor M12. Pixel circuit 51B has a so-called internal threshold voltage correction function, which corrects the threshold voltage of transistor M12 by the back gate. Specifically, a back gate potential that makes the threshold voltage of transistor M12 0V is maintained in capacitor C12. Thus, regardless of the non-uniformity of the threshold voltage of the transistor and its degradation over time, the threshold voltage of transistor M12 can be constantly corrected to 0V or near 0V.

[0640] The aforementioned semiconductor device can be suitably used in pixel circuit 51B. For example, it can be used as transistor M11, transistor M13, transistor M14, transistor M15, and transistor M16. Figure 1BOne or more of transistors 100 to 100G shown, etc., can be used as transistor M12, and one of transistors 200 to 200D can be used.

[0641] The transistor M12 used as the driving transistor preferably has high saturation. By using one of transistors 200 to 200D with a long channel length as transistor M12, a display device with high reliability can be realized. Furthermore, by using one or more of transistors 100 to 100G as transistors M11, M13, M14, M15, and M16, the occupied area of ​​the pixel circuit 51B can be reduced, thereby realizing a high-definition display device.

[0642] Furthermore, transistor M12 can also be one of transistors 100 to 100G. By using a transistor with a short channel length as transistor M12, a display device with high brightness can be realized. In addition, the area occupied by the pixel circuit 51B can be reduced, thereby realizing a high-definition display device.

[0643] By using multiple transistors and capacitors in the pixel circuit, a high-performance display device can be realized. By using a semiconductor device according to one aspect of the present invention, the occupied area can be reduced even when the number of transistors and capacitors increases, thereby enabling a high-performance and high-definition display device. For example, display devices with a resolution of 300 ppi or higher, 500 ppi or higher, 1000 ppi or higher, 2000 ppi or higher, or 3000 ppi or higher can be realized.

[0644] One aspect of the semiconductor device of the present invention can reduce the occupied area, thus increasing the pixel aperture ratio in a bottom-emitting structure display device. For example, a display device with an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

[0645] Note that in this specification, aperture ratio refers to the proportion of the area from which light is emitted relative to the pixel area.

[0646] <Example 1 of the structure of a display device>

[0647] Figure 42A An example of a cross-section of a portion of the display device 50A including the region of FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the region including the end is shown.

[0648] Figure 42AThe display device 50A shown includes transistors 205D, 205R, 205G, 207G, 207B, light-emitting elements 130R, 130G, and 130B, located between substrates 151 and 152. Light-emitting element 130R is a display element included in pixel 230R that emits red light; light-emitting element 130G is a display element included in pixel 230G that emits green light; and light-emitting element 130B is a display element included in pixel 230B that emits blue light.

[0649] The display device 50A adopts an SBS structure. The SBS structure allows for optimization of materials and structure for each light-emitting element, increasing the freedom of material and structural selection and making it easier to improve brightness and reliability.

[0650] The display device 50A adopts a top-emitting type. In the top-emitting type, transistors and the like can be arranged in a manner that overlaps with the light-emitting area of ​​the light-emitting element, so the pixel aperture ratio can be further improved compared with the bottom-emitting type.

[0651] Transistors 205D, 205R, 205G, 207G, and 207B are all formed on substrate 151. These transistors can be manufactured using some shared processes.

[0652] One or more of transistors 205D, 205R, 205G, 207G, and 207B may be used, which may be one or more of transistors 100 to 100G and transistors 200 to 200D. Figure 42A The diagram shows a structural example in which the transistor 100 is used as transistor 205D, transistor 205R, and transistor 205G, and the transistor 200 is used as transistor 207G and transistor 207B.

[0653] By using one or more of the aforementioned transistors 100 to 100G as transistors disposed in the display unit 162, a high-definition display device can be realized. Furthermore, one or more of transistors 200 to 200D with high saturation can be appropriately used as driving transistors for the light-emitting elements 130R, 130G, and 130B. Thus, a display device with high reliability can be realized.

[0654] By using one or more of transistors 100 to 100G in the circuit section 164, a high-speed display device can be realized. Sometimes, the transistors in the circuit section 164 need to have a larger on-state current than the transistors in the display section 162. Transistors with short channel lengths are preferably used in the circuit section 164. For example, one or more of transistors 100 to 100G can be appropriately used in the peripheral circuit section 164. By using one or more of transistors 100 to 100G in the peri...

Claims

1. A semiconductor device, comprising: First transistor; Second transistor; First insulating layer; as well as Second insulating layer, The first transistor includes a first conductive layer, a second conductive layer, and a first semiconductor layer. The second transistor includes a third conductive layer, a third insulating layer, and a second semiconductor layer. The first insulating layer is located on the first conductive layer. The first insulating layer has a first opening that extends to the first conductive layer. The second conductive layer is located on the first insulating layer. The second conductive layer has a second opening in the region overlapping with the first opening. The first semiconductor layer has a region in the first opening that contacts the top surface of the first conductive layer and the side surface of the first insulating layer. The first semiconductor layer has a region in the second opening that contacts the side surface of the second conductive layer. The second insulating layer is located on top of the first insulating layer. The third conductive layer is located on the second insulating layer. The third insulating layer is located on the third conductive layer. Furthermore, the second semiconductor layer has a region that overlaps with the third conductive layer through the third insulating layer.

2. The semiconductor device according to claim 1, The end of the third insulating layer is the same as or substantially the same as the end of the second insulating layer.

3. The semiconductor device according to claim 1 or 2, The end of the second insulating layer is in contact with the top surface of the first insulating layer.

4. The semiconductor device according to claim 1 or 2, The end of the second insulating layer is in contact with the top surface of the second conductive layer.

5. The semiconductor device according to claim 1 or 2, The first semiconductor layer has a region that contacts the top surface of the second conductive layer.

6. The semiconductor device according to claim 1 or 2, The first semiconductor layer does not contact the second insulating layer.

7. The semiconductor device according to claim 1 or 2, The first semiconductor layer and the second semiconductor layer each comprise metal oxides.

8. The semiconductor device according to claim 1, The first insulating layer includes a fourth insulating layer and a fifth insulating layer on the fourth insulating layer. The fourth insulating layer comprises silicon and oxygen. Furthermore, the fifth insulating layer comprises silicon and nitrogen.

9. The semiconductor device according to claim 8, The first insulating layer includes a sixth insulating layer. The sixth insulating layer is located between the first conductive layer and the fourth insulating layer. Furthermore, the sixth insulating layer comprises silicon and nitrogen.

10. The semiconductor device according to claim 8, The first insulating layer includes a sixth insulating layer. The sixth insulating layer is located between the first conductive layer and the fourth insulating layer. Furthermore, the sixth insulating layer comprises one or both of aluminum and hafnium, as well as oxygen.

11. The semiconductor device according to claim 8, The first insulating layer includes a fourth insulating layer and a fifth insulating layer on the fourth insulating layer. The fourth insulating layer comprises silicon and oxygen. Furthermore, the fifth insulating layer comprises one or both of aluminum and hafnium, as well as oxygen.

12. The semiconductor device according to claim 11, The first insulating layer includes a sixth insulating layer. The sixth insulating layer is located between the first conductive layer and the fourth insulating layer. Furthermore, the sixth insulating layer comprises silicon and nitrogen.

13. The semiconductor device according to claim 11, The first insulating layer includes a sixth insulating layer. The sixth insulating layer is located between the first conductive layer and the fourth insulating layer. Furthermore, the sixth insulating layer comprises one or both of aluminum and hafnium, as well as oxygen.

14. The semiconductor device according to any one of claims 8 to 13, further comprising: The seventh insulating layer, The top surface of the seventh insulating layer is in contact with the bottom surface of the first conductive layer. Furthermore, the seventh insulating layer comprises silicon and nitrogen.

15. The semiconductor device according to claim 1 or 2, further comprising: capacitor, The capacitor includes a second conductive layer, a third conductive layer, and a second insulating layer sandwiched between the second conductive layer and the third conductive layer.

16. A method for manufacturing a semiconductor device, comprising the following steps: Form the first conductive layer; A first insulating film is formed on the first conductive layer; A second conductive layer having a region overlapping the first conductive layer is formed on the first insulating film; A second insulating film is formed on the first insulating film and the second conductive layer; A third conductive layer is formed on the second insulating film; A third insulating film is formed on the second insulating film and the third conductive layer; By processing the second insulating film and the third insulating film, a first insulating layer and a second insulating layer with consistent or substantially consistent ends are formed. By processing the second conductive layer, a fourth conductive layer with a first opening is formed in the region overlapping with the first conductive layer; By processing the first insulating film, a third insulating layer is formed in the region overlapping with the first opening, having a second opening; While forming a first semiconductor layer having a region in the first opening that contacts the top surface of the first conductive layer and the side surface of the third insulating layer, and having a region in the second opening that contacts the side surface of the fourth conductive layer, a second semiconductor layer having a region that overlaps with the third conductive layer is formed on the second insulating layer. A fourth insulating layer is formed on the first semiconductor layer and the second semiconductor layer; as well as While forming a fifth conductive layer having a region overlapping with the first semiconductor layer on the fourth insulating layer, a sixth conductive layer having a region overlapping with the second semiconductor layer is also formed.

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