Semiconductor device

Abstract

Provided is a transistor having good electrical characteristics. Provided is a transistor having a large on-state current. Provided is a transistor having low parasitic capacitance. Provided are a transistor, a semiconductor device, or a memory device capable of achieving miniaturization or high integration. In the semiconductor device, a first conductive layer and a second conductive layer, which are located at different heights across a first insulating layer, are one or the other of a source electrode and a drain electrode of a first transistor, the first insulating layer and the second conductive layer include a first opening that reaches the first conductive layer, and a semiconductor layer is provided so as to cover the opening. The gate electrode includes a third conductive layer provided so as to cover the opening, and a fourth conductive layer laminated on the third conductive layer, the fourth conductive layer covering the upper end of the opening.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a storage device, a display device, and an electronic device. Furthermore, another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), and driving or manufacturing methods for the aforementioned devices.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips incorporating integrated circuits, and electronic components that house chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes include semiconductor devices in their design. Background Technology

[0004] In recent years, semiconductor devices have been developed, with LSIs, CPUs, and memory being the main components used in them. A CPU is an assembly of semiconductor integrated circuits (including at least transistors and memory) that are fabricated from semiconductor wafers into chips and have electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on circuit boards, such as printed circuit boards, and are used as components of various electronic devices.

[0006] Furthermore, the technique of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as suitable semiconductor thin films for transistors. Among other materials, oxide semiconductors have garnered attention.

[0007] Furthermore, it is known that the leakage current of transistors using oxide semiconductors is extremely small in the off state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current of transistors using oxide semiconductors. Additionally, for example, Patent Document 2 discloses a storage device that utilizes the characteristic of low leakage current of transistors using oxide semiconductors to achieve long-term retention of stored content.

[0008] In recent years, with the miniaturization and weight reduction of electronic devices, the demand for further high-density integrated circuits has increased. Furthermore, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique in which multiple memory cells are stacked in an overlapping manner by layering a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby increasing the density of integrated circuits. Furthermore, Patent Document 4 discloses a technique for achieving high-density integrated circuits by arranging the channels of transistors using oxide semiconductor films longitudinally.

[0009] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Publication No. 2013-211537.

[0010] [Non-patent literature] [Non-patent literature 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53. Summary of the Invention

[0011] The technical problem that the invention aims to solve One objective of this invention is to provide a transistor with excellent electrical characteristics. Furthermore, one objective of this invention is to provide a transistor with a large on-state current. Furthermore, one objective of this invention is to provide a transistor with low parasitic capacitance. Furthermore, one objective of this invention is to provide a transistor, semiconductor device, or memory device capable of miniaturization or high integration. Furthermore, one objective of this invention is to provide a display device with high definition or high aperture ratio. Furthermore, one objective of this invention is to provide a transistor, semiconductor device, display device, or memory device with high reliability. Furthermore, one objective of this invention is to provide a semiconductor device, display device, or memory device with low power consumption. Furthermore, one objective of this invention is to provide a memory device with high operating speed. Furthermore, one objective of this invention is to provide a method for manufacturing the aforementioned transistor, semiconductor device, display device, or memory device.

[0012] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims.

[0013] means of solving technical problems One aspect of the present invention is a semiconductor device comprising: a first transistor on a first insulating layer; and a second insulating layer, wherein the first transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode on the first insulating layer; the first conductive layer is one of a source electrode and a drain electrode of the first transistor; the second conductive layer is the other of a source electrode and a drain electrode of the first transistor; the second insulating layer is disposed between the first conductive layer and the second conductive layer; the second conductive layer is disposed on the second insulating layer; the second insulating layer and the second conductive layer have a first opening extending to the first conductive layer; and the semiconductor layer has a first region contacting the top surface of the first conductive layer in the first opening. The first opening includes a second region that contacts the side of the second insulating layer, a third region that contacts the side of the second conductive layer, and a fourth region that contacts the top surface of the second conductive layer. A gate insulating layer is disposed on and in contact with the semiconductor layer. The gate electrode includes a third conductive layer and a fourth conductive layer on the third conductive layer. The third conductive layer has a fifth region that overlaps with the second region through the gate insulating layer, a sixth region that overlaps with the third region through the gate insulating layer, and a seventh region that overlaps with the fourth region through the gate insulating layer. The fourth conductive layer covers the seventh region, the upper end and the vicinity of the upper end of the first opening, and does not cover the area below the vicinity of the upper end of the first opening.

[0014] Additionally, one aspect of the present invention is a semiconductor device comprising: a first transistor on a first insulating layer; and a second insulating layer, wherein the first transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode on the first insulating layer; the first conductive layer is one of the source electrode and drain electrode of the first transistor; the second conductive layer is the other of the source electrode and drain electrode of the first transistor; the second insulating layer is disposed between the first conductive layer and the second conductive layer; the second conductive layer is disposed on the second insulating layer; the second insulating layer and the second conductive layer have a first opening extending to the first conductive layer; the semiconductor layer has a first region contacting the top surface of the first conductive layer in the first opening, and a second region contacting the top surface of the first conductive layer in the first opening. The first opening has a second region that contacts the side of the second insulating layer, a third region that contacts the side of the second conductive layer, and a fourth region that contacts the top surface of the second conductive layer. A gate insulating layer is disposed on and in contact with the semiconductor layer. The gate electrode includes a third conductive layer and a fourth conductive layer on the third conductive layer. The third conductive layer has a fifth region that overlaps with the second region through the gate insulating layer, a sixth region that overlaps with the third region through the gate insulating layer, and a seventh region that overlaps with the fourth region through the gate insulating layer. The fourth conductive layer covers the seventh region, the upper end of the first opening, and the area near the upper end. The fourth conductive layer includes the second opening, and the second opening overlaps with the first opening when viewed from above.

[0015] Furthermore, in the above structure, the width of the second opening is preferably smaller than the width of the first opening.

[0016] In the above structure, preferably, the first opening has an eighth region with a tapered sidewall and a ninth region with a steeper sidewall than the eighth region. The eighth region includes the upper end of the first opening, and the ninth region is located below the eighth region. The eighth region includes the sidewall of the second conductive layer, and the ninth region includes the sidewall of the second insulating layer.

[0017] In the above structure, preferably, the angle formed between the sidewall of the eighth region and the top surface of the first insulating layer is more than 20 degrees and less than 75 degrees, and the angle formed between the sidewall of the ninth region and the top surface of the first insulating layer is greater than 75 degrees and less than 90 degrees.

[0018] Furthermore, in the above structure, the lower end of the first opening in the fourth conductive layer is preferably located below the lower end of the eighth region.

[0019] Furthermore, in the above structure, the lower end of the first opening in the fourth conductive layer is preferably located above the lower end of the eighth region.

[0020] In addition, in the above structure, preferably, the second insulating layer includes a first layer, a second layer on the first layer and a third layer on the second layer, the eighth region includes the side surface of the second conductive layer and the side surface of the third layer, and the ninth region includes the side surface of the second layer.

[0021] In addition, in the above structure, it is preferred that the first layer and the third layer are both silicon nitride layers, and the second layer is a silicon oxide layer or a silicon oxynitride layer.

[0022] Additionally, one aspect of the present invention is a semiconductor device comprising: a first transistor on a first insulating layer; a second insulating layer; and a third insulating layer, wherein the first transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode on the first insulating layer; the first conductive layer is one of the source electrode and the drain electrode of the first transistor; the second conductive layer is the other of the source electrode and the drain electrode of the first transistor; the second insulating layer is disposed between the first conductive layer and the second conductive layer; the second conductive layer is disposed on the second insulating layer; the second insulating layer and the second conductive layer have a first opening extending to the first conductive layer; the semiconductor layer has a first region contacting the top surface of the first conductive layer in the first opening and a third region contacting the second insulating layer in the first opening. The second region is in side contact with the second region, the third region is in side contact with the second conductive layer in the first opening, and the fourth region is in contact with the top surface of the second conductive layer. A gate insulating layer is disposed on and in contact with the semiconductor layer. The gate electrode includes a third conductive layer and a fourth conductive layer on the third conductive layer. The third conductive layer has a fifth region that overlaps with the second region through the gate insulating layer, a sixth region that overlaps with the third region through the gate insulating layer, and a seventh region that overlaps with the fourth region through the gate insulating layer. The fourth conductive layer covers the seventh region, the upper end and the vicinity of the upper end of the first opening, and the third insulating layer has a region in contact with the sixth region, a region in contact with the fourth conductive layer at the upper end of the first opening, and a region that covers the top surface of the second insulating layer through the fourth conductive layer.

[0023] Invention Effects According to one aspect of the present invention, a transistor with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a transistor with a large on-state current can be provided. Furthermore, according to one aspect of the present invention, a transistor with low parasitic capacitance can be provided. Furthermore, according to one aspect of the present invention, a transistor, semiconductor device, or memory device capable of miniaturization or high integration can be provided. Furthermore, according to one aspect of the present invention, a display device with high definition or high aperture ratio can be provided. Furthermore, according to one aspect of the present invention, a transistor, semiconductor device, display device, or memory device with high reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device, display device, or memory device with low power consumption can be provided. Furthermore, according to one aspect of the present invention, a memory device with high operating speed can be provided. Furthermore, according to one aspect of the present invention, a method for manufacturing the above-mentioned transistor, semiconductor device, display device, or memory device can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims. Attached Figure Description

[0025] Figure 1A This is a plan view showing an example of a semiconductor device. Figure 1B and Figure 1C This is a cross-sectional view showing an example of a semiconductor device. Figure 2A This is a plan view showing an example of a semiconductor device. Figure 2B and Figure 2C This is a cross-sectional view showing an example of a semiconductor device. Figure 2D This is a plan view showing an example of a semiconductor device. Figures 3A to 3D This is a cross-sectional view showing an example of a semiconductor device. Figure 4A This is a plan view showing an example of a semiconductor device. Figure 4B and Figure 4C This is a cross-sectional view showing an example of a semiconductor device. Figures 5A to 5C This is a cross-sectional view showing an example of a semiconductor device. Figure 6A and Figure 6B This is a cross-sectional view showing an example of a semiconductor device. Figures 7A to 7C This is a cross-sectional view showing an example of a semiconductor device. Figures 8A to 8C This is a cross-sectional view showing an example of a semiconductor device. Figures 9A to 9C This is a cross-sectional view showing an example of a semiconductor device. Figure 10A This is a plan view showing an example of a semiconductor device. Figure 10B and Figure 10C This is a cross-sectional view showing an example of a semiconductor device. Figures 11A to 11C This is a cross-sectional view showing an example of a semiconductor device. Figure 12A and Figure 12B This is a cross-sectional view showing an example of a semiconductor device. Figure 13A and Figure 13B This is a cross-sectional view showing an example of a semiconductor device. Figure 14A and Figure 14B This is a cross-sectional view showing an example of a semiconductor device. Figures 15A to 15C This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figures 16A to 16B This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 17A This is a floor plan showing an example of a storage device. Figure 17B and Figure 17C This is a cross-sectional view showing an example of a storage device. Figure 18A This is a floor plan showing an example of a storage device. Figure 18B This is a cross-sectional view showing an example of a storage device. Figure 19 This is a cross-sectional view showing an example of a storage device. Figure 20 This is a cross-sectional view showing an example of a storage device. Figure 21 This is a block diagram illustrating an example of the structure of a semiconductor device. Figures 22A to 22H This is a diagram illustrating an example of the circuit structure of a memory cell. Figure 23A and Figure 23B This is a three-dimensional diagram illustrating an example of the structure of a semiconductor device. Figure 24 This is a block diagram illustrating the CPU. Figure 25A and Figure 25B It is a 3D diagram of a semiconductor device. Figure 26A and Figure 26B It is a 3D diagram of a semiconductor device. Figure 27A and Figure 27B It is a diagram that shows the various storage devices in a hierarchical manner. Figure 28A and Figure 28B This is a perspective view showing an example of a display device. Figure 29 This is a cross-sectional view showing an example of a display device. Figure 30 This is a cross-sectional view showing an example of a display device. Figures 31A to 31C This is a diagram showing an example of the structure of a display device. Figure 32A and Figure 32B This is a diagram showing an example of an electronic component. Figures 33A to 33C This is a diagram illustrating an example of a large computer. Figure 33D This is a diagram illustrating an example of a space device. Figure 33E This is a diagram illustrating an example of a secondary storage system that can be used in a data center. Figures 34A to 34F This is a diagram illustrating an example of an electronic device. Figures 35A to 35G This is a diagram illustrating an example of an electronic device. Figures 36A to 36F This is a diagram illustrating an example of an electronic device. Figure 37A and Figure 37B This is a diagram showing the electrical characteristics of a transistor. Figure 38A and Figure 38B This is a diagram showing the electrical characteristics of a transistor. Figure 39A and Figure 39B This is a diagram showing the electrical characteristics of a transistor. Figure 40A and Figure 40B This is a diagram showing the electrical characteristics of a transistor. Figure 41 This is a graph showing the results of STEM observations. Figure 42 This is a graph showing the results of STEM observations. Figure 43 This is a graph showing the results of the EDX analysis. Figure 44 This is a graph showing the results of the EDX analysis. Figure 45 This is a graph showing the results of the EDX analysis. Figure 46 This is a graph showing the results of the EDX analysis. Figure 47 It is a circuit diagram used for circuit simulation. Figure 48A and Figure 48B It is a timing diagram illustrating the operation of the circuit. Figure 49 This is a graph showing the results of STEM observations. Figure 50 This is a graph showing the results of STEM observations. Figure 51 This is a graph showing the results of STEM observations. Detailed Implementation

[0026] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0027] Note that in the invention structure described below, the same symbols are used in different figures to show the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when parts with the same function are indicated, the same shading lines are sometimes used without additional symbols.

[0028] For ease of understanding, the positions, dimensions, and extents of the components shown in the accompanying drawings may not represent their actual positions, dimensions, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, dimensions, and extents disclosed in the accompanying drawings.

[0029] Note that, for convenience, ordinal numbers such as "first" and "second" are used in this specification, etc., but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, the ordinal numbers used for constituent elements in one part of this specification may sometimes differ from those used for the same constituent element in other parts of this specification or in the claims.

[0030] A transistor is a type of semiconductor device that can amplify current or voltage and control switching operations, such as turning on or off. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0031] In this specification and other materials, transistors that use oxide semiconductors or metal oxides as semiconductor layers and transistors that include oxide semiconductors or metal oxides in the channel formation region are sometimes referred to as OS transistors. Furthermore, transistors that include silicon in the channel formation region are sometimes referred to as Si transistors.

[0032] In this specification and the like, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (also called a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) that forms a channel, and current can flow between the source and drain through the channel-forming region. Note that in this specification and the like, the channel-forming region refers to the region through which current primarily flows.

[0033] Furthermore, in cases where transistors of different polarities are used or the current direction changes during circuit operation, the functions of the source and drain may sometimes be interchanged. Therefore, in this specification, the source and drain may be interchanged.

[0034] Note that impurities in semiconductors refer to elements other than the main components of the semiconductor. For example, elements with a concentration below 0.1 atomic% can be considered impurities. The presence of impurities can sometimes lead to an increase in the defect state density or a decrease in crystallinity of the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter its properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water sometimes also acts as an impurity. Furthermore, the incorporation of impurities can sometimes lead to oxygen vacancies (also referred to as V) in the oxide semiconductor. O The formation of ).

[0035] Note that in this specification, oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content.

[0036] For example, the content of elements such as hydrogen, oxygen, carbon, and nitrogen in the membrane can be analyzed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less or 1 atomic% or less). When comparing elemental contents, it is more preferable to use a combined analysis of SIMS and XPS.

[0037] Furthermore, depending on the situation or state, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be changed into a "conductive film." Similarly, an "insulating film" can be changed into an "insulating layer."

[0038] In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and less than 10°. Therefore, it also includes a state where the angle is -5° or more and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is -30° or more and less than 30°. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is 80° or more and less than 100°. Therefore, it also includes a state where the angle is 85° or more and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is 60° or more and less than 120°.

[0039] In this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include, in addition to electrodes or wiring, switching elements such as transistors, resistors, coils, and other elements with various functions.

[0040] Furthermore, in this specification and other materials, unless otherwise specified, off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and source. gs Below the threshold voltage V th (V in p-channel transistor) gs Higher than V th ) state.

[0041] In this specification, normally-on characteristic refers to the state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate. Normally-off characteristic refers to the state in which no current flows through the transistor when no voltage is applied to the gate or when the gate is supplied with a ground potential.

[0042] In this specification, the top surface shape of a constituent element refers to the outline shape of the constituent element when viewed from a plane. Furthermore, "viewed from a plane" means viewed from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0043] In this specification, "generally consistent top surface shape" means that at least a portion of the outline of each layer in the stack overlaps. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, in reality, there are cases where the outlines do not overlap; sometimes the upper layer is inside or outside the lower layer. In such cases, it can also be said that the "top surface shape is generally consistent." When the top surface shapes are consistent or generally consistent, it can also be said that the ends are aligned or substantially aligned, or that the side ends are consistent or generally consistent.

[0044] In this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region where the angle (also referred to as the cone angle) formed by the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Here, the side surface of the constituent element, the substrate surface, and the surface to be formed do not necessarily have to be completely flat; they may be approximately planar with slight curvature or approximately planar with slight irregularities.

[0045] In this specification and the like, when it is stated that "A is in contact with B", at least a portion of A is in contact with B. Therefore, for example, it can be said that A includes the area in contact with B.

[0046] In this specification, etc., when it is stated that "A is located on B", at least a portion of A is located on B. Therefore, for example, it can be said that A includes the area located on B.

[0047] In this specification and the like, when it is stated that "A covers B", at least a portion of A covers B. Therefore, for example, it can be said that A includes the area that covers B.

[0048] In this specification and the like, when it is stated that "A overlaps with B", at least a portion of A overlaps with B. Therefore, for example, it can be said that A includes the region that overlaps with B.

[0049] In this specification, devices manufactured using a metal mask or FMM (Fine Metal Mask) are sometimes referred to as devices having an MM (Metal Mask) structure. Furthermore, devices manufactured without a metal mask or FMM are sometimes referred to as devices having an MML (Metal Mask Less) structure.

[0050] In this specification and other materials, the structure in which light-emitting elements (also known as light-emitting devices) with different emission wavelengths are fabricated with separate light-emitting layers is sometimes referred to as an SBS (Side By Side) structure. Because the SBS structure allows for the optimization of materials and structure for each light-emitting element, the freedom of material and structure selection is increased, and it is easy to achieve improvements in brightness and reliability.

[0051] In this specification and other materials, holes or electrons are sometimes referred to as "carriers." Specifically, a hole injection layer or electron injection layer is sometimes referred to as a "carrier injection layer," a hole transport layer or electron transport layer as a "carrier transport layer," and a hole blocking layer or electron blocking layer as a "carrier blocking layer." Note that the above distinctions between carrier injection layer, carrier transport layer, and carrier blocking layer are sometimes unclear. Furthermore, sometimes a single layer functions as two or three of the following: a carrier injection layer, a carrier transport layer, and a carrier blocking layer.

[0052] In this specification, the light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Examples of layers included in the EL layer (also referred to as functional layers) include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification, the light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes. In this specification, sometimes one of the pairs of electrodes is referred to as a pixel electrode, and the other as a common electrode.

[0053] In this specification, the sacrificial layer (also known as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape in the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0054] In this specification, etc., "island" refers to the state in which two or more layers formed in the same process and using the same material are physically separated. For example, an island EL layer refers to an EL layer that is physically separated from its adjacent EL layers.

[0055] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is disconnected due to the shape of the surface to which it is formed (e.g., a step).

[0056] Note that arrows indicating the X, Y, and Z directions are sometimes included in the accompanying drawings and other materials of this specification. Note that in this specification, "X direction" refers to the direction along the X-axis, and unless explicitly stated otherwise, its direction (clockwise or counterclockwise) is not always distinguished. The same applies to "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are intersecting directions. For example, the X, Y, and Z directions are orthogonal to each other.

[0057] (Implementation Method 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described.

[0058] One aspect of the semiconductor device of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, a first insulating layer, and a second insulating layer.

[0059] A first insulating layer is located on a first conductive layer, and a second conductive layer is located on the first insulating layer. The first insulating layer and the second conductive layer include an opening extending into the first conductive layer. An oxide semiconductor layer is in contact with at least the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer within the opening. The second insulating layer is located on the oxide semiconductor layer within the opening. A third conductive layer overlaps with the oxide semiconductor layer within the opening, separated by the second insulating layer. Note that the opening is also referred to as an aperture.

[0060] The first conductive layer is used as one of the source and drain electrodes of the transistor. The second conductive layer is used as the other of the source and drain electrodes of the transistor. The third conductive layer is used as the gate electrode of the transistor, and the second insulating layer is used as the gate insulating layer.

[0061] In this specification, etc., it is simply referred to as "when viewed in section," but more specifically, it can sometimes be changed to "when viewed in section from the same direction." For example, when explaining the relationship between multiple constituent elements, the relationship when viewed in section from the same direction is explained. In this case, the relationship between the multiple constituent elements can be explained with reference to a cross-sectional view.

[0062] In one embodiment of the present invention, the source and drain electrodes of the transistor are located at different heights, so the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction has a height (vertical) component; therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc.

[0063] Because the source electrode, semiconductor layer, and drain electrode can be stacked, the area occupied by a transistor of one aspect of the present invention can be much smaller than that of a so-called planar transistor in which the semiconductor layer is configured as a planar shape.

[0064] Note that in this specification, "end-aligned" means that at least a portion of the contours of stacked layers overlap when viewed from a plane. This includes, for example, cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, strictly speaking, sometimes the contours do not overlap and the contour of the upper layer is inside or outside the contour of the lower layer; these cases can also be described as "end-aligned".

[0065] Note that, generally speaking, it is sometimes difficult to clearly distinguish between "completely identical" and "substantially identical". Therefore, in this specification and other materials, "identical" sometimes includes both cases of complete identicalness and cases of substantial identicalness.

[0066] <Example 1 of semiconductor device structure> Reference Figures 1A to 3D The structure of a semiconductor device according to one aspect of the present invention is described. Figure 1A It is a plan view of a semiconductor device including transistor 200. Figure 1B It is along Figure 1A The cross-sectional view of the dotted line A1-A2 shown. Figure 1C It is along Figure 1A The cross-sectional view shown is the dotted-dash line A3-A4. Figure 2A It is a cross-sectional view of the XY plane including the insulating layer 280. Figure 2B Is Figure 1B A magnified view of the area enclosed by the dotted line. Note that in... Figure 1A In the plan view, some constituent elements are omitted for clarity. Sometimes, some constituent elements are also omitted in the plan view shown below.

[0067] Figures 1A to 1C , Figure 2A and Figure 2B The semiconductor device shown includes an insulating layer 210 on a substrate (not shown), a transistor 200 on the insulating layer 210, and an insulating layer 280 on the insulating layer 210. The insulating layers 210 and 280 are used as interlayer films.

[0068] Transistor 200 includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. The conductive layers 220 and 240 are located at different heights.

[0069] In transistor 200, oxide semiconductor layer 230 is used as semiconductor layer, conductive layer 260 is used as gate electrode, insulating layer 250 is used as gate insulating layer, conductive layer 220 is used as one of source electrode and drain electrode, and conductive layer 240 is used as the other of source electrode and drain electrode.

[0070] The regions of the oxide semiconductor layer 230 that are in contact with the conductive layer 220 and the regions of the oxide semiconductor layer 230 that are in contact with the conductive layer 240 are preferably used as low resistance regions.

[0071] like Figure 1B and Figure 1C As shown, the insulating layer 280 and the conductive layer 240 are provided with openings 290 that reach the conductive layer 220. Here, the bottom of the opening 290 is the top surface of the conductive layer 220, and the sidewalls of the opening 290 are the sidewalls of the insulating layer 280 and the conductive layer 240. The opening 290 includes openings in both the insulating layer 280 and the conductive layer 240. In other words, the opening in the region of the insulating layer 280 that overlaps with the conductive layer 220 is part of the opening 290, and the opening in the region of the conductive layer 240 that overlaps with the conductive layer 220 is another part of the opening 290. Note that the opening 290 in the insulating layer 280 is referred to as opening 290a, and the opening 290 in the conductive layer 240 is referred to as opening 290b.

[0072] At least a portion of the constituent elements of transistor 200 are disposed inside opening 290. Specifically, at least a portion of each of oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 is located inside opening 290. Oxide semiconductor layer 230 is in contact with the top surface of conductive layer 220, the side surface of insulating layer 280, and the side surface of conductive layer 240 within opening 290.

[0073] The insulating layer 280 includes an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b. The insulating layer 280a has a region contacting the top surface of the insulating layer 210, a region contacting the side surface of the conductive layer 220, and a region contacting the top surface of the conductive layer 220. The insulating layer 280c has a region contacting the bottom surface of the conductive layer 240. The conductive layer 220 can be a single layer or have a multilayer structure. Figure 1B Examples are shown of conductive layer 220 having a three-layer structure on insulating layer 210, consisting of conductive layer 220a, conductive layer 220b, and conductive layer 220c stacked sequentially.

[0074] An oxide semiconductor layer 230 is disposed inside the opening 290 of the insulating layer 280. Furthermore, in the transistor 200, one of the source and drain electrodes (in this conductive layer 220) is below and the other (in this conductive layer 240) is above, thus the transistor 200 has a structure in which current flows vertically. That is, a channel is formed along the sidewall of the opening 290 of the insulating layer 280.

[0075] The oxide semiconductor layer 230 contacts the top surface of the conductive layer 220 and the side surface of the conductive layer 240 inside the opening 290. The oxide semiconductor layer 230 also contacts a portion of the top surface of the conductive layer 240. Thus, by making the oxide semiconductor layer 230 contact not only the side surface of the conductive layer 240 but also its top surface—for example, compared to the case where the oxide semiconductor layer 230 contacts only the side surface of the conductive layer 240 without contacting its top surface—the contact area between the oxide semiconductor layer 230 and the conductive layer 240 can be increased. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0076] The conductive layer 240 has an opening 290b in the region overlapping with the conductive layer 220. Furthermore, the conductive layer 240 is preferably not disposed inside the opening 290a of the insulating layer 280. That is, the conductive layer 240 preferably does not have a region that contacts the side surface of the insulating layer 280 in the opening 290a. By adopting this structure, both the opening 290b of the conductive layer 240 and the opening 290a of the insulating layer 280 can be formed simultaneously. Furthermore, by adopting a structure where the side surface of the conductive layer 240 in the opening 290b is consistent with or substantially consistent with the side surface of the insulating layer 280 in the opening 290a, the thickness distribution of the oxide semiconductor layer 230 disposed inside the opening 290 can be made uniform. Moreover, separation of the oxide semiconductor layer 230 due to the step between the conductive layer 240 and the insulating layer 280 can be suppressed.

[0077] The conductive layer 260 is preferably composed of a stacked structure of a conductive layer 260a and a conductive layer 260b on the conductive layer 260a. Alternatively, the conductive layer 260a and the conductive layer 260b may each have a stacked structure.

[0078] The width of the opening 290 is a width D. The width D sometimes varies in the depth direction. For example, it can be the width of the upper end of the opening 290a in the insulating layer 280. Alternatively, it can be the width of its lower end. Or, it can be half the depth of the opening 290a in the insulating layer 280. Alternatively, it can be the width of the opening 290b in the conductive layer 240.

[0079] The arrangement of the oxide semiconductor layer 230 and the insulating layer 250 inside the opening 290 reflects the shape of the opening 290. Specifically, the oxide semiconductor layer 230 is provided to cover the bottom and sidewalls of the opening 290, and the insulating layer 250 is provided to cover the oxide semiconductor layer 230. The oxide semiconductor layer 230 is preferably provided to contact the sidewall of the insulating layer 280 in the opening 290a. In addition, the insulating layer 250 is arranged to face the sidewall of the insulating layer 280 in the opening 290a through the oxide semiconductor layer 230.

[0080] The conductive layer 260 is disposed along the recess of the insulating layer 250, which reflects the shape of the opening 290. Miniaturization of the transistor 200 can be achieved by reducing the width D; however, when the width D is reduced, if the aspect ratio of the opening 290 is high, the coverage of the sidewalls of the opening 290 may decrease depending on the formation method or thickness of the constituent elements disposed inside the opening. Furthermore, there is a concern that further reduction in coverage of the inside of the opening is possible when the width D is reduced and the oxide semiconductor layer 230 is made thicker.

[0081] In one embodiment of the semiconductor device of the present invention, miniaturization of the transistor 200 can be achieved by arranging a highly coverlable conductive layer 260a covering the sidewalls of the opening 290 and arranging a thick conductive layer 260b at the upper end of the opening 290. The conductive layer 260 is suitable for placement within the fine opening 290, thereby reducing the wiring resistance of the conductive layer 260. Furthermore, the conductive layer 260 can be suitable for placement even when the thickness of the oxide semiconductor layer 230 is increased.

[0082] The conductive layer 260b is disposed at the upper end of the opening 290, but for example, there are areas in the opening 290 where the conductive layer 260b is not disposed. Figure 2D An example top view of conductive layer 260b is shown. Figure 2D In the example shown, the conductive layer 260b includes an opening 281 when viewed from above. The opening 281 overlaps with the opening 290, and the opening width of the opening 281 is smaller than that of the opening 290.

[0083] exist Figure 2D In the middle, opening 281 is surrounded by opening 290.

[0084] The opening 290 preferably has a tapered shape at its upper end. Furthermore, the opening 290 preferably has a region with a tapered shape at its upper end and a region located deeper than this region, whose sidewalls are steeper than the upper end. Steepness here refers to a situation where, for example, the angle relative to the sidewalls of the insulating layer 210 is perpendicular or nearly perpendicular.

[0085] By giving the opening 290 the shape described above, the conductive layer 260 can also have an appropriate shape when the size of the transistor 200 is made smaller. Specifically, for example, the conductive layer 260 can be formed at the upper end of the opening 290 in such a way that the conductive layer 260a has high coverage of the sidewalls of the opening 290 and the conductive layer 260b has a relatively thick thickness.

[0086] The film disposed inside the opening 290 can be formed using atomic layer deposition (ALD), sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), etc.

[0087] The conductive layer 260a is preferably formed using a deposition method with high coverage. For example, by using a high-coverage method such as ALD or metal CVD, a conductive layer 260a with a high aspect ratio structure can be deposited. Furthermore, a film with few defects such as pinholes can be deposited. Therefore, this film can be deposited with high coverage in the region with steep sidewalls of the opening 290.

[0088] Furthermore, the conductive layer 260b is preferably formed using a method with a faster deposition rate than the conductive layer 260a. For example, the conductive layer 260b can be formed by sputtering or the like. As an example, sputtering has a faster deposition rate and better productivity than the ALD method, so it is suitable as a method for forming thick conductive layers. By increasing the thickness of the conductive layer 260b to increase the cross-sectional area, the resistance can be reduced. On the other hand, in methods suitable for thick films, deposition methods with anisotropic deposition rates have high aspect ratios, sometimes making it difficult to cover openings with steep sidewalls. For example, sputtering sometimes has difficulty covering the steep sidewall regions of the opening 290. Therefore, when the width D of the opening 290 becomes smaller, sometimes the conductive layer 260b is not embedded in a region from the bottom to a certain height within the opening 290. In this case, by using a method with high coverage to form a conductive layer 260a, the conductive layer 260a can cover the oxide semiconductor layer 230 and the insulating layer 250 in the opening, so the conductive layer 260 can be used as the gate electrode of the transistor 200.

[0089] The conductive layer 260b preferably has a region covering the top surface of the insulating layer 280. In this region, the conductive layer 260b covers the top surface of the insulating layer 280, for example, through the conductive layer 240. Alternatively, for example, it covers the top surface of the insulating layer 280 through the oxide semiconductor layer 230.

[0090] Furthermore, the conductive layer 260b preferably has a region covering the side surface of the opening 290b of the conductive layer 240. In this region, the conductive layer 260b covers the side surface of the opening 290b, for example, through the oxide semiconductor layer 230. Alternatively, for example, the side surface of the opening 290b is covered through the insulating layer 250.

[0091] The sidewall of the opening 290 has an area covered by the conductive layer 260b and an area not covered by the conductive layer 260b. For example, the conductive layer 260b only covers the area above the opening, including the upper end of the opening 290.

[0092] The upper end of the opening 290 preferably has a tapered shape. At least a portion of the sidewall of the region having the tapered shape is preferably covered by the conductive layer 260b.

[0093] The opening 290 preferably has a region with steeper sidewalls than the upper end, deeper than the region having a conical shape. Compared to the region with a conical shape, the region with steep sidewalls is less likely to be covered by the conductive layer 260b. Therefore, the sidewalls of this steep region may, for example, not be covered by the conductive layer 260b. Alternatively, for example, only the upper end and nearby portion of the sidewalls of this steep region may be covered by the conductive layer 260b, while the portion below this portion may not be covered by the conductive layer 260b.

[0094] exist Figure 1B and Figure 1C In the transistor 200 shown, in the opening 290, the sidewalls of the conductive layer 240 and the insulating layer 280c include regions with a tapered shape, and the sidewalls of the insulating layer 280b and the insulating layer 280a include regions steeper than the sidewalls of the conductive layer 240. Figure 2B In the cross-section shown, the height P1 of the lower end of the conductive layer 260b is located below the height P2 of the lower end of the region with the conical shape.

[0095] Figure 2C Show Figure 2B These are variations, differing only in the shape of the conductive layer 260b. Figure 2C In the cross-section shown, the height P1 of the lower end of the conductive layer 260b is above the height P2 of the lower end of the region with the conical shape.

[0096] The insulating layer 250 preferably has a structure that provides good coverage of the sidewalls of the opening 290 and is able to suppress short circuits between the conductive layer 240 and the conductive layer 260.

[0097] The conductive layer 260 has a region located on the insulating layer 280. Figure 1B and Figure 1CIn the conductive layer 260, the insulating layer 280 has regions that respectively cover the conductive layer 240, the oxide semiconductor layer 230 and the insulating layer 250.

[0098] The conductive layer 240 preferably has areas that are not covered by the conductive layer 260. In the areas that do not overlap with the conductive layer 260, the ends of the conductive layer 240 are located outside the ends of the conductive layer 260. In the areas of the conductive layer 240 that do not overlap with the conductive layer 260, a conductive layer is disposed on top thereon, which can make the conductive layer electrically connected to the conductive layer 240.

[0099] Figure 1B The diagram shows a structure in which the end of the conductive layer 240 outside the opening 290 is located outside the end of the conductive layer 260. By adopting this structure, plugs or the like can be provided in the region of the conductive layer 240 extending outside the conductive layer 260, and electrically connected to the conductive layers such as wiring and electrodes located on the upper layers of the conductive layers 240 and 260.

[0100] The insulating layer 250 is disposed in contact with the top surface of the oxide semiconductor layer 230. Furthermore, the insulating layer 250 preferably has a region in contact with the top surface of the conductive layer 240, a region in contact with the side surface of the conductive layer 240, and a region in contact with the top surface of the insulating layer 280.

[0101] like Figure 1B and Figure 1C As shown, a portion of the insulating layer 250 is located outside the opening 290, i.e., on the conductive layer 240 and the insulating layer 280. In this case, the insulating layer 250 preferably covers the end of the oxide semiconductor layer 230. This prevents a short circuit between the conductive layer 260 and the oxide semiconductor layer 230. Furthermore, the insulating layer 250 preferably covers the end of the conductive layer 240. This prevents a short circuit between the conductive layer 260 and the conductive layer 240.

[0102] Insulating layer 250 is used as the gate insulating layer of transistor 200. By thinning the gate insulating layer, the gate potential applied when transistor 200 is operating can be reduced. In addition, transistor 200 can be operated at high speed.

[0103] Here, Figure 1B and Figure 1CThe diagram shows a structure where the end of the oxide semiconductor layer 230 on the outer side of the opening 290 is located inside the end of the conductive layer 240. Note that the invention is not limited thereto. For example, in the X direction, sometimes the end of the oxide semiconductor layer 230 coincides with or substantially coincides with the end of the conductive layer 240. Alternatively, sometimes the end of the oxide semiconductor layer 230 is located outside the end of the conductive layer 240. By having the end of the oxide semiconductor layer 230 located outside the end of the conductive layer 240, and by having the oxide semiconductor layer 230 cover the end of the conductive layer 240, the withstand voltage between the conductive layer 240 and the conductive layer 260 can sometimes be further improved, and the leakage current flowing through the insulating layer 250 located between the conductive layer 240 and the conductive layer 260 can be further reduced.

[0104] By setting the angle formed between the sidewall of the opening 290 and the top surface of the insulating layer 210 to 60 degrees or less, more preferably 50 degrees or less, and even more preferably 40 degrees or less, the sidewall of the opening 290 can have a tapered shape. Furthermore, when the angle formed between the top surface of the insulating layer 210 and the sidewall of the opening 290 is set to less than 20 degrees, the width D of the opening 290 increases, sometimes making it difficult to miniaturize the transistor 200. Therefore, when the sidewall of the opening 290 has a tapered shape, for example, the angle formed between the top surface of the insulating layer 210 and the sidewall of the opening 290 can be 20 degrees or more and 75 degrees or less, preferably 20 degrees or more and 70 degrees or less, more preferably 20 degrees or more and 60 degrees or less, and even more preferably 20 degrees or more and 50 degrees or less.

[0105] By making the angle formed between the sidewall of the opening 290 and the top surface of the insulating layer 210 greater than 60 degrees and less than 90 degrees, preferably more than 70 degrees and less than 90 degrees, more preferably more than 75 degrees and less than 90 degrees, further preferably greater than 75 degrees and less than 90 degrees, and even more preferably more than 80 degrees and less than 90 degrees, the sidewall of the opening 290 can have a steep shape, thereby enabling the miniaturization or high integration of semiconductor devices.

[0106] Alternatively, for example, the sidewalls of the opening 290 may sometimes have an inverted conical shape. In other words, the angle formed by the side surface of the insulating layer 280 and the top surface of the insulating layer 210 in the opening 290 may sometimes be greater than 90 degrees.

[0107] The sidewall of the opening 290 is preferably provided, for example, in a manner perpendicular to the top surface of the insulating layer 210. Figure 3A The angles θ1a, θ1b, θ1c, and θ2 formed by the sides of the insulating layers 280a, 280b, 280c, and conductive layer 240 in the opening 290 with the top surface of the insulating layer 210 are shown. Figure 3AThe angles θ1a, θ1b, θ1c, and θ2 shown in the accompanying drawings can be measured, for example, by observing an image of a cross-section of a transistor including one aspect of the present invention. Furthermore, in the image of the cross-section, in cases where the side surface is curved or has unevenness, a straight line approximating the side surface can be drawn to determine the angle. The side surface of the layer can also be divided into several regions and approximate straight lines drawn for each region. Additionally, a straight line connecting the upper and lower ends of the side surface of the layer can be used as the side surface. Similarly, in cases where the top surface is curved or has unevenness, a straight line approximating the top surface can be drawn to determine the angle. In this case, an approximate straight line can be drawn within the area including the top surface, for example, the area including the opening 290. Additionally, a straight line connecting the two ends of this area of ​​the top surface can be used as the top surface. Figure 3A In this context, angles θ1a, θ1b, θ1c, and θ2 are, for example, greater than 20 degrees and less than 90 degrees.

[0108] Figure 3A An example is shown where the conductive layer 240 and the insulating layer 280c have a tapered shape. Figure 3A In the middle, the portion with a conical shape is surrounded by a dotted line. Angles θ2 and θ1c are each preferably 20 degrees or more and 75 degrees or less, more preferably 20 degrees or more and 70 degrees or less, further preferably 20 degrees or more and 60 degrees or less, and even more preferably 20 degrees or more and 50 degrees or less.

[0109] The angles θ1b and θ1a are preferably greater than 60 degrees and less than 90 degrees, more preferably greater than 70 degrees and less than 90 degrees, further preferably greater than 75 degrees and less than 90 degrees, even more preferably greater than 75 degrees and less than 90 degrees, and even more preferably greater than 80 degrees and less than 90 degrees.

[0110] Here, angles θ1a, θ1b, θ1c and θ2 are each the angles formed with the top surface of the insulating layer 210, but they can also be the angles formed with the top surface of the conductive layer 220.

[0111] Furthermore, by setting the thickness of the insulating layer 280c to, for example, 50 nm or less, 30 nm or less, preferably 20 nm or less, and more preferably 10 nm or less, even if the insulating layer 280c has a tapered shape, the size of the opening 290 will not be excessively increased, thereby reducing the occupied area of ​​the transistor, which is therefore preferred.

[0112] Figure 3B Show Figure 3A Examples of variations. Figure 3B An example is shown where, in addition to the conductive layer 240 and the insulating layer 280c, the sidewalls of the insulating layer 280a also have a tapered shape. Figure 3BIn the diagram, the portion with a conical shape is surrounded by a dashed line. The conical shape of the sidewalls of the insulating layer 280a improves the coverage of the bottom of the opening 290 and the adjacent oxide semiconductor layer 230, insulating layer 250, and conductive layer 260a. Furthermore, by sufficiently thinning the insulating layer 280a, the increase in the size of the transistor 200 can be suppressed. The insulating layer 280a can be, for example, 50 nm or less, 30 nm or less, preferably 20 nm or less, and more preferably 10 nm or less.

[0113] in addition, Figure 3C and Figure 3D Show each Figure 3A and Figure 3B Examples of variations. Figure 3C and Figure 3D An example is shown where the lower end of the sidewall of the conductive layer 240 is discontinuous with the upper end of the sidewall of the insulating layer 280c. Figure 3C and Figure 3D In the example shown, the lower end of the sidewall of the conductive layer 240 is moved outward by a length d1 from the upper end of the sidewall of the insulating layer 280c. This is achieved by having a [missing information - likely a measurement or design feature] at the upper end of the opening 290. Figure 3C and Figure 3D The stepped shape shown can, for example, improve the coverage of the conductive layer 260b. Figure 3C and Figure 3D In the middle, the cone-shaped part is surrounded by a dotted line.

[0114] In addition, for example, Figures 4A to 5C As shown, angles θ2 and θ1c can also be different.

[0115] Figure 4A It is a plan view of a semiconductor device including transistor 200. Figure 4B It is along Figure 4A The cross-sectional view of the dotted line A1-A2 shown. Figure 4C It is along Figure 4A The cross-sectional view shown is the dotted-dash line A3-A4. Figure 5A Is Figure 4B An enlarged view of the area surrounded by a dashed line. Furthermore, Figure 5B This is a diagram illustrating angles θ1a, θ1b, θ1c, and θ2, corresponding to... Figure 4B The cross-section shown. (As shown) Figure 5B As shown, angle θ2 is different from angle θ1c.

[0116] exist Figure 5BIn the example shown, the angle θ2 is larger than the angle θ1c. Each of the angle θ2 and the angle θ1c is preferably 20 degrees or more and 60 degrees or less, more preferably 20 degrees or more and 50 degrees or less, and still more preferably 20 degrees or more and 40 degrees or less. By making the angle θ2 larger than the angle θ1c, the conical shape at the upper end of the opening 290 can be in the shape of a concave portion, and sometimes the coverage of the conductive layer 260b can be further improved.

[0117] In addition, as Figure 5C shown, sometimes the angle θ2 is smaller than the angle θ1c.

[0118] In addition, Figures 4A to 4C A structural example in which the end of the conductive layer 240 coincides with the end of the oxide semiconductor layer 230 is shown.

[0119] In addition, the insulating layer 250 may also be formed of two or more layers stacked. Figure 6A An example of a stacked structure in which the insulating layer 250 has an insulating layer 250a and an insulating layer 250b on the insulating layer 250a is shown.

[0120] The oxide semiconductor layer 230 may also have a stacked structure of two or more layers. Figure 6A An example of a two-layer structure in which the oxide semiconductor layer 230 has an oxide layer 230a and an oxide layer 230b on the oxide layer 230a is shown. In addition, Figure 6B An example of a three-layer structure in which the oxide semiconductor layer 230 has an oxide layer 230c, an oxide layer 230a on the oxide layer 230c, and an oxide layer 230b on the oxide layer 230a is shown.

[0121] <OS transistor> In the transistor 200, the oxide semiconductor layer 230 including the channel formation region contains a metal oxide (also referred to as an oxide semiconductor) used as a semiconductor. That is, the transistor 200 can be said to be an OS transistor.

[0122] In an OS transistor, when there are oxygen vacancies (V O ) and impurities in the channel formation region of the oxide semiconductor, the electrical characteristics are likely to vary and the reliability may decrease. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (sometimes hereinafter referred to as V O H), and electrons that become carriers may be generated. Therefore, when the channel formation region in the oxide semiconductor contains oxygen vacancies, the OS transistor tends to have a normally-on characteristic. Thus, in the channel formation region in the oxide semiconductor, it is preferable to minimize oxygen vacancies and impurities. In other words, it is preferable that the carrier concentration in the channel formation region of the oxide semiconductor is reduced and it is i-type (intrinsic) or substantially i-type.

[0123] On the other hand, the source and drain regions of the OS transistor are preferably the following regions: due to the higher oxygen vacancy rate compared to the channel formation region, V... O High concentrations of impurities such as hydrogen, nitrogen, and metal elements increase carrier concentration, thus reducing resistance. In other words, compared to the channel formation region, the source and drain regions of an OS transistor are preferably n-type regions with high carrier concentration and low resistance.

[0124] The region of the oxide semiconductor layer 230 that contacts the insulating layer 280 and its vicinity are used as the channel formation region of the transistor 200. One of the regions of the oxide semiconductor layer 230 that contacts the conductive layer 220 and the region of the oxide semiconductor layer 230 that contacts the conductive layer 240 is used as the source region, and the other is used as the drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0125] When the oxide semiconductor layer 230 contacts the conductive layer 220, metal compounds or oxygen vacancies are formed, reducing the resistance of the region of the oxide semiconductor layer 230 in contact with the conductive layer 220. This reduces the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220. Similarly, when the oxide semiconductor layer 230 contacts the conductive layer 240, the region of the oxide semiconductor layer 230 in contact with the conductive layer 240 also reduces the resistance. This reduces the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240.

[0126] like Figure 2A As shown, the insulating layer 280 is in complete contact with the edge of the oxide semiconductor layer 230. Therefore, the channel formation region of the transistor 200 may be formed entirely at the edge of the oxide semiconductor layer 230 within the opening 290 (the entire area in contact with the insulating layer 280). Furthermore, Figure 2A It can also be described as a cross-sectional view on the XY plane including the channel formation region of the oxide semiconductor layer 230.

[0127] The channel length of transistor 200 is the distance between the source and drain regions. In other words, the channel length of transistor 200 can be said to be determined by the thickness of the insulating layer 280 on the conductive layer 220. Figure 1C In the diagram, the channel length L of transistor 200 is indicated by a dashed double arrow. In cross-section, the channel length L is the distance between the end of the region where the oxide semiconductor layer 230 and the conductive layer 220 contact and the end of the region where the oxide semiconductor layer 230 and the conductive layer 240 contact. That is, the channel length L is equivalent to the length of the side surface of the opening 290 of the insulating layer 280 in cross-section.

[0128] In planar transistors, the channel length is limited by the exposure limits of photolithography, making further miniaturization difficult. However, in a semiconductor device according to one aspect of the present invention, the channel length of the transistor can be set according to the thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be set to a very fine structure below the exposure limit of photolithography (e.g., below 60 nm, 50 nm, 40 nm, 30 nm, 20 nm, or 10 nm, or above 0.1 nm, 1 nm, or 5 nm). Consequently, the on-state current of the transistor 200 increases, thereby improving frequency characteristics.

[0129] Since the channel length of the transistor included in one aspect of the semiconductor device of the present invention depends on the thickness of the insulating layer 280 on the conductive layer 220, for example, when the channel length is set to 60 nm or more, the occupied area of ​​the transistor, specifically, for example, the area of ​​the transistor when viewed from above, is also approximately determined by the width of the opening 290. As explained later, the width D of the opening 290 is preferably, for example, 5 nm or more, 10 nm or more, or 20 nm or more and 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. As an example, when the channel length is set to 150 nm, the width of the opening 290 can also be less than 150 nm. That is, a transistor with an opening width narrower than the channel length can be formed, the occupied area of ​​the transistor can be reduced, and high integration of the semiconductor device can be achieved.

[0130] Furthermore, by setting the channel length of the transistor to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the insulating layer 280 and the formation of the opening 290 in the insulating layer 280.

[0131] Therefore, the channel length of the transistor included in the semiconductor device of one aspect of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more and 1 μm or less, 500 nm or less, or 300 nm or less.

[0132] Furthermore, as described above, a channel forming region, a source region, and a drain region can be formed within the opening 290. Therefore, compared to lateral transistors such as planar transistors where the channel forming region, source region, and drain region are respectively provided on the XY plane, the area occupied by the transistor 200 can be reduced. This allows for high integration of the semiconductor device. Moreover, when the semiconductor device according to one aspect of the present invention is used in a memory device, the storage capacity per unit area can be increased.

[0133] In addition, such as Figure 2AAs shown, the oxide semiconductor layer 230, insulating layer 250, and conductive layer 260 are arranged in a concentric circle. Therefore, the side of the conductive layer 260 located at the center faces the side of the oxide semiconductor layer 230 across the insulating layer 250. In other words, when viewed from a plane, the entire edge of the oxide semiconductor layer 230 forms the channel formation region. At this time, for example, the channel width of the transistor 200 is determined by the length of the edge of the oxide semiconductor layer 230. That is to say, the channel width of the transistor 200 is determined by the width of the opening 290 (the diameter if the opening 290 is circular when viewed from a plane). Figure 1C and Figure 2A In the diagram, a double-headed arrow with a double-dotted line indicates the width D of the opening 290. Figure 2A In the diagram, the double-headed dotted arrow represents the channel width W of transistor 200. By increasing the width D of the opening 290, the channel width per unit area can be increased, thereby increasing the on-state current.

[0134] When the opening 290 is formed using photolithography, the width D of the opening 290 is subject to the exposure limit of the photolithography. Furthermore, the width D of the opening 290 is set according to the thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 disposed in the opening 290. The width D of the opening 290 is preferably, for example, 5 nm or more, 10 nm or more, or 20 nm or more but 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular when viewed from a plane, the width D of the opening 290 is equivalent to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0135] Furthermore, the channel length L of transistor 200 is preferably at least smaller than the channel width W of transistor 200. The channel length L of transistor 200 is preferably 0.1 times or more and 0.99 times or less than the channel width W of transistor 200, more preferably 0.5 times or more and 0.8 times or less. By adopting this structure, transistors with good electrical characteristics and high reliability can be realized.

[0136] Furthermore, by forming the opening 290 in a circular shape when viewed from the plane, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged in a concentric circle. As a result, the distance between the conductive layer 260 and the oxide semiconductor layer 230 is approximately uniform, so a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0137] Note that this embodiment shows an example where the shape of the opening 290 when viewed from a plane is circular, but the present invention is not limited thereto. For example, the shape of the opening 290 when viewed from a plane may also be an ellipse or a roughly circular shape, a quadrilateral or a polygonal shape, or a shape in which the corners of the quadrilateral or other polygonal shape are rounded.

[0138] like Figure 7A As shown, a recess overlapping the opening 290 can also be formed on the top surface of the conductive layer 220. By forming at least a portion of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 in a manner that embeds into the recess, the gate electric field of the conductive layer 260 can be easily applied to the vicinity of the conductive layer 220 of the oxide semiconductor layer 230. Figure 7B Is Figure 7A Enlarged view of the area enclosed by the dotted line. The bottom of the conductive layer 260, which serves as the gate electrode, is located below the top surface of the conductive layer 220. Therefore, the conductive layers 260 and 220 have regions that overlap each other, separated by the oxide semiconductor layer 230 and the insulating layer 250.

[0139] Figure 7C Show Figure 7B Examples of variations. In Figure 7C In this configuration, the bottom of the conductive layer 260 is located above the top surface of the conductive layer 220. By forming the oxide semiconductor layer 230 and the insulating layer 250 in a manner that embeds them into the recesses of the conductive layer 220, the distance between the conductive layer 260 and the conductive layer 220 can be shortened. Furthermore, the conductive layer 220 can contact the side surface of the oxide semiconductor layer 230. Figure 7B The area where conductive layer 260 and conductive layer 220 overlap is greater than Figure 7C This area in the text.

[0140] By making contact between the conductive layer 220 and the oxide semiconductor layer 230 on the side, the contact area between the conductive layer 220 and the oxide semiconductor layer 230 can be increased, thereby reducing the contact resistance.

[0141] Furthermore, by having regions where conductive layers 220 and 260 overlap, such as the channel formation region of the oxide semiconductor layer 230, a gate electric field can be easily applied, thereby improving the electrical characteristics of the transistor. Moreover, since a gate electric field can be easily applied to the region of the oxide semiconductor layer 230 that contacts the conductive layer 220, the on-state current of the transistor can be increased, for example.

[0142] <Structure Example of a Semiconductor Device 2> The conductive layer 240 can also have a stacked structure of two or more layers. Figure 8A and Figure 1BThe main difference is that the conductive layer 240 has a stacked structure of conductive layer 240a and conductive layer 240b on conductive layer 240a. Figure 8B Is Figure 8A A magnified view of the area surrounded by a dotted line. Figure 8C This is a diagram illustrating angles θ1a, θ1b, θ1c, θ2a, and θ2b, corresponding to... Figure 8A The cross-section shown is shown. Additionally, angles θ2a and θ2b correspond to the sidewalls of conductive layers 240a and 240b, respectively.

[0143] Note that, although Figure 8A The example shown is a two-layer stack of conductive layer 240, but conductive layer 240 can also be a stack of three or more layers. In addition, conductive layer 260a and conductive layer 260b can also have a stacked structure.

[0144] exist Figure 8C In the example shown, angle θ2b is larger than angle θ2a. Both angle θ2b and angle θ2a are preferably 20 degrees or more and 60 degrees or less, more preferably 20 degrees or more and 50 degrees or less, and even more preferably 20 degrees or more and 40 degrees or less. By making angle θ2b larger than angle θ2a, the tapered shape at the upper end of the opening 290 can be concave, which can sometimes further improve the coverage of the conductive layer 260b.

[0145] in addition, Figure 9A , Figure 9B and Figure 9C Show each Figure 8A , Figure 8B and Figure 8C Examples of variations. Figure 9A An example is shown where the lower end of the sidewall of conductive layer 240b is discontinuous with the upper end of the sidewall of conductive layer 240a. Figure 9B Is Figure 9A A magnified view of the area surrounded by a dotted line. Figure 9C This is a diagram illustrating angles θ1a, θ1b, θ1c, θ2a, and θ2b, corresponding to... Figure 9A The cross-section shown. (As shown) Figure 9C As shown, the position of the lower end of the sidewall of conductive layer 240b is moved outward by a length d2 from the position of the upper end of the sidewall of conductive layer 240a.

[0146] exist Figure 9A In this structure, the oxide semiconductor layer 230 has a region that contacts the top surface of the conductive layer 240a. This increases the contact area between the oxide semiconductor layer 230 and the conductive layer 240b, thereby reducing the contact resistance.

[0147] Additionally, by making the upper end of the opening 290 have Figure 9A The stepped shape shown can, for example, improve the coverage of the conductive layer 260b.

[0148] <Structure Example of a Semiconductor Device 3> Although Figure 1B , Figure 1C The example shown is where the sidewalls of both the conductive layer 240 and the insulating layer 280c in the opening 290 have a tapered shape. However, as shown in FIG10, the sidewalls of the conductive layer 240 can also have a tapered shape, and the sidewalls of the insulating layer 280c can also have a steep shape. The main difference between FIG10 and FIG1 is that the sidewalls of the insulating layer 280c have a steep shape.

[0149] Figure 10A It is a plan view of a semiconductor device including transistor 200. Figure 10B It is along Figure 10A The cross-sectional view of the dotted line A1-A2 shown. Figure 10C It is along Figure 10A The cross-sectional view shown is the dotted-dash line A3-A4. Figure 11A Is Figure 10B An enlarged view of the area surrounded by a dashed line. Furthermore, Figure 11B This is a diagram illustrating angles θ1a, θ1b, θ1c, and θ2, corresponding to... Figure 10B The cross-section shown.

[0150] Figure 11B Show Figure 11A Examples of variations, Figure 11B and Figure 11A The difference is that the sidewalls of the conductive layer 240 have a steep shape, while the sidewalls of the insulating layer 280c have a tapered shape.

[0151] <Insulation layer 283 and insulation layer 285> like Figure 12A As shown, in a semiconductor device, an insulating layer 283 and an insulating layer 285 can be disposed on the transistor 200. Both insulating layers 283 and 285 serve as interlayer films. The insulating layer 283 is disposed such that it covers conductive layers 260a and 260b. Figure 12A In the middle, the insulating layer 283 contacts the conductive layer 260a in the opening 290, and contacts the conductive layer 260b at the upper end of the opening 290. Additionally, in Figure 12A In this context, insulating layer 283 covers the top surface of conductive layer 260b. Additionally, in... Figure 12A In the middle, the insulating layer 283 has a region that covers the top surface of the insulating layer 280 through the conductive layers 260b and 260a.

[0152] exist Figure 12AIn the example shown, an insulating layer 283 is formed using a deposition method that forms a film with high coverage and isotropic properties, and an insulating layer 285 is formed that is embedded inside the opening 290 and has its top surface planarized.

[0153] in addition, Figure 12B An example is shown of an insulating layer 283 that forms the interior of the embedded opening 290 and whose top surface is planarized. Note that... Figure 12B An example is shown where the top surface of the insulating layer 283 is planarized, but the top surface of the insulating layer 283 may not be planarized.

[0154] in addition, Figure 13A An example is shown where the insulating layer 283 does not extend into the interior of the opening 290, but forms a region 277 within the opening 290. As... Figure 13A The insulating layer 283 shown can be formed by methods such as sputtering or PECVD. By preventing the insulating layer 283 from entering the interior of the opening 290, the contact area between the inner wall of the opening 290 and the conductive layer 260a is reduced. When undesirable conditions arise due to the contact between the insulating layer 283 and the conductive layer 260a, the incorporation of impurity elements can be suppressed.

[0155] Region 277 is, for example, a void. Region 277 contains, for example, one or more elements selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements. Furthermore, region 277 has, for example, a relative permittivity approximately equal to that of air. When region 277 contains air, for example, the relative permittivity of region 277 has a value of 1 or near that. For example, the relative permittivity of region 277 is greater than 0.8 and less than 1.2.

[0156] When region 277 is a void, for example, the relative permittivity of region 277 is smaller than that of insulating layer 250. Furthermore, for example, the relative permittivity of region 277 is smaller than that of insulating layer 283.

[0157] In addition, Figure 13B In the example shown, a conductive layer 260b formed at the upper end of the opening 290 covers the upper part of the opening 290. As a result, a region 277 is formed inside the opening 290.

[0158] <Examples of variations of semiconductor devices> Figure 14A The semiconductor device shown illustrates an example where an insulating layer 282 is disposed on a conductive layer 240, and an insulating layer 250 and a conductive layer 260 are formed such that openings and openings 290 of the insulating layer 282 are embedded therein. Figure 14AIn the structure, in the region of the winding wiring in the conductive layer 260, for example, the region formed on the insulating layer 282 is provided between the conductive layer 240 and the conductive layer 240. Therefore, the distance between the wirings can be increased by increasing the thickness of the insulating layer 282. This reduces the parasitic capacitance between the region of the conductive layer 260 formed on the insulating layer 282 and the conductive layer 240. Furthermore, as... Figure 14A As shown, in one aspect of the semiconductor device of the present invention, an insulating layer 284 may be provided on the conductive layer 260.

[0159] Although Figure 14A An example is shown where the insulating layer 250 is arranged to cover the sidewall of the opening in the insulating layer 282, but it can also be arranged as follows: Figure 14B As shown, after the insulating layer 250 is provided in such a way that it covers the top surface of the oxide semiconductor layer 230 and the top surface of the insulating layer 280, the insulating layer 282 is provided on the insulating layer 250.

[0160] Structural Materials for Semiconductor Devices The following describes the materials that can be used in the semiconductor device of this embodiment. Note that the layers constituting the semiconductor device of this embodiment may have either a single-layer structure or a stacked structure.

[0161] [Insulating layer] Inorganic insulating films are preferably used as insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 284, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxynitride insulating films, and oxynitride insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, gallium zinc oxide films, and hafnium aluminum oxide films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxynitride insulating films include silicon oxynitride films, aluminum oxynitride films, gallium oxynitride films, yttrium oxynitride films, and hafnium oxynitride films. Examples of oxynitride insulating films include silicon oxynitride films and aluminum oxynitride films. In addition, organic insulating films can also be used as insulating layers included in semiconductor devices.

[0162] Furthermore, by surrounding a transistor using metal oxides with an insulating layer that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. For example, the insulating layer that suppresses the permeation of impurities and oxygen can be a single layer or a stack of insulating layers selected from one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the material used for the insulating layer that suppresses the permeation of impurities and oxygen can be metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, as well as metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0163] Specifically, it is preferable to use an insulating layer that blocks impurities such as water, hydrogen, and oxygen.

[0164] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, barrier properties refer to properties that make it difficult for the corresponding substance to diffuse, properties that make it difficult for the corresponding substance to pass through, properties that result in low permeability of the corresponding substance, functions that inhibit the diffusion of the corresponding substance, or functions that inhibit the permeation of the corresponding substance. Additionally, hydrogen, referred to as the corresponding substance, can refer to hydrogen atoms, hydrogen molecules, water molecules, and OH-. - At least one of the following: substances bonded to hydrogen. Furthermore, unless otherwise specified, impurities referred to as corresponding substances refer to impurities in the channel-forming region or semiconductor layer, such as at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N₂O, NO, NO₂, etc.), copper atoms, etc. Additionally, oxygen referred to as corresponding substances refers to at least one of oxygen atoms, oxygen molecules, etc.

[0165] Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen, as well as oxygen, include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. For example, oxides containing aluminum and hafnium (hafnium aluminate) can be included. Examples of metal nitrides include aluminum nitride, silicon oxynitride, and silicon nitride.

[0166] Furthermore, insulating layers that are in contact with or near the oxide semiconductor layer, such as gate insulating layers, preferably have regions containing oxygen that has been removed by heating (hereinafter sometimes referred to as excess oxygen). For example, by contacting or placing an insulating layer with regions containing excess oxygen in contact with or near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of insulating layers that readily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide with vacancies.

[0167] For example, with the advancements in transistor miniaturization and high integration, problems such as leakage current sometimes arise due to the thinning of the gate insulating layer. By using a material with a high relative permittivity (high-k) in the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. Moreover, by using a material with a high relative permittivity in the dielectric layer of a capacitor, devices with larger capacitance values ​​can be realized. On the other hand, by using a material with a low relative permittivity in the insulating layer used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials based on the function of the insulating layer. Furthermore, materials with a low relative permittivity are also materials with high dielectric strength.

[0168] Materials with relatively high permittivity include, for example, aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0169] Examples of materials with low relative permittivity include polyesters, polyolefins, polyamides (nylon, aramids, etc.), polyimides, polycarbonates, and acrylic resins. Furthermore, examples of inorganic insulating materials with low relative permittivity other than those mentioned above include fluorinated silica, carbon-containing silica, and silica containing both carbon and nitrogen. Porous silica is also an example. Additionally, these silicas may contain nitrogen.

[0170] For example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon oxynitride can be used on both sides of layers such as gate insulating layers where materials with high relative permittivity are used, and layers such as interlayer films where materials with low relative permittivity are used. Among these materials, for example, the relative permittivity is relatively low compared to high-k materials such as hafnium oxide, so they are sometimes described as materials with low relative permittivity in this specification, etc.

[0171] Furthermore, ferroelectric materials can be used as insulating layers in semiconductor devices. Examples of ferroelectric materials include hafnium oxide, zirconium oxide, and HfZrO. X(X is a real number greater than 0) and other metal oxides. Furthermore, materials that can exhibit ferroelectric properties include those with element J1 added to hafnium oxide (here, element J1 is selected from one or more of zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to 1. Furthermore, materials that can exhibit ferroelectric properties include those with element J2 added to zirconium oxide (here, element J2 is selected from one or more of hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). Furthermore, the ratio of the number of zirconium atoms to the number of element J2 atoms can be appropriately set; for example, the ratio can be set to 1:1 or close to 1. In addition, lead titanate (PbTiO2) can also be used as a material that can exhibit ferroelectric properties. X Piezoelectric ceramics with perovskite structure include barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate.

[0172] Furthermore, metal nitrides containing elements M1, M2, and nitrogen can be cited as materials that can exhibit ferroelectric properties. Here, element M1 is selected from one or more of aluminum, gallium, indium, etc. Furthermore, element M2 is selected from one or more of boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, the atomic ratio of element M1 to element M2 can be appropriately set. Moreover, metal oxides containing element M1 and nitrogen sometimes exhibit ferroelectric properties even without element M2. Furthermore, materials that can exhibit ferroelectric properties include those to which element M3 is added. Note that element M3 is selected from one or more of magnesium, calcium, strontium, zinc, cadmium, etc. Here, the atomic ratio of element M1, element M2, and element M3 can be appropriately set.

[0173] In addition, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and κ-type alumina such as GaFeO3 can be cited as materials that can exhibit ferroelectric properties.

[0174] Note that while metal oxides and metal nitrides are shown among the ferroelectric materials described above, the list is not limited to these. For example, metal oxynitrides (containing nitrogen in the metal oxides) or metal oxynitrides (containing oxygen in the metal nitrides) may also be used.

[0175] Furthermore, as a material that can exhibit ferroelectricity, for example, a mixture or compound composed of multiple materials selected from the above-mentioned materials can be used. Additionally, the insulating layer 130 can have a laminated structure composed of multiple materials selected from the above-mentioned materials. Note that the crystal structure (properties) of the materials listed above may vary not only depending on the deposition conditions but also depending on various processes, etc. Therefore, in this specification, materials exhibiting ferroelectricity are referred not only to ferroelectric materials but also to materials that can exhibit ferroelectricity.

[0176] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when processed into thin films of a few nanometers. Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when their area is extremely small. Therefore, by using metal oxides containing one or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0177] In this specification and the like, a material that can be formed in a layered manner and possess ferroelectric properties is sometimes referred to as a ferroelectric layer. Furthermore, in this specification and the like, a device that includes a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0178] Furthermore, ferroelectricity is thought to arise from the displacement of oxygen or nitrogen in the crystal contained within the ferroelectric layer under the influence of an applied electric field. Moreover, the presence of ferroelectricity is presumed to depend on the structure of the crystal contained within the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 needs to contain a crystal. In particular, the insulating layer preferably has a crystal with an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure of the crystal contained in the insulating layer can be any one or more selected from isometric, tetragonal, orthorhombic, monoclinic, and hexagonal crystal systems. Alternatively, the insulating layer may have an amorphous structure. In this case, the insulating layer may also have a composite structure of amorphous and crystalline structures.

[0179] Insulating layer 250 is used as the gate insulating layer of transistor 200. Insulating layer 250 is preferably made of a material with a high relative permittivity.

[0180] The insulating layer 250 preferably has the function of trapping and fixing hydrogen. This reduces the hydrogen concentration in the oxide semiconductor layer 230 (especially in the channel formation region of the transistor). Therefore, the Vt in the channel formation region can be reduced. O H is used to make the channel forming region i-shaped or substantially i-shaped.

[0181] Materials used as insulating layers with the function of trapping or fixing hydrogen include metal oxides such as hafnium oxides, aluminum oxides, aluminum and hafnium oxides (hafnium aluminate), and magnesium oxides. Furthermore, these metal oxides may also contain zirconium; for example, oxides containing hafnium and zirconium can be cited. In metal oxides with amorphous structures, the ability to trap or fix hydrogen is high because some oxygen atoms have dangling bonds. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure can be achieved by including silicon in these oxides. For example, an oxide containing hafnium and silicon (hafnium silicate) is preferred. Furthermore, sometimes a portion of the metal oxide has one or both of a crystalline region and a grain boundary.

[0182] Furthermore, the function of capturing or fixing the corresponding substance can also be described as possessing the property that the corresponding substance is not easily diffused. Therefore, the function of capturing or fixing the corresponding substance can also be referred to as barrier property.

[0183] When the insulating layer 250 has a stacked structure, it is preferable to use a layer with the function of trapping and fixing hydrogen in any one of the layers (hereinafter referred to as the first insulating layer of the insulating layer 250). Furthermore, when the insulating layer 250 has a two-layer stacked structure, a layer with the function of trapping and fixing hydrogen is used as the layer in contact with the oxide semiconductor layer 230. When it has a stacked structure of three or more layers, a layer with the function of trapping and fixing hydrogen is used as the layer closest to the oxide semiconductor layer 230, thereby more effectively trapping or fixing hydrogen contained in the oxide semiconductor layer 230. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0184] In addition to the first insulating layer, the insulating layer 250 preferably also includes a hydrogen barrier insulating layer as a second insulating layer. Materials for the hydrogen barrier insulating layer include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon oxynitride.

[0185] As the first insulating layer of insulating layer 250, hafnium silicate is preferably used, for example. Furthermore, the first insulating layer of insulating layer 250 preferably has an amorphous structure. By adopting an amorphous structure for the first insulating layer of insulating layer 250, the formation of grain boundaries can be suppressed. By suppressing the formation of grain boundaries, the flatness of the insulating layer can be improved. As a result, the thickness distribution of the insulating layer becomes more uniform, reducing extremely thin sections and thus improving the withstand voltage of the insulating layer. Furthermore, the thickness distribution of the film disposed on the insulating layer can be made more uniform.

[0186] Furthermore, by suppressing the formation of grain boundaries in the insulating layer, leakage current originating from defect states at the grain boundaries can be reduced. Therefore, the insulating layer can be used as an insulating film with low leakage current.

[0187] Since hafnium oxide is a material with a high relative permittivity, hafnium silicate is also a material with a high relative permittivity depending on its silicon content. Therefore, when insulating layer 250a is used as the gate insulating layer, the gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the gate insulating layer. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced.

[0188] Therefore, as the first insulating layer of the insulating layer 250, it is preferable to use an oxide containing one or both of aluminum and hafnium, more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably aluminum oxide having an amorphous structure.

[0189] Furthermore, by using a hydrogen-barrier insulating layer as the second insulating layer 250, the diffusion of impurities contained in the conductive layer 260 into the oxide semiconductor layer 230 can be suppressed. Silicon nitride has high hydrogen barrier properties, so it is suitable for use as the insulating layer 250. Here, the second insulating layer is preferably the upper layer of the first insulating layer.

[0190] By adopting the above structure, a semiconductor device with good electrical characteristics can be provided. Furthermore, a semiconductor device with high reliability can be provided. Furthermore, a semiconductor device with small non-uniformity in the electrical characteristics of the transistor can be provided. Furthermore, a semiconductor device with large on-state current can be provided.

[0191] Furthermore, the insulating layer 250 may also include an insulating layer with a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0192] The insulating layer 250 preferably includes a layer capable of supplying oxygen to the oxide semiconductor layer 230. An oxide can be used as the oxygen-supplying layer. By including silicon oxide or silicon oxynitride in the insulating layer 250, oxygen can be suitably supplied from the insulating layer 250 to the oxide semiconductor layer 230.

[0193] Alternatively, insulating layer 250 may include an insulating layer with a thermally stable structure between a pair of insulating layers that have the function of capturing and fixing hydrogen.

[0194] Furthermore, the insulating layer 250 preferably includes an oxygen-barrier insulating layer. This suppresses oxidation of the conductive layers 240 and 260, etc. When the insulating layer 250 has a laminated structure, the layers in contact with the conductive layer 240 and the layers in contact with the conductive layer 260 are preferably oxygen-barrier insulating layers.

[0195] The layer in insulating layer 250 that contacts conductive layer 240 is preferably less permeable to oxygen than insulating layer 280. When this layer has oxygen-barrier properties, oxidation of the side surface of conductive layer 240, resulting in the formation of an oxide film on that side surface, can be suppressed. Therefore, a decrease in the on-state current or field-effect mobility of transistor 200 can be suppressed.

[0196] For example, by using a hydrogen and oxygen barrier insulating layer as the second insulating layer, oxidation of the conductive layer 260 can be suppressed. Furthermore, the formation of oxygen vacancies in the oxide semiconductor layer 230 due to the diffusion of oxygen contained in the oxide semiconductor layer 230 into the conductive layer 260 can be suppressed.

[0197] Examples of oxides that serve as oxygen barrier insulating layers include hafnium-containing oxides, aluminum-containing oxides, oxides containing both aluminum and hafnium (hafnium aluminate), magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon oxynitride. Additionally, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing both aluminum and hafnium (hafnium aluminate), and oxides containing both hafnium and silicon (hafnium silicate).

[0198] Oxides containing hafnium and silicon (hafnium silicate) are excellent insulating layers that not only serve as oxygen barrier insulating layers but also, as mentioned above, can easily achieve amorphous structures and have the function of trapping or fixing hydrogen.

[0199] In addition to being used as an oxygen-barrier insulating layer, silicon nitride, as mentioned above, is also an excellent insulating layer with high hydrogen barrier properties.

[0200] As the insulating layer 250, it is preferable to adopt a two-layer structure in which a first insulating layer with the function of capturing or fixing hydrogen and a second insulating layer with the hydrogen and oxygen blocking properties are stacked sequentially from the oxide semiconductor layer 230 side.

[0201] As an example, an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer, and silicon nitride can be used as the second insulating layer.

[0202] Here, when the insulating layer 250 has a two-layer structure of insulating layer 250a and insulating layer 250b on insulating layer 250a, the first insulating layer can be used as insulating layer 250a, and the second insulating layer can be used as insulating layer 250b.

[0203] As the insulating layer 250, a three-layer structure is preferably adopted from the oxide semiconductor layer 230 side, wherein a third insulating layer containing a material with a relatively low relative permittivity, a first insulating layer having the function of trapping or fixing hydrogen, and a second insulating layer having hydrogen and oxygen blocking properties are sequentially stacked. The material with a relatively low relative permittivity contained in the third insulating layer refers to a material whose relative permittivity is lower than that of any one or more other layers in the stacked structure. Here, silicon oxide or silicon oxynitride can be used as the third insulating layer. The third insulating layer is the layer in contact with the oxide semiconductor layer 230. By using an oxide in the third insulating layer, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, by providing the second insulating layer, the diffusion of oxygen contained in the third insulating layer to the conductive layer 260 can be suppressed, thereby suppressing the oxidation of the conductive layer 260. In addition, the reduction of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0204] As an example, silicon oxide or silicon oxynitride can be used as the third insulating layer, an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer, and silicon nitride can be used as the second insulating layer.

[0205] Here, when the insulating layer 250 has the above-described three-layer structure, the insulating layer 250a may have a two-layer stacked structure of a third insulating layer and a first insulating layer, and the insulating layer 250b may use a second insulating layer. Alternatively, the insulating layer 250a may use a third insulating layer, and the insulating layer 250b may have a two-layer stacked structure of a first insulating layer and a second insulating layer.

[0206] As the insulating layer 250, it is preferably a four-layer structure in which a fourth insulating layer with oxygen-barrier properties, a third insulating layer containing a material with a relatively low relative permittivity, a first insulating layer with hydrogen-trapping or fixing functions, and a second insulating layer with both hydrogen and oxygen-barrier properties are sequentially stacked from one side of the oxide semiconductor layer 230. The first to third insulating layers can adopt the same structure as the layers used in the above three-layer structure. The fourth insulating layer is the layer in contact with the oxide semiconductor layer 230. When the fourth insulating layer has oxygen-barrier properties, it can suppress the detachment of oxygen from the oxide semiconductor layer 230. As the fourth insulating layer, aluminum oxide is preferably used, for example. Since aluminum oxide has the function of trapping or fixing hydrogen, it is suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230.

[0207] For example, aluminum oxide can be used as the fourth insulating layer, silicon oxide or silicon oxynitride can be used as the third insulating layer, an oxide containing one or both of aluminum and hafnium can be used as the first insulating layer, and silicon nitride can be used as the second insulating layer.

[0208] Here, when the insulating layer 250 has the above-described four-layer structure, the insulating layer 250a can have a three-layer stacked structure of a fourth insulating layer, a third insulating layer, and a first insulating layer, and the insulating layer 250b can use a second insulating layer. Alternatively, the insulating layer 250a can have a two-layer stacked structure of a fourth insulating layer and a third insulating layer, and the insulating layer 250b can have a two-layer stacked structure of a first insulating layer and a second insulating layer. Alternatively, the insulating layer 250a can use a fourth insulating layer, and the insulating layer 250b can have a three-layer stacked structure of a third insulating layer, a first insulating layer, and a second insulating layer.

[0209] In particular, the thickness of the region in the insulating layer 250 that overlaps with the channel formation region of the oxide semiconductor layer 230 is preferably 0.1 nm or more and 30 nm or less, more preferably 0.1 nm or more and 20 nm or less, even more preferably 0.1 nm or more and 10 nm or less, even more preferably 0.1 nm or more and 8.0 nm or less, and even more preferably 0.5 nm or more and 7.0 nm or less.

[0210] To achieve transistor miniaturization, the thickness of each layer constituting the insulating layer 250 is preferably thin. The thickness of each layer constituting the insulating layer 250 is, for example, 0.1 nm or more and 10 nm or less, 0.1 nm or more and 5 nm or less, 0.5 nm or more and 5 nm or less, 1 nm or more and less than 5 nm, or 1 nm or more and 3 nm or less. Note that at least a portion of each layer constituting the insulating layer 250 may be a region having the aforementioned thickness.

[0211] Typically, the thicknesses of the fourth, third, first, and second insulating layers are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. This structure allows for good electrical characteristics even when transistors are miniaturized or highly integrated.

[0212] Insulating layer 210 is used as an interlayer film, so its relative permittivity is preferably low. By using a material with a low relative permittivity as the interlayer film, parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are suitable for use as insulating layer 210 because they have thermal stability.

[0213] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced. This suppresses the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.

[0214] As the insulating layer 210, a hydrogen-blocking insulating layer is preferably used. By providing hydrogen-blocking properties for the insulating layer 210 disposed on the outside of the oxide semiconductor layer 230, hydrogen diffusion into the oxide semiconductor layer 230 can be suppressed.

[0215] In addition, materials that can be used as hydrogen barrier insulating layers include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon oxynitride.

[0216] For example, silicon nitride film is preferably used as insulating layer 210.

[0217] The insulating layer 210 may also have a two-layer stacked structure. For example, an insulating layer with the function of trapping or fixing hydrogen can be used as the upper layer of the insulating layer 210. Thus, hydrogen in the oxide semiconductor layer 230 diffuses through the conductive layer 220 to the upper layer of the insulating layer 210, and the hydrogen can be trapped or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0218] For example, it is preferable to use a silicon nitride film as the lower layer of the insulating layer 210 and an oxide film (hafnium silicate film) containing hafnium and silicon as the upper layer.

[0219] As one or more of insulating layers 283 and 285, a hydrogen-blocking insulating layer is preferably used. This can suppress the diffusion of hydrogen from above the insulating layer 283 into the oxide semiconductor layer 230. Since both silicon nitride film and silicon oxynitride film have the characteristics of low impurity release (e.g., water and hydrogen) and low permeability of oxygen and hydrogen, they are suitable for use in insulating layer 283.

[0220] Silicon nitride deposited by sputtering is particularly preferred as one or more of insulating layers 283 and 285. Because sputtering does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulating layer 283 can be reduced. By depositing insulating layer 283 by sputtering, a high-density silicon nitride can be formed.

[0221] Furthermore, one or more of insulating layers 283 and 285 may be used, and these insulating layers may have the function of trapping or fixing hydrogen. By employing this structure, the diffusion of hydrogen from above insulating layers 283 and 285 into the oxide semiconductor layer 230 can be suppressed, and the hydrogen contained in the oxide semiconductor layer 230 can be trapped or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. Hafnium silicate, etc., may be used as one or more of insulating layers 283 and 285.

[0222] Furthermore, the insulating layer 283 can also be a laminated structure of an insulating layer with the function of trapping or fixing hydrogen and a hydrogen-blocking insulating layer. For example, the insulating layer 283 can also be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.

[0223] Furthermore, the semiconductor device may also exclude either insulating layer 283 or insulating layer 285.

[0224] Furthermore, the insulating layer 285 can be made of a material with a low relative permittivity, for example. By using a material with a low relative permittivity for the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0225] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 285 is preferably reduced. This can suppress the mixing of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.

[0226] The insulating layer 280 is preferably the hydrogen-barrier insulating layer described above. The insulating layer 280 is disposed around the oxide semiconductor layer 230. By providing hydrogen barrier properties on the outer side of the oxide semiconductor layer 230, hydrogen diffusion into the oxide semiconductor layer 230 can be suppressed. For example, the insulating layer 280 preferably comprises a silicon nitride film.

[0227] Furthermore, silicon nitride also has oxygen-barrier properties. Therefore, by using silicon nitride in the insulating layer 280, the formation of excessive oxygen vacancies in the oxide semiconductor layer 230 due to oxygen detachment can be suppressed.

[0228] Furthermore, by using silicon nitride for the insulating layer 280, excess oxygen can be prevented from being supplied to the oxide semiconductor layer 230. Therefore, excess oxygen in the channel formation region of the oxide semiconductor layer 230 can be prevented, thus improving the reliability of the transistor 200.

[0229] Furthermore, the insulating layer 280 preferably includes the aforementioned oxide insulating film, oxynitride insulating film, or an insulating layer having a region containing excess oxygen.

[0230] For example, an insulating layer having regions containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. By using a sputtering method that does not require the use of hydrogen-containing molecules as a deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. Thus, by depositing at least a portion of the layer constituting the insulating layer 280, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0231] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced. This suppresses the incorporation of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor layer 230.

[0232] Note that the thickness of the insulating layer 280 on the conductive layer 220 corresponds to the channel length of the transistor 200, so the thickness of the insulating layer 280 is appropriately set according to the design value of the channel length of the transistor 200.

[0233] The insulating layer 280 preferably has a stacked structure having an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b.

[0234] The insulating layer 280b is in contact with the channel formation region of the oxide semiconductor layer 230. By using an oxygen-containing insulating layer as the insulating layer 280b, oxygen can be supplied to the oxide semiconductor layer 230.

[0235] The insulating layer 280b preferably has a region with a higher oxygen content compared to at least one of the insulating layers 280a and 280c. In particular, the insulating layer 280b preferably has a region with a higher oxygen content compared to each of the insulating layers 280a and 280c. By increasing the oxygen content of the insulating layer 280b, it is easier to form an i-type region in the oxide semiconductor layer 230 near the insulating layer 280b.

[0236] As the insulating layer 280b, a film that releases oxygen upon heating is more preferably used. Since oxygen is released from the insulating layer 280b by heating during the transistor 200 manufacturing process, oxygen can be supplied to the oxide semiconductor layer 230. By supplying oxygen from the insulating layer 280b to the oxide semiconductor layer 230, especially to the channel formation region of the oxide semiconductor layer 230, oxygen vacancies and Vo in the oxide semiconductor layer 230 can be reduced. O H can be used to realize transistors with good electrical characteristics and high reliability.

[0237] Furthermore, in order to improve the electrical characteristics and reliability of OS transistors, it is important to optimize the amount of oxygen supplied to the oxide semiconductor while sufficiently reducing the hydrogen concentration in the oxide semiconductor.

[0238] As an example, the amount of oxygen molecules released from the insulating layer 280b is preferably 1.0 × 10⁻⁶. 14 molecules / cm 2 Above and less than 1.0 × 10 15 molecules / cm 2 Note that the amount of oxygen molecules released can also be measured using thermal desorption spectroscopy.

[0239] In particular, when the channel length of transistor 200 is short, the oxygen vacancies and V in the channel formation region... O Hydrogen (H) has a particularly significant impact on electrical characteristics and reliability. Therefore, by optimizing the amount of oxygen supplied to the oxide semiconductor layer 230 while sufficiently reducing the hydrogen concentration in the oxide semiconductor layer 230, a short-channel length transistor with good electrical characteristics and high reliability can be realized.

[0240] The insulating layer 280b is preferably formed using a deposition method such as sputtering or PECVD. In particular, when using sputtering, hydrogen gas is not required as the deposition gas, thereby achieving a film with extremely low hydrogen content. Therefore, hydrogen supply to the oxide semiconductor layer 230 can be suppressed, thereby stabilizing the electrical characteristics of the transistor 200.

[0241] To increase the amount of oxygen supplied to the oxide semiconductor layer 230, it is preferable, for example, to perform heat treatment or plasma treatment in an oxygen-containing atmosphere after the formation of the insulating layer 280b. Alternatively, an oxide film can be deposited on the top surface of the insulating layer 280b using a sputtering method in an oxygen atmosphere to supply oxygen. This oxide film can then be removed. By performing this treatment, oxygen can be supplied to the insulating layer 280b, thereby increasing the amount of oxygen supplied to the oxide semiconductor layer 230.

[0242] Furthermore, in the oxide semiconductor layer 230, the oxygen supply to the regions contacting the insulating layers 280a and 280c is smaller compared to the region contacting the insulating layer 280b. Therefore, the regions of the oxide semiconductor layer 230 contacting the insulating layers 280a and 280c are sometimes made to have low resistance. In other words, by adjusting the thickness of the insulating layer 280a, the range of the region used as one of the source and drain regions can be controlled. Similarly, by adjusting the thickness of the insulating layer 280c, the range of the other region used as the source and drain regions can be controlled. Thus, the thicknesses of the insulating layers 280a and 280c can be appropriately set according to the required characteristics of the transistor.

[0243] Furthermore, a material with a low relative permittivity is preferably used as the insulating layer 280b. This reduces parasitic capacitance generated between wirings. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280b.

[0244] Oxygen-barrier insulating layers are preferably used as insulating layers 280a and 280c. By providing insulating layer 280a between insulating layer 280b and conductive layer 220, the increase in resistance of conductive layer 220 due to oxidation of conductive layer 220 can be suppressed. Furthermore, by providing insulating layer 280c between insulating layer 280b and conductive layer 240, the increase in resistance of conductive layer 240 due to oxidation of conductive layer 240 can be suppressed.

[0245] Furthermore, an insulating layer with hydrogen trapping or fixing function can be used as insulating layer 280a. By employing this structure, hydrogen diffusion from below insulating layer 280a to oxide semiconductor layer 230 can be suppressed, and hydrogen contained in oxide semiconductor layer 230 can be trapped or fixed. Therefore, the hydrogen concentration in oxide semiconductor layer 230 can be reduced. Magnesium oxide, aluminum oxide, hafnium oxide, or oxides containing hafnium and silicon can be used as insulating layer 280a. Furthermore, for example, a laminate of aluminum oxide and silicon nitride on the aluminum oxide can be used as insulating layer 280a. Similarly, an insulating layer with hydrogen trapping or fixing function can be used as insulating layer 280c.

[0246] For example, silicon nitride can be used for insulating layers 280a and 280c, and silicon oxide can be used for insulating layer 280b.

[0247] [Conductive layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, etc.) included in the semiconductor device are preferably made of metal elements selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., alloys containing the above-mentioned metal elements, or alloys combining the above-mentioned metal elements. As alloys containing the above-mentioned metal elements, nitrides or oxides of the alloys may also be used. For example, tantalum nitride, titanium nitride, ruthenium nitride, nitrides containing molybdenum, nitrides containing tungsten, titanium, and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc., are preferred. Furthermore, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides may also be used.

[0248] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, as well as conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metallic elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are not easily oxidized, have the function of inhibiting oxygen diffusion, or maintain conductivity even when absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, indium tin oxide with added silicon (also known as ITSO), indium zinc oxide (also known as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification, conductive films deposited using oxygen-containing conductive materials are sometimes referred to as oxide conductive films.

[0249] Conductive materials with tungsten, copper, or aluminum as the main components have high conductivity and are therefore preferred.

[0250] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0251] Furthermore, when using metal oxides in the channel formation region of a transistor, the conductive layer used as the gate electrode preferably employs a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material. In this case, it is preferable to provide the oxygen-containing conductive material on one side of the channel formation region. By providing the oxygen-containing conductive material on one side of the channel formation region, oxygen detached from this conductive material can be easily supplied to the channel formation region.

[0252] The conductive layer 260 can be made of the aforementioned metal elements, alloys composed of the aforementioned metal elements, or alloys combining the aforementioned metal elements. For example, materials with high conductivity, such as tungsten, are preferred. Furthermore, the conductive layer 260 is preferably made of a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion. As mentioned above, examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. This helps to suppress the decrease in conductivity of the conductive layer 260.

[0253] The conductive layer 260 preferably uses a conductive material containing the metal element and oxygen contained in the metal oxide forming the channel. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can also be used. Furthermore, indium gallium zinc oxide containing nitrogen can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Alternatively, hydrogen mixed in from an external insulating layer or the like can sometimes be trapped.

[0254] The conductive layer 260 can be, for example, 3 nm or more and 500 nm or less. The thickness of the conductive layer 260 can be, for example, more than the thickness of the insulating layer 250. By increasing the thickness of the conductive layer 260, the resistance of the conductive layer 260 can be reduced.

[0255] Furthermore, the conductive layer 260 preferably adopts a two-layer structure of conductive layer 260a and conductive layer 260b on conductive layer 260a.

[0256] By using a conductive material that has the function of suppressing oxygen diffusion as the conductive layer 260a, for example, the release of oxygen from the oxide semiconductor layer 230 can be suppressed, thereby suppressing the formation of oxygen vacancies in the oxide semiconductor layer 230.

[0257] Furthermore, by using a conductive material that is not easily oxidized as the conductive layer 260a, the decrease in conductivity caused by oxidation of the conductive layer 260a due to oxygen release from the oxide semiconductor layer 230 or from the insulating layer 250 can be suppressed.

[0258] The material used for conductive layer 260b preferably has higher conductivity than the material used for conductive layer 260a. Furthermore, by increasing the thickness of conductive layer 260b, the current flowing through conductive layer 260b can be further increased.

[0259] By using a deposition method with high coverage as conductive layer 260a, conductive layer 260a can be appropriately formed along the sidewall of opening 290.

[0260] As the conductive layer 260a, for example, a conductive material containing nitrogen or a conductive material containing oxygen can be used. Furthermore, as the conductive layer 260a, for example, a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed can be used.

[0261] As the conductive layer 260a, a conductive material containing the aforementioned metal elements and nitrogen can be used, such as tantalum nitride, titanium nitride, ruthenium nitride, nitride containing molybdenum, nitride containing tungsten, titanium and aluminum, nitride containing tantalum and aluminum, etc.

[0262] Furthermore, as the conductive layer 260a, a conductive material containing the aforementioned metal elements and oxygen can be used, such as ruthenium oxide, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc.

[0263] Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may be used. Additionally, indium gallium zinc oxide containing nitrogen may also be used.

[0264] As the conductive layer 260a, titanium, tantalum, ruthenium, and materials containing one or more of these metallic elements are preferred because they are conductive materials that are not easily oxidized, conductive materials that have the function of inhibiting oxygen diffusion, or materials that can maintain conductivity even when absorbing oxygen.

[0265] As the conductive layer 260b, for example, the aforementioned metal element, an alloy containing the aforementioned metal element, or an alloy combining the aforementioned metal elements can be used. For example, tungsten can be used.

[0266] Furthermore, conductive layer 260a may also have a stacked structure. Furthermore, conductive layer 260b may also have a stacked structure. When conductive layer 260a has a stacked structure, for example, multiple materials suitable for conductive layer 260a can be stacked. Alternatively, multiple materials selected from those suitable for a conductive layer in one aspect of the present invention can be stacked. When conductive layer 260b has a stacked structure, for example, multiple materials suitable for use as conductive layer 260b can be stacked. Alternatively, multiple materials selected from those suitable for a conductive layer in one aspect of the present invention can be stacked.

[0267] Conductive layers 220 and 240 are conductive layers in contact with the oxide semiconductor layer 230. Therefore, conductive materials that are not easily oxidized, conductive materials that maintain low resistance even when oxidized, oxide conductive materials, or conductive materials that have the function of inhibiting oxygen diffusion are preferably used. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. As a result, the decrease in conductivity of conductive layers 220 and 240 can be suppressed.

[0268] By using an oxygen-containing conductive material as conductive layer 220 or conductive layer 240, conductivity can be maintained even if conductive layer 220 or conductive layer 240 absorbs oxygen. Furthermore, when an oxygen-containing insulating layer such as hafnium oxide is used as insulating layer 210, conductive layer 220 can also maintain conductivity, which is therefore preferred. For example, ITO, ITSO, and IZO (registered trademark) are preferred as conductive layers 220 and 240.

[0269] When the conductive layer 220 adopts a three-layer structure in which a first conductive layer (e.g., conductive layer 220a), a second conductive layer (e.g., conductive layer 220b), and a third conductive layer (e.g., conductive layer 220c) are sequentially stacked on the insulating layer 210, it is preferable, for example, to use a non-oxidizable conductive material or a conductive material with the function of inhibiting oxygen diffusion as the first conductive layer, to use a highly conductive material as the second conductive layer, and to use an oxygen-containing conductive material as the third conductive layer. Specifically, for example, it is preferable to use titanium nitride as the first conductive layer, tungsten as the second conductive layer, and ITO or ITSO as the third conductive layer. In this case, titanium nitride is in contact with the insulating layer 210, and ITO or ITSO is in contact with the oxide semiconductor layer 230. By adopting this structure, conductivity can be maintained even when the conductive layer 220 is in contact with the oxide semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 due to the insulating layer 210 can be suppressed. Furthermore, by using tungsten, which has high conductivity, as the second conductive layer, the conductivity of the conductive layer 220 can be improved.

[0270] Furthermore, when the conductive layer 240 has a two-layer stacked structure (e.g., conductive layer 240a and conductive layer 240b), it is preferable, for example, to use a material with higher conductivity than the upper layer as the lower layer, and to use an oxygen-containing conductive material as the upper layer. Specifically, for example, it is preferable to use ruthenium, tungsten, titanium nitride, or tantalum nitride as the lower layer, and ITO or ITSO as the upper layer. In this case, ITO or ITSO is in contact with the oxide semiconductor layer 230. By adopting this structure, conductivity can be maintained even when the conductive layer 240 is in contact with the oxide semiconductor layer 230. In addition, by using a material with higher conductivity than the upper layer as the lower layer, the conductivity of the conductive layer 240 can be improved.

[0271] Furthermore, when the conductive layer 240 employs a two-layer stacked structure, a highly conductive material can be used as the upper layer (e.g., conductive layer 240b), and an oxygen-containing conductive material can be used as the lower layer (e.g., conductive layer 240a). In this case, for example... Figures 9A to 9C As shown, by adopting a structure in which the top surface of the oxide semiconductor layer 230 contacts the conductive layer 240a, the contact resistance between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0272] [Oxide semiconductor layer 230] As described above, the oxide semiconductor layer 230 has a channel formation region. This channel formation region is i-type (intrinsic) or substantially i-type. The oxide semiconductor layer 230 also has a source region and a drain region. This source region and the drain region are n-type regions (low-resistance regions) with higher carrier concentrations compared to the channel formation region.

[0273] There are no particular restrictions on the crystallinity of the semiconductor material used for the oxide semiconductor layer 230; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with a portion of crystalline regions) can be used. When using single-crystal semiconductors or crystalline semiconductors, the degradation of transistor characteristics can be suppressed, so they are preferred.

[0274] The bandgap of the metal oxide used as the semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider bandgap, the off-state current of the transistor can be reduced. The off-state current of the OS transistor is small, thus significantly reducing the power consumption of the semiconductor device. Furthermore, the OS transistor has high frequency characteristics, enabling the semiconductor device to operate at high speeds.

[0275] Examples of metal oxides that can be used in the oxide semiconductor layer 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Note that element M is a metallic or semi-metallic element with a high bonding energy with oxygen, for example, a metallic or semi-metallic element with a higher bonding energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. Note that in this specification, metallic and semi-metallic elements are sometimes collectively referred to as "metallic elements," and the term "metallic element" sometimes includes semi-metallic elements.

[0276] The oxide semiconductor layer 230 may use, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also known as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), aluminum zinc oxide (Al-Zn oxide, also known as... Indium aluminum zinc oxide (In-Al-Zn oxide, also known as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also known as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also known as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also known as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also known as IGAZO, IGZAO, or IAGZO), etc. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used. Alternatively, the above-mentioned oxides having an amorphous structure can be used. For example, indium oxide or indium tin oxide having an amorphous structure can be used.

[0277] The field-effect mobility of a transistor can be improved by increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements in the metal oxide. Furthermore, transistors with high on-state currents can be realized.

[0278] Note that metal oxides can also replace indium or contain one or more metals with high period numbers in addition to indium. There is a tendency that the greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0279] Metal oxides can also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved due to increased carrier concentration or narrower band gap. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0280] Furthermore, by increasing the ratio of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. As a result, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0281] Furthermore, by increasing the ratio of the number of atoms of element M to the total number of atoms of all metal elements in the metal oxide, a metal oxide with a wider band gap can be obtained. Additionally, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, thereby enabling transistors with low off-state currents. Furthermore, threshold voltage drift of the transistor can be suppressed. Moreover, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0282] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the oxide semiconductor layer 230. Therefore, by varying the composition of the metal oxide to correspond to the required electrical characteristics and reliability of the transistor, a semiconductor device with both excellent electrical characteristics and high reliability can be realized.

[0283] When the metal oxide is an In-M-Zn oxide, the ratio of the number of In atoms in the In-M-Zn oxide is preferably greater than or equal to the ratio of the number of M atoms. Examples of the atomic ratios of the metal elements in this In-M-Zn oxide include In:M:Zn = 1:1:0.5, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 1:1:2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, and compositions in their vicinity. Furthermore, the surrounding composition includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current or field-effect mobility of transistors can be improved.

[0284] In In-M-Zn oxides, the atomic ratio of In can also be less than that of M. Examples of such metallic atomic ratios in In-M-Zn oxides include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, and compositions close to these ratios. Increasing the proportion of M atoms in the metal oxide can suppress the formation of oxygen vacancies.

[0285] Note that when element M contains multiple metallic elements, the total proportion of the number of atoms of each metallic element can be the proportion of the number of atoms of element M.

[0286] In this specification, the proportion of indium atoms relative to the total number of atoms of all metallic elements contained herein is sometimes stated as the indium content. The same applies to other metallic elements.

[0287] Furthermore, when the metal oxide is an In-Zn oxide, examples of the atomic ratio of the metal element in the In-Zn oxide include In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, and compositions close to these ratios. In addition, In-Zn oxides may also contain trace amounts of element M. For example, when Sn is included as element M, examples of the atomic ratio of the metal element in the metal oxide include In:Sn:Zn = 2:0.1:1, In:Sn:Zn = 4:0.1:1, and compositions close to these ratios.

[0288] For analyzing the composition of the metal oxide used in the oxide semiconductor layer 230, methods such as energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, multiple methods can be combined. Note that the actual content of elements with low concentrations may differ from the analytically obtained content due to the limitations of analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content. Furthermore, it can sometimes be difficult to quantify element M or to detect element M at all.

[0289] Metal oxides can be formed appropriately using sputtering or ALD methods. Note that when metal oxides are formed using sputtering, the composition of the deposited metal oxide sometimes differs from that of the target material. In particular, the zinc content in the deposited metal oxide can sometimes be reduced to about 50% of the zinc content in the target material. Furthermore, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), and pulsed laser deposition (PLD) methods can also be used when depositing metal oxides.

[0290] The oxide semiconductor layer 230 may also have a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers comprising the oxide semiconductor layer 230 may also be the same or substantially the same. By employing a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thus reducing manufacturing costs.

[0291] The compositions of the two or more metal oxide layers included in the oxide semiconductor layer 230 may also be different.

[0292] The oxide semiconductor layer 230 may have a two-layer structure (e.g., a two-layer structure of oxide layer 230a and oxide layer 230b on oxide layer 230a).

[0293] For example, oxide layer 230a is preferably made of a material with higher conductivity than oxide layer 230b. By using a material with high conductivity for oxide layer 230a, which contacts the source electrode and the drain electrode (conductive layer 220 and conductive layer 240), the contact resistance between oxide semiconductor layer 230 and conductive layer 220 and between oxide semiconductor layer 230 and conductive layer 240 can be reduced, thereby enabling transistors with high on-state current.

[0294] Here, when a material with high conductivity is used in the oxide layer 230b disposed on the side of the conductive layer 260 used as the gate electrode, it sometimes causes a drift in the threshold voltage of the transistor 200, thereby increasing the drain current (hereinafter also referred to as the cutoff current) flowing when the gate voltage is 0V. Specifically, when the transistor 200 is an n-channel transistor, the threshold voltage sometimes decreases. Therefore, it is preferable to use a material with lower conductivity than the oxide layer 230a for the oxide layer 230b. As a result, when the transistor 200 is an n-channel transistor, the threshold voltage can be increased, and a transistor with a small cutoff current can be realized. Note that the state with a small cutoff current is sometimes referred to as normally off.

[0295] By having the oxide semiconductor layer 230 have a stacked structure as described above and using a material with higher conductivity than oxide layer 230b for oxide layer 230a, a transistor with normally off operation and high on-state current can be realized. Thus, a semiconductor device that combines low power consumption and high performance can be realized.

[0296] Furthermore, the carrier concentration of oxide layer 230a is preferably higher than that of oxide layer 230b. By increasing the carrier concentration of oxide layer 230a, the conductivity increases, which reduces the contact resistance between oxide semiconductor layer 230 and conductive layer 220, as well as the contact resistance between oxide semiconductor layer 230 and conductive layer 240, thereby enabling a transistor with a large on-state current. Conversely, by decreasing the carrier concentration of oxide layer 230b, the conductivity decreases, thereby enabling a normally off transistor.

[0297] Note that the oxide semiconductor layer 230 is not limited to the structure described above; the oxide layer 230a can also be made of a material with a lower conductivity than the oxide layer 230b. Furthermore, the carrier concentration of the oxide layer 230a can also be lower than that of the oxide layer 230b.

[0298] Furthermore, the band gap of the first metal oxide used in oxide layer 230a is preferably different from the band gap of the second metal oxide used in oxide layer 230b. For example, the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.

[0299] The band gap of the first metal oxide used for oxide layer 230a is preferably smaller than that of the second metal oxide used for oxide layer 230b. This reduces the contact resistance between oxide semiconductor layer 230 and conductive layer 220, as well as between oxide semiconductor layer 230 and conductive layer 240, thereby enabling a transistor with a large on-state current. Furthermore, when transistor 200 is an n-channel transistor, the threshold voltage can be increased, thereby enabling a normally-off transistor. Moreover, due to the large band gap of the second metal oxide, the generation and induction of charge carriers in oxide layer 230b and at the interface between oxide layer 230b and insulating layer 250 can be suppressed. This improves the reliability of the transistor.

[0300] For example, the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide. More specifically, it is preferable, for example, to use a metal oxide with an In:M:Zn ratio of 1:1:1 or similar as oxide layer 230a, and to use a metal oxide with an In:M:Zn ratio of 1:3:2 or similar as oxide layer 230b. In this case, one or more of gallium, aluminum, and tin are particularly preferred as element M.

[0301] Note that the oxide semiconductor layer 230 is not limited to the structure described above, and the band gap of the first metal oxide can also be larger than that of the second metal oxide.

[0302] Furthermore, the content of element M in the first metal oxide is preferably lower than that in the second metal oxide. The first metal oxide may also contain trace amounts of element M or may not contain element M at all. For example, the first metal oxide used for oxide layer 230a is preferably an In-Zn oxide, and the second metal oxide used for oxide layer 230b is preferably an In-M-Zn oxide. Specifically, the first metal oxide may be an In-Zn oxide, and the second metal oxide may be an In-Ga-Zn oxide.

[0303] For example, as oxide layer 230a, metal oxides with an In:Zn ratio of 1:1 or similar, In:Zn ratio of 2:1 or similar, In:Sn:Zn ratio of 2:0.1:1 or similar, In:Zn ratio of 4:1 or similar, In:Sn:Zn ratio of 4:0.1:1 or similar, or indium oxide are preferred. Furthermore, as oxide layer 230b, metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, In:Ga:Zn ratio of 1:3:2 or similar, or In:Ga:Zn ratio of 1:3:4 or similar are preferred. This increases the on-state current of transistor 200, thus enabling a transistor structure with less non-uniformity and higher reliability.

[0304] The oxide semiconductor layer 230 is not limited to the above structure, and the content of element M in the first metal oxide can also be higher than the content of element M in the second metal oxide.

[0305] The oxide semiconductor layer 230 preferably comprises a crystalline metal oxide layer. Examples of crystalline metal oxide structures include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nanocrystalline structure. By using a crystalline metal oxide layer in the oxide semiconductor layer 230, the defect state density in the oxide semiconductor layer 230 can be reduced, thereby enabling a highly reliable semiconductor device. Note that a CAAC structure is a crystal structure in which multiple microcrystals (typically, multiple IGZO microcrystals) have a c-axis orientation and are connected on the ab plane in a manner where the multiple microcrystals are not oriented as described above. Compared to a polycrystalline structure, no distinct grain boundaries are observed on the ab plane in the CAAC structure, thus enabling a highly reliable semiconductor device.

[0306] The higher the crystallinity of the metal oxide layer used for the oxide semiconductor layer 230, the lower the defect state density in the oxide semiconductor layer 230 can be. On the other hand, by using a metal oxide layer with low crystallinity, transistors capable of carrying large currents can be realized.

[0307] The higher the substrate temperature (stage temperature) during the formation of the metal oxide layer, the more crystalline the metal oxide layer can be formed. In addition, the higher the oxygen flow rate ratio relative to the overall deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), the more crystalline the metal oxide layer can be formed.

[0308] The crystallinity of the oxide semiconductor layer 230 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of the above methods can be used for analysis.

[0309] The oxide semiconductor layer 230 may also have a stacked structure of two or more metal oxide layers with different crystallinity. For example, it may have a stacked structure of a first metal oxide layer and a second metal oxide layer disposed on the first metal oxide layer, wherein the second metal oxide layer may have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer may have a region with lower crystallinity than the first metal oxide layer. In this case, the compositions of the first metal oxide layer and the second metal oxide layer may be different, the same, or substantially the same.

[0310] For example, as oxide layer 230a, a metal oxide with an In:M:Zn ratio of 1:3:2 or similar, or an In:M:Zn ratio of 1:3:4 or similar, is preferably used. As oxide layer 230b, a metal oxide with an In:M:Zn ratio of 1:1:1 or similar, is preferably used. By using a metal oxide with a high Zn:In ratio as oxide layer 230a, the crystallinity of oxide layer 230a can be improved. Furthermore, by forming oxide layer 230b on the highly crystallinity oxide layer 230a, the crystallinity of oxide layer 230b is easily improved. Therefore, the overall crystallinity of oxide semiconductor layer 230 can be improved, which is preferred. In this case, gallium, aluminum, or tin is particularly preferred as element M. For example, two IGZOs with different compositions can also be stacked. For example, a stacked structure selected from any one of indium oxide, indium gallium oxide and IGZO and any one of IAZO, IAGZO and ITZO (registered trademarks) can also be used.

[0311] In addition, the oxide semiconductor layer 230 may also have a three-layer structure (e.g., a stacked structure of oxide layer 230c, oxide layer 230a on oxide layer 230c and oxide layer 230b on oxide layer 230a).

[0312] Oxide layer 230a and oxide layer 230b can adopt the structure described above. Oxide layer 230c can adopt the same structure as that used in oxide layer 230b.

[0313] For example, as oxide layer 230a, metal oxides with an In:Zn ratio of 1:1 or similar, In:Zn ratio of 2:1 or similar, In:Sn:Zn ratio of 2:0.1:1 or similar, In:Zn ratio of 4:1 or similar, In:Sn:Zn ratio of 4:0.1:1 or similar, or indium oxide are preferably used. Furthermore, as oxide layers 230b and 230c, metal oxides with an In:Ga:Zn ratio of 1:1:1 or similar, In:Ga:Zn ratio of 1:3:2 or similar, or In:Ga:Zn ratio of 1:3:4 or similar are preferably used.

[0314] Preferably, the band gaps of oxide layers 230b and 230c are both larger than the band gap of oxide layer 230a. Thus, oxide layer 230a is sandwiched between oxide layers 230b and 230c with larger band gaps, and oxide layer 230a is primarily used as the current path (channel). By sandwiching oxide layer 230a with oxide layers 230b and 230c, the trap levels at and near the interface of oxide layer 230a can be reduced. This allows for the realization of an embedded-channel transistor with the channel far from the insulating layer interface, thereby improving field-effect mobility. Furthermore, the influence of interface states that can form on the back channel side can be reduced to suppress transistor optical degradation (e.g., optical negative bias degradation), thereby improving transistor reliability.

[0315] The thickness of the oxide semiconductor layer 230 is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less. Furthermore, in transistors used in more miniaturized semiconductor devices, the thickness of the oxide semiconductor layer 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.

[0316] Furthermore, when depositing the oxide semiconductor layer, both sputtering and ALD deposition methods are preferred. For example, when forming a second oxide semiconductor using the ALD method after forming a first oxide semiconductor with a CAAC structure using sputtering, it is expected that the atomic layer of the second oxide semiconductor will fill or repair the voids in the atomic-level crystalline portions or the nanocrystal voids of the CAAC structure of the first oxide semiconductor. Additionally, a heat treatment (e.g., 100°C or higher and 500°C or lower, preferably 200°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower) can be performed after forming the second oxide semiconductor layer using the ALD method. Through this heat treatment, it is expected that the voids in the atomic-level crystalline portions of the CAAC structure of the first oxide semiconductor will be repaired by the second oxide semiconductor (in other words, by the individual crystalline molecules formed using the ALD method).

[0317] When an oxide semiconductor layer is formed using both sputtering and ALD methods, if the thickness of the oxide semiconductor layer formed by ALD is thin, it can be considered that the oxide semiconductor layer does not have a stacked structure of the oxide semiconductor layer formed by sputtering and the oxide semiconductor layer formed by ALD, but has a single-layer structure. For example, when the thickness of the oxide semiconductor layer formed by ALD exceeds 0 nm but is less than 3 nm, preferably more than 0 nm but less than 2 nm, and more preferably more than 0 nm but less than 1 nm, the oxide semiconductor layer formed by both sputtering and ALD deposition methods can be regarded as a single-layer structure. On the other hand, when the thickness of the oxide semiconductor layer formed by ALD exceeds 3 nm, it can sometimes be considered to have a stacked structure, a multilayer structure, or a multi-layer structure of the oxide semiconductor layer formed by sputtering and the oxide semiconductor layer formed by ALD.

[0318] The oxide semiconductor formed using the two deposition methods described above can be considered as a structure in which the gaps in the crystalline regions of a CAAC structure are filled by atomic layers formed using the ALD method. Furthermore, this structure can be analyzed using methods such as cross-sectional SEM, cross-sectional STEM, cross-sectional TEM, and EDX.

[0319] Furthermore, compared to oxide semiconductor layers with a CAAC structure formed using only one deposition method, oxide semiconductor layers with a CAAC structure formed using both deposition methods sometimes exhibit higher relative permittivity, film density, and film hardness. Thus, by using oxide semiconductor layers with a CAAC structure formed using both deposition methods in the channel formation region of transistors, transistors with excellent characteristics can be realized (e.g., transistors with high on-state current, high field-effect mobility, low S-value, high frequency characteristics (also known as f-characteristics), high reliability, etc.).

[0320] Sometimes, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to metal atoms to form water, thus creating oxygen vacancies (V0) in the oxide semiconductor film. O Furthermore, sometimes hydrogen enters the defects in oxygen vacancies (hereinafter referred to as V). O H is used as a donor to generate electrons as charge carriers. Additionally, sometimes electrons are generated as charge carriers due to the bonding of a portion of the hydrogen with oxygen atoms bonded to metal atoms. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have always-on characteristics (i.e., a negative threshold voltage). Furthermore, because hydrogen in oxide semiconductors is easily mobile due to heat, electric fields, etc., a large amount of hydrogen in the oxide semiconductor may lead to a decrease in transistor reliability.

[0321] In other words, it is preferable to minimize the V in the oxide semiconductor layer 230. O H is used to make the oxide semiconductor layer 230 a high-purity intrinsic or substantially high-purity intrinsic. To obtain this V... O For oxide semiconductors with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen from the oxide semiconductor (sometimes described as dehydration or dehydrogenation treatment); and repair oxygen vacancies by supplying oxygen to the oxide semiconductor. This is achieved by... O When oxide semiconductors with sufficiently reduced impurities such as hydrogen are used in the channel formation region of transistors, they can impart stable electrical characteristics. Note that the process of supplying oxygen to oxide semiconductors to repair oxygen vacancies is sometimes referred to as oxidation treatment.

[0322] The carrier concentration of the oxide semiconductor used as the channel formation region is preferably 1 × 10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 More preferably, less than 1×10 16 cm -3 Further optimization of less than 1×10 13 cm -3 More preferably, less than 1×10 12cm -3 Note that there is no specific limit to the lower limit of the carrier concentration of the oxide semiconductor in the region used as the channel formation region; for example, it can be set to 1 × 10⁻⁶. -9 cm -3 .

[0323] Here, we will explain the effects of various impurities in metal oxides (oxide semiconductors).

[0324] When an oxide semiconductor contains silicon or carbon, one of Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 Below. Furthermore, the silicon concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 The following is more preferably 3×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 3×10 18 atoms / cm 3 Hereinafter, 1×10 is further preferred. 18 atoms / cm 3 the following.

[0325] Furthermore, when nitrogen is included in oxide semiconductors, electrons are generated as charge carriers, increasing the charge carrier concentration and making them more susceptible to n-type conversion. As a result, transistors using nitrogen-containing oxide semiconductors tend to exhibit always-on characteristics. Alternatively, when nitrogen is included in oxide semiconductors, trapped states can sometimes form. Consequently, the electrical characteristics of the transistor can sometimes be unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor, measured using SIMS, is set to 1 × 10⁻⁶.20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is more preferably 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0326] Furthermore, hydrogen contained in oxide semiconductors reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons are sometimes generated as charge carriers. Additionally, sometimes a portion of the hydrogen bonds with oxygen bonded to metal atoms, generating electrons as charge carriers. Therefore, transistors using hydrogen-containing oxide semiconductors tend to have always-on characteristics. Thus, it is preferable to minimize the amount of hydrogen in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor, as measured using SIMS, is set to be less than 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 5×10 19 atoms / cm 3 More preferably less than 1×10 19 atoms / cm 3 More preferably less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3 .

[0327] Furthermore, when oxide semiconductors contain alkali metals or alkaline earth metals, defect states are sometimes formed, generating charge carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit always-on characteristics. Consequently, the concentration of alkali metals or alkaline earth metals in the channel formation region of the oxide semiconductor, as measured by SIMS, is set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0328] By using oxide semiconductors with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0329] Furthermore, transistors using other semiconductor materials in the channel formation region can also be used in the semiconductor device of this embodiment. Examples of such other semiconductor materials include semiconductors or compound semiconductors composed of a single element. Examples of semiconductors composed of a single element include silicon or germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. Additionally, examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may also contain impurities as dopants.

[0330] Silicon, as a semiconductor material that can be used as a transistor, can be categorized into monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. For example, low-temperature polycrystalline silicon (LTPS) can be cited as a polycrystalline silicon.

[0331] Furthermore, the semiconductor layer of a transistor can also contain layered materials used as semiconductors. Layered materials are a general term for a group of materials with layered crystal structures. A layered crystal structure is a structure formed by layers of covalent or ionic bonds stacked together by bonds weaker than covalent and ionic bonds, such as van der Waals forces. Layered materials exhibit high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material with high two-dimensional conductivity, which serves as a semiconductor, in the channel formation region, transistors with large on-state currents can be provided.

[0332] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (belonging to Group 16 elements). Furthermore, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0333] [Substrate] Substrates for forming transistors can be, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium-stabilized zirconium oxide substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon on Insulator) substrates, can also be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components mounted on a substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements.

[0334] <Examples of Semiconductor Device Manufacturing Methods> Reference Figures 15A to 16B This describes a method for manufacturing semiconductor devices. Here, as an example, it is illustrated... Figure 4B The manufacturing method of the structure shown. Note that, regarding the materials and forming methods of each component, the same parts as those already described are sometimes omitted.

[0335] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, CVD, vacuum evaporation, PLD, ALD, and other methods.

[0336] Examples of sputtering methods include RF sputtering, which uses a high-frequency power supply, DC sputtering, which uses a DC power supply, and pulsed DC sputtering, which changes the voltage applied to the electrodes in a pulsed manner. Additionally, there is RF-DC sputtering, which combines RF and DC sputtering. RF sputtering is preferred for deposition using insulating targets. DC sputtering is primarily used when depositing with conductive targets. Furthermore, in DC sputtering, in addition to forming conductive films, insulating films can also be formed through reactive sputtering. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-DC sputtering allows for control of ion energy during deposition and the potential on one side of the target. Therefore, compared to RF sputtering, deposition-related damage can be reduced. Furthermore, films of high quality can be obtained.

[0337] As sputtering methods, ionization sputtering and long-range ballistic sputtering can be used, for example. Ionization sputtering involves ionizing sputtered particles generated from a target using RF or similar methods, and then depositing them anisotropically using a self-bias voltage or similar method. Furthermore, in long-range ballistic sputtering, anisotropic deposition can be achieved by increasing the distance between the sputtering target and the substrate.

[0338] Note that CVD methods can be categorized into PECVD, thermal CVD (TCVD), and photoCVD. Furthermore, they can be classified based on the source gas used, such as metal CVD (MCVD) and metal-organic CVD (MOCVD).

[0339] By utilizing the PECVD method, high-quality films can be obtained at relatively low temperatures. Furthermore, because it does not use plasma, thermal CVD is a deposition method that reduces plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) included in semiconductor devices sometimes accumulate charge due to receiving charge from plasma. This accumulated charge can sometimes damage the wiring, electrodes, and components in the semiconductor device. On the other hand, because thermal CVD does not produce this plasma damage, the yield of semiconductor devices can be improved. Moreover, since no plasma damage occurs during deposition in thermal CVD, films with fewer defects can be obtained.

[0340] As ALD methods, there are thermal ALD (thermal ALD) methods that use only thermal energy to cause the precursors and reactants to react, and PEALD (Plasma Enhanced ALD) methods that use reactants excited by plasma.

[0341] Alternating current deposition (ALD) can deposit atoms in each layer, thus offering advantages such as the ability to deposit extremely thin films, deposit structures with high aspect ratios, deposit with fewer defects such as pinholes, achieve excellent coverage, and deposit at low temperatures. In the Plasma Enhanced Alternating Current deposition (PEALD), the use of plasma allows for film formation at even lower temperatures, making it sometimes preferred. The precursors used in ALD sometimes contain impurities such as carbon. Therefore, films formed using ALD sometimes contain more impurities such as carbon compared to films formed using other deposition methods. Furthermore, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0342] Unlike deposition methods that use particles released from a target, CVD and ALD are deposition methods that form films due to reactions on the surface of the workpiece. Therefore, CVD and ALD are deposition methods that are less affected by the shape of the workpiece and offer high step coverage. In particular, ALD exhibits good step coverage and thickness uniformity, making it suitable for forming films covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other deposition methods, such as CVD, which has a faster deposition rate.

[0343] CVD or ALD methods allow control of the film composition by adjusting the source gas flow rate ratio. For example, when using CVD and ALD, films of arbitrary composition can be deposited based on the source gas flow rate ratio. Furthermore, for example, when using CVD or ALD, films with continuously varying compositions can be formed by changing the source gas flow rate ratio during deposition. When deposition is performed while changing the source gas flow rate ratio, the deposition time can be shortened compared to deposition using multiple chambers because the time required for transmission and pressure adjustment is eliminated. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0344] Furthermore, when using CVD, films of arbitrary composition can be deposited based on the source gas flow rate ratio. For example, when using CVD, films with continuously varying compositions can be deposited by changing the source gas flow rate ratio during deposition. When deposition is performed while changing the source gas flow rate ratio, the deposition time can be shortened compared to using multiple deposition chambers because the time required for transfer or pressure adjustment is eliminated. Therefore, this can sometimes improve the productivity of semiconductor devices.

[0345] When using the ALD method, membranes of arbitrary composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, by controlling the number of cycles for each precursor while introducing multiple different precursors, membranes of arbitrary composition can be deposited.

[0346] Thin films (insulating films, semiconductor films, and conductive films, etc.) constituting semiconductor devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0347] Furthermore, when processing thin films constituting semiconductor devices, photolithography or similar methods can be used. Alternatively, nanoimprinting, sandblasting, or lift-off methods can be employed to process the thin films. Additionally, island-shaped thin films can be directly formed using deposition methods that utilize metal masks or similar masking techniques.

[0348] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, then processing the film through etching or similar means, and finally removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to shape the film into the desired form.

[0349] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these rays. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can also be used. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams allow for extremely fine processing and are therefore preferred. Note that when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0350] As a method for etching thin films, dry etching, wet etching, and sandblasting can be used.

[0351] First, a conductive layer 220 is formed on the insulating layer 210, an insulating layer 280 is formed on the conductive layer 220, and a conductive layer 240 is formed on the insulating layer 280. Here, the insulating layer 280 has a three-layer stacked structure of insulating layer 280a, insulating layer 280b, and insulating layer 280c.

[0352] Note that it is preferable to perform a planarization process using Chemical Mechanical Polishing (CMP) after depositing the insulating layer 280 to planarize the top surface of the insulating layer 280. By performing the planarization process on the insulating layer 280, the surface on which the conductive layer 240 is formed for wiring can be flattened, thereby suppressing the breakage of the conductive layer 240. Alternatively, the planarization process can be omitted, which can reduce manufacturing costs.

[0353] Next, an opening 290 is formed at the position where the conductive layer 240 and the insulating layer 280 overlap with the conductive layer 220. Figure 15A ).

[0354] Because of the high aspect ratio of the opening 290, it is preferable to use anisotropic etching to process a portion of the conductive layer 240 and a portion of the insulating layer 280. In particular, dry etching is suitable for microfabrication and is therefore preferred. Furthermore, this processing can be performed under different conditions depending on the layers.

[0355] Here, it is preferable to use processing conditions that give the sidewalls of the conductive layer 240 and the insulating layer 280c a tapered shape. Furthermore, it is preferable to use processing conditions that give the sidewalls of the insulating layer 280b a steep shape.

[0356] The insulating layer 280a can be formed using either processing conditions with tapered sidewalls or processing conditions with steep sidewalls.

[0357] Here, by appropriately selecting and changing the materials of insulating layer 280c and insulating layer 280b, the same dry etching conditions can be used to make insulating layer 280c have a conical shape and insulating layer 280b have a steep shape.

[0358] Next, a heat treatment may be performed. For example, the heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower.

[0359] Furthermore, the heat treatment is performed in an atmosphere of nitrogen or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen and oxygen gas, the ratio of oxygen gas is preferably set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, in order to replenish the detached oxygen, the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By performing the above-described heat treatment, impurities such as water contained in the insulating layer 280, etc., can be reduced before the deposition of the oxide semiconductor layer 230, which will be described later.

[0360] Furthermore, the gas used in the above-described heat treatment is preferably of high purity. For example, the water content of the gas used in the above-described heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the insulating layer 280 can be prevented as much as possible.

[0361] The conductive layer 240 and the insulating layer 280 can be formed using either the same mask or different masks.

[0362] Next, an oxide semiconductor layer 230 is formed to cover the opening 290. The oxide semiconductor layer 230 is formed in contact with the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the top and side surfaces of the conductive layer 240.

[0363] The oxide semiconductor layer 230 can be deposited, for example, by sputtering, CVD, MBE, PLD or ALD.

[0364] The oxide semiconductor layer 230 is preferably formed within the opening 290 along the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the side surface of the conductive layer 240, forming a film with the most uniform thickness possible. Thinner films can be deposited with high control by using the ALD method. Therefore, the oxide semiconductor layer 230 is preferably deposited using the ALD method.

[0365] Furthermore, when the oxide semiconductor layer 230 has high crystallinity, the diffusion of impurities in the oxide semiconductor layer 230 is suppressed, thus the electrical characteristics of the transistor are less likely to change, thereby improving reliability. Depositing the oxide semiconductor layer 230 using sputtering is preferable because it is easier to form a highly crystalline layer compared to using the ALD method.

[0366] For example, when forming the oxide semiconductor layer 230 using sputtering, oxygen or a mixture of oxygen and rare gases is used as the sputtering gas. By increasing the oxygen content in the sputtering gas, excess oxygen in the deposited oxide film can be increased. Furthermore, when depositing the aforementioned oxide film using sputtering, an In-M-Zn oxide target or the like can be used.

[0367] When forming the oxide semiconductor layer 230 using sputtering, an oxygen-excess oxide semiconductor is formed when deposition is performed under conditions where the oxygen content in the sputtering gas is more than 30% and less than 100%, preferably more than 70% and less than 100%. Transistors using the oxygen-excess oxide semiconductor in the channel formation region can achieve relatively high reliability. Note that the invention is not limited to this. In this case, an oxygen-deficient oxide semiconductor is formed when the oxygen content in the sputtering gas is set to more than 1% and less than 30%, preferably more than 5% and less than 20%. Transistors using the oxygen-deficient oxide semiconductor in the channel formation region can have higher field-effect mobility. Furthermore, by performing deposition while heating the substrate, the crystallinity of the oxide semiconductor layer can be improved.

[0368] Next, the conductive layer 240 and the oxide semiconductor layer 230 are processed into island shapes. Figure 15B Here, the same mask can be used to process the conductive layer 240 and the oxide semiconductor layer 230 together.

[0369] Alternatively, the processes of forming the conductive layer 240 into an island shape and forming the oxide semiconductor layer 230 into an island shape can be performed independently. In this case, for example, the processes of forming the conductive layer 240 into an island shape and forming the openings 290 in the conductive layer 240 can be performed independently, and the order of these processes is not limited. Alternatively, etching can be performed after exposure using a mask for forming square island shapes and after exposure using a mask for forming circular openings, thereby performing island formation and opening formation in one step. Furthermore, exposure using multi-level grayscale masks (typically halftone masks or grayscale masks) can also be used.

[0370] Next, an insulating layer 250 is formed on the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 250 is formed in contact with the oxide semiconductor layer 230.

[0371] Next, a heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range where the oxide semiconductor layer 230 is not polycrystalline. The heat treatment temperature is preferably 100°C or higher and 650°C or lower, more preferably 250°C or higher and 600°C or lower, and even more preferably 350°C or higher and 550°C or lower. Details of the heat treatment can be found above.

[0372] Furthermore, the gas used in the above-mentioned heat treatment is preferably of high purity. By using a high-purity gas for heat treatment, the absorption of moisture and the like by the oxide semiconductor layer 230 can be prevented as much as possible.

[0373] In this embodiment, as a heat treatment, a process is performed for 1 hour at a nitrogen to oxygen gas flow ratio of 4:1 and a temperature of 450°C. This oxygen-containing heat treatment reduces impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230. By reducing impurities in the film, the crystallinity of the oxide semiconductor layer 230 is improved, resulting in a denser structure with higher density. Therefore, the crystalline region in the oxide semiconductor layer 230 can be increased, and the in-plane non-uniformity of the crystalline region in the oxide semiconductor layer 230 can be reduced. Therefore, the in-plane non-uniformity of the electrical characteristics of the transistor can be reduced.

[0374] Furthermore, when the insulating layer 280 contains oxygen, it is preferable to supply oxygen from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230 through heat treatment. This reduces oxygen vacancies and VoH.

[0375] Next, a conductive layer 260af is formed on the insulating layer 250. Figure 15CThe conductive layer 260af is formed such that an oxide semiconductor layer 230 and an insulating layer 250 are sandwiched therebetween, and the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the top and side surfaces of the conductive layer 240 are covered.

[0376] The conductive layer 260af is formed in contact with the insulating layer 250 disposed in the opening 290 with a high aspect ratio. Therefore, the deposition of the conductive layer 260af preferably uses a deposition method with good coverage, and more preferably uses ALD, metal CVD, etc.

[0377] Next, a conductive layer 260bf is formed on the conductive layer 260af. Figure 16A The conductive layer 260bf is preferably deposited using sputtering. By using sputtering, the conductive layer 260bf can be formed to cover the upper end of the opening 290. Furthermore, by using sputtering, a film of appropriate thickness can be formed at a high deposition rate, thereby improving the efficiency of the manufacturing process. Moreover, by using sputtering, the conductive layer 260bf does not penetrate into the deep regions of the opening 290. Therefore, in the opening 290, especially in the deep regions, the sidewalls are not covered by the conductive layer 260bf.

[0378] Next, a portion of conductive layer 260bf and a portion of conductive layer 260af are removed using a mask to form conductive layer 260b and conductive layer 260a. Figure 16B ).

[0379] The semiconductor device of one aspect of the present invention can be manufactured through the above-described process.

[0380] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0381] (Implementation Method 2) In this embodiment, refer to Figures 17 to 18. Figure 20 This invention describes a storage device according to one aspect of the present invention. The storage device according to one aspect of the present invention includes a storage cell. The storage cell includes a transistor and a capacitor.

[0382] <Example 1 of storage device structure> Reference Figures 17A to 17C Describe the structure of a storage device that includes transistors and capacitors. Figure 17A It is a plan view of a storage device including transistor 200 and capacitor 100. Figure 17B It is along Figure 17A The cross-sectional view of the dotted line A1-A2 shown. Figure 17C It is along Figure 17A The cross-sectional view shown is the dotted-dash line A3-A4.

[0383] Figures 17A to 17C The illustrated storage device includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, storage cells 150 on the conductive layer 110, insulating layers 180 and 280 on the conductive layer 110, and an insulating layer 283 on the storage cells 150. Insulating layers 140, 180, 280, and 283 serve as interlayer films. The conductive layer 110 serves as wiring.

[0384] The storage cell 150 includes a capacitor 100 on the conductive layer 110 and a transistor 200 on the capacitor 100.

[0385] Capacitor 100 includes a conductive layer 115 on conductive layer 110, an insulating layer 130 on conductive layer 115, and a conductive layer 120 on insulating layer 130. Conductive layer 120 serves as one of a pair of electrodes (sometimes referred to as the upper electrode), conductive layer 115 serves as the other of the pair of electrodes (sometimes referred to as the lower electrode), and insulating layer 130 serves as the dielectric. That is, capacitor 100 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0386] like Figure 17B and Figure 17C As shown, an opening 190 is provided in the insulating layer 180, leading to the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region that contacts the top surface of the conductive layer 110 in the opening 190, a region that contacts the side surface of the insulating layer 180 in the opening 190, and a region that contacts at least a portion of the top surface of the insulating layer 180. The insulating layer 130 is disposed such that at least a portion of it is located in the opening 190. The conductive layer 120 is disposed such that at least a portion of it is located in the opening 190. Furthermore, as... Figure 17B and Figure 17C As shown, the conductive layer 120 is preferably provided in a manner that embeds it into the opening 190. Furthermore, the film disposed inside the opening 190 is preferably formed using a method with high coverage, such as ALD. Thus, the film has good coverage. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are preferably formed using ALD, metal CVD, or the like.

[0387] The capacitor 100 has a structure in which the upper and lower electrodes are opposed to each other with a dielectric material not only on the bottom surface but also on the side surface within the opening 190, thus increasing the electrostatic capacitance per unit area. Therefore, the deeper the opening 190, the larger the electrostatic capacitance of the capacitor 100 can be. In this way, by increasing the electrostatic capacitance per unit area of ​​the capacitor 100, the read operation of the storage device can be stabilized. Furthermore, it can promote the miniaturization or high integration of storage devices.

[0388] Figure 17B and Figure 17C An example is shown where the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. By adopting this structure, miniaturization or high integration of the storage device can be achieved.

[0389] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. Furthermore, a conductive layer 120 is provided on the insulating layer 130 in a manner that it is embedded in the opening 190. A capacitor 100 having this structure can be referred to as a trench capacitor or a grooved capacitor.

[0390] An insulating layer 280 is disposed on the capacitor 100. That is, the insulating layer 280 is disposed on the conductive layer 115, the insulating layer 130, and the conductive layer 120. In other words, the conductive layer 120 is disposed beneath the insulating layer 280.

[0391] Transistor 200 includes conductive layer 120 (corresponding to Figure 1B The conductive layer 220, conductive layer 240 on insulating layer 280, oxide semiconductor layer 230, insulating layer 250 on oxide semiconductor layer 230, and conductive layer 260 on insulating layer 250 are used as semiconductor layers, conductive layer 260 is used as gate electrode, insulating layer 250 is used as gate insulating layer, conductive layer 120 is used as one of source electrode and drain electrode, and conductive layer 240 is used as the other of source electrode and drain electrode.

[0392] Regarding transistor 200, please refer to the description in Embodiment 1 (Figures 1 and 2, etc.), so detailed description is omitted. In addition, the transistors included in the memory cell 150 are not limited to transistor 200 of Figures 1 to 2, etc., and each of the transistors illustrated in Embodiment 1 may also be used.

[0393] like Figures 17A to 17CAs shown, transistor 200 overlaps with capacitor 100. Furthermore, the opening 290 of a portion of the structure where transistor 200 is disposed has a region overlapping with the opening 190 of a portion of the structure where capacitor 100 is disposed. Specifically, conductive layer 120 is used as one of the source and drain electrodes of transistor 200 and as the upper electrode of capacitor 100, so transistor 200 and capacitor 100 share a common structure. By employing this structure, transistor 200 and capacitor 100 can be disposed in a manner that does not significantly increase the occupied area when viewed from a planar perspective. Therefore, the occupied area of ​​memory cell 150 can be reduced, and the storage capacity of the memory device can be increased by arranging memory cells 150 at a high density. In other words, high integration of the memory device can be achieved.

[0394] Furthermore, by placing the transistor 200 above the capacitor 100, the transistor 200 is not affected by the heat treatment during the manufacture of the capacitor 100. Therefore, it is possible to suppress the degradation of the electrical characteristics of the transistor 200, such as threshold voltage fluctuations and increased parasitic resistance, as well as the increase in uneven electrical characteristics caused by such degradation.

[0395] Figure 22A A circuit diagram of the storage device shown in this embodiment is illustrated. Figure 22A As shown, Figures 17A to 17C The structure shown is used as a storage cell. Storage cell 951 includes transistor M1 and capacitor CA. Here, transistor M1 corresponds to transistor 200, and capacitor CA corresponds to capacitor 100.

[0396] One of the source and drain terminals of transistor M1 is connected to one of the electrodes of capacitor CA. The other of the source and drain terminals of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL. The other of the electrodes of capacitor CA is connected to wiring CAL.

[0397] Here, wiring BIL corresponds to conductive layer 240, wiring WOL corresponds to conductive layer 260, and wiring CAL corresponds to conductive layer 110. For example... Figures 17A to 17C As shown, preferably, conductive layer 260 extends in the X direction and conductive layer 240 extends in the Y direction. By employing this structure, the wiring BIL and wiring WOL intersect each other. Furthermore, in Figure 17A The wiring CAL (conductive layer 110) is arranged in a planar shape, but the present invention is not limited thereto. For example, the wiring CAL may also be parallel to the wiring WOL (conductive layer 260) or the wiring BIL (conductive layer 240).

[0398] Note that the storage unit will be described in detail in the following implementation.

[0399] [Capacitor 100] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 120. Furthermore, a conductive layer 110 is disposed below the conductive layer 115. The conductive layer 115 has a region that contacts the conductive layer 110.

[0400] A conductive layer 110 is disposed on the insulating layer 140. The conductive layer 110 is used as a wiring CAL, and may be disposed in a planar manner, for example. As the conductive layer 110, a single layer or a stack of conductive materials described in [Conductor] of Embodiment 1 can be used. As the conductive layer 110, for example, a highly conductive material such as tungsten can be used. By using a highly conductive material in this way, the conductivity of the conductive layer 110 can be improved, thereby enabling the conductive layer 110 to fully perform its function as a wiring CAL.

[0401] Furthermore, the conductive layer 115 is preferably made of a conductive material that is not easily oxidized, either as a single layer or in a stack, or a conductive material that has the function of suppressing oxygen diffusion. For example, titanium nitride or indium tin oxide with added silicon can also be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten can also be used. Alternatively, for example, a structure in which first titanium nitride, tungsten, and second titanium nitride are stacked sequentially can also be used. By adopting this structure, oxidation of the conductive layer 110 due to the insulating layer 130 can be suppressed when an oxide is used in the insulating layer 130. In addition, oxidation of the conductive layer 110 due to the insulating layer 180 can be suppressed when an oxide is used as the insulating layer 180.

[0402] An insulating layer 130 is disposed on the conductive layer 115. The insulating layer 130 is disposed in such a way that it contacts the top surface and side surface of the conductive layer 115. That is, the insulating layer 130 preferably covers the side end of the conductive layer 115. This prevents short circuits between the conductive layer 115 and the conductive layer 120.

[0403] Alternatively, the side end of the insulating layer 130 can be aligned with the side end of the conductive layer 115. By employing this structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, thereby simplifying the manufacturing process of the storage device.

[0404] A material with a high relative permittivity (high-k) is preferably used as the insulating layer 130. By using a high-k material for the insulating layer 130, the thickness of the insulating layer 130 can be increased to a level that can suppress leakage current and sufficiently ensure the electrostatic capacitance of the capacitor 100.

[0405] Furthermore, as the insulating layer 130, it is preferable to use an insulator made of a high-k material, and more preferably a laminate structure using a material with a high relative permittivity (high-k) and a material with a dielectric strength greater than that high-k material. For example, as the insulating layer 130, an insulating film in which zirconium oxide, alumina, and zirconium oxide are stacked sequentially can be used. Alternatively, for example, an insulating film in which zirconium oxide, alumina, zirconium oxide, and alumina are stacked sequentially can be used. Furthermore, for example, an insulating film in which hafnium zirconium oxide, alumina, hafnium zirconium oxide, and alumina are stacked sequentially can be used. By using an insulating layer with a high dielectric strength, such as alumina, the dielectric strength can be increased, thereby suppressing electrostatic discharge damage to the capacitor 100.

[0406] Furthermore, a ferroelectric material can also be used as the insulating layer 130. For details regarding ferroelectric materials, please refer to the description in Embodiment 1.

[0407] Metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nm, and are therefore preferred for use in the insulating layer 130. The thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, further preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). Furthermore, for example, the thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, the capacitor 100 can be combined with miniaturized semiconductor elements such as transistors to form a semiconductor device.

[0408] Furthermore, metal oxides containing one or both of hafnium and zirconium can exhibit ferroelectricity even when their area is extremely small, and are therefore preferred for insulating layer 130. For example, the ferroelectric layer can have an area (occupied area) of 100 μm when viewed from a plane. 2 Below, 10μm 2 Below, 1μm 2 Below or 0.1μm 2 The following can also exhibit ferroelectric properties. Furthermore, sometimes ferroelectric layers can exist even with a top-view area (occupied area) of 10000 nm. 2 Below or 1000nm 2 The following also exhibit ferroelectric properties. By reducing the area of ​​the ferroelectric layer, the occupied area of ​​the capacitor 100 can be reduced.

[0409] Ferroelectric materials are insulators that exhibit the property of becoming internally polarized under the influence of an applied electric field and maintaining this polarization even when the electric field is zero. Therefore, non-volatile storage elements can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. Non-volatile storage elements using ferroelectric capacitors are sometimes called FeRAM (Ferroelectric Random Access Memory), ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, with one of the source and drain terminals of the transistor electrically connected to a terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as capacitor 100, the storage device shown in this embodiment is used as a ferroelectric memory.

[0410] The conductive layer 120 is disposed in contact with a portion of the top surface of the insulating layer 130. Furthermore, the side portion of the conductive layer 120 is preferably located inside the side portion of the conductive layer 115 in both the X and Y directions. Note that in a structure where the insulating layer 130 covers the side portion of the conductive layer 115, the side portion of the conductive layer 120 may also be located outside the side portion of the conductive layer 115.

[0411] The conductive layer 120 can be formed in a single layer or in a stack using the conductive material described in the [Conductive Layer] section of Embodiment 1. Preferably, the conductive layer 120 is made of a conductive material that is not easily oxidized or has the function of suppressing oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. Furthermore, for example, a structure in which tantalum nitride is stacked on titanium nitride may also be used. In this case, the titanium nitride is in contact with the insulating layer 130, and the tantalum nitride is in contact with the oxide semiconductor layer 230. By employing this structure, excessive oxidation of the conductive layer 120 due to the oxide semiconductor layer 230 can be suppressed. Furthermore, when an oxide is used for the insulating layer 130, excessive oxidation of the conductive layer 120 due to the insulating layer 130 can be suppressed. Alternatively, the conductive layer 120 may, for example, have a structure in which tungsten is stacked on titanium nitride.

[0412] Because the conductive layer 120 has a region in contact with the oxide semiconductor layer 230, it is preferable to use an oxygen-containing conductive material. By using an oxygen-containing conductive material as the conductive layer 120, conductivity can be maintained even if the conductive layer 120 absorbs oxygen. Furthermore, when an oxygen-containing insulating layer such as zirconium oxide is used as the insulating layer 130, the conductive layer 120 can also maintain conductivity, which is also preferred. For example, a single layer or a stack of materials such as ITO, ITSO, and IZO (registered trademark) can be used as the conductive layer 120.

[0413] Insulating layer 180 is used as an interlayer film, so its relative permittivity is preferably low. By using a material with a low relative permittivity in the interlayer film, parasitic capacitance generated between wirings can be reduced. As insulating layer 180, a single layer or a stack of insulating layers containing a material with a low relative permittivity can be used. Silicon oxide and silicon oxynitride have thermal stability and are therefore preferred.

[0414] Note that in Figure 17B and Figure 17C The diagram shows the insulating layer 180 as a single layer, but the invention is not limited to this. The insulating layer 180 may also have a two-layer structure, or a stacked structure with three or more layers.

[0415] <Example 2 of storage device structure> The storage cell 150 of the transistor 200 and capacitor 100 shown in this embodiment can be used as a storage cell of a storage device. The transistor 200 is a transistor whose channel is formed in a semiconductor layer containing oxide semiconductor. Because the off-state current of the transistor 200 is small, its use in a storage device allows for long-term retention of stored content. In other words, since refresh operations are not required or occur at extremely low frequencies, the power consumption of the storage device can be significantly reduced. Furthermore, due to the high frequency characteristics of the transistor 200, high-speed read and write operations of the storage device are possible.

[0416] A storage cell array can be constructed by arranging the storage cells 150 in a three-dimensional and matrix manner.

[0417] Figure 18A This is a floor plan of the storage device. Figure 18A An example is shown where two × two storage cells (storage cells 150a to 150d) are arranged in the X and Y directions.

[0418] Figure 18B It is along Figure 18A The cross-sectional view shown is along the dashed-dot line A3-A4. Figure 18A and Figure 18B In the middle, two storage units (in Figure 18B In this configuration, storage cells 150a and 150b are connected to a common wiring (conductive layer 246).

[0419] Here, Figure 18A and Figure 18B The memory cells 150a and 150b shown both have the same structure as memory cell 150. Memory cell 150a includes a capacitor 100a and a transistor 200a, and memory cell 150b includes a capacitor 100b and a transistor 200b. Furthermore, Figure 18AThe storage cells 150c and 150d shown also have the same structure as storage cell 150. Therefore, in Figure 18A and Figure 18B In the storage device shown, the same reference numerals are used for components that have the same function as those in the storage device shown in FIG10. Furthermore, for details regarding storage cells 150a to 150d, please refer to the description of storage cell 150 in <Example 1 of Storage Device Structure>.

[0420] like Figure 18A and Figure 18B As shown, conductive layers 260 used for wiring WOL are respectively disposed in memory cells 150a and 150b. Furthermore, as... Figure 18A As shown, a conductive layer 260 is provided in a manner shared between memory cells 150a and 150c, and another conductive layer 260 is provided in a manner shared between memory cells 150b and 150d. Furthermore, a conductive layer 240, serving as part of the wiring BIL, is provided in a manner shared between memory cells 150a and 150b. In other words, the conductive layer 240 is in contact with the oxide semiconductor layer 230 of memory cells 150a and 150b. Additionally, another conductive layer 240 is provided in a manner shared between memory cells 150c and 150d.

[0421] Here, Figure 18A and Figure 18B The illustrated storage device includes conductive layers 245 and 246 electrically connected to storage cells 150a and 150b, serving as plugs (or connection electrodes). Conductive layer 245 is disposed within openings formed in insulating layers 140, 180, 130, and 280 and contacts the bottom surface of conductive layer 240. Furthermore, conductive layer 246 is disposed within openings formed in insulating layers 285, 283, and 250 and contacts the top surface of conductive layer 240. Conductive materials suitable for conductive layer 240 can be used as conductive layers 245 and 246.

[0422] Conductive layers 245 and 246 are used as plugs or wiring for electrically connecting circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, as well as for wiring, electrodes, or terminals, to memory cells 150a and 150b. For example, a structure can be adopted where conductive layer 245 is connected to the plug or wiring of memory cells 150a and 150b. Figure 18B The read amplifier (not shown) under the storage device is electrically connected, and the conductive layer 246 is disposed with the read amplifier (not shown) under the storage device. Figure 18BThe same storage device (not shown) is electrically connected to the storage device shown. In this case, conductive layers 245 and 246 are used as part of the wiring BIL. Thus, by... Figure 18B By placing storage devices on top of or below the storage device shown, the storage capacity per unit area can be increased.

[0423] Furthermore, memory cells 150a and 150b are linearly symmetrical about the perpendicular bisector of the dashed line A3-A4. Therefore, transistors 200a and 200b are also arranged linearly symmetrically, sandwiching conductive layers 245 and 246. Here, conductive layer 240 serves as one of the source and drain electrodes of transistor 200a and another of the source and drain electrodes of transistor 200b. Moreover, transistors 200a and 200b share conductive layers 245 and 246, which act as a connector. Thus, by employing the above structure as a connection between two transistors and a connector, a memory device capable of miniaturization or high integration can be provided.

[0424] Furthermore, the conductive layer 110 used for wiring CAL can be disposed separately in memory cells 150a and 150b, or it can be disposed together in memory cells 150a and 150b. Note that, as Figure 18B As shown, the conductive layer 110 is disposed separately from the conductive layer 245 to prevent short circuit between the conductive layer 110 and the conductive layer 245.

[0425] also, Figure 19 This shows n layers (n is an integer greater than or equal to 3) stacked along the Z direction. Figure 18A The example shown is of four storage units. Figure 19 It is along Figure 18A The cross-sectional view shown is the dotted-dash line A3-A4.

[0426] Figure 19 The storage device shown includes an n-layer storage layer 160. Specifically, a storage layer 160[2] is disposed on storage layer 160[1], and (n-2) layers of storage layers are disposed on storage layer 160[2], with storage layer 160[n] being the topmost layer. There is no particular limitation on the number of storage cells included in a single storage layer 160, and it may include more than two storage cells. The storage cells included in the n-layer storage layer 160 are electrically connected to a readout amplifier (not shown) disposed under the n-layer storage layer 160 through conductive layers 245, 246, 247, and 248.

[0427] like Figure 19As shown, by stacking multiple storage cells, the cells can be configured in an integrated manner without increasing the footprint of the storage cell array. In other words, a 3D storage cell array can be constructed.

[0428] Figure 20 An example of a cross-sectional structure of a storage device having a layer containing memory cells stacked on top of a drive circuit including a sense amplifier is shown.

[0429] exist Figure 20 In the middle, the storage cell 150 (transistor 200 and capacitor 100) is disposed above the transistor 300.

[0430] Transistor 300 is one of the transistors included in the sense amplifier.

[0431] Figure 20 The storage unit 150 shown can be referred to the description of storage unit 150 in <Example 1 of the structure of storage device>.

[0432] like Figure 20 As shown, by employing a structure in which the read amplifier is arranged overlapping the memory cell 150, the bit line can be shortened. This reduces the bit line capacitance, thereby enabling high-speed driving of the memory device.

[0433] Figure 20 The storage device shown can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, transistor 300 corresponds to the transistor included in the sense amplifier 927 in semiconductor device 900. Furthermore, storage cell 150 corresponds to storage cell 950.

[0434] Transistor 300 is disposed on substrate 311 and includes a conductive layer 316 serving as a gate, an insulating layer 315 serving as a gate insulator, a semiconductor region 313 formed by a portion of substrate 311, and low-resistance regions 314a and 314b serving as source or drain regions. Transistor 300 may be p-channel or n-channel.

[0435] Here, in Figure 20In the transistor 300 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductive layer 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulating layer 315 in between. The conductive layer 316 can also be made of a material with an adjustable work function. Because of the convex portion of the semiconductor substrate, this transistor 300 is also called a FIN-type transistor. Furthermore, an insulating layer for forming the convex portion can be provided in contact with the upper surface of the convex portion. Although the case where the convex portion is formed by processing a portion of the semiconductor substrate is shown here, a semiconductor film with convex portions can also be formed by processing an SOI substrate.

[0436] Notice, Figure 20 The structure of transistor 300 shown is only an example and is not limited to the structure described above. Appropriate transistors can be used depending on the circuit structure or driving method.

[0437] Wiring layers, including interlayer films, wiring, and plugs, can also be provided between the various structures. Furthermore, multiple wiring layers can be provided depending on the design. Here, in conductive layers that function as plugs or wiring, the same symbol is sometimes used to represent multiple structures. Furthermore, in this specification, wiring and plugs electrically connected to wiring can also be considered as a single component. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a plug.

[0438] For example, on transistor 300, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductive layers 328 are embedded in insulating layers 320 and 322, and conductive layers 330 are embedded in insulating layers 324 and 326. Additionally, conductive layers 328 and 330 are used as connectors or wiring.

[0439] Furthermore, the insulating layer used as an interlayer film can be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulating layer 322, its top surface can also be planarized by a planarization process using CMP or the like.

[0440] Alternatively, a wiring layer can be formed on the insulating layer 326 and the conductive layer 330. For example, in Figure 20 In the middle, insulating layers 350, 352, and 354 are stacked in sequence. Furthermore, a conductive layer 356 is formed in insulating layers 350, 352, and 354. The conductive layer 356 is used as a plug or wiring.

[0441] The insulating layers described above, which can be used in semiconductor devices or storage devices, can be used as insulating layers 352 and 354, which are used as interlayer films.

[0442] As conductive layers used as plugs or wiring, such as conductive layers 328, 330, and 356, conductive materials suitable for conductive layer 240 can be used. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred; tungsten is particularly preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0443] The conductive layer 240 included in transistor 200 is electrically connected to the low-resistance region 314b, which serves as the source or drain region of transistor 300, through conductive layers 643, 642, 644, 645, 646, 356, 330, and 328.

[0444] Conductive layer 643 is embedded in insulating layer 280. Conductive layer 642 is disposed on insulating layer 130 and embedded in insulating layer 641. Conductive layer 642 can be manufactured using the same materials and processes as conductive layer 120. Conductive layer 644 is embedded in insulating layers 180 and 130. Conductive layer 645 is embedded in insulating layer 647. Conductive layer 645 can be manufactured using the same materials and processes as conductive layer 110. Conductive layer 646 is embedded in insulating layer 648. Transistor 300 and conductive layer 110 are electrically insulated by insulating layer 648.

[0445] As described above, the storage device of this embodiment includes transistors that reduce parasitic capacitance, thereby improving operating speed. Furthermore, because capacitors and transistors are stacked in the storage device of this embodiment, the area occupied by the storage cells when viewed from a planar perspective can be reduced, thereby enabling a highly integrated storage device.

[0446] This implementation method can be appropriately combined with other implementation methods.

[0447] (Implementation Method 3) In this embodiment, a semiconductor device 900 according to one aspect of the present invention is described. The semiconductor device 900 can be used as a storage device.

[0448] Figure 21 This is a block diagram illustrating a structural example of a semiconductor device 900. Figure 21 The semiconductor device 900 shown includes a driving circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Figure 21 An example of a storage array 920 including multiple storage cells 950 configured in a matrix is ​​shown.

[0449] As storage unit 950, the storage device (storage unit 150, etc.) described in Embodiment 2 can be used.

[0450] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and peripheral circuit 915. The peripheral circuit 915 includes peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0451] In the semiconductor device 900, the aforementioned circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, while signal RDA is a signal output to the outside. Signal CLK is the clock signal.

[0452] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Furthermore, signals PON1 and PON2 can also be generated in the control circuit 912.

[0453] The control circuit 912 is a logic circuit that controls the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 to execute the aforementioned operating mode.

[0454] The voltage generation circuit 928 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 928. For example, when a signal of level H is applied as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0455] The peripheral circuit 911 is used to write and read data from the storage unit 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0456] Row decoder 941 and column decoder 942 are used to decode the signal ADDR. Row decoder 941 is used to specify the row to be accessed, and column decoder 942 is used to specify the column to be accessed. Row driver 923 is used to select the row specified by row decoder 941. Column driver 924 has the following functions: writing data to memory cell 950; reading data from memory cell 950; and storing the read data.

[0457] Input circuit 925 has the function of holding signal WDA. The data held in input circuit 925 is output to column driver 924. The output data of input circuit 925 is the data written to memory cell 950 (Din). The data read from memory cell 950 by column driver 924 (Dout) is output to output circuit 926. Output circuit 926 has the function of holding Dout. In addition, output circuit 926 has the function of outputting Dout to the outside of semiconductor device 900. The data signal output from output circuit 926 is signal RDA.

[0458] PSW931 controls the supply of V to the external circuit 915. DD The PSW932 has the function of controlling the supply of V to the line driver 923. HM The function of the semiconductor device 900. Here, the high supply voltage of the semiconductor device 900 is V. DD The low supply voltage is GND (ground potential). Additionally, V HM It is a high power supply voltage used to make the word line high, which is higher than V. DD The PSW931 is controlled to turn on / off using signal PON1, and the PSW932 is controlled to turn on / off using signal PON2. Figure 21 In the middle, the peripheral circuit 915 is supplied with V DD The number of power domains can be 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0459] Reference Figures 22A to 22H This section describes an example of the structure of a storage cell that can be used in storage cell 950.

[0460] The following discussion of connecting two components includes cases where they are electrically connected via circuit elements (transistors, switches, diodes, resistors, etc.). An electrical connection refers to a state where current can flow between two components. Furthermore, when two components are connected via a switch or transistor, current can flow even when the switch or transistor is in the ON state, and therefore this is also included in the scope of an electrical connection.

[0461] [DOSRAM] Figure 22AAn example circuit structure of a DRAM-type memory cell is shown. In this specification, DRAM using OS transistors is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Memory cell 951 includes transistor M1 and capacitor CA.

[0462] Transistor M1 may also include a front gate (sometimes simply referred to as the gate) and a back gate. In this case, the back gate may also be connected to a wiring supplied with a constant potential or signal, and the front gate and the back gate may also be connected.

[0463] The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitor CA is connected to wiring CAL.

[0464] The BIL (Bite Line) is used as the bit line, and the WOL (Word Line) is used as the word line. The CAL (Chip Line) is used to apply a specified potential to the second terminal of the capacitor CA. During data writing and reading, it is preferable to apply a low-level potential (sometimes called a reference potential) to the CAL.

[0465] Data writing and reading are performed by applying a high-level potential to the wiring WOL to turn on the transistor M1, thereby making the wiring BIL and the first terminal of the capacitor CA conductive (allowing current to flow).

[0466] Furthermore, the memory cell that can be used as memory cell 950 is not limited to memory cell 951, and the circuit structure can be changed. For example, it can also be used... Figure 22B The storage cell 952 is shown. Storage cell 952 is an example excluding capacitor CA and wiring CAL. The first terminal of transistor M1 is in a floating state.

[0467] In memory cell 952, the potential written by transistor M1 is maintained in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0468] An OS transistor is preferably used as transistor M1. OS transistors have the characteristic of extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. That is, transistor M1 can hold written data for a long time, thereby reducing the refresh frequency of the memory cell. Furthermore, the memory cell refresh operation can be omitted. In addition, due to the very low leakage current, multi-valued data or analog data can be held in memory cells 951 and 952.

[0469] [NOSRAM] Figure 22C An example circuit structure of a gain-cell type memory cell including two transistors and one capacitor is shown. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and the like, a memory device including a gain-cell type memory cell that uses transistor OS for transistor M2 is sometimes referred to as NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0470] Transistor M2's first terminal is connected to capacitor CB's first terminal; transistor M2's second terminal is connected to wiring WBL; and transistor M2's gate is connected to wiring WOL. Capacitor CB's second terminal is connected to wiring CAL. Transistor M3's first terminal is connected to wiring RBL; transistor M3's second terminal is connected to wiring SL; and transistor M3's gate is connected to capacitor CB's first terminal.

[0471] Wiring WBL is used as the write bit line, wiring RBL as the read bit line, and wiring WOL as the word line. Wiring CAL is used to apply a predetermined potential to the second terminal of capacitor CB. During data writing, data holding, and data reading, it is preferable to apply a low-level potential (sometimes called the reference potential) to wiring CAL.

[0472] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M2 and thus connects wiring WBL to the first terminal of capacitor CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL to write that potential to the first terminal of capacitor CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL, which turns off transistor M2, thereby maintaining the potential of the first terminal of capacitor CB and the potential of the gate of transistor M3.

[0473] Data is read out by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate and the second terminal of transistor M3, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0474] For example, a structure that combines the wiring WBL and wiring RBL into a single wiring BIL can also be adopted. Figure 22D An example of the circuit structure of the memory cell in this case is shown. In memory cell 954, the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. That is, memory cell 954 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0475] Figure 22E The memory cell 955 shown is an example where the capacitor CB and wiring CAL of memory cell 953 are omitted. Furthermore, Figure 22F The memory cell 956 shown is an example of omitting the capacitor CB and wiring CAL found in memory cell 954. This structure improves the integration density of the memory cells.

[0476] Note that it is preferable to use the OS transistor as at least as transistor M2. In particular, it is preferable to use the OS transistor as both transistor M2 and transistor M3.

[0477] Because the OS transistor has extremely low off-state current, transistor M2 can hold written data for an extended period, thereby reducing the refresh frequency of the memory cells. Furthermore, the memory cell refresh operation can be omitted. Additionally, due to the very low leakage current, multi-valued or analog data can be held in memory cells 953, 954, 955, and 956.

[0478] The memory cells 953, 954, 955, and 956, which use OS transistors as transistor M2, are a type of NOSRAM.

[0479] Si transistors can also be used as transistor M3. Si transistors can improve field-effect mobility and can be p-channel transistors, thus increasing the freedom of circuit design.

[0480] Furthermore, when the OS transistor is used as transistor M3, the memory cell can be constructed from a unipolar circuit.

[0481] also, Figure 22G A gain-cell type memory cell 957 with three transistors and one capacitor is shown. The memory cell 957 includes transistors M4 to M6 and capacitor CC.

[0482] Transistor M4's first terminal is connected to capacitor CC's first terminal; transistor M4's second terminal is connected to wiring BIL; and transistor M4's gate is connected to wiring WOL. Capacitor CC's second terminal is connected to transistor M5's first terminal and wiring GNDL. Transistor M5's second terminal is connected to transistor M6's first terminal; transistor M5's gate is connected to capacitor CC's first terminal. Transistor M6's second terminal is connected to wiring BIL; and transistor M6's gate is connected to wiring RWL.

[0483] The BIL (Bite Line) is used as the bit line, the WOL (Write Word Line) is used as the write word line, and the RWL (Read Word Line) is used as the read word line. The GNDL (Read Word Line) is used to supply a low-level potential.

[0484] Data writing is performed by applying a high-level potential to wiring WOL, which turns on transistor M4 and connects wiring BIL to the first terminal of capacitor CC. Specifically, when transistor M4 is on, a potential corresponding to the information to be recorded is applied to wiring BIL to write that potential to the first terminal of capacitor CC and the gate of transistor M5. Then, a low-level potential is applied to wiring WOL, which turns off transistor M4, thereby maintaining the potential of the first terminal of capacitor CC and the potential of the gate of transistor M5.

[0485] Data readout is performed by pre-charging the wiring BIL to a predetermined potential, then making the wiring BIL electrically floating and applying a high-level potential to the wiring RWL. By making the wiring RWL high, transistor M6 is turned on, and the wiring BIL and the second terminal of transistor M5 are connected. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL will change correspondingly to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of the wiring BIL. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0486] Note that it is preferable to use the OS transistor as at least transistor M4.

[0487] Si transistors can also be used as transistors M5 and M6. As mentioned above, the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, depending on factors such as the crystallization state of the silicon used in the semiconductor layer.

[0488] Furthermore, when OS transistors are used as transistors M5 and M6, the memory cell can be constructed from unipolar circuits.

[0489] [OS-SRAM] Figure 22H An example of SRAM (Static Random Access Memory) using OS transistors is shown. In this specification, etc., SRAM using OS transistors will be referred to as OS-SRAM (Oxide Semiconductor-SRAM). Furthermore, Figure 22H The storage unit 958 shown is an SRAM-type storage unit capable of backup.

[0490] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, capacitor CD1, and capacitor CD2. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0491] Transistor M7's first terminal is connected to wiring BIL. Transistor M7's second terminal is connected to the first terminal of transistors MS1 and MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. Transistor M7's gate is connected to wiring WOL. Transistor M8's first terminal is connected to wiring BILB. Transistor M8's second terminal is connected to the first terminal of transistors MS2 and MS4, the gate of transistor MS1 and MS3, and the first terminal of transistor M9. Transistor M8's gate is connected to wiring WOL.

[0492] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0493] The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, and the gate of transistor M9 is connected to the wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, and the gate of transistor M10 is connected to the wiring BRL.

[0494] The second terminal of capacitor CD1 is connected to wiring GNDL, and the second terminal of capacitor CD2 is also connected to wiring GNDL.

[0495] The BIL and BILB wirings are used as bit lines, the WOL wiring is used as word lines, and the BRL wiring is used to control the on and off states of transistors M9 and M10.

[0496] Wiring VDL provides a high-level potential, and wiring GNDL provides a low-level potential.

[0497] Data is written by applying a high-level potential to the wiring WOL and the wiring BRL. Specifically, when transistor M10 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the second terminal side of transistor M10.

[0498] Storage cell 958 uses transistors MS1 to MS2 to form an inverter loop, so the inverted signal of the data signal corresponding to this potential is input to the second terminal of transistor M8. Since transistor M8 is in the on state, the potential applied to wiring BIL, that is, the inverted signal of the signal input to wiring BIL, is output to wiring BILB. In addition, since transistors M9 and M10 are in the on state, the potentials of the second terminals of transistor M7 and transistor M8 are maintained by the first terminals of capacitor CD2 and capacitor CD1, respectively. Then, by applying a low-level potential to wiring WOL and a low-level potential to wiring BRL to turn off transistors M7 to M10, the potentials of the first terminals of capacitor CD1 and capacitor CD2 are maintained.

[0499] Data readout is performed as follows: First, the wiring BIL and wiring BILB are pre-charged to a predetermined potential. Then, a high-level potential is applied to wiring WOL and wiring BRL. This causes the potential of the first terminal of capacitor CD1 to be refreshed by the inverter loop of storage cell 958 and output to wiring BILB. Similarly, the potential of the first terminal of capacitor CD2 is refreshed by the inverter loop of storage cell 958 and output to wiring BIL. Since wiring BIL and wiring BILB change from their pre-charged potentials to the potentials of the first terminals of capacitor CD2 and capacitor CD1, respectively, the potential held by the storage cell can be read from the potentials of wiring BIL or wiring BILB.

[0500] Transistors M7 to M10 are preferably OS transistors. This allows transistors M7 to M10 to hold written data for an extended period, thus reducing the refresh frequency of the memory cell. Alternatively, the refresh operation of the memory cell can be omitted.

[0501] Furthermore, Si transistors are preferably used as transistors MS1 to MS4.

[0502] The driving circuitry 910 and the memory array 920 of the semiconductor device 900 can also be disposed on the same plane. Furthermore, as... Figure 23AAs shown, the driving circuit 910 and the memory array 920 can also overlap. By overlapping the driving circuit 910 and the memory array 920, the signal transmission distance can be shortened. Furthermore, as... Figure 23B As shown, multiple memory arrays 920 can also be stacked on the driving circuit 910.

[0503] Next, an example of an arithmetic processing device that may include the aforementioned storage device or other semiconductor device will be described.

[0504] Figure 24 This is a block diagram of the arithmetic unit 960. Figure 24 The computing device 960 shown can be used, for example, as a CPU (Central Processing Unit). Furthermore, the computing device 960 can also be used with processors such as GPUs (Graphics Processing Units), TPUs (Tensor Processing Units), and NPUs (Neural Processing Units), which have more (tens to hundreds) processor cores than a CPU capable of parallel processing.

[0505] Figure 24 The illustrated arithmetic unit 960, on a substrate 990, includes: an ALU 991 (ALU: Arithmetic Logic Unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. It may also include a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be located on different chips.

[0506] Cache 999 is connected to the main memory located on different chips via cache interface 989. Cache interface 989 has the function of supplying a portion of the data stored in the main memory to cache 999. In addition, cache interface 989 has the function of outputting a portion of the data held in cache 999 to ALU 991 or register 996, etc., via bus interface 998.

[0507] As described later, the memory array 920 can be arranged in a manner that stacks on the computing device 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 can have the function of supplying data held in the memory array 920 to the cache 999. Furthermore, in this case, it is preferable that a portion of the cache interface 989 includes a driver circuit 910.

[0508] Note that you can also choose not to set cache 999 and use only storage array 920 as a cache.

[0509] Figure 24 The arithmetic device 960 shown is merely an example with a simplified structure; therefore, the actual arithmetic device 960 has various structures depending on its application. For example, it is preferable to include... Figure 24 The computing device 960 shown has a multi-core structure, which consists of a single core and multiple cores that operate simultaneously. The more cores, the better the computing performance. More cores are preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, and sixteen cores or more are even more preferred. Furthermore, when used in servers or other applications requiring very high computing performance, a multi-core structure with 16 or more cores is preferred, more preferably 32 or more cores, and more preferably 64 or more cores. Additionally, the number of bits that can be processed in the internal computing circuitry, data bus, etc., of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0510] Instructions input to the arithmetic unit 960 via the bus interface 998 are input to the instruction decoder 993 and, after being decoded, are input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0511] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing the program of the arithmetic unit 960, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask state. The register controller 997 generates the address of register 996 and reads and writes register 996 according to the state of the arithmetic unit 960.

[0512] Furthermore, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0513] exist Figure 24In the arithmetic unit 960 shown, the register controller 997 selects the holding operation of register 996 according to instructions from ALU 991. In other words, the register controller 997 selects whether data is held in the memory cells of register 996 by flip-flops or by capacitors. When data is held by flip-flops, a power supply potential is supplied to the memory cells in register 996. When data is held by capacitors, the data is overwritten to the capacitors, and the power supply potential to the memory cells in register 996 can be stopped.

[0514] The storage array 920 and the computing device 960 can be arranged overlappingly. Figure 25A and Figure 25B This is a perspective view of semiconductor device 970A. Semiconductor device 970A includes a layer 930 on top of a computing device 960, on which memory arrays are disposed. Layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The computing device 960 and each memory array have overlapping areas. To facilitate understanding of the structure of semiconductor device 970A, in... Figure 25B The computing device 960 and the layer 930 are shown separately in the middle.

[0515] By overlapping the layer 930, which includes the memory array, and the computing device 960, the connection distance between them can be shortened. This improves communication speed between them. Furthermore, the shorter connection distance reduces power consumption.

[0516] As a stacking method for the layer 930 including the memory array and the computing device 960, the following methods can be used: directly stacking the layer 930 including the memory array on the computing device 960 (also known as monolithic stacking); or forming the computing device 960 and the layer 930 on different substrates, bonding the two substrates together, and electrically connecting them using bonding techniques such as through-holes or conductive films (Cu-Cu bonding, etc.). The former method does not require consideration of misalignment during bonding, thus reducing both chip size and manufacturing costs.

[0517] Here, the computing device 960 does not include cache 999, and the memory arrays 920L1, 920L2, and 920L3 disposed in layer 930 can all be used as caches. For example, memory arrays 920L1, 920L2, and 920L3 can be used as L1 cache (also called level 1 cache), L2 cache (also called level 2 cache), and L3 cache (also called level 3 cache), respectively. Among the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, memory array 920L1 has the smallest capacity and the highest access frequency.

[0518] Note that when the cache 999 in the arithmetic unit 960 is used as an L1 cache, the memory arrays in layer 930 can be used as lower-level caches or main memory. Main memory is a type of memory with a larger capacity and lower access frequency than the cache.

[0519] In addition, such as Figure 25B As shown, drive circuits 910L1, 910L2, and 910L3 are provided. Drive circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, drive circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and drive circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

[0520] Note that although the case shown here is three storage arrays used as cache, it is also possible to have one, two, or more than four.

[0521] When the storage array 920L1 is used as a cache, the driver circuit 910L1 can also be used as part of the cache interface 989, and the driver circuit 910L1 can also be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 can also be used as part of the cache interface 989 or connected to a part of the cache interface 989.

[0522] Whether the storage array 920 is used as cache or as main memory depends on the control circuit 912 included in each drive circuit 910. The control circuit 912 can use a portion of the multiple storage cells 950 contained in the semiconductor device 900 as RAM based on signals supplied from the arithmetic unit 960.

[0523] In the semiconductor device 900, a portion of the multiple storage cells 950 can be used as cache and the remainder as main memory. That is, the semiconductor device 900 can function as both cache and main memory. The semiconductor device 900 according to one embodiment of the invention can, for example, be used as a general-purpose memory.

[0524] Alternatively, a layer 930 including a storage array 920 may be provided in a manner that overlaps with the computing device 960. Figure 26A This is a 3D view of the semiconductor device 970B.

[0525] In the semiconductor device 970B, a memory array 920 can be divided into multiple regions and assigned different functions for use. Figure 26A This shows an example of using region L1, region L2, and region L3 as L1 cache, L2 cache, and L3 cache, respectively.

[0526] Furthermore, in the semiconductor device 970B, the capacity of each of regions L1 to L3 can be changed according to the situation. For example, the capacity of the L1 cache can be increased by increasing the area of ​​region L1. By adopting this structure, efficient computational processing can be achieved, thereby increasing processing speed.

[0527] In addition, multiple storage arrays can be stacked. Figure 26B This is a 3D view of the semiconductor device 970C.

[0528] Semiconductor device 970C includes a layer 930L1 comprising a memory array 920L1, a layer 930L2 comprising a memory array 920L2, and a layer 930L3 comprising a memory array 920L3. The memory array 920L1, physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, furthest from the arithmetic unit 960, can be used as a lower-level cache or main memory. By employing this structure, the capacity of each memory array can be increased, thus further improving processing power.

[0529] This implementation method can be appropriately combined with other implementation methods.

[0530] (Implementation Method 4) This embodiment illustrates an example of the application of a storage device according to one aspect of the present invention.

[0531] Generally speaking, various storage devices are used in semiconductor devices such as computers, depending on their purpose. Figure 27A The various memory devices used in semiconductor devices are shown in a hierarchical manner. Higher-level memory devices are required to operate at faster speeds, while lower-level memory devices are required to have larger storage capacities and higher recording densities. Figure 27A In this context, from the topmost level, the cache includes memory installed as registers in processing devices such as the CPU, L1 cache, L2 cache, L3 cache, main memory, and secondary storage. Note that although an example including up to L3 cache is shown here, it may also include caches at lower levels.

[0532] Because memory installed along with registers in arithmetic processing devices such as CPUs is used for temporary storage of calculation results, it is accessed frequently by the processing device. Therefore, faster operating speed is required compared to storage capacity. Furthermore, registers also have the function of holding settings information of the processing device.

[0533] A cache is a system that copies and maintains a portion of the information held in main memory. By copying frequently used data to the cache, the speed of data access can be improved. A cache requires less storage capacity than main memory, but its operating speed is higher. Furthermore, data that is modified in the cache is copied and provisioned to main memory.

[0534] Main memory has the function of storing programs, data, etc. read from secondary storage.

[0535] Secondary storage serves to hold data that needs to be preserved long-term and various programs used by computing devices. Therefore, compared to faster operating speeds, secondary storage requires larger storage capacity and higher recording density. For example, high-capacity non-volatile storage devices such as 3D NAND can be used.

[0536] According to one aspect of the present invention, a storage device (OS memory) using oxide semiconductors operates at high speed and can retain data for long periods. Therefore, as Figure 27A As shown, a storage device according to one aspect of the present invention can be used for both a cache hierarchy and a main memory hierarchy. Furthermore, a storage device according to one aspect of the present invention can also be used for a secondary storage hierarchy.

[0537] also, Figure 27B Examples are shown of cases where SRAM is used for one part of the cache and OS memory of one aspect of the present invention is used for another part.

[0538] The lowest level cache can be referred to as an LLC (Last Level Cache). LLCs do not require faster operating speeds than their parent caches, but are required to have larger storage capacity. One embodiment of the OS memory of this invention has a fast operating speed and can retain data for long periods, making it suitable for use with LLCs. Note that one embodiment of the OS memory of this invention can also be used with FLCs (Final Level Cache).

[0539] For example, such as Figure 27B As shown, SRAM can be used for higher-level caches (L1 cache, L2 cache, etc.) and the OS memory of one embodiment of the present invention can be used for LLC. Furthermore, as... Figure 27B As shown, DRAM can be used in main memory in addition to OS memory.

[0540] This implementation method can be appropriately combined with other implementation methods.

[0541] (Implementation Method 5) This embodiment describes a display device according to one aspect of the present invention.

[0542] One aspect of the semiconductor device of the present invention can be used in a display device or a module including the display device. Examples of modules including the display device include modules in which the display device is mounted with connectors such as flexible printed circuit boards (FPC) or TCP (Tape Carrier Package), and modules in which integrated circuits (ICs) are mounted via COG (Chip On Glass) or COF (Chip On Film) methods.

[0543] Furthermore, the display device of this embodiment may also have the function of a touch panel. For example, various detection elements (also called sensor elements) capable of detecting the approach or contact of a detection object such as a finger can be used in the display device.

[0544] For example, sensor types include electrostatic capacitive, resistive film, surface acoustic wave, infrared, optical, and pressure-sensitive types.

[0545] Examples of electrostatic capacitive sensors include surface-type and projected-type electrostatic capacitive sensors. Furthermore, projected-type electrostatic capacitive sensors include self-capacitance and mutual-capacitance sensors. Mutual-capacitance sensors are preferred, as they allow for simultaneous multi-point detection.

[0546] Examples of touch panels include Out-Cell, On-Cell, and In-Cell types. Note that an In-Cell touch panel refers to a structure in which electrodes constituting the detection element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0547] [Display Module] Figure 28A A perspective view of display module 170 is shown. Display module 170 includes display device 600A and FPC 298. Note that the display device included in display module 170 is not limited to display device 600A, but may also be display device 600B, which will be described later.

[0548] The display module 170 includes a substrate 291 and a substrate 299. The display module 170 includes a display section 297. The display section 297 is an image display area in the display module 170, and can display light from each pixel disposed in the pixel section 294 described below.

[0549] Figure 28BThis is a three-dimensional schematic diagram of one side of the substrate 291. A circuit section 292, a pixel circuit section 293 on the circuit section 292, and a pixel section 294 on the pixel circuit section 293 are stacked on the substrate 291. Furthermore, a terminal section 295 for connecting to the FPC 298 is provided on the portion of the substrate 291 that does not overlap with the pixel section 294. The terminal section 295 is electrically connected to the circuit section 292 via a wiring section 296 composed of multiple wirings.

[0550] In one aspect of the present invention, the semiconductor device can be applied to one or both of the circuit section 292 and the pixel circuit section 293.

[0551] The pixel unit 294 includes a plurality of pixels 294a arranged periodically. Figure 28B The right side shows a magnified view of pixel 294a. Figure 28B An example is shown where a pixel 294a includes a sub-pixel 130R that emits red light, a sub-pixel 130G that emits green light, and a sub-pixel 130B that emits blue light.

[0552] Subpixels include display elements. Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electromechanical Systems) elements using shutter-based or light-interference methods, as well as display elements employing microencapsulation, electrophoresis, electrowetting, or electronic powder fluid methods (registered trademark), can be used. Furthermore, QLED (Quantum-dot LED) technology utilizing a light source and employing quantum dot materials for color conversion can also be used.

[0553] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, MiniLEDs and Micro LEDs can be used as LEDs.

[0554] There are no particular limitations on the arrangement of pixels in the display device of this embodiment, and various methods can be used. Examples of pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement. Figure 28B This shows an example of a pixel arrangement using stripes.

[0555] The pixel circuit section 293 includes a plurality of pixel circuits 293a arranged periodically.

[0556] A pixel circuit 293a controls the driving of multiple elements included in a pixel 294a. A pixel circuit 293a may contain three circuits controlling the emission of light from a single light-emitting element. For example, the pixel circuit 293a may employ a structure with at least one selection transistor, one current control transistor (driving transistor), and a capacitor for each light-emitting element. In this case, the gate of the selection transistor receives a gate signal, and the source receives a source signal. This realizes an active matrix display device.

[0557] The circuit section 292 includes circuitry for each pixel circuit 293a of the driving pixel circuit section 293. For example, it preferably includes one or both of a gate line driving circuit and a source line driving circuit. Furthermore, it may include at least one of an arithmetic circuit, a storage circuit, and a power supply circuit.

[0558] The FPC298 is used for wiring to supply video signals or power potentials from the outside to the circuit section 292. Additionally, ICs can be mounted on the FPC298.

[0559] The display module 170 can adopt a structure in which one or both of the pixel circuit section 293 and circuit section 292 are stacked on the lower side of the pixel section 294, so that the display section 297 can have an extremely high aperture ratio (effective display area ratio). In addition, the pixels 294a can be arranged at an extremely high density, thereby enabling the display section 297 to have extremely high resolution.

[0560] This high-definition display module 170 is suitable for use in VR devices such as HMDs or AR devices such as glasses. For example, because the display module 170 has an extremely high-definition display section 297, even when the user magnifies the display section through a lens, the pixels are not visible, thus achieving a highly immersive display. Furthermore, the display module 170 can also be applied to electronic devices with relatively small display sections. For example, it is suitable for use in the display sections of wearable electronic devices such as watch-type devices.

[0561] [Example 1 of a display device structure] Figure 29 This is a cross-sectional view of display device 600A. Display device 600A is an example of a display device employing an MML (Metal Mask Less) structure. That is, display device 600A includes light-emitting elements manufactured without high-precision metal masks.

[0562] In display devices employing the MML structure, the island-shaped light-emitting layers in the light-emitting elements are formed by photolithography after depositing a light-emitting layer across the entire surface. Therefore, it is possible to achieve high-definition or high-aperture-ratio display devices that have been difficult to achieve until now. Furthermore, since light-emitting layers can be formed separately for each color, extremely vivid, high-contrast, and high-quality display devices can be realized. For example, when using three light-emitting elements—one emitting blue light, one emitting green light, and one emitting red light—to construct a display device, three island-shaped light-emitting layers can be formed by repeatedly forming the light-emitting layers three times and using photolithography.

[0563] Because devices with MML structures can be manufactured without metal masks, the resolution limitations imposed by the alignment accuracy of metal masks can be exceeded. Furthermore, manufacturing devices without metal masks eliminates the need for equipment related to metal mask fabrication and the metal mask cleaning process. Additionally, in photolithography, the same equipment used in transistor manufacturing can be used, eliminating the need for specialized equipment for manufacturing devices with MML structures. Thus, by utilizing MML structures, manufacturing costs can be reduced, making them suitable for mass production.

[0564] In display devices with MML structures, it is not necessary to use special pixel arrangements such as Pentile arrangement to improve sharpness in a pseudo-method. Thus, a display device can be realized in which a so-called stripe arrangement in which each sub-pixel of R, G, and B is arranged in one direction and has high sharpness (e.g., 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more).

[0565] Furthermore, by providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element. The sacrificial layer can remain in the finished display device or be removed during the manufacturing process. For example, Figure 29 and Figure 30 The sacrificial layer 618a shown is part of the sacrificial layer disposed on the light-emitting layer.

[0566] Furthermore, by employing a deposition process using a range mask and a processing process using a resist mask, light-emitting elements can be manufactured with a simpler process.

[0567] Figure 29 This is a cross-sectional schematic diagram of a display device (semiconductor device) 600A according to one embodiment of the present invention. In the display device 600A, pixel circuits, driving circuits, etc., are disposed on a substrate 410. Figure 29In the display device 600A, in addition to component layers 620, 630 and 660, a wiring layer 670 is also shown. The wiring layer 670 is a layer on which wiring is provided.

[0568] In component layer 630, pixel circuitry for the display device is preferably provided. In component layer 620, driving circuitry for the display device (one or both of gate driver and source driver) is preferably provided. Furthermore, component layer 620 may also include one or more types of circuitry such as arithmetic circuitry and memory circuitry.

[0569] As an example, the element layer 620 includes a substrate 410 on which a transistor 400d is formed. Furthermore, a wiring layer 670 is disposed above the transistor 400d, and the wiring layer 670 contains a connection layer that allows the transistor 400d to connect with a conductive layer or transistor disposed in the element layer 630. Figure 29 The conductive layer 514 in the middle is electrically connected to the wiring. Furthermore, above the wiring layer 670 are component layers 630 and 660, where component layer 630 includes, for example, a transistor MTCK. Component layer 660 includes a light-emitting element 650 (…). Figure 29 The light-emitting elements include 650R, 650G, and 650B.

[0570] Transistor 400d is an example of a transistor included in element layer 620. Furthermore, transistor MTCK is an example of a transistor included in element layer 630. Additionally, light-emitting elements (light-emitting element 650R, light-emitting element 650G, and light-emitting element 650B) are an example of light-emitting elements included in element layer 660.

[0571] As a transistor MTCK, for example, an OS transistor can be used. Figure 29 An example is shown where the transistor 200 described in the above embodiment is used as a transistor MTCK.

[0572] As substrate 410, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium) can be used. Furthermore, besides semiconductor substrates, substrate 410 can also be, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate containing stainless steel foil, a tungsten substrate, a substrate containing tungsten foil, a flexible substrate, a laminated film, or a paper or substrate film containing fibrous material. In this embodiment, the case where substrate 410 is a semiconductor substrate containing silicon as a material is described. Therefore, the transistors in element layer 620 can be Si transistors.

[0573] Transistor 400d includes a device separation layer 412, a conductive layer 416, an insulating layer 415, an insulating layer 417, a semiconductor region 413 formed by a portion of a substrate 410, a low-resistance region 414a serving as a source region or a drain region, and a low-resistance region 414b. Therefore, transistor 400d is a Si transistor. Although Figure 29 The diagram shows a structure in which the source or drain of transistor 400d is electrically connected to conductive layer 514 disposed in element layer 630 via conductive layer 428, conductive layer 430 and conductive layer 456. However, the electrical connection structure of a display device according to one embodiment of the present invention is not limited to this.

[0574] Transistor 400d can be implemented as a Fin-type structure, for example, by employing a structure in which the top surface of semiconductor region 413 and the side surfaces in the channel width direction are covered by a conductive layer 416 with an insulating layer 415 serving as a gate insulating layer. By forming a Fin-type transistor 400d, the effective channel width can be increased, thus improving the on-state characteristics of transistor 400d. Furthermore, since the effect of the electric field at the gate electrode can be enhanced, the off-state characteristics of transistor 400d can be improved. Alternatively, transistor 400d can also have a planar structure without a Fin-type structure.

[0575] Furthermore, transistor 400d can be either a p-channel transistor or an n-channel transistor. Additionally, multiple transistors 400d can be provided, and both p-channel and n-channel transistors can be used.

[0576] The channel formation region of semiconductor region 413, the region theren, and the low-resistance regions 414a and 414b used as source or drain regions preferably comprise silicon-based semiconductors, specifically monocrystalline silicon. Alternatively, the aforementioned regions may also be formed using germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride, for example. Silicon with effective quality controlled by applying stress to the crystal lattice to change the interplanar spacing can be used. Furthermore, transistor 400d may, for example, be a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide.

[0577] As the conductive layer 416 used as the gate electrode, a semiconductor material such as silicon containing elements that impart n-type conductivity, such as arsenic or phosphorus, or elements that impart p-type conductivity, such as boron or aluminum, can be used. Alternatively, as the conductive layer 416, conductive materials such as metallic materials, alloy materials, or metal oxide materials can be used.

[0578] Furthermore, since the work function is determined by the material of the conductive layer, the threshold voltage of the transistor can be adjusted by selecting the material of the conductive layer. Specifically, titanium nitride and tantalum nitride, or both, are preferably used as the conductive layer. In order to achieve both conductivity and embeddability, a stack of metal materials, tungsten and aluminum, or both, is preferably used as the conductive layer, especially tungsten in terms of heat resistance.

[0579] To separate the multiple transistors formed on the substrate 410 from each other, a device separation layer 412 is provided. The device separation layer can be formed, for example, using LOCOS (Local Oxidation of Silicon), STI (Shallow Trench Isolation), or mesa isolation.

[0580] Figure 29 An insulating layer 420 and an insulating layer 422 are sequentially stacked on the transistor 400d from the substrate 410 side.

[0581] As insulating layers 420 and 422, for example, one or more selected from silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, and aluminum nitride can be used.

[0582] The insulating layer 422 can also be used as a planarization film to flatten the steps generated by the transistor 400d, etc., which are covered by the insulating layer 420 and the insulating layer 422. For example, in order to improve flatness, the top surface of the insulating layer 422 can also be planarized by a planarization process using CMP or the like.

[0583] A conductive layer 428 is embedded in insulating layers 420 and 422, and is connected to transistors such as MTCK disposed above insulating layer 422. Furthermore, the conductive layer 428 functions as a connector or wiring.

[0584] In the display device 600A, a wiring layer 670 is provided on the transistor 400d. The wiring layer 670 includes, for example, an insulating layer 424, an insulating layer 426, a conductive layer 430, an insulating layer 450, an insulating layer 452, an insulating layer 454, and a conductive layer 456.

[0585] Insulating layers 424 and 426 are sequentially stacked on insulating layer 422 and conductive layer 428. Furthermore, in the region overlapping with conductive layer 428, openings are formed in insulating layers 424 and 426. A conductive layer 430 is embedded within these openings.

[0586] Furthermore, insulating layers 450, 452, and 454 are sequentially stacked on insulating layer 426 and conductive layer 430. Additionally, in the region overlapping with conductive layer 430, openings are formed in insulating layers 450, 452, and 454. Furthermore, conductive layer 456 is embedded within these openings.

[0587] The conductive layers 430 and 456, for example, have the function of a plug or wiring for connecting to the transistor 400d.

[0588] For example, similar to insulating layer 592 described later, insulating layers 424 and 450 preferably use insulating layers having barrier properties selected from one or more of hydrogen, oxygen, and water. Furthermore, similar to insulating layer 594 described later, insulating layers 426, 452, and 454 preferably use insulating layers with relatively low permittivity to reduce parasitic capacitance generated between wirings. In addition, insulating layers 426, 452, and 454 are used as interlayer insulating films and planarization films.

[0589] Furthermore, the conductive layer 456 preferably includes a conductive layer having a barrier effect selected from one or more of hydrogen, oxygen, and water.

[0590] Note that tantalum nitride is preferably used as a hydrogen-barrier conductive layer. Furthermore, by layering tantalum nitride and highly conductive tungsten, not only can the conductivity of the wiring be maintained, but hydrogen diffusion from the transistor 400d can also be suppressed. In this case, the hydrogen-barrier tantalum nitride layer is preferably in contact with the hydrogen-barrier insulating layer 450.

[0591] Furthermore, an insulating layer 513 is disposed above the insulating layer 454 and the conductive layer 456. An insulating layer IS1 is disposed on the insulating layer 513. Furthermore, conductive layers for use as connectors or wiring are embedded in the insulating layers IS1 and 513. Thus, transistor 400d can be electrically connected to the conductive layer 514 disposed in the element layer 630. Alternatively, one of the source and drain of transistor MTCK can be electrically connected to one of the source and drain of transistor 400d.

[0592] A transistor MTCK is disposed on an insulating layer IS1. Furthermore, insulating layers IS3, 574, and 581 are sequentially stacked on the transistor MTCK. Additionally, a conductive layer MPG, serving as a connector or wiring, is embedded within insulating layers IS3, 574, and 581.

[0593] The insulating layer 574 preferably has the function of suppressing the diffusion of impurities such as water and hydrogen (e.g., one or both of hydrogen atoms and hydrogen molecules). In other words, the insulating layer 574 is preferably used as a barrier insulating film to suppress the incorporation of such impurities into the transistor MTCK. Furthermore, the insulating layer 574 preferably has the function of suppressing the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules). For example, the oxygen permeability of the insulating layer 574 is preferably lower than that of the insulating layers IS2 and IS3. The insulating layer 280 of the above embodiment can be used as the insulating layer IS2.

[0594] Therefore, insulating layer 574 is preferably used as a barrier insulating film to inhibit the diffusion of impurities such as water and hydrogen. Thus, insulating layer 574 is preferably made of an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms (making it difficult for the aforementioned impurities to permeate). Alternatively, it is preferable to use an insulating material that has the function of inhibiting the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) (making it difficult for the aforementioned oxygen to permeate).

[0595] As an insulating layer that has the function of suppressing the permeation of impurities such as water and hydrogen and oxygen, the material shown in Embodiment 1 that can be used as an insulating layer with the function of suppressing the permeation of impurities and oxygen can be used.

[0596] Particularly preferred is the use of aluminum oxide or silicon nitride as the insulating layer 574. This suppresses the diffusion of impurities such as water and hydrogen from above the insulating layer 574 to the transistor MTCK. Alternatively, it suppresses the diffusion of oxygen contained in insulating layers such as IS3 from above the insulating layer 574.

[0597] Insulating layer 581 is preferably used as an interlayer film and its dielectric constant is lower than that of insulating layer 574. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, the relative dielectric constant of insulating layer 581 is preferably less than 4, more preferably less than 3. For example, the relative dielectric constant of insulating layer 581 is preferably less than 0.7 times the relative dielectric constant of insulating layer 574, more preferably less than 0.6 times. By using an interlayer film with a low dielectric constant as insulating layer 581, parasitic capacitance generated between wirings can be reduced.

[0598] Furthermore, the concentration of impurities such as water and hydrogen in the insulating layer 581 is preferably reduced. In this case, silicon oxide, silicon oxynitride, silicon oxynitride, or silicon nitride can be used as the insulating layer 581, for example. Furthermore, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide can be used as the insulating layer 581, for example. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferred because they readily form regions containing oxygen released by heating. Furthermore, resin can be used as the insulating layer 581. In addition, combinations of the above-mentioned materials can be appropriately used as materials that can be used in the insulating layer 581.

[0599] Insulating layer 592 and insulating layer 594 are stacked sequentially on insulating layer 574 and insulating layer 581.

[0600] Furthermore, the insulating layer 592 preferably uses a barrier insulating film (referred to as a barrier insulating film) that prevents impurities such as water and hydrogen from diffusing from the substrate 410 and the transistor MTCK to the area above the insulating layer 592 (e.g., the area where light-emitting elements 650R, 650G, and 650B are disposed). Therefore, the insulating layer 592 preferably uses an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (making it difficult for these impurities to permeate). Furthermore, depending on the situation, the insulating layer 592 preferably uses an insulating material that has the function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms (making it difficult for these impurities to permeate). Alternatively, it is preferable to have the function of suppressing the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules).

[0601] As a hydrogen-barrier membrane, silicon nitride formed by CVD can be used, for example.

[0602] The amount of hydrogen removed can be analyzed, for example, using thermal desorption spectrometry (TDS). For instance, in a TDS study with a membrane surface temperature ranging from 50°C to 500°C, when the amount of hydrogen removed (converted to hydrogen atoms) is expressed per unit area of ​​insulating layer 424, the amount of hydrogen removed from insulating layer 424 can be 10 × 10⁻⁶. 15 atoms / cm 2 The following is preferred: 5×10 15 atoms / cm 2 the following.

[0603] Similar to insulating layer 581, insulating layer 594 is preferably an interlayer film with a low dielectric constant. Therefore, insulating layer 594 can use materials that are also suitable for insulating layer 581.

[0604] Furthermore, the dielectric constant of insulating layer 594 is preferably lower than that of insulating layer 592. For example, the relative dielectric constant of insulating layer 594 is preferably less than 4, more preferably less than 3. Additionally, for example, the relative dielectric constant of insulating layer 594 is preferably 0.7 times or less than that of insulating layer 592, more preferably 0.6 times or less. By using an interlayer film with a low dielectric constant as insulating layer 594, parasitic capacitance generated between wirings can be reduced.

[0605] Furthermore, conductive layers MPG, serving as plugs or wiring, are embedded in insulating layers GI1 and IS3, and conductive layers 596, serving as plugs or wiring, are embedded in insulating layers 592 and 594. In particular, conductive layers MPG and 596 are electrically connected to light-emitting elements disposed above insulating layer 594. Note that the same symbol is sometimes used to denote multiple conductive layers serving as plugs or wiring. Furthermore, in this specification, wiring and plugs connected to wiring can also be a single component. That is, a portion of the conductive layer is sometimes used as wiring, and a portion of the conductive layer is sometimes used as a plug. Insulating layer GI1 can be insulating layer 250 as described in the above embodiment.

[0606] The materials used for the plugs and wiring (conductive layer MPG, conductive layer 428, conductive layer 430, conductive layer 456, conductive layer 514, and conductive layer 596) can be single layers or stacks of conductive materials selected from one or more of metallic materials, alloy materials, metal nitride materials, and metal oxide materials. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred; tungsten is particularly preferred. Furthermore, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0607] Insulating layer 598 and insulating layer 599 are sequentially formed on insulating layer 594 and conductive layer 596.

[0608] Similar to insulating layer 592, as an example, insulating layer 598 preferably uses an insulating layer having barrier properties for one or more of hydrogen, oxygen, and water. Furthermore, similar to insulating layer 594, insulating layer 599 preferably uses an insulating layer with a relatively low permittivity to reduce parasitic capacitance generated between wirings. In addition, insulating layer 599 serves as an interlayer insulating film and a planarization film.

[0609] A light-emitting element 650 and a connecting portion 640 are formed on the insulating layer 599.

[0610] The connecting portion 640, sometimes referred to as the cathode contact portion, is electrically connected to the cathode electrode of each of the light-emitting elements 650R, 650G, and 650B. Figure 29In the connecting portion 640 shown, a conductive layer formed using the same process and materials as conductive layers 611a to 611c is electrically connected to the common electrode 615 described later. Although Figure 29 An example is shown in which the conductive layer is electrically connected to the common electrode 615 through the common layer 614 described later, but the conductive layer may also be in direct contact with the common electrode 615.

[0611] The connecting portion 640 can be arranged either around the four sides of the display portion when viewed from a plane, or it can be arranged inside the display portion (for example, between adjacent light-emitting elements 650) (not shown).

[0612] The light-emitting element 650R includes a conductive layer 611a as a pixel electrode. Similarly, the light-emitting element 650G includes a conductive layer 611b as a pixel electrode, and the light-emitting element 650B includes a conductive layer 611c as a pixel electrode.

[0613] The conductive layers 611a, 611b, and 611c are respectively connected to the conductive layer 596 embedded in the insulating layer 594 through the conductive layer (plug) embedded in the insulating layer 599.

[0614] Light-emitting element 650R includes layer 613a, a common layer 614 on layer 613a, and a common electrode 615 on the common layer 614. Furthermore, light-emitting element 650G includes layer 613b, a common layer 614 on layer 613b, and a common electrode 615 on the common layer 614. Furthermore, light-emitting element 650B includes layer 613c, a common layer 614 on layer 613c, and a common electrode 615 on the common layer 614.

[0615] As materials for the pair of electrodes (pixel electrode and common electrode) forming the light-emitting element, metals, alloys, conductive compounds, and mixtures thereof can be appropriately used. Specifically, examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys appropriately combined with them. Furthermore, examples of such materials include indium tin oxide (In-Sn oxide, also known as ITO), In-Si-Sn oxide (also known as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Additionally, examples of such materials include aluminum alloys (alloys containing aluminum, nickel, and lanthanum, such as Al-Ni-La), and silver alloys (alloys containing silver and magnesium, and alloys containing silver, palladium, and copper, such as Ag-Pd-Cu, also known as APC). In addition, as materials, examples include elements belonging to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys of these elements in appropriate combinations, and graphene.

[0616] The 600A display device adopts an SBS structure. The SBS structure allows for optimization of materials and structure for each light-emitting element, increasing the freedom of material and structural selection and making it easier to improve brightness and reliability.

[0617] Furthermore, the display device 600A adopts a top-emitting type. In the top-emitting type, transistors and the like can be arranged in a manner that overlaps with the light-emitting area of ​​the light-emitting element, so the pixel aperture ratio can be further improved compared to the bottom-emitting type.

[0618] Layer 613a is formed to cover the top and side surfaces of conductive layer 611a. Similarly, layer 613b is formed to cover the top and side surfaces of conductive layer 611b. Furthermore, layer 613c is formed to cover the top and side surfaces of conductive layer 611c. Therefore, the entire area where conductive layers 611a, 611b, and 611c are disposed can be used as the light-emitting area of ​​light-emitting elements 650R, 650G, and 650B, thereby improving the pixel aperture ratio.

[0619] In light-emitting element 650R, layer 613a and common layer 614 can be collectively referred to as EL layers. Similarly, in light-emitting element 650G, layer 613b and common layer 614 can be collectively referred to as EL layers. Similarly, in light-emitting element 650B, layer 613c and common layer 614 can be collectively referred to as EL layers.

[0620] The EL layer includes at least a light-emitting layer. The light-emitting layer contains one or more light-emitting materials. Suitable light-emitting materials are those that emit light in colors such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red. Alternatively, materials that emit near-infrared light may also be used as light-emitting materials.

[0621] Light-emitting materials contained in light-emitting elements include, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0622] In addition to the luminescent material (guest material), the luminescent layer may also contain one or more organic compounds (host material, auxiliary material, etc.). As one or more organic compounds, one or both of the following can be used: a material with high hole transport (hole transport material) and a material with high electron transport (electron transport material). Furthermore, as one or more organic compounds, bipolar materials (materials with both high electron and hole transport properties) or TADF materials can also be used.

[0623] In addition to the light-emitting layer, the EL layer may also include one or more of the following: a layer containing a material with high hole injection capability (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking capability (electron blocking layer), a layer containing a material with high electron injection capability (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking capability (hole blocking layer). Furthermore, the EL layer may also include one or both of a bipolar material and a TADF material.

[0624] Light-emitting elements can use low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet printing, and coating.

[0625] Light-emitting elements can be single-structured (with only one light-emitting unit) or series-structured (containing multiple light-emitting units). Each light-emitting unit includes at least one light-emitting layer. A series struct...

Claims

1. A semiconductor device, comprising: The first transistor on the first insulating layer; as well as Second insulating layer, The first transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode on the first insulating layer. The first conductive layer is one of the source electrode and the drain electrode of the first transistor, and the second conductive layer is the other of the source electrode and the drain electrode of the first transistor. The second insulating layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer is disposed on the second insulating layer. The second insulating layer and the second conductive layer are provided with a first opening that reaches the first conductive layer. The semiconductor layer has a first region that contacts the top surface of the first conductive layer in the first opening, a second region that contacts the side surface of the second insulating layer in the first opening, a third region that contacts the side surface of the second conductive layer in the first opening, and a fourth region that contacts the top surface of the second conductive layer. The gate insulating layer is disposed on and in contact with the semiconductor layer. The gate electrode includes a third conductive layer and a fourth conductive layer on the third conductive layer. The third conductive layer has a fifth region that overlaps with the second region across the gate insulating layer, a sixth region that overlaps with the third region across the gate insulating layer, and a seventh region that overlaps with the fourth region across the gate insulating layer. The fourth conductive layer covers the seventh region, the upper end of the first opening, and the vicinity of the upper end. Furthermore, the fourth conductive layer does not cover the area below the upper end of the first opening.

2. The semiconductor device according to claim 1, The first opening has an eighth region with tapered sidewalls and a ninth region with steeper sidewalls compared to the eighth region. The eighth region includes the upper end of the first opening. The ninth region is located below the eighth region. The eighth region includes the side surface of the second conductive layer. Furthermore, the ninth region includes the side surface of the second insulating layer.

3. The semiconductor device according to claim 2, The angle formed between the sidewall of the eighth region and the top surface of the first insulating layer is greater than 20 degrees and less than 75 degrees. Furthermore, the angle formed between the sidewall of the ninth region and the top surface of the first insulating layer is greater than 75 degrees and less than 90 degrees.

4. The semiconductor device according to claim 2 or 3, The lower end of the first opening in the fourth conductive layer is located below the lower end of the eighth region.

5. The semiconductor device according to claim 2 or 3, The lower end of the first opening in the fourth conductive layer is located above the lower end of the eighth region.

6. The semiconductor device according to claim 2, The second insulating layer includes a first layer, a second layer on the first layer, and a third layer on the second layer. The eighth region includes the side surface of the second conductive layer and the side surface of the third layer. Furthermore, the ninth region includes the side surface of the second layer.

7. The semiconductor device according to claim 6, Both the first layer and the third layer are silicon nitride layers. Furthermore, the second layer is a silicon oxide layer or a silicon oxynitride layer.

8. A semiconductor device, comprising: The first transistor on the first insulating layer; as well as Second insulating layer, The first transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode on the first insulating layer. The first conductive layer is one of the source electrode and the drain electrode of the first transistor, and the second conductive layer is the other of the source electrode and the drain electrode of the first transistor. The second insulating layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer is disposed on the second insulating layer. The second insulating layer and the second conductive layer are provided with a first opening that reaches the first conductive layer. The semiconductor layer has a first region that contacts the top surface of the first conductive layer in the first opening, a second region that contacts the side surface of the second insulating layer in the first opening, a third region that contacts the side surface of the second conductive layer in the first opening, and a fourth region that contacts the top surface of the second conductive layer. The gate insulating layer is disposed on and in contact with the semiconductor layer. The gate electrode includes a third conductive layer and a fourth conductive layer on the third conductive layer. The third conductive layer has a fifth region that overlaps with the second region across the gate insulating layer, a sixth region that overlaps with the third region across the gate insulating layer, and a seventh region that overlaps with the fourth region across the gate insulating layer. The fourth conductive layer covers the seventh region, the upper end of the first opening, and the vicinity of the upper end. The fourth conductive layer includes a second opening. Furthermore, the second opening overlaps with the first opening when viewed from above.

9. The semiconductor device according to claim 8, The width of the second opening is smaller than the width of the first opening.

10. The semiconductor device according to claim 8, The first opening has an eighth region with tapered sidewalls and a ninth region with steeper sidewalls compared to the eighth region. The eighth region includes the upper end of the first opening. The ninth region is located below the eighth region. The eighth region includes the side surface of the second conductive layer. Furthermore, the ninth region includes the side surface of the second insulating layer.

11. The semiconductor device according to claim 10, The angle formed between the sidewall of the eighth region and the top surface of the first insulating layer is greater than 20 degrees and less than 75 degrees. Furthermore, the angle formed between the sidewall of the ninth region and the top surface of the first insulating layer is greater than 75 degrees and less than 90 degrees.

12. The semiconductor device according to claim 10 or 11, The lower end of the first opening in the fourth conductive layer is located below the lower end of the eighth region.

13. The semiconductor device according to claim 10 or 11, The lower end of the first opening in the fourth conductive layer is located above the lower end of the eighth region.

14. The semiconductor device according to claim 10, The second insulating layer includes a first layer, a second layer on the first layer, and a third layer on the second layer. The eighth region includes the side surface of the second conductive layer and the side surface of the third layer. Furthermore, the ninth region includes the side surface of the second layer.

15. The semiconductor device according to claim 14, Both the first layer and the third layer are silicon nitride layers. Furthermore, the second layer is a silicon oxide layer or a silicon oxynitride layer.

16. A semiconductor device, comprising: The first transistor on the first insulating layer; Second insulating layer; as well as The third insulating layer, The first transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, a gate insulating layer, and a gate electrode on the first insulating layer. The first conductive layer is one of the source electrode and the drain electrode of the first transistor, and the second conductive layer is the other of the source electrode and the drain electrode of the first transistor. The second insulating layer is disposed between the first conductive layer and the second conductive layer. The second conductive layer is disposed on the second insulating layer. The second insulating layer and the second conductive layer are provided with a first opening that reaches the first conductive layer. The semiconductor layer has a first region that contacts the top surface of the first conductive layer in the first opening, a second region that contacts the side surface of the second insulating layer in the first opening, a third region that contacts the side surface of the second conductive layer in the first opening, and a fourth region that contacts the top surface of the second conductive layer. The gate insulating layer is disposed on and in contact with the semiconductor layer. The gate electrode includes a third conductive layer and a fourth conductive layer on the third conductive layer. The third conductive layer has a fifth region that overlaps with the second region across the gate insulating layer, a sixth region that overlaps with the third region across the gate insulating layer, and a seventh region that overlaps with the fourth region across the gate insulating layer. The fourth conductive layer covers the seventh region, the upper end of the first opening, and the vicinity of the upper end. Furthermore, the third insulating layer has a region that contacts the sixth region, a region that contacts the fourth conductive layer at the upper end of the first opening, and a region that covers the top surface of the second insulating layer through the fourth conductive layer.

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