Integrated circuit device with multi-length gate electrode

Abstract

The IC device includes a gate electrode having a plurality of lengths. A length of a first portion of the gate electrode over a channel region in a semiconductor structure may be longer (e.g., about 0.5-3 nm) than a length of a second portion of the gate electrode over a channel region in another semiconductor structure. The pitch at the two portions of the gate electrode may be the same or substantially similar. Length differentiation of the gate electrode may be achieved by removing dielectric material surrounding the semiconductor structure using dry cleaning. A greater amount of dielectric material may be removed at the first region than at the second region such that the gap at the first region may be longer than the gap at the second region. A conductive material may be provided to fill the gap to form a gate electrode.

Description

Cross Reference to Related Applications

[0001] This application claims the benefit of priority to U.S. Application No. 18 / 333,758, filed June 13, 2023, entitled “INTEGRATED CIRCUIT DEVICE WITH MULTI-LENGTH GATE ELECTRODE,” which is hereby incorporated by reference in its entirety. BACKGROUND

[0002] Integrated circuit (IC) fabrication typically includes two phases. The first phase is referred to as front-end-of-line (FEOL). The second phase is referred to as back-end-of-line (BEOL). In FEOL, various semiconductor device components (e.g., transistors, capacitors, resistors, etc.) can be patterned in a wafer. In BEOL, metal layers, vias, and insulating layers can be formed to interconnect the various components. BEOL typically begins with the formation of a first metal layer on a wafer. The first metal layer is often referred to as M0. More metal layers can be formed on top of M0, and these metal layers are often referred to as Ml, M2, etc.

[0003] Standard cell methodology is a popular method of designing IC devices (e.g., application specific ICs). Standard cells can provide logic functionality (e.g., AND, OR, XOR, etc.), storage functionality (e.g., flip-flops, latches, etc.), other types of functionality, or some combination thereof. A standard cell typically includes a set of transistors and interconnect structures, such as a set of parallel gate electrodes stacked on top of each other along a horizontal axis of the standard cell. The width of a standard cell can depend on the number of gate electrodes along the horizontal axis of the standard cell. The distance between two immediately adjacent gate electrodes along the horizontal axis of the standard cell can be referred to as the contact poly pitch (CPP). BRIEF DESCRIPTION OF DRAWINGS

[0004] The embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For purposes of description herein, the same reference numerals are used in the drawings and the detailed description to indicate the same elements. Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which:

[0005] Figure 1 is a perspective view of an IC device with multi-length gate electrodes in accordance with some embodiments of the present disclosure.

[0006] Figure 2 shows an IC device with a FEOL portion having multi-length gate electrodes and a BEOL portion in accordance with some embodiments of the present disclosure.

[0007] Figure 3A and 3Bis a cross-sectional view of an IC device with a multi-length gate electrode according to some embodiments of the present disclosure.

[0008] Figure 4 is a top view of an IC device with a multi-length gate electrode according to some embodiments of the present disclosure.

[0009] Figures 5A-5L shows a process of fabricating an IC device with a multi-length gate electrode according to some embodiments of the present disclosure.

[0010] Figures 6A-6B is a top view of a wafer and die that can facilitate one or more IC devices with a multi-length gate electrode according to some embodiments of the present disclosure.

[0011] Figure 7 is a side cross-sectional view of an example IC package that can include one or more IC devices with a multi-length gate electrode according to some embodiments of the present disclosure.

[0012] Figure 8 is a cross-sectional side view of an IC device assembly that can include components with one or more IC devices with a multi-length gate electrode according to some embodiments of the present disclosure.

[0013] Figure 9 is a block diagram of an example computing device that can include one or more components with one or more IC devices with a multi-length gate electrode according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] The systems, methods, and devices of the present disclosure each have several innovative aspects, no single one of which is solely responsible for the overall inventiveness. The details of one or more implementations of the subject matter described in this specification are set forth in the description below.

[0015] The size of the gate electrode in the direction along the horizontal axis of the standard cell is often referred to as the length of the gate electrode or gate length Lg. The gate length can be the distance between the source region and the drain region of the transistor. Adjustment of the gate length in the same CPP is typically done by changing the thickness of the self-aligned double patterning (SADP) spacer (also referred to as the "gate spacer"). However, spacer adjustment can create more complexity in the SADP process. Spacer adjustment also has a limit of minimum thickness gap. It can also cause source-drain opening width difference, which can cause variation in epitaxial growth. One solution is to use additional thin spacer deposition to increase the gate length. However, due to the lower thickness limit of the spacer deposition process, adding a thin spacer can limit the minimum Lg increment. Another solution is to use a trimming (e.g., etching) process to thin the SADP spacer to reduce the gate length. However, SADP spacer trimming can cause a significant increase in SADP spacer thickness variation, which in turn can cause Lg variation.

[0016] Embodiments of the present disclosure can improve at least some of the above challenges and issues by providing an IC device including a multi-length gate electrode. An example multi-length gate electrode has two or more different lengths. For example, a portion of the multi-length gate electrode has a length that is greater than another portion of the multi-length gate electrode. The length difference can be facilitated by a spacer thinning process based on dry cleaning. For example, more dry cleaning steps in the spacer thinning process can be employed to obtain a greater gate length, while less dry cleaning steps are employed for a smaller gate length. The etch selectivity of the spacer thinning process based on dry cleaning can control the consumption of the sidewall of the gate spacer. Block patterning can be used to determine the etch area for each removal step.

[0017] In various embodiments of the present disclosure, an IC device can include a gate electrode having multiple lengths. For example, a first portion of the gate electrode has a length that is greater than a second portion of the gate electrode. The first portion of the gate electrode can be over a channel region in a semiconductor structure in the IC device. The second portion of the gate electrode can be over a channel region in another semiconductor structure in the IC device. The difference between the two lengths of the gate electrode can be in a range from about 0.5 nanometers (nm) to about 3 nm. A distance from the first portion of the gate electrode to another gate electrode (e.g., gate pitch) can be the same or substantially similar to a distance from the second portion of the gate electrode to another gate electrode. A size of a shallow trench isolation (STI) region under the first portion of the gate electrode can be less than a corresponding size of an STI region under the second portion of the gate electrode. Additionally or alternatively, a size of a gate insulator between the first portion of the gate electrode and the semiconductor structure can be less than a corresponding size of a gate insulator between the second portion of the gate electrode and the other semiconductor structure.

[0018] In some embodiments, an IC device can be formed by, for example, forming semiconductor structures over a substrate. The semiconductor structures can be planar structures or non-planar structures (e.g., fins, nanoribbons, etc.). A gate spacer can be formed to at least partially surround each semiconductor structure. The gate spacer includes a dielectric material such as an oxide. An open trench can exist between two adjacent semiconductor structures. A surface of the gate spacer can face the semiconductor structures, and an opposite surface of the gate spacer can face the open trench. The length of the open trench can be adjusted by controlling how much of the dielectric material is removed from the gate spacer using dry cleaning. In a first removal step of a spacer thinning process, dry cleaning is applied to a target region of the gate spacer. In subsequent removal steps of the spacer thinning process, dry cleaning is applied to a portion of the target region but not to the remaining portion of the target region. In this way, the portion of the gate spacer that goes through multiple removal steps will be thinner than the remaining portion of the gate spacer. This spacer thinning process can result in open trenches of multiple lengths. After the removal process, a conductive material can be provided to fill the open trenches to form at least a partial gate electrode. Because the open trenches have multiple lengths, the gate electrode can have multiple lengths.

[0019] The removal process in the present disclosure can enable Lg adjustment in a manufacturing flow without causing a change in source-drain trench width. Furthermore, the present disclosure can enable more precise Lg control (e.g., below about 2 nm) by using the inner sidewall of the spacer trim. There is also no complexity of SADP, resulting in better variable control of dummy poly trunk patterning.

[0020] It is noted that in some settings, the term “nanoribbon” has been used to describe an elongated semiconductor structure having a substantially rectangular transverse cross-section (e.g., in a plane perpendicular to the longitudinal axis of the structure), while the term “nanowire” has been used to describe a similar structure but having a substantially circular or square transverse cross-section. Hereinafter, the single term “nanoribbon” is used to describe an elongated semiconductor structure regardless of the shape of the transverse cross-section. Thus, as used herein, the term “nanoribbon” is used to encompass an elongated semiconductor structure having a substantially rectangular transverse cross-section (possibly with rounded corners), an elongated semiconductor structure having a substantially square transverse cross-section (possibly with rounded corners), an elongated semiconductor structure having a substantially circular or elliptical / ovular transverse cross-section, and an elongated semiconductor structure having a transverse cross-section of any polygonal shape.

[0021] In the following, some descriptions can refer to a particular source or drain (S / D) region or contact as a source region / contact or a drain region / contact. However, which region / contact of a transistor or diode is considered to be the source region / contact and which region / contact is considered to be the drain region / contact is not important unless otherwise noted, as the designation of source and drain is generally interchangeable as is common in the field of field effect transistors (FETs). Thus, the description of some illustrative embodiments of source and drain regions / contacts provided herein apply to embodiments where the designation of source and drain regions / contacts can be reversed.

[0022] As used herein, the term “metal layer” can refer to a layer above a substrate that includes electrically conductive interconnect structures for providing electrical connectivity between different IC components. The metal layers described herein can also be referred to as “interconnect layers” to clearly indicate that these layers include electrically conductive interconnect structures that can but need not be metal.

[0023] The systems, methods, and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the overall inventiveness of the disclosure disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below.

[0024] In the following detailed description, various aspects of the illustrative implementations can be described using terminology commonly employed by those skilled in the art such as, for example, the terms “connect” or “couple.” As used in the present disclosure, the terms “connect” or “couple” refer to an electrical or magnetic connection or link between the things that are connected or coupled and, unless otherwise indicated, are not intended to mean that any intermediate device or devices are necessarily present in an electrical circuit or magnetic coupling between the things that are connected or coupled. The term “circuit” refers to one or more passive and / or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms “oxide,” “carbide,” “nitride,” and the like refer to compounds containing oxygen, carbon, nitrogen, and the like, respectively, the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, and the term “low-k dielectric” refers to a material having a lower k than silicon oxide. The terms “substantially,” “approximately,” “about,” “near,” and “around” generally mean to within + / - 10% of a particular value, such as within + / - 5% of a particular value or within + / - 2% of a particular value, based on the context of the particular value as described herein or as known in the art. Similarly, the terms indicating orientation of various elements (e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between elements) generally mean to within + / - 8% of a particular value, such as within + / - 5% of a particular value or within + / - 2% of a particular value, based on the context of the particular value as described herein or as known in the art. Furthermore, the term “or” refers to an inclusive “or” rather than an exclusive “or.”

[0025] The terms "over," "under," "between," and "on," as used herein refer to a relative positioning of one material layer or component with respect to other layers or components. For example, a layer disposed over or under another layer can be directly in contact with the other layer or can have one or more intervening layers. Moreover, a layer that is disposed between two layers can be directly in contact with the two layers, or can have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless otherwise specifically stated, a feature that is positioned between two features can be directly in contact with the adjacent features or can have one or more intervening layers.

[0026] For purposes of the present disclosure, the phrase "A and / or B" or the phrase "A or B" means (A), (B), or (A and B). For purposes of the present disclosure, the phrase "A, B, and / or C" or the phrase "A, B, or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). When used with a measurement range, the term "between" includes the end point values of the measurement range. As used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0027] The description can use the phrases "in an embodiment," or "in embodiments," which can each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "containing," etc. shall be construed as open-ended. The disclosure can use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are employed for convenience, and thus, they can not necessarily describe absolute position. The appended drawings are not necessarily to scale. Unless otherwise indicated, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either in time, in space, in ranking, or in any other manner.

[0028] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown, by way of illustration, embodiments that can be implemented. It is understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For the purpose of convenience and clarity in the Figure 7 A-7B, then such a collection can be referred to herein without the use of a letter, e.g., as "A-7." Figure 7

[0029] ​In the drawings, some schematic diagrams of example structures of various devices and components described herein can be shown in precise right angles and straight lines, but it should be understood that such schematic diagrams can not reflect real process limitations, which can cause features to appear not so “ideal” when any of the structures described herein are examined using, for example, scanning electron microscope (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects can also be visible, for example, imperfectly straight edges of material, tapered vias or other openings, unintentional rounding of corners, or variations in thickness of different material layers, incidental screw dislocations within crystalline regions, edge dislocations or combined dislocations, and / or incidental dislocation defects of single atoms or clusters of atoms. Other defects not listed here can be present but are common in the art of device manufacturing. Examining the layout and mask data using, for example, an optical microscope, TEM, or SEM and reverse engineering components of the device to reconstruct the circuit, and / or examining cross sections of the device using, for example, physical failure analysis (PFA) to detect shapes and locations of various device elements described herein will allow determination of whether an IC device with multiple length gate electrodes as described herein is present.

[0030] Various operations can be described as multiple discrete actions or operations, in turn, in a manner that can most benefit the understanding of the claimed subject matter. The

[0031] Various IC devices with multiple length gate electrodes as described herein can be implemented in or associated with one or more components associated with an IC, or / and can be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC can include components mounted on the IC or components connected to the IC. Depending on the components associated with an IC, the IC can be analog or digital, and can be used for a variety of applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc. The IC can be used as part of a chipset for performing one or more related functions in a computer.

[0032] Figure 1 is a perspective view of an IC device 100 with multiple length gate electrodes 140 according to some embodiments of the present disclosure. The IC device 100 also includes a support structure 110, a dielectric layer 120, and a plurality of semiconductor structures 130 (referred to as “semiconductor structures 130” respectively). For illustration purposes, inFigure 1 Not all components of IC device 100 are shown. IC device 100 may include different, fewer, or more components. For example, IC device 100 may include in Figure 1 Gate insulators or spacers not shown.

[0033] The support structure 110 can be any suitable structure, such as a substrate, die, wafer, or chip, upon which transistors can be constructed. The support structure 110 can be, for example, as discussed below. Figure 6A The wafer 2000, and can be a die or included in a die, as discussed below. Figure 6B The die 2002 is a single-element die. In some embodiments, the support structure 110 may be a semiconductor substrate made of a semiconductor material system, including, for example, an N-type or P-type material system, and in some embodiments, the channel region described herein may be part of the support structure 110. In some embodiments, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or silicon-on-insulator substructures. In other embodiments, the semiconductor substrate may be formed using alternative materials, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-V, II-VI, or IV group materials. In some embodiments, the substrate may be amorphous. In some embodiments, the support structure may be a printed circuit board (PCB) substrate. One or more transistors, such as transistor 170, may be constructed on the support structure 110.

[0034] While some examples of materials that can form the support structure 110 are described herein, any material that can be used as the basis on which an IC can be built falls within the spirit and scope of this disclosure. In various embodiments, the support structure 110 may include any such substrate, possibly having some layers and / or devices already formed thereon, not specifically shown in this figure. As used herein, the term "support" does not necessarily mean that it provides mechanical support for IC devices / structures (e.g., transistors, capacitors, interconnects, etc.) built thereon. For example, some other structures (e.g., carrier substrates or packaging substrates) may provide such mechanical support, and the support structure 110 may provide material "support" because, for example, the IC devices / structures described herein are built based on the semiconductor material of the support structure 110. However, in some embodiments, the support structure 110 may provide mechanical support.

[0035] A dielectric layer 120 is positioned along the Z-axis over various portions of the support structure 110. The dielectric layer 120 comprises one or more dielectric materials, such as oxides or other low-k dielectric materials. Example oxides in the dielectric layer may include silicon oxide (SiO), silicon oxycarbide (SiOC), silicon oxycarbonide (SiOCN), etc. The dielectric layer 120 includes a plurality of dielectric structures 125 (referred to as "dielectric structures 125"). Each dielectric structure 125 is positioned along the Z-axis over a corresponding portion of the support structure 110. Dielectric structures 124 may be positioned along the X-axis between two semiconductor structures 130. The dielectric structures 125 may be STI structures, which provide electrical isolation between adjacent transistors. The dielectric structures 125 can be formed by etching shallow trenches into the substrate and filling the shallow trenches with a dielectric material.

[0036] The semiconductor structure 130 is located on top of the support structure 110. Figure 1 In one embodiment, the semiconductor structure 130 has a fin-like shape, having a longitudinal axis substantially parallel to the Y-axis and a transverse cross-section substantially parallel to the XZ plane. The dimension of the semiconductor structure 130 along the Y-axis may be larger than its dimension in the other direction. The semiconductor structures 130 are arranged parallel to each other and stacked along the X-axis. Two adjacent semiconductor structures 130 are partially separated by a dielectric structure 125 between them. In other embodiments, the semiconductor structure 130 may have different shapes, such as nanoribbons, other non-planar shapes, or planar shapes.

[0037] Semiconductor structure 130 may provide at least one source region, channel region, and drain region of a transistor. The channel region of the transistor may include a channel material. The channel material may consist of a semiconductor material system, including, for example, an N-type or P-type material system. In some embodiments, the channel material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the channel material may include a compound semiconductor having a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In some embodiments, the channel material may include a compound semiconductor having a first sublattice of at least one element from Group II of the periodic table (e.g., Zn, Cd, Hg) and a second sublattice of at least one element from Group IV of the periodic table (e.g., C, Si, Ge, Sn, Pb). In some embodiments, the channel material is an epitaxial semiconductor material deposited using an epitaxial deposition process. Epitaxial semiconductor materials can have polycrystalline structures with grain sizes between approximately 2 nm and 100 nm (inclusive of all values ​​and ranges therein).

[0038] For some example N-type transistor embodiments (i.e., embodiments where the transistor is an NMOS (N-type metal-oxide-semiconductor) transistor or an N-type TFET), the channel material may advantageously comprise a III-V material with high electron mobility, such as, but not limited to, InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InxGaAs-xAs fin embodiments, the In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., ln 0.7 Ga 0.3 As). In some embodiments with the highest mobility, the channel material can be an intrinsic III-V material, i.e., a III-V semiconductor material that is not intentionally doped with any electroactive impurities. In alternative embodiments, a nominal impurity dopant level can be present within the channel material, for example, to further fine-tune the threshold voltage Vt, or to provide HALO pocket injection, etc. However, even for impurity-doped embodiments, the impurity dopant level within the channel material can be relatively low, for example, below 10. 15 One dopant atom per cubic centimeter (cm³) -3 ), and advantageously below 10 13 cm -3These materials can be amorphous or polycrystalline, for example, having grain sizes between 0.5 nanometers and 100 nanometers.

[0039] For some example P-type transistor embodiments (i.e., embodiments where the transistor is a PMOS (P-type metal-oxide-semiconductor) transistor or a P-type TFET), the channel material can advantageously be a group IV material with high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some example embodiments, the channel material can have a Ge content between 0.6 and 0.9%, and advantageously at least 0.7%. In some embodiments with the highest mobility, the channel material can be an intrinsic group III-V (or group IV for P-type devices) material, without intentionally doped with any electroactive impurities. In alternative embodiments, one or more nominal impurity dopant levels can be present within the channel material, for example, to further set the threshold voltage (Vt) or to provide HALO pocket injection, etc. However, even for impurity-doped embodiments, the impurity dopant level within the channel portion is relatively low, for example, below 10%. 15 cm -3 And advantageously below 10 13 cm -3 These materials can be amorphous or polycrystalline, for example, having grain sizes between 0.5 nanometers and 100 nanometers.

[0040] In some embodiments, the channel material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, zinc aluminum oxide, or tungsten oxide. Typically, for thin-film transistors (TFTs), the channel material can include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, molybdenum disulfide, n- or p-type amorphous or polycrystalline silicon, monocrystalline silicon, germanium, indium arsenide, indium gallium arsenide, indium selenide, indium antimonide, zinc antimonide, antimony selenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphite, black phosphorus, zinc sulfide, indium sulfide, gallium sulfide, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium. In some embodiments, thin-film channel material can be deposited at relatively low temperatures, which allows the channel material to be deposited within the thermal budget imposed on back-end manufacturing to avoid damage to other components, such as front-end components of logic devices.

[0041] As mentioned above, channel materials can include IGZO. IGZO-based devices possess several desirable electrical and manufacturing characteristics. Compared to other semiconductors, IGZO exhibits high electron mobility, for example, in the range of 20-50 times that of amorphous silicon. Furthermore, amorphous IGZO (a-IGZO) transistors typically offer higher band gaps, lower temperature process compatibility, and lower manufacturing costs compared to other semiconductors.

[0042] IGZO can be deposited as a uniform amorphous phase while maintaining a higher carrier mobility than oxide semiconductors such as zinc oxide. Different IGZO formulations include varying ratios of indium oxide, gallium oxide, and zinc oxide. One particular form of IGZO has the chemical formula lnGaO3(ZnO)5. Another example form of IGZO has an indium:gallium:zinc ratio of 1:2:1. In various other examples, IGZO can have a gallium:indium ratio of 1:1, a gallium:indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), and / or a gallium:indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). IGZO can also contain a third dopant, such as aluminum or nitrogen.

[0043] In a transistor, the source and drain regions are connected to the channel region. The source and drain regions may each comprise a semiconductor material with dopant. In some embodiments, the source and drain regions have the same semiconductor material, which may be the same as the channel material of the channel region. The semiconductor material of the source or drain region may be a group IV material, a compound of a group IV material, a group III / V material, a compound of a group III / V material, a group II / VI material, a compound of a group II / VI material, or other semiconductor materials. Examples of group II materials include zinc (Zn), cadmium (Cd), etc. Examples of group III materials include aluminum (Al), boron (B), indium (In), gallium (Ga), etc. Examples of group IV materials include silicon (Si), germanium (Ge), carbon (C), etc. Examples of group V materials include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), etc. Examples of group VI materials include sulfur (S), selenium (Se), tellurium (Te), oxygen (O), etc. Compounds of group IV materials may be binary compounds, such as SiC, SiGe, etc. Group III / V materials can be binary, ternary, or quaternary compounds, such as GaN and InN. Group II / VI materials can also be binary, ternary, or quaternary compounds, such as CdSe, CdS, CdTe, ZnO, ZnSe, ZnS, ZnTe, CdZnTe, CZT, HgCdTe, and HgZnTe.

[0044] In some embodiments, the dopants in the source and drain regions are of the same type. In other embodiments, the dopants in the source and drain regions can be of different (e.g., opposite) types. In one example, the source region has an N-type dopant and the drain region has a P-type dopant. In another example, the source region has a P-type dopant and the drain region has an N-type dopant. Example N-type dopants include Te, S, As, tin (Sn), Si, Ga, Se, S, In, Al, Cd, chlorine (Cl), iodine (I), fluorine (F), etc. Example P-type dopants include beryllium (Be), Zn, magnesium (Mg), Sn, P, Te, lithium (Li), sodium (Na), Ga, Cd, etc.

[0045] In some embodiments, the source and drain regions may be highly doped, for example, having about 1.10... 21 cm -3 The dopant concentration is adjusted to favorably form ohmic contacts with the corresponding S / D contacts (sometimes interchangeably referred to as "S / D electrodes"), although in some embodiments these regions may also have lower dopant concentrations and may form Schottky contacts. Regardless of the exact doping level, the source and drain regions can be regions with higher dopant concentrations than other regions (e.g., higher dopant concentrations than the channel region), and thus may be referred to as "highly doped" (HD) regions.

[0046] The channel region may include one or more semiconductor materials with a doping concentration significantly lower than that of the source and drain regions. For example, in some embodiments, the channel material of the channel region may be an intrinsic (e.g., undoped) semiconductor material or alloy that is not intentionally doped with any electrically active impurities. In alternative embodiments, a nominal impurity dopant level may be present within the channel material, for example, to set the threshold voltage Vt or to provide HALO pocket injection, etc. However, in such impurity-doped embodiments, the impurity dopant level within the channel material is still significantly lower than the dopant levels in the source and drain regions, for example, below 10⁻⁶. 15 cm -3 or below 10 13 cm -3 Depending on the context, the term "S / D terminal" can refer to the S / D region of a transistor or an S / D contact or electrode.

[0047] A multi-length gate electrode 140 is located above the dielectric layer 120. Figure 1In this configuration, a multi-length gate electrode 140 surrounds a semiconductor structure 130. The multi-length gate electrode 140 and the semiconductor structure 130 can form a full-ring gate transistor. The multi-length gate electrode 140 has a longitudinal axis substantially parallel to the X-axis. The multi-length gate electrode 140 has two portions: a conductive region 150 with a length of 155 and a conductive region 160 with a length of 165. Lengths 155 and 165 are two different gate lengths of the multi-length gate electrode 140. Length 155 or 165 can be the distance between the source and drain regions in the semiconductor structure 130 along the Y-axis, or it can be the length of the channel region in the semiconductor structure 130. The two lengths 155 and 165 are different. Length 165 is greater than length 155. In some embodiments, length 165 is approximately 0.5 to 3 nm. Even if not in Figure 1 As shown, the portion of the dielectric layer below the conductive region 150 may have a smaller Z-axis dimension than the corresponding Z-axis dimension of another portion of the dielectric layer below the conductive region 160. In some embodiments, the multi-length gate electrode 140 may include two or more different gate lengths.

[0048] The multi-length gate electrode 140 includes one or more conductive materials, such as metals, polysilicon, other types of conductive materials, or combinations thereof. In some embodiments, the selection of the conductive material in the multi-length gate electrode 140 may depend on whether the transistor is a P-type transistor or an N-type transistor. For P-type transistors, gate electrode materials that can be used in different portions of the gate electrode may include, but are not limited to, Ru, palladium, platinum, Co, nickel, and conductive metal oxides (e.g., ruthenium oxide). For N-type transistors, gate electrode materials that can be used in different portions of the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0049] In some embodiments, the multi-length gate electrode 140 may include a stack of multiple gate electrode materials, wherein zero or more of the materials in the stack are work-function materials, and at least one material in the stack is a filler metal layer. For other purposes, other materials / layers may be included alongside the gate electrode, such as diffusion barrier layers and / or adhesive layers.

[0050] The multi-length gate electrode 140 can be electrically coupled to a power plane, ground plane, or signal plane to facilitate power or signal transmission of the transistor. The power plane, ground plane, or signal plane can be a metal layer (or a portion of a metal layer, such as a metal rail), which can be along the Z-axis above the multi-length gate electrode 140, for example, above the multi-length gate electrode 140 (e.g., a front metal layer) or below the support structure 110 (e.g., a back metal layer). Although in Figure 1Although not shown, IC device 100 may include one or more other gate electrodes, which may be multi-length gate electrodes. The gate electrode may be a dummy gate electrode, which may not be coupled to any power plane, ground plane, or signal plane.

[0051] Figure 2 An IC device 200 with a FEOL portion 201 and a BEOL portion 202 according to some embodiments of the present disclosure is shown, the FEOL portion 201 having a multi-length gate electrode. For illustrative purposes, Figure 2 A cross-sectional view of the IC device 200 in the XZ plane is shown. The FEOL portion 201 includes a support structure 210, a dielectric layer 220, a semiconductor structure 230, a gate electrode 240, and a gate insulator 250. The BEOL portion 202 includes metal layers 260, 270, and 280, vias 265, 275, and 285, and an electrical insulator 290. In other embodiments, the IC device 200 may include fewer, more, or different components. For example, the FEOL portion 201 may include more transistors or other types of semiconductor devices, such as resistors, capacitors, inductors, etc. Furthermore, the BEOL portion 202 may include different numbers of metal layers or different numbers of vias.

[0052] The support structure 210 includes one or more semiconductor materials. In some embodiments, the support structure 210 may be a semiconductor substrate. Figure 1 An embodiment of the support structure 110. The dielectric layer 220 comprises one or more dielectric materials, such as oxides. The dielectric layer 220 may be... Figure 1 An embodiment of the dielectric layer 220 in [the structure]. For example... Figure 2 As shown, the dielectric layer 220 has two different depths, 225 and 227, along the Z-axis. Depth 225 is smaller than depth 227. In some embodiments, the difference between the two depths 225 and 227 can be in the range of about 1 nm to about 10 nm.

[0053] Semiconductor structure 230 is situated on support structure 210. In some embodiments, semiconductor structure 230 can be formed based on support structure 210, for example, by epitaxial deposition. Semiconductor structure 230 can provide a source region, a drain region, and a channel region for at least one transistor. For example, the portion of semiconductor structure 230 below gate electrode 240 can be a channel region. The region surrounding the channel region can be a source region and a drain region. Embodiments of semiconductor structure 230 may include... Figure 1 One of the semiconductor structures in 130.

[0054] The gate electrode 240 is conductive. For example... Figure 2As shown, the gate electrode 240 at least partially surrounds the semiconductor structure 230. Various portions of the gate electrode 240 lie on the semiconductor structure 230. Other portions of the gate electrode 240 lie on the dielectric layer 220. The gate electrode 240 may have multiple different lengths. In some embodiments, the length of the portion of the gate electrode 240 above the portion of the dielectric layer 220 having a height 225 is less than the length of the portion of the gate electrode 240 above the portion of the dielectric layer 220 having a height 227. Embodiments of the gate electrode 240 may include... Figure 1 The multi-length gate electrode 140 in the middle.

[0055] In some embodiments, height 225 may be greater than height 235 of the active portion of semiconductor structure 230 (e.g., the portion surrounded by gate electrode 240). Height 225 may be approximately twice the height 235. In an example, height 225 may be approximately 100 nm, and height 235 may be in the range of approximately 40 nm to 60 nm.

[0056] The semiconductor structure 230 is also partially surrounded by a gate insulator 250. The gate insulator 250 separates the semiconductor structure 230 from the gate electrode 240. Figure 2 As shown, a gate insulator 250 is located between each semiconductor structure 230 and the gate electrode 240. In some embodiments, the thickness of the gate insulator 250 above different semiconductor structures 230 (or below different portions of the gate electrode 240) may be different. For example, the thickness of the gate insulator 250 below a longer portion of the gate electrode 240 may be less than the thickness of the gate insulator 250 below a shorter portion of the gate electrode 240. The gate insulator 250 includes one or more electrical insulators (e.g., dielectric materials, hysteresis materials, etc.). Example dielectric materials include oxides (e.g., Si-based oxides, metal oxides, etc.), high-k dielectrics, etc. Example hysteresis materials include ferroelectric materials, antiferroelectric materials, etc.

[0057] Metal layers 260, 270, and 280 can facilitate the supply of electrical signals to transistors or other devices (e.g., diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc.) in the FEOL section 201. In some embodiments, at least one of metal layers 260, 270, and 280 can be electrically coupled to the gate electrode 240 for power or signal transmission. Even in Figure 2As not shown, metal layers 260, 270, or 280 may be electrically coupled to trench electrodes over the source or drain regions of semiconductor structure 230. Metal layers 260, 270, or 280 may have one or more conductive materials, such as metals. Metal layers 260, 270, or 280 may include one or more metal rails parallel to each other and separated from each other by an electrical insulator 290. In some embodiments, metal layer 260 may be M2, metal layer 270 may be M1, and metal layer 280 may be M0. The metal rails in metal layer 260 may have a longitudinal axis substantially perpendicular to the longitudinal axis of the metal rails in metal layers 270 or 280. The metal rails in metal layer 270 may have a longitudinal axis substantially perpendicular to the longitudinal axis of the metal rails in metal layer 280.

[0058] Vias 265, 275, and 285 may provide a conductive path between metal layers 260, 270, and 280, or between at least one of metal layers 260, 270, and 280 and a device or structure in FEOL portion 201. Each of vias 265, 275, and 285 may include one or more conductive materials, such as metals. Examples of metals include tungsten (W), molybdenum (Mo), ruthenium (Ru), or other metals.

[0059] Metal layers 260, 270, and 280, as well as vias 265, 275, and 285, may be partially or entirely surrounded by electrical insulator 290. Certain portions of metal layers 260, 270, and 280, as well as vias 265, 275, and 285, may be insulated by electrical insulator 290. Electrical insulator 290 may include one or more electrical insulators. The electrical insulator may be a dielectric material, a hysteretic material, etc. Example dielectric materials include oxides (e.g., Si-based oxides, metal oxides, etc.), low-k dielectrics, high-k dielectrics, etc. Example hysteretic materials include ferroelectric materials, antiferroelectric materials, etc.

[0060] Figure 3A and 3B This is a cross-sectional view of an IC device having a multi-length gate electrode 330 according to some embodiments of the present disclosure. Figure 3A The cross-section 300A of the IC device is shown. Figure 3B Cross-section 300B of the IC device is shown. Cross-sections 300A and 300B can be substantially parallel to the YZ plane. Cross-section 300A can be located at the portion of the multi-length gate electrode having a length greater than the nominal gate length, and cross-section 300B can be located at the portion of the multi-length gate electrode having the nominal gate length. For illustrative purposes, Figure 3A and 3B Not all components of IC device 300 may be shown.

[0061] Section 300A shows a support structure 310, a semiconductor structure 330A, an electrical insulator 335, a conductive structure 340A, a dielectric structure 345A (referred to as "dielectric structure 345A"), an electrical insulator 347, a gate insulator 350A, metal layers 360, 370, and 380, and an electrical insulator 390. Section 300B shows a support structure 310, a semiconductor structure 330B, an electrical insulator 335, a conductive structure 340B, a dielectric structure 345B (referred to as "dielectric structure 345B"), an electrical insulator 347, a gate insulator 350B, metal layers 360, 370, and 380, and an electrical insulator 390. In other embodiments, different, fewer, or more components of the IC device 300 may be visible in sections 300A or 300B.

[0062] Support structure 310 can be Figure 1 Support structure 110 or Figure 2 An embodiment of the support structure 210. Semiconductor structures 330A and 330B can be formed based on the support structure 310. Semiconductor structures 330A and 330B can be formed, for example, through an STI structure (e.g., Figure 1 The dielectric structures 145 in the semiconductor are separated from each other. In some embodiments, semiconductor structures 330A and 330B may be substantially parallel. Embodiments of semiconductor structures 330A or 330B may be... Figure 1 One of the semiconductor structures 130 or Figure 2 One of the semiconductor structures 230 in the example. Metal layers 360, 370, or 380 can be... Figure 2 Examples of metal layers 260, 270, or 280. Electrical insulator 390 may be... Figure 2 An embodiment of the electrical insulator 290 in the example.

[0063] Conductive structures 340A and 340B are two distinct portions of a multi-length gate electrode. The length of conductive structure 340A along the Y-axis is greater than the length of conductive structure 340B along the Y-axis. In some embodiments, the difference between the two lengths can be a maximum of about 3 nm. The length difference can be no less than 0.5 nm. In some embodiments, conductive structures 340A and 340B can be separate structures. Furthermore, conductive structures 340A and 340B can be made of different conductive materials. In other embodiments, the multi-length gate electrode can be an integrated structure.

[0064] A conductive structure 340A is located between two dielectric structures 345A. Similarly, a conductive structure 340B is located between two dielectric structures 345B. Dielectric structures 345A or 345B may include one or more dielectric materials, such as oxides. Dielectric structures 345A or 345B may be gate spacers. In some embodiments, a pair of dielectric structures 345A and 345B may be part of an integrated dielectric structure. Figure 3A and 3B As shown, the length of dielectric structure 345A along the Y-axis is less than the length of dielectric structure 345B along the Y-axis.

[0065] In some embodiments, the lengths of dielectric structures 345A and 345B can be adjusted to obtain the desired lengths of conductive structures 340A and 340B. For example, dielectric structures 345A or 345B can be formed, for example, by dry-cleaning etching of pre-formed dielectric structures. More etching steps than those used for dielectric structure 345B can be used to form dielectric structure 345A to achieve a smaller length of dielectric structure 345A. Furthermore, conductive structures 340A are formed in the gaps between dielectric structures 345A, and conductive structures 340B are formed in the gaps between dielectric structures 345B.

[0066] The gate insulator 350A separates the conductive structure 340A from the semiconductor structure 330A. Figure 3A In one embodiment, a gate insulator 350A surrounds the conductive structure 340A and separates the conductive structure 340A from the dielectric structure 345A. In other embodiments, the gate insulator 350A may not be present between the conductive structure 340A and the dielectric structure 345A. Similarly, a gate insulator 350B separates the conductive structure 340B from the semiconductor structure 330B. Figure 3B In one embodiment, the gate insulator 350B surrounds the conductive structure 340B and separates the conductive structure 340B from the dielectric structure 345B. In other embodiments, the gate insulator 350B may not be present between the conductive structure 340B and the dielectric structure 345B.

[0067] like Figure 3A and Figure 3B As shown, the Z-axis dimension of the portion of the gate insulator 350A between the conductive structure 340A and the semiconductor structure 330A is smaller than the corresponding dimension of the portion of the gate insulator 350A between the conductive structure 340A and the semiconductor structure 330A. In some embodiments, the smaller dimension of the gate insulator 350A may be caused by additional etching steps for forming the dielectric structure 345A. The gate insulator 350A or 350B may include one or more electrical insulators. The gate insulator 350A or 350B may beFigure 2 An embodiment of the gate insulator 250.

[0068] Figure 4 This is a top view of an IC device 400 having multiple gate electrodes 410A-440C according to some embodiments of the present disclosure. The multiple gate electrodes 410A-440C are collectively referred to as "multiple multiple gate electrodes 410" or "multiple gate electrodes 410". The IC device 400 also includes trench electrodes 420A-420D (collectively referred to as "multiple trench electrodes 420" or "trench electrodes 420") and semiconductor structures 430A and 430B. The IC device 400 may include different, fewer, or more components. For example, the IC device 400 may include different numbers of semiconductor structures, trench electrodes, or gate electrodes. For illustrative purposes, Figure 4 Not all components of IC device 400 may be shown.

[0069] Multi-length gate electrodes 410 are stacked along the horizontal axis of the IC device 400, which may be substantially parallel to the Y-axis. The multi-length gate electrodes 410 may be... Figure 1 Multi-length gate electrode 140 in Figure 2 The gate electrode 240 in Figure 3, or the embodiment of the multi-length gate electrode including conductive structures 340A and 340B in Figure 3. Each multi-length gate electrode 410 includes two portions 413 and 415. Figure 4 As shown, portion 413 has a larger dimension along the Y-axis than portion 415. In some embodiments, at least one of the multi-length gate electrodes 410 is coupled to a power plane, a ground plane, or a signal plane. For example, multi-length gate electrode 410B may be coupled to a power plane, a ground plane, or a signal plane. Multi-length gate electrodes 410A or 410C may be dummy gate electrodes.

[0070] The distance between any two adjacent multi-length gate electrodes 410 (e.g., the distance between multi-length gate electrodes 410A and 410B, or the distance between multi-length gate electrodes 410B and 410C) can be the gate pitch in the IC device 400. Although portions 413 and 415 have different lengths, the gate pitch 417 at portion 413 and the gate pitch 419 at portion 415 are the same or substantially similar. Gate pitch 417 can be the distance along the Y-axis from the center of portion 413 of the multi-length gate electrode 410 to the center of the adjacent portion 413 of the multi-length gate electrode 410. Gate pitch 419 can be the distance along the Y-axis from the center of portion 415 of the multi-length gate electrode 410 to the center of the adjacent portion 415 of the multi-length gate electrode 410.

[0071] The trench electrode 420 can be a conductive structure. The trench electrode 420 can be located along the Z-axis above the source or drain region of the transistor in the IC device 400. The trench electrode 420 can be electrically coupled to a power plane, a ground plane, or a signal plane. In some embodiments, two or more trench electrodes 420 can be at the same potential. For example, two or more trench electrodes 420 can be electrically coupled or form a single electrode. The trench electrode 420 can also be referred to as a trench contact. The trench electrode 420 above the source region can also be referred to as a source contact or a drain contact. The trench electrode 420 above the drain region can also be referred to as a drain electrode or a drain contact.

[0072] Semiconductor structures 430A and 430B are stacked along the vertical axis of the IC device 400, which may be substantially parallel to the X-axis. Embodiments of semiconductor structures 430A or 430B may include... Figure 1 One of the semiconductor structures in 130 Figure 2 One of the semiconductor structures 230 in Figure 3 or semiconductor structures 330A or 330B in Figure 3.

[0073] A multi-length gate electrode 410, a trench electrode 420, and semiconductor structures 430A and 430B can form a transistor in an IC device. For example, a portion 413 of the multi-length gate electrode 410B, trench electrodes 420A and 420C, and a portion of semiconductor structure 430A below the multi-length gate electrode 410B and trench electrodes 420A and 420C can constitute a transistor. A portion 415 of the multi-length gate electrode 410B, trench electrodes 420B and 420D, and a portion of semiconductor structure 430B below the multi-length gate electrode 410B and trench electrodes 420B and 420D can constitute another transistor. The portion of semiconductor structure 430A or 430B below the trench electrode 420 can be a source region or a drain region. The portion of semiconductor structure 430A or 430B below the multi-length gate electrode 410B can be a channel region of a transistor. In other embodiments, the IC device 400 may include one or more additional transistors.

[0074] Figures 5A-5L The present disclosure illustrates a process for manufacturing an IC device having a multi-length gate electrode according to some embodiments of the present disclosure. The IC device may be... Figure 1 IC device 100 Figure 2 IC device 200 in Figure 3 or IC device in Figure 3 Figure 4 An embodiment of IC device 400 in the example. Figures 5A-5L The sequence of processes shown may not represent the order in which the components forming IC device 500 are formed. For example, the components shown in the figure may be formed before the components shown in the previous figure. Although reference Figures 5A-5LThe process is described, but other processes for forming IC devices with multi-length gate electrodes can be used alternatively. For example, combined with Figures 5A-5L Some of the steps described can be changed, eliminated, divided, or combined.

[0075] Figure 5A and 5B The formation of semiconductor structure 530 (referred to as "semiconductor structure 530") is shown. Figure 5B It shows Figure 5A The cross-section shown in the BB plane or CC plane. Figure 5A and 5B In this embodiment, a semiconductor structure 530 is formed on a substrate 510. The semiconductor structure 530 can be formed using an epitaxial deposition process. For example, one or more semiconductor materials can be deposited onto the surface of the substrate 510. The semiconductor structure 530 can be formed by epitaxial growth of one or more semiconductor materials. Embodiments of the substrate 510 can be support structures 110, 210, or 310. Embodiments of the semiconductor structure 530 can be one of semiconductor structures 130, 230, 330A and 330B, and 430A and 430B.

[0076] Figure 5C and 5D The formation of dielectric layer 501, electrical insulator 502, dummy gate electrode 503, hard mask 504 and gate spacer 505 is shown. Figure 5D It shows Figure 5C The cross-section shown in the BB plane or CC plane. Figure 5C and Figure 5D In this structure, a dielectric layer 501 is formed on a substrate 510. The dielectric layer 501 may include dielectric structures that separate the semiconductor structures 530 from each other. The dielectric structures may be used as STI (Surface Mount Technology). The dielectric structures may be formed by forming trenches in the substrate 510 and depositing one or more dielectric materials into the trenches. An electrical insulator 502 is formed to at least partially surround the semiconductor structure 530. The electrical insulator 502 may include one or more electrical insulators. For example, a dummy gate electrode 503 is formed on the gate insulator 502 by depositing metal onto the gate insulator 502. Furthermore, a hard mask 504 is formed on the dummy gate electrode 503. The hard mask 504 may include one or more dielectric materials (e.g., nitrides) having desired mechanical properties. A gate spacer 505 may surround the dummy gate electrode 503. At least a portion of the semiconductor structure may be surrounded by an electrical insulator 506.

[0077] Figure 5E and 5F The removal of the dummy gate electrode 503 and the hard mask 504 is shown.Figure 5F It shows Figure 5E The cross-section is shown in the BB plane or CC plane. In some embodiments, the dummy gate electrode 503 may be removed after providing an electrical insulator (e.g., over the source / drain region of the semiconductor structure 530). This exposes the gate spacer 505. The gate spacer 505 surrounds the trench 507.

[0078] Figures 5G-5I The process for thinning the gate spacer 505 is shown. Figure 5H It shows Figure 5G The cross-section in the BB plane is shown in Figure 51. Figure 5G The cross-section in the CC plane is shown. Gate spacer 505 can be thinned using dry cleaning. This process may include multiple dry cleaning steps. A portion of gate spacer 505 may undergo fewer dry cleaning steps than another portion of gate spacer 505. For example, the entire gate spacer 505 may be thinned in a first dry cleaning step, and a portion of gate spacer 505 may be further thinned in a second dry cleaning step (optionally one or more subsequent dry cleaning steps). In each dry cleaning step, the inner sidewalls of the gate spacer (e.g., the sidewalls facing trench 507) are trimmed and a portion of the gate spacer is removed. Figure 5H The cross-section in Figure 51 is in the portion that has undergone more dry cleaning steps, while the cross-section in Figure 52 is in the portion that has undergone fewer dry cleaning steps. In Figure 51, the gate spacer 505 is thinned to become the gate spacer 508, and the trench 507 is expanded to become the trench 509 having a length 511 along the Y-axis. Figure 5H In this process, the gate spacer 505 is thinned to become the gate spacer 512, and the trench 507 is extended to become the trench 513 having a length 514 along the Y-axis. The length 514 is greater than the length 511. In some embodiments, the length 514 is approximately 3 nm longer than the length 511.

[0079] The process also removes Figures 5G-5I The embodiment shows an electrical insulator 502. In other embodiments, part or all of the electrical insulator 502 may still remain after the process. For example, certain areas of the electrical insulator 502 may be blocked during the process, for example, for thick gate insulator devices using the electrical insulator 502 as the initial gate insulator. The process may change the dielectric layer 501 to 520. The portion of the dielectric layer 501 below the portion of the gate spacer 505 that undergoes more dry cleaning steps has a more significant recess than the portion of the dielectric layer 501 below the portion of the gate spacer 505 that undergoes less dry cleaning steps. As a result, the dielectric layer 501 has two different dimensions 515 and 527 along the Z-axis.

[0080] Figures 5J-5L The process for forming the gate electrode 540 and the gate insulator 550 is shown. Figure 5K It shows Figure 5J The cross section in the BB plane is shown. Figure 5L It shows Figure 5J The cross-section in the CC plane is shown. The gate electrode 540 can be formed by providing one or more conductive materials into at least trenches 509 and 513. Since trenches 509 and 513 have different lengths, different portions of the gate electrode 540 have different lengths. Figure 5K The length of the gate electrode 540 in the cross-section shown is greater than Figure 5L The length of the gate electrode 540 in the cross-section shown. Although the gate electrode 540 has multiple different lengths, the gate spacing of the IC device 500 can be the same or substantially similar. In some embodiments, the gate electrode 540 may at least partially surround the semiconductor structure 530. A gate insulator 550 may at least partially surround the gate electrode 540. The gate insulator 550 may include a portion of an electrical insulator 502. Although in Figures 5A-5L Not shown, but IC device 500 may include items that can be used in the circuit. Figures 5J-5L One or more additional components are formed after the process in the middle. Although Figures 5A-5L The process for forming two different gate lengths is shown, but more than two different gate lengths can be formed by using the process.

[0081] Figures 6A-6B This is a top view of a wafer 2000 and a die 2002 that can facilitate one or more IC devices having gate electrodes of multiple lengths according to some embodiments of the present disclosure. In some embodiments, according to some embodiments of the present disclosure, the die 2002 may be included in an IC package. For example, any of the dies 2002 may serve as Figure 7Any of the dies 2256 in the IC package 2200 shown. The wafer 2000 may be made of semiconductor material and may include one or more dies 2002 having IC devices formed on the surface of the wafer 2000. Each of the dies 2002 may be a repeating unit of a semiconductor product including any suitable IC (e.g., an IC with multi-length gate electrodes as described herein). After the manufacture of the semiconductor product is completed (e.g., after the manufacture of the IC device with multi-length gate electrodes as described herein), the wafer 2000 may undergo a unitization process in which each of the dies 2002 is separated from each other to provide a discrete “chip” of the semiconductor product. In particular, the IC device with multi-length gate electrodes as disclosed herein may be in the form of a wafer 2000 (e.g., without unitization) or a die 2002 (e.g., with unitization). Die 2002 may include one or more diodes, one or more transistors, and optionally supporting circuitry to route electrical signals to III-N diodes and III-N transistors, as well as any other IC components, wherein the III-N diodes have N-doped wells and capping layers. In some embodiments, wafer 2000 or die 2002 may implement electrostatic discharge (ESD) protection devices, radio frequency front-end devices, memory devices (e.g., static random access memory (SRAM) devices), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 2002.

[0082] Figure 7 This is a side cross-sectional view of an example IC package 2200 that may include one or more IC devices having gate electrodes of multiple lengths, according to some embodiments of the present disclosure. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

[0083] like Figure 7 As shown, IC package 2200 may include package substrate 2252. Package substrate 2252 may be formed of a dielectric material (e.g., formed of ceramic, glass, a combination of organic and inorganic materials, a deposited film, an epoxy resin film having filler particles, etc., and may have embedded portions of different materials), and may have conductive paths of dielectric material extending through the space between surfaces 2272 and 2274, or between different locations on surface 2272 and / or between different locations on surface 2274.

[0084] The package substrate 2252 may include conductive contacts 2263 coupled to conductive path 2262 through the package substrate 2252, thereby allowing the circuitry within die 2256 and / or the interposer 2257 to be electrically coupled to the respective conductive contacts in conductive contacts 2264 (or to other devices included in the package substrate 2252, not shown).

[0085] IC package 2200 may include an interposer 2257, which is coupled to package substrate 2252 via conductive contacts 2261, first-level interconnects 2265, and conductive contacts 2263 of package substrate 2252. Figure 7 The first-level interconnect 2265 shown is a solder bump, but any suitable first-level interconnect 2265 can be used. In some embodiments, the interposer 2257 is not included in the IC package 2200; instead, the die 2256 can be directly coupled to the conductive contact 2263 at the face 2272 via the first-level interconnect 2265.

[0086] IC package 2200 may include one or more dies 2256, which are coupled to interposer 2257 via conductive contacts 2254, first-level interconnects 2258, and conductive contacts 2260 of interposer 2257. The conductive contacts 2260 can be coupled to conductive paths (not shown) through interposer 2257, thereby allowing circuitry within die 2256 to be electrically coupled to individual conductive contacts in conductive contacts 2261 (or electrically coupled to other devices included in interposer 2257, not shown). Figure 7 The first-level interconnect 2258 shown is a solder bump, but any suitable first-level interconnect 2258 can be used. As used herein, "conductive contact" can refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; conductive contacts can be recessed in the surface of a component, flush with the surface of a component, or extend away from the surface of a component, and can take any suitable form (e.g., conductive pad or socket).

[0087] In some embodiments, an underfill material 2266 may be disposed around the first-level interconnect 2265 between the package substrate 2252 and the interposer 2257, and a molding compound 2268 may be disposed around the die 2256 and the interposer 2257 and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the molding compound 2268. Example materials that may be used for the underfill material 2266 and the molding compound 2268 are epoxy molding materials, as appropriate. The second-level interconnect 2270 may be coupled to the conductive contact 2264. Figure 7The second-level interconnect 2270 shown is a solder ball (e.g., for a ball grid array arrangement), but any suitable second-level interconnect 2270 can be used (e.g., a pin in a pin grid array arrangement or a pad in a disk grid array arrangement). The second-level interconnect 2270 can be used to couple IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and referenced below. Figure 8 The subject of discussion.

[0088] Die 2256 may take the form of any embodiment of die 2002 discussed herein and may facilitate any embodiment of an IC device having multiple gate electrodes of various lengths. In embodiments where IC package 2200 includes multiple dies 2256, IC package 2200 may be referred to as a multi-chip package. Importantly, even in such embodiments of the MCP implementation of IC package 2200, one or more IC devices having multiple gate electrodes of various lengths may be provided in a single chip according to any embodiment described herein. Die 2256 may include circuitry for performing any desired function. For example, one or more of dies 2256 may be ESD protection dies, including one or more IC devices having multiple gate electrodes of various lengths as described herein, one or more of dies 2256 may be logic dies (e.g., silicon-based dies), one or more of dies 2256 may be memory dies (e.g., high-bandwidth memory), etc. In some embodiments, any of the dies 2256 may include one or more IC devices having multi-length gate electrodes, as discussed above; in some embodiments, at least some of the dies 2256 may not include any III-N diodes having N-doped wells and capping layers.

[0089] Figure 7 The IC package 2200 shown can be a flip-chip package, but other package architectures can be used. For example, the IC package 2200 can be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 can be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although in Figure 7 Two dies 2256 are shown in the IC package 2200, but the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0090] Figure 8This is a cross-sectional side view of an IC device assembly 2300 including components having one or more IC devices having multi-length gate electrodes, according to some embodiments of the present disclosure. The IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first surface 2340 of the circuit board 2302 and an opposing second surface 2342 of the circuit board 2302; typically, components may be disposed on one or both of surfaces 2340 and 2342. In particular, any suitable component of the IC device assembly 2300 may include any of the IC devices having multi-length gate electrodes according to any of the embodiments disclosed herein; for example, any of the IC packages discussed below with reference to the IC device assembly 2300 may take the form described above. Figure 7 The form of any of the embodiments of the IC package 2200 discussed (e.g., may include one or more IC devices having a multi-length gate electrode in / on die 2256).

[0091] In some embodiments, circuit board 2302 may be a PCB comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally combined with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB substrate.

[0092] Figure 8 The illustrated IC device assembly 2300 includes an on-intermediate package (IP) structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling member 2316. The coupling member 2316 electrically and mechanically couples the IP structure 2336 to the circuit board 2302 and may include solder balls (e.g., as shown in the image). Figure 8 (as shown), the convex and concave portions of the socket, adhesive, bottom filler material and / or any other suitable electrical and / or mechanical coupling structure.

[0093] The interposer-on-package structure 2336 may include an IC package 2320 coupled to the interposer 2304 via a coupling member 2318. The coupling member 2318 may take any suitable form for the application, such as the form discussed above with reference to coupling member 2316. For example, the IC package 2320 may be or include a die (…). Figure 6B The die 2002), IC devices (e.g., Figures 1-2 (IC devices) or any other suitable components. In particular, IC package 2320 may include one or more IC devices having multi-length gate electrodes as described herein. Although inFigure 8 A single IC package 2320 is shown, but multiple IC packages can be coupled to interposer 2304; in fact, additional interposers can be coupled to interposer 2304. Interposer 2304 can provide an intermediate substrate for bridging board 2302 and IC package 2320. Typically, interposer 2304 can extend connections to wider pitches or reroute connections to different connections. For example, interposer 2304 can couple IC package 2320 (e.g., die) to BGA of coupling component 2316 to couple to board 2302. Figure 8 In the illustrated embodiment, the IC package 2320 and the circuit board 2302 are attached to opposite sides of the interposer 2304; in other embodiments, the IC package 2320 and the circuit board 2302 may be attached to the same side of the interposer 2304. In some embodiments, three or more components may be interconnected via the interposer 2304.

[0094] Interposer 2304 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic materials, or polymeric materials such as polyimide. In some embodiments, interposer 2304 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other group III-V and IV materials. Interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. Interposer 2304 may also include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD protection devices, and memory devices. More complex devices, such as additional RF (radio frequency) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on interposer 2304. In some embodiments, IC devices with multi-length gate electrodes as described herein may also be implemented in / on the interposer 2304. The interposer-on-interposer structure 2336 may take the form of any interposer-on-interposer structure known in the art.

[0095] IC device assembly 2300 may include IC package 2324 coupled to a first side 2340 of circuit board 2302 via coupling member 2322. Coupling member 2322 may take the form of any embodiment discussed above with reference to coupling member 2316, and IC package 2324 may take the form of any embodiment discussed above with reference to IC package 2320.

[0096] Figure 8The illustrated IC device assembly 2300 includes a stacked package structure 2334 coupled to a second side 2342 of a circuit board 2302 via a coupling member 2328. The stacked package structure 2334 may include IC packages 2326 and 2332 coupled together via a coupling member 2330, such that IC package 2326 is disposed between the circuit board 2302 and IC package 2332. The coupling members 2328 and 2330 may take the form of any embodiment of the coupling member 2316 discussed above, and the IC packages 2326 and 2332 may take the form of any embodiment of the IC package 2320 discussed above. The stacked package structure 2334 can be configured according to any stacked package structure known in the art.

[0097] Figure 9 This is a block diagram of an example computing device 2400 that may include one or more components having one or more IC devices having multi-length gate electrodes, according to some embodiments of the present disclosure. For example, according to some embodiments of the present disclosure, any suitable component of the computing device 2400 may include a die (e.g., Figure 6B The die 2002 includes one or more IC devices having gate electrodes of multiple lengths. Any component of the computing device 2400 may include one or more IC devices having gate electrodes of multiple lengths (e.g., in conjunction with the above). Figure 1 , 2 (Any embodiment of the IC device with multi-length gate electrodes described in 4 and 5) and / or IC package (e.g., Figure 7 IC package 2200). Any component of computing device 2400 may include IC device assemblies (e.g., IC package 2200). Figure 8 IC device assembly 2300).

[0098] exist Figure 9 Multiple components are shown as included in computing device 2400, but any one or more of these components may be omitted or copied, as applicable to the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single SoC (System-on-a-Chip) die.

[0099] Additionally, in various embodiments, the computing device 2400 may not include... Figure 9The computing device 2400 may include one or more of the components shown, but may include interface circuitry for coupling to one or more components. For example, the computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 2418 or audio output device 2408 may be coupled.

[0100] Computing device 2400 may include processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 2402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing device. Computing device 2400 may include memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 2404 may include memory that shares a die with processing device 2402. This memory may be used as a cache memory and may include, for example, eDRAM and / or spin-transfer torque magnetic random access memory (STT-MRAM).

[0101] In some embodiments, computing device 2400 may include communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communication for transmitting data to and from computing device 2400. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation via a non-solid medium. This term does not imply that the associated devices do not include any wires, although in some embodiments they may not include any wires.

[0102] The 2412 communication chip can implement any of a variety of wireless standards or protocols, including but not limited to IEEE standards, such as Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any modifications, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are often referred to as WiMAX networks. WiMAX is an acronym for Global Microwave Access Interoperability, a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The 2412 communication chip can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 2412 can operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, and above. In other embodiments, the communication chip 2412 can operate according to other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0103] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 may include multiple communication chips. For example, a first communication chip 2412 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 2412 may be dedicated to wireless communications, and the second communication chip 2412 may be dedicated to wired communications.

[0104] In various embodiments, IC devices with multi-length gate electrodes as described herein can be particularly advantageous for use as portions of ESD circuits protecting power amplifiers, low-noise amplifiers, filters (including arrays of filters and filter banks), switches, or other active components. In some embodiments, IC devices with multi-length gate electrodes as described herein can be used in PMICs, for example, as high-current rectifier diodes. In some embodiments, IC devices with multi-length gate electrodes as described herein can be used in audio devices and / or various input / output devices.

[0105] The computing device 2400 may include a battery / power circuit 2414. The battery / power circuit 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit systems for coupling components of the computing device 2400 to a power source (e.g., AC mains power) that is separate from the computing device 2400.

[0106] The computing device 2400 may include a display device 2406 (or a corresponding interface circuitry system, as discussed above). For example, the display device 2406 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0107] The computing device 2400 may include an audio output device 2408 (or a corresponding interface circuitry system, as discussed above). For example, the audio output device 2408 may include any device that generates audible indicators, such as a speaker, headphones, or earphones.

[0108] The computing device 2400 may include an audio input device 2418 (or a corresponding interface circuitry system, as discussed above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0109] The computing device 2400 may include a GPS device 2416 (or a corresponding interface circuitry system, as discussed above). The GPS device 2416 may communicate with a satellite-based system and may receive the location of the computing device 2400, as is known in the art.

[0110] The computing device 2400 may include another output device 2410 (or a corresponding interface circuitry system, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0111] The computing device 2400 may include another input device 2420 (or a corresponding interface circuitry system, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick-response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0112] The computing device 2400 can have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), super mobile personal computer, etc.), desktop computing device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, the computing device 2400 can be any other electronic device that processes data.

[0113] The following paragraphs provide various examples of the embodiments disclosed herein.

[0114] Example 1 provides an IC device comprising: a first conductive structure having a first vertical axis; a second conductive structure having a second vertical axis substantially parallel to the first vertical axis; a first semiconductor structure; and a second semiconductor structure situated on the first semiconductor structure, wherein: a first portion of the first conductive structure is situated on a portion of the first semiconductor structure, a second portion of the first conductive structure is situated on a portion of the second semiconductor structure, the first portion has a dimension in a direction substantially perpendicular to the first vertical axis that is larger than the second portion in said direction, and the distance from the center of the first portion to the second vertical axis is the same as or substantially similar to the distance from the center of the second portion to the second vertical axis.

[0115] Example 2 provides an IC device according to Example 1, wherein the difference between the size of the first portion and the size of the second portion is at most about 3 nanometers.

[0116] Example 3 provides an IC device according to Example 2, wherein the difference between the size of the first portion and the size of the second portion is at least about 0.5 nanometers.

[0117] Example 4 provides an IC device according to any of the preceding examples, further comprising: a first dielectric structure located over a first portion of a first conductive structure in the direction; and a second dielectric structure located over a second portion of the first conductive structure in the direction, wherein the dimension of the first dielectric structure in the direction is smaller than the dimension of the second dielectric structure in the direction.

[0118] Example 5 provides an IC device according to any of the foregoing examples, further comprising: a first dielectric structure at least partially located between a first portion of a first conductive structure and a portion of a first semiconductor structure; and a second dielectric structure at least partially located between a second portion of the first conductive structure and a portion of the second semiconductor structure, wherein the dimension of the first dielectric structure in the direction is smaller than the dimension of the second dielectric structure in the direction.

[0119] Example 6 provides an IC device according to any of the foregoing examples, further comprising: a first dielectric region located over a first portion of a first conductive structure in a different direction substantially perpendicular to the direction and the first longitudinal axis; and a second dielectric region located over a second portion of the first conductive structure in the different directions, wherein the size of the first dielectric region is smaller than the size of the second dielectric region.

[0120] Example 7 provides an IC device according to any of the foregoing examples, wherein the first semiconductor structure has fins or nanoribbons.

[0121] Example 8 provides an IC device comprising: a first transistor including a first source region, a first drain region, and a first channel region, wherein the first source region is located above the first drain region along a horizontal axis of the IC device; a second transistor located above the first transistor along a vertical axis of the IC device, the second transistor including a second source region, a second drain region, and a second channel region; a first gate electrode including a first portion and a second portion, wherein the first portion is located above the first channel region, and the second portion is located above the second channel region; and a second gate electrode located above the first gate electrode along a horizontal axis of the IC device, wherein the dimension of the first portion along the horizontal axis is greater than the dimension of the second portion along the horizontal axis, and the distance from the first portion to the second gate electrode along the horizontal axis is the same as or substantially similar to the distance from the second portion to the second gate electrode.

[0122] Example 9 provides an IC device according to Example 8, wherein a first gate electrode has a longitudinal axis along a vertical axis, and a first source region, a first drain region, and a first channel region are located in a semiconductor structure having a longitudinal axis along a horizontal axis.

[0123] Example 10 provides an IC device according to Example 9, wherein the semiconductor structure includes fins or nanoribbons.

[0124] Example 11 provides an IC device according to any one of Examples 8-10, wherein a first source region, a first drain region, and a first channel region are located in a first semiconductor structure, a second source region, a second drain region, and a second channel region are located in a second semiconductor structure, and the first semiconductor structure is located above the second semiconductor structure in a direction along the vertical axis.

[0125] Example 12 provides an IC device according to any one of Examples 8-11, wherein the second gate includes a third portion and a fourth portion, and the dimension of the third portion along the horizontal axis is greater than the dimension of the fourth portion along the horizontal axis.

[0126] Example 13 provides an IC device according to any one of Examples 8-12, wherein the difference between the size of the first portion and the size of the second portion is in the range of about 0.5 nanometers to about 3 nanometers.

[0127] Example 14 provides an IC device according to any one of Examples 8-13, wherein the first transistor further includes a first gate insulator between a first portion of the first gate electrode and a first channel region; and the second transistor further includes a second gate insulator between a second portion of the first gate electrode and a second channel region, wherein the dimension of the first gate insulator along the horizontal axis is smaller than the dimension of the second gate insulator along the horizontal axis.

[0128] Example 15 provides a method for forming an IC device, comprising: forming a semiconductor structure on a substrate; forming a dielectric structure, the semiconductor structure being at least partially surrounded by the dielectric structure; reducing the size of a first portion of the dielectric structure to a first predetermined size; reducing the size of a second portion of the dielectric structure to a second predetermined size; and forming a conductive structure, wherein the first portion of the conductive structure is located between the first portion of the semiconductor structure and the first portion of the dielectric structure, and the second portion of the conductive structure is located between the second portion of the semiconductor structure and the second portion of the dielectric structure.

[0129] Example 16 provides a method according to Example 15, wherein reducing the size of the second portion of the dielectric structure to a second predetermined size includes: reducing the size of the second portion of the dielectric structure to a first predetermined size; and further reducing the size of the second portion of the dielectric structure from the first predetermined size to the second predetermined size.

[0130] Example 17 provides a method according to Example 15 or 16, wherein reducing the size of a first portion of the dielectric structure to a first predetermined size includes removing a portion of the first portion of the dielectric structure by using dry cleaning.

[0131] Example 18 provides a method according to any one of Examples 15-17, wherein reducing the size of the second portion of the dielectric structure to a second predetermined size includes removing a portion of the second portion of the dielectric structure by using dry cleaning.

[0132] Example 19 provides a method according to any one of Examples 15-18, wherein the difference between the first predetermined size and the second predetermined size is in the range of about 0.5 nanometers to about 3 nanometers.

[0133] Example 20 provides a method according to any one of Examples 15-19, wherein forming a semiconductor structure on a substrate includes forming fins or nanoribbons comprising semiconductor material on the substrate.

[0134] Example 21 provides an IC package comprising: an IC device according to any one of Examples 1-14; and additional IC components coupled to the device.

[0135] Example 22 provides an IC package according to Example 21, wherein additional IC components include one of a package substrate, an interposer, or another IC die.

[0136] Example 23 provides an IC package according to Example 21 or Example 22, wherein the IC device according to any one of Examples 1-14 may include at least one of a memory device, a computing device, a wearable device, a handheld electronic device, and a wireless communication device, or a portion thereof.

[0137] Example 24 provides an electronic device comprising: a carrier substrate; and one or more of an IC device according to Examples 1-14 and an IC package according to any one of Examples 21-23 coupled to the carrier substrate.

[0138] Example 25 provides an electronic device according to Example 24, wherein the carrier substrate is a motherboard.

[0139] Example 26 provides an electronic device according to Example 24, wherein the carrier substrate is a PCB.

[0140] Example 27 provides an electronic device according to any one of Examples 24-26, wherein the electronic device is a wearable electronic device or a handheld electronic device.

[0141] Example 28 provides an electronic device according to any one of Examples 24-27, wherein the electronic device further includes one or more communication chips and an antenna.

[0142] Example 29 provides an electronic device according to any one of Examples 24-28, wherein the electronic device is an RF transceiver.

[0143] Example 30 provides an electronic device according to any one of Examples 24-28, wherein the electronic device is one of a switch, power amplifier, low noise amplifier, filter, filter bank, duplexer, upconverter, or downconverter of an RF communication device, such as an RF transceiver.

[0144] Example 31 provides an electronic device according to any one of Examples 24-30, wherein the electronic device is a computing device.

[0145] Example 32 provides an electronic device according to any one of Examples 24-31, wherein the electronic device is included in a base station of a wireless communication system.

[0146] Example 33 provides an electronic device according to any one of Examples 24-31, wherein the electronic device is included in a user equipment device of a wireless communication system.

[0147] Example 34 provides a method according to any one of Examples 15-20, further comprising a process for forming an IC device according to any one of claims 1-14.

[0148] Example 35 provides a method according to any one of Examples 15-20, further comprising a process for forming an IC package according to any one of Claims 21-23.

[0149] Example 36 provides a method according to any one of Examples 15-20, further comprising a process for forming an electronic device according to any one of Claims 24-33.

[0150] The foregoing description of embodiments of this disclosure (including those described in the abstract) is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. While specific embodiments and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art. These modifications can be made to this disclosure based on the detailed description above.

Claims

1. An integrated circuit (IC) device, comprising: A first conductive structure having a first vertical axis; The second conductive structure has a second longitudinal axis that is substantially parallel to the first longitudinal axis; First semiconductor structure; as well as A second semiconductor structure is located on top of the first semiconductor structure. in: A first portion of the first conductive structure is located on top of a portion of the first semiconductor structure. The second portion of the first conductive structure is located on top of a portion of the second semiconductor structure. The first portion has a larger dimension in a direction substantially perpendicular to the first longitudinal axis than the second portion in that direction, and The distance from the center of the first part to the second vertical axis is the same as or substantially similar to the distance from the center of the second part to the second vertical axis.

2. The IC device according to claim 1, wherein, The difference between the dimensions of the first portion and the dimensions of the second portion is at most about 3 nanometers.

3. The IC device according to claim 2, wherein, The difference between the size of the first portion and the size of the second portion is at least about 0.5 nanometers.

4. The IC device according to any one of claims 1-3, further comprising: A first dielectric structure is located above the first portion of the first conductive structure in the said direction; as well as A second dielectric structure is located above the second portion of the first conductive structure in the said direction.

5. The IC device according to claim 4, wherein, The dimension of the first dielectric structure in the direction is smaller than the dimension of the second dielectric structure in the direction.

6. The IC device according to any one of claims 1-3, further comprising: A first dielectric structure, at least partially located between the first portion of the first conductive structure and the portion of the first semiconductor structure; as well as A second dielectric structure is located at least partially between the second portion of the first conductive structure and the portion of the second semiconductor structure.

7. The IC device according to claim 6, wherein, The dimension of the first dielectric structure in the direction is smaller than the dimension of the second dielectric structure in the direction.

8. The IC device according to any one of claims 1-3, further comprising: The first dielectric region is located on the first portion of the first conductive structure in different directions substantially perpendicular to the said direction and the first longitudinal axis. as well as The second dielectric region is located above the second portion of the first conductive structure in the different directions.

9. The IC device according to claim 8, wherein, The size of the first dielectric region is smaller than the size of the second dielectric region.

10. The IC device according to any one of claims 1-9, wherein, The first semiconductor structure has fins or nanoribbons.

11. An integrated circuit (IC) device, comprising: The first transistor includes a first source region, a first drain region, and a first channel region, wherein the first source region is located above the first drain region along the horizontal axis of the IC device. The second transistor is located above the first transistor along the vertical axis of the IC device, and the second transistor includes a second source region, a second drain region, and a second channel region. A first gate electrode includes a first portion and a second portion, wherein the first portion is located over a first channel region, and the second portion is located over a second channel region; and The second gate electrode is located above the first gate electrode along the horizontal axis of the IC device. Wherein, the dimension of the first portion along the horizontal axis is greater than the dimension of the second portion along the horizontal axis, and the distance from the first portion to the second gate electrode along the horizontal axis is the same as or substantially similar to the distance from the second portion to the second gate electrode.

12. The IC device according to claim 11, wherein: The first gate electrode has a longitudinal axis along the vertical axis, and The first source region, the first drain region, and the first channel region are located in a semiconductor structure having a vertical axis along the horizontal axis.

13. The IC device according to claim 12, wherein, The semiconductor structure includes fins or nanoribbons.

14. The IC device according to any one of claims 11-13, wherein: The first source region, the first drain region, and the first channel region are located in the first semiconductor structure. The second source region, the second drain region, and the second channel region are located in the second semiconductor structure, and The first semiconductor structure is positioned above the second semiconductor structure in the direction along the vertical axis.

15. The IC device according to any one of claims 11-14, wherein: The second gate electrode includes a third portion and a fourth portion, and The dimension of the third part along the horizontal axis is greater than the dimension of the fourth part along the horizontal axis.

16. The IC device according to any one of claims 11-15, wherein, The difference between the size of the first portion and the size of the second portion is in the range of about 0.5 nanometers to about 3 nanometers.

17. The IC device according to any one of claims 11-16, wherein: The first transistor further includes a first gate insulator between the first portion of the first gate electrode and the first channel region; and The second transistor further includes a second gate insulator between the second portion of the first gate electrode and the second channel region.

18. The IC device according to claim 17, wherein, The dimension of the first gate insulator along the horizontal axis is smaller than the dimension of the second gate insulator along the horizontal axis.

19. A method for forming an integrated circuit (IC) device, comprising: A semiconductor structure is formed on a substrate; A dielectric structure is formed, wherein the semiconductor structure is at least partially surrounded by the dielectric structure; The size of the first portion of the dielectric structure is reduced to a first predetermined size; The size of the second portion of the dielectric structure is reduced to a second predetermined size; as well as Forming a conductive structure, The first portion of the conductive structure is located between the first portion of the semiconductor structure and the first portion of the dielectric structure, and the second portion of the conductive structure is located between the second portion of the semiconductor structure and the second portion of the dielectric structure.

20. The method according to claim 19, wherein, Reducing the size of the second portion of the dielectric structure to the second predetermined size includes: The size of the second portion of the dielectric structure is reduced to the first predetermined size.

21. The method according to claim 20, wherein, Reducing the size of the second portion of the dielectric structure to the second predetermined size further includes: Furthermore, the size of the second portion of the dielectric structure is reduced from the first predetermined size to the second predetermined size.

22. The method according to any one of claims 19-21, wherein, Reducing the size of the first portion of the dielectric structure to the first predetermined size includes: A portion of the first part of the dielectric structure is removed by using dry cleaning.

23. The method according to any one of claims 19-22, wherein, Reducing the size of the second portion of the dielectric structure to the second predetermined size includes: A portion of the second part of the dielectric structure is removed by using dry cleaning.

24. The method according to any one of claims 19-23, wherein, The difference between the first predetermined size and the second predetermined size is in the range of about 0.5 nanometers to about 3 nanometers.

25. The method according to any one of claims 19-24, wherein, Forming the semiconductor structure on the substrate includes: Fins or nanoribbons comprising semiconductor material are formed on the substrate.

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