Method and system for improving DC calibration efficiency based on ATE equipment

Abstract

The invention relates to the technical field of integrated circuit automatic test equipment, in particular to a method and system for improving DC calibration efficiency based on ATE equipment. The method comprises the following steps: detecting whether complete ADC calibration data exists in ATE equipment or not; if the complete ADC calibration data exists, verifying all channels of the ATE based on the complete ADC calibration data, and selecting data points to judge whether each channel meets a preset technical specification and meets a linearity requirement or not through verification; if all the channels pass the verification, DC calibration is ended; and if at least one channel which does not pass the verification exists, performing DC calibration on the channel which does not pass the verification. According to the invention, the problems of low efficiency and long time consumption caused by the fact that all channels need to be comprehensively calibrated when the current ATE carries out DC calibration in the maintenance stage can be solved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit automatic test equipment, and particularly relates to a method and system for improving DC calibration efficiency based on ATE equipment. BACKGROUND

[0002] With the promotion of the international situation and the rapid development of the integrated circuit industry, the requirement for efficiency of chip testing is increasing, especially ATE (Automatic Test Equipment) as the core equipment of chip testing, which is used for automatic detection of the performance of electronic devices, and the process efficiency of the maintenance stage directly affects the cost and capacity of the overall test link. As a key link in the maintenance of ATE equipment, DC (direct current parameter) calibration is used for standardizing correction of the direct current parameter measurement channel of the test system, and ensures that the measurement accuracy of voltage, current and other direct current signals meets the technical specifications (SPEC) of semiconductor testing, and the efficiency is crucial to the availability of the equipment.

[0003] At present, the mainstream DC calibration method in the industry follows the logic of "full channel recalibration": first, the calibration data of the ADC (core module in the precision measurement unit, used for high-precision direct current parameter measurement) is obtained, and then complete DC calibration is performed on all channels of the equipment based on the ADC calibration data. In order to ensure the linearity of calibration, at least 5 data points need to be collected for each channel during calibration, then all channels are recompensated, and whether the data meets the SPEC is verified.

[0004] However, this traditional method has exposed significant defects in actual application:

[0005] On the one hand, each DC calibration needs to perform a complete calibration process repeatedly on all channels, even if most of the channels are normal, they still need to go through data point collection, recompensation, compliance verification and other steps, resulting in a large amount of time occupied by redundant operations, especially in devices with a large number of channels, the time-consuming problem is more prominent;

[0006] On the other hand, if individual channels of the equipment fail to calibrate due to hardware failure (such as circuit damage, signal drift, etc.), the traditional method cannot directly locate the faulty channel, and needs to be confirmed by checking one by one after completing the calibration of all channels, further prolonging the calibration period.

[0007] The above problems directly lead to a significant reduction in the DC calibration process efficiency of ATE equipment in the maintenance stage, not only increasing the downtime of the equipment, but also increasing the maintenance cost, which is difficult to meet the high requirements of the integrated circuit industry for test efficiency. Therefore, a technical solution is needed to optimize the DC calibration process, reduce redundant operations, and quickly locate abnormal channels, in order to improve the maintenance efficiency of ATE equipment. SUMMARY

[0008] The present application aims to provide a method and system for improving the DC calibration efficiency of ATE equipment, to solve the problem of low efficiency and long time consumption caused by the need for full calibration of all channels during DC calibration in the maintenance phase of current ATE equipment.

[0009] To achieve the above-mentioned purpose, in the first aspect of the present application, a method for improving the DC calibration efficiency of ATE equipment is provided, comprising the following steps:

[0010] Detecting whether complete ADC calibration data exists in the ATE equipment;

[0011] If the complete ADC calibration data exists, verifying all channels of the ATE equipment based on the complete ADC calibration data, the verification is performed by selecting data points to determine whether each channel meets the preset technical specifications and satisfies the linearity requirement; if all channels pass the verification, the DC calibration ends;

[0012] If at least one channel fails to pass the verification, performing DC calibration on the channel that fails to pass the verification.

[0013] Further, in the method for improving the DC calibration efficiency of ATE equipment, if the complete ADC calibration data is not detected in the ATE equipment, the ADC calibration data is reacquired.

[0014] Further, in the method for improving the DC calibration efficiency of ATE equipment, the number of data points selected in the verification is the minimum number required to satisfy the verification.

[0015] Further, in the method for improving the DC calibration efficiency of ATE equipment, the minimum number required to satisfy the verification is two.

[0016] Further, in the method for improving the DC calibration efficiency of ATE equipment, when at least one channel fails to pass the verification, the calibration is performed by collecting at least five data points to ensure linearity.

[0017] Further, in the method for improving the DC calibration efficiency of ATE equipment, if the channel still does not meet the preset technical specifications after the DC calibration on the channel that fails to pass the verification, it is determined that the channel has a hardware fault.

[0018] In the second aspect of the present application, a system for improving the DC calibration efficiency of ATE equipment is also provided, comprising:

[0019] a detection unit configured to detect whether complete ADC calibration data exists in the ATE device, and output a prompt for obtaining the complete ADC calibration data if the complete ADC calibration data is not detected;

[0020] a verification unit configured to verify all channels of the ATE device based on the ADC calibration data if the detection unit detects that the complete ADC calibration data exists, by selecting data points to determine whether each channel meets a preset technical specification and satisfies a linearity requirement;

[0021] a calibration unit configured to perform DC calibration on a channel that fails the verification if the verification unit determines that at least one channel fails the verification.

[0022] Further, in the system for improving the DC calibration efficiency of the ATE device, the verification unit selects a minimum number of data points required for verification.

[0023] Further, in the system for improving the DC calibration efficiency of the ATE device, the calibration unit performs DC calibration on the channel that fails the verification by collecting at least five data points to ensure linearity.

[0024] Further, in the system for improving the DC calibration efficiency of the ATE device, the system further comprises a fault determination unit configured to determine that a hardware fault exists in the channel if the channel still does not meet the preset technical specification after the calibration unit performs DC calibration on the channel that fails the verification.

[0025] Compared with the prior art, the present application has at least the following technical effects:

[0026] The present application first detects whether complete ADC calibration data exists in the ATE device, and if the complete ADC calibration data exists, performs rapid verification on all channels based on the data. During the verification process, specific data points are selected to determine whether each channel meets a preset technical specification and satisfies a linearity requirement. If all channels pass the verification, the DC calibration is directly ended, and if there is a channel that fails the verification, only these channels are subjected to traditional DC calibration. Compared with the traditional method, the present application can avoid redundant calibration operations on channels that have met the verification requirements, greatly shorten the overall calibration time, and significantly improve the calibration efficiency. At the same time, since the verification process strictly checks the linearity and technical specification, the calibration quality can also be effectively guaranteed. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a flowchart of the method for improving the DC calibration efficiency of the ATE device in an embodiment of the present application;

[0028] Figure 2A detailed flow chart of a method for improving DC calibration efficiency based on an ATE device in an embodiment of the present application;

[0029] Figure 3 A block diagram of a system for improving DC calibration efficiency based on an ATE device in an embodiment of the present application. DETAILED DESCRIPTION

[0030] A method and system for improving DC calibration efficiency based on an ATE device in an embodiment of the present application will be described in more detail below with reference to the accompanying drawings, in which a preferred embodiment of the present application is shown. It should be understood that modifications can be made to the present application as described herein without departing from the spirit and scope of the present application, which should be interpreted only in the broadest sense possible. Accordingly, the following description should be interpreted as a broad description of the present application and not as a limitation of the present application.

[0031] For the sake of brevity, the full structure of an actual implementation of an embodiment of the present application is not described in detail. In the following description, numerous specific details are set forth to provide a thorough understanding of the present application. One skilled in the relevant art will recognize, however, that the present application can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail. Those skilled in the art will appreciate that from the description of the present application herein, modifications to, or variations of, the present application can be apparent in light of the present disclosure. It is therefore contemplated to be within the scope of the present application to carry out the present application in a manner that includes either or both of other specific details or other methods, components, materials, and the like.

[0032] The present application is described more fully hereinafter with reference to the accompanying drawings, in which one or more embodiments of the present application are shown. Like numbers refer to like elements throughout. The present application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, the sketches are highly simplified and are not to scale, and are merely intended to conceptually illustrate the features of the present application. Thus, the present application should not be construed as limited to the embodiments set forth herein, but should be given the broadest possible interpretation accessible under the statutes.

[0033] In the field of semiconductor testing, electronic device production, etc., ATE is widely used in performance testing of various electronic devices, and DC calibration is a key link to ensure testing accuracy. The traditional DC calibration method of ATE device usually adopts a comprehensive calibration strategy, that is, unified data acquisition and parameter compensation of more than five points are performed on all channels of the device, regardless of whether these channels really need calibration. This way has significant drawbacks: on the one hand, repeated calibration of most stable channels will cause time waste and reduce the efficiency of the device; on the other hand, the traditional method cannot quickly distinguish whether the calibration failure is caused by software parameter drift or the substantial damage of the hardware itself, which may cause maintenance personnel to blindly replace the hardware and increase the maintenance cost. Therefore, how to improve the efficiency of DC calibration and accurately locate the fault under the premise of ensuring the calibration accuracy has become a technical problem to be solved in the field of ATE device.

[0034] Embodiment one

[0035] In view of this, as Figure 1 shown, in view of these limitations of the prior art, the present embodiment proposes a method for improving DC calibration efficiency based on ATE equipment to solve the problem that current ATE equipment needs to perform comprehensive calibration on all channels during the DC calibration in the maintenance stage, resulting in low efficiency and long time consumption. The method comprises the following steps:

[0036] S1: detecting whether complete ADC calibration data exists in the ATE equipment;

[0037] S2: if the complete ADC calibration data exists, verifying all channels of the ATE equipment based on the complete ADC calibration data, the verification being performed by selecting data points to judge whether each channel meets the preset technical specifications and satisfies the linearity requirement; if all channels pass the verification, the DC calibration ends;

[0038] S3: if at least one channel fails to pass the verification, performing DC calibration on the channel that fails to pass the verification.

[0039] It should be noted that before starting the DC calibration process of the ATE equipment, the selection of the subcard and the slot number should be completed to determine the target range of this calibration. The specific operation is as follows: the device operation interface displays a list of subcard types on the left side, and the operator selects the target subcard type according to the maintenance requirements. The right side of the interface synchronously displays the physical slot number corresponding to the subcard of this type (the slots of the equipment frame are numbered in the order from top to bottom, and each slot uniquely corresponds to a subcard). The operator needs to select the specific slot number from the drop-down menu. After the selection is completed, the interface generates a "calibration task list" to display the selected subcard type, slot number and total number of channels. The operator confirms that there is no error and clicks the "start quick DC calibration" button. The system locks the selected subcard and slot, and only executes the subsequent calibration process for the channels contained therein.

[0040] After the system locks the target subcard and slot, the ADC calibration data detection program is automatically started to perform step S1: detecting whether complete ADC calibration data exists in the ATE equipment. Specifically, the program accesses the storage partition bound to the target subcard inside the equipment to retrieve whether complete ADC calibration data packets exist. The complete ADC calibration data is used to correct the inherent error in the ADC conversion process and needs to meet the following conditions: including the ADC conversion coefficients (such as voltage conversion coefficients and current conversion coefficients) of all channels of the subcard, offset parameters (Offset), calibration time stamps and CRC check codes (to ensure that the data has not been tampered with).

[0041] Further, for step S1, as Figure 2If the complete ADC calibration data is not detected in the ATE device, the complete ADC calibration data is reacquired.

[0042] Specifically, if any of the following issues are detected in the ATE device: missing key parameters in the ADC calibration data packet, mismatched checksum, or expired timestamp, it is determined that "complete ADC calibration data was not detected in the ATE device." In this case, the ATE device's display interface will immediately report an error, indicating that complete ADC calibration data is missing. This channel needs to be calibrated separately until complete ADC calibration data is obtained.

[0043] By performing step S1 above, the integrity of the ADC calibration data in the ATE equipment is pre-checked, which can avoid the distortion of results caused by the lack of reference data in subsequent calibration. At the same time, the calibration prerequisites are clarified in advance, reducing invalid operations and laying the foundation for efficient calibration.

[0044] For step S2, as Figure 2 If complete ADC calibration data is detected in the target daughter card and slot, the system will use this ADC calibration data as a benchmark to initiate a verification process (VERIFY) for all channels contained therein. The verification process is carried out in various functional modes supported by the daughter card, including VSIM mode (voltage source simulation mode, used to simulate output DC voltage), VSVM mode (voltage measurement mode, used to measure external DC voltage), and DCL mode (DC load mode, used to simulate DC load current), to ensure the reliability of the channels under different operating scenarios.

[0045] The specific verification operation is as follows: For each functional mode of each channel, the system selects two special data points for acquisition—these two data points are key characteristic points of the range in that mode (for example, in the 0-5V range of VSVM mode, 0.5V and 4.5V are selected as data points, corresponding to 10% and 90% of the range respectively; such points can effectively reflect whether the linearity meets the standard). During acquisition, the system controls the signal conditioning module of the target daughter card to send a preset DC signal (such as 0.5V) to the channel. After receiving the signal, the channel converts the analog signal into a digital signal through its internal ADC module (based on existing complete ADC calibration data). The conversion result is transmitted to the main control unit in real time and recorded.

[0046] Furthermore, the criteria for passing the verification are that the selected data points conform to the preset technical specifications (SPEC) and meet the linearity requirements.

[0047] Specifically, the measured value is compared with the SPEC standard range corresponding to the data point (e.g., the measured value of the 0.5V signal needs to be between 0.4995V-0.5005V, with an error of ≤±0.1%), and if it is within the range, it meets the SPEC requirements. Based on the theoretical linear relationship of two data points (e.g., the theoretical linear equation of 0.5V and 4.5V is y=x, the slope is 1, and the intercept is 0), the linear deviation of the actual measured value is calculated, and if the deviation is ≤0.05%, it is determined that the linearity meets the requirements.

[0048] If all channels meet the above conditions in all functional modes, the system determines that "the verification is passed", that is, the calibration of all channels in the target slot is completed, and the DC calibration process is ended.

[0049] For step S3, if at least one channel does not pass the verification in any functional mode (i.e., the measured value exceeds the SPEC range or the linear deviation exceeds the standard), the system will automatically mark the channel as "calibration-required channel" (the marking information is only recorded in the system background log and is not displayed on the operation interface to avoid interfering with the operator), and re-performs DC calibration on the channel to achieve targeted calibration of the problem channel, thereby avoiding the redundant operation of calibrating the channel in the traditional way and reducing the overall calibration time.

[0050] The specific calibration process is as follows: for each calibration-required channel, the system uses the traditional DC calibration mode, that is, at least 5 data points are uniformly collected within the range of its corresponding functional mode to ensure the linearity after calibration. More accurate compensation parameters are calculated through multi-point data to ensure that the linearity of the channel within the full range meets the requirements.

[0051] After calibration, the system re-executes the verification process for the channel, and if the measured value meets the SPEC, it is determined that "the calibration is qualified", the compensation coefficient of the channel is updated to the storage area, and the system determines that the previous failure of the channel to pass the verification is due to software parameter drift, and the DC calibration is ended. If the measured value after re-verification still does not meet the SPEC (e.g., the measured value of the 5V signal is 5.02V, which exceeds the allowable error of ±0.02V), the system determines that there is a hardware fault in the channel, which needs to be repaired.

[0052] In summary, in the method and system for improving the DC calibration efficiency based on the ATE device provided in the embodiments of the present application, firstly, it is detected whether there is complete ADC calibration data in the ATE device, if there is, then the data is used to quickly verify all channels. In the verification process, whether each channel meets the preset technical specifications and satisfies the linearity requirement is judged by selecting specific data points. If all channels pass the verification, the DC calibration is directly ended, if there is a channel that does not pass the verification, only the traditional DC calibration is performed on these channels. Compared with the traditional method, the present application can avoid redundant calibration operation on the channels that have met the verification requirements, greatly shorten the overall calibration time, and significantly improve the calibration efficiency. At the same time, since the verification process strictly checks the linearity and technical specifications, the calibration quality can also be effectively guaranteed.

[0053] Embodiment two

[0054] As Figure 3 The present embodiment provides a system for improving the DC calibration efficiency based on the ATE device, which realizes the precision and efficiency of the calibration process through modular design, to solve the problem of low DC calibration efficiency in the maintenance stage of the ATE device, which specifically includes a detection unit, a verification unit and a calibration unit.

[0055] The detection unit is used to detect whether there is complete ADC calibration data in the ATE device, and its detection range covers the ADC calibration data packet in the storage partition bound with the target sub-card, including the ADC conversion coefficient (voltage, current conversion coefficient), offset parameter, calibration timestamp and CRC check code and other key contents of each channel. If complete ADC calibration data is not detected (such as missing key parameters, verification failure or timestamp expiration), the detection unit will immediately output a prompt to obtain complete ADC calibration data, guiding the operator to perform separate ADC calibration on the target channel until the required ADC calibration data is obtained, laying a reliable foundation for the subsequent process.

[0056] The verification unit is used to start after the detection unit confirms that the complete ADC calibration data is detected, and verify all channels of the ATE device based on the ADC calibration data. According to the verification requirements, the unit selects the number of data points that meet the minimum number required for verification (usually 2, such as 0.1V and 4.9V in the 0-5V range, corresponding to 2% and 98% of the range), and in various functional modes of the device (such as VSIM voltage source simulation mode, VSVM voltage measurement mode, DCL direct current load mode), whether each channel meets the preset technical specifications (SPEC) and meets the linearity requirements are judged through these data points, including whether the measured value of the data point is within the preset error range (such as ±0.1%), and the linear deviation of the actual measured value is calculated based on the two-point theoretical linear relationship (such as ≤0.05%). If all channels pass the verification, the system determines that the DC calibration is complete; if there is a channel that does not pass the verification, the verification unit will mark it as a "calibration channel" and pass it to the calibration unit, and the marking information is only recorded in the background log to avoid interfering with the operator's judgment of the overall process.

[0057] The calibration unit is used to perform DC calibration on the channel that does not pass the verification when the verification unit determines that there is at least one channel that does not pass the verification.

[0058] The calibration unit is used to receive the "calibration channel" list passed by the verification unit and perform targeted DC calibration on these channels that do not pass the verification. In order to ensure the linearity of the calibration, the calibration unit uses the method of collecting at least 5 data points for calibration, that is, uniformly selecting data points within the range of the corresponding functional mode, calculating compensation parameters through multi-point fitting to ensure that the linearity of the channel within the full range meets the requirements. After calibration, the calibration unit will automatically re-execute the verification process for the channel, and if the measured value meets the SPEC, the compensation coefficient of the channel will be updated to the storage area, and the system determines that the channel that does not pass the verification is due to software parameter drift, and the DC calibration is complete.

[0059] Further, the system further comprises a fault determination unit for determining that the channel has a hardware fault if the measured value in the channel does not meet the SPEC after the calibration unit performs DC calibration on the channel that does not pass the verification, and displaying the specific fault channel number and prompt information on the operation interface to guide the maintenance personnel to perform hardware maintenance.

[0060] In summary, through the cooperative work of the above-mentioned units, the system can effectively avoid redundant calibration operations on normal channels, greatly shorten the overall calibration time, and at the same time, can realize the accurate distinction between "software calibration" and "hardware maintenance", thereby improving the maintenance efficiency of the ATE device.

[0061] The above merely describes the preferred embodiments of the present application and does not limit the present application in any way. Any person skilled in the art can make any form of equivalent replacement or modification to the technical solutions and technical contents disclosed by the present application without departing from the scope of the technical solutions of the present application, and such changes still belong to the protection scope of the present application.

Claims

1. A method for improving DC calibration efficiency based on ATE equipment, characterized in that, Includes the following steps: Check if complete ADC calibration data exists in the ATE equipment; If the complete ADC calibration data exists, then based on the complete ADC calibration data, all channels of the ATE device are verified. The verification is performed by selecting data points to determine whether each channel meets the preset technical specifications and linearity requirements. If all channels pass the verification, the DC calibration ends. If at least one channel fails the verification, then the channel that fails the verification is DC calibrated.

2. The method according to claim 1, characterized in that, If the complete ADC calibration data is not detected in the ATE device, the ADC calibration data is reacquired.

3. The method according to claim 1, characterized in that, The number of data points selected in the verification is the minimum number required to satisfy the verification.

4. The method according to claim 3, characterized in that, The minimum number required to satisfy the verification is two.

5. The method according to claim 1, characterized in that, If at least one channel fails the verification, when performing DC calibration on the channel that fails the verification, calibration shall be performed by collecting at least five data points to ensure linearity.

6. The method according to claim 1, characterized in that, If the channel that failed verification still does not meet the preset technical specifications after DC calibration, then the channel is determined to have a hardware fault.

7. A system for improving DC calibration efficiency based on ATE equipment, characterized in that, include: The detection unit is used to detect whether complete ADC calibration data exists in the ATE equipment; If not detected, a prompt to obtain the complete ADC calibration data will be output; The verification unit is used to verify all channels of the ATE device based on the ADC calibration data when the detection unit detects the existence of complete ADC calibration data. The verification is performed by selecting data points to determine whether each channel meets the preset technical specifications and linearity requirements. A calibration unit is used to perform DC calibration on the channels that have failed verification when the verification unit determines that at least one channel has failed verification.

8. The system according to claim 7, characterized in that, The number of data points selected by the verification unit is the minimum number required to satisfy the verification.

9. The system according to claim 7, characterized in that, When the calibration unit performs DC calibration on the unverified channel, it uses a method of collecting at least five data points to ensure linearity.

10. The system according to claim 7, characterized in that, It also includes a fault determination unit, which is used to determine that the channel has a hardware fault if the channel still does not meet the preset technical specifications after the calibration unit performs DC calibration on the channel that failed verification.

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