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Abstract

The application discloses a special integrated circuit and a watchdog circuit thereof, and relates to the technical field of integrated circuit design.The watchdog circuit comprises a first watchdog module, a second watchdog module, a third watchdog module, a watchdog feeding instruction processing module and an abnormal state processing module.The first watchdog module is used for monitoring the frequency relation between the external clock input by the micro control unit of the upper computer and the internal clock of the special integrated circuit;the second watchdog module and the third watchdog module are respectively used for monitoring the correctness of different watchdog feeding time sequences;and the watchdog feeding instruction processing module is used for monitoring the legality of the watchdog feeding instructions of the second watchdog module and the third watchdog module.Through the cooperative work of the modules, the all-around monitoring of the clock synchronization, the watchdog feeding time sequence correctness and the instruction legality is realized, the blind area of the single monitoring dimension in the related art is covered, and the operation reliability of the ASIC chip in the embedded system is improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an application-specific integrated circuit and its watchdog circuit. Background Technology

[0002] As a key module to ensure the stable operation of embedded systems, the watchdog circuit's core function is to periodically detect the system's operating status and trigger a reset mechanism to restore the system to normal operation when an abnormality occurs.

[0003] In related technologies, watchdog designs have several limitations: 1) They cannot detect clock synchronization anomalies between the host computer's MCU (Microcontroller Unit) and ASIC (Application Specific Integrated Circuit), which may lead to misjudgment or missed judgment when the clocks of the two are out of sync; 2) They use fixed instructions or a single sequence for watchdog feeding, which is not flexible enough and cannot adapt to the reliability requirements of different application scenarios; and they do not perform legality verification, which poses a risk of being triggered by random signals, making the watchdog feeding mechanism unsafe.

[0004] Therefore, how to provide a watchdog circuit design that can comprehensively monitor clock synchronization, watchdog timing correctness, and instruction validity, thereby improving the operational reliability of ASIC chips in embedded systems, is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide an application-specific integrated circuit and its watchdog circuit to achieve comprehensive monitoring of clock synchronization, watchdog timing correctness and instruction legality, thereby improving the operational reliability of ASIC chips in embedded systems.

[0006] To solve the above technical problems, the present invention provides a watchdog circuit for an application-specific integrated circuit, comprising: a first watchdog module, a second watchdog module, a third watchdog module, a watchdog feed instruction processing module, and an abnormal state processing module;

[0007] The first watchdog module is used to monitor the frequency relationship between the external clock input to the microcontroller unit of the host computer and the internal clock of the application-specific integrated circuit; the second watchdog module is a window-type watchdog architecture, and the third watchdog module is a timeout-type watchdog architecture.

[0008] The watchdog feeding instruction processing module is used to verify the legality of the target watchdog feeding instruction sent by the microcontroller unit; if the target watchdog feeding instruction is legal, the module controls the target watchdog module to perform the watchdog feeding operation; wherein, the target watchdog feeding instruction is the watchdog feeding instruction corresponding to the target watchdog module, and the target watchdog module is the second watchdog module or the third watchdog module.

[0009] The abnormal state handling module is used to perform reset control on the dedicated integrated circuit and / or the microcontroller unit according to the abnormal signals of the first watchdog module, the second watchdog module and the third watchdog module respectively.

[0010] On the other hand, the first watchdog module includes:

[0011] A bidirectional counter is used to cross-count the external clock and the internal clock; if the count value corresponding to any monitoring clock signal within a preset clock period is not within the corresponding pre-designed value range, an abnormal signal of the first watchdog module is sent to the abnormal state processing module; wherein, the monitoring clock signal includes the external clock and the internal clock.

[0012] On the other hand, the bidirectional counter includes a first counter and a second counter;

[0013] The first counter is used to update the count value corresponding to the internal clock when the rising edge of the external clock is detected; after each preset clock cycle, a clearing operation is performed and the count value before clearing corresponding to the internal clock is detected; if the count value before clearing corresponding to the internal clock is not within the preset value range, an abnormal signal of the first watchdog module is sent to the abnormal state handling module.

[0014] The second counter is used to update the count value corresponding to the external clock when the rising edge of the internal clock is detected; after each preset clock cycle, a clearing operation is performed and the count value before clearing corresponding to the external clock is detected; if the count value before clearing corresponding to the external clock is not within the preset value range, an abnormal signal of the first watchdog module is sent to the abnormal state handling module.

[0015] On the other hand, the second watchdog module includes a first incrementing counter, a low threshold register, and a high threshold register. Specifically, when the watchdog module receives a feeding signal corresponding to the feeding operation, if the count value of the first incrementing counter is not within a preset counting interval, it sends an abnormal signal of the second watchdog module to the abnormal state handling module. The low threshold register is used to store the lower limit value of the preset counting interval, and the high threshold register is used to store the upper limit value of the preset counting interval.

[0016] On the other hand, the third watchdog module includes a second incrementing counter and a fixed threshold register; specifically, when the watchdog module receives the dog-feeding signal corresponding to the dog-feeding operation, if the count value of the second incrementing counter is greater than or equal to the fixed threshold stored in the fixed threshold register, the third watchdog module sends an abnormal signal to the abnormal state handling module.

[0017] On the other hand, the abnormal state processing module is specifically used to count the received abnormal signals; when the count value of the received abnormal signals is greater than the error count threshold, the dedicated integrated circuit and / or the microcontroller unit are reset.

[0018] On the other hand, the reset control of the dedicated integrated circuit and / or the microcontroller unit when the count value of the received abnormal signal is greater than the error count threshold includes:

[0019] When the count of received abnormal signals exceeds the error count threshold, check whether the configuration parameter in the reset enable configuration register is an enabled parameter.

[0020] If so, the dedicated integrated circuit is reset and a reset signal is output to the microcontroller unit.

[0021] On the other hand, the watchdog instruction processing module includes a memory, a first sequence index counter, and a second sequence index counter; wherein, the memory is used to store n pairs of preset check sequences and preset response sequences, the preset check sequence including a preset check instruction and a sequence index, the preset response sequence including a preset response instruction and a sequence index, the sequence index in each pair of preset check sequences and preset response sequences is the same, and the sequence index in different pairs of preset check sequences is different; the first sequence index counter is used to store the current sequence index corresponding to the second watchdog module, and the second sequence index counter is used to store the current sequence index corresponding to the third watchdog module;

[0022] The target watchdog feeding instruction includes a watchdog identifier and a feeding sequence instruction. Specifically, the feeding instruction processing module, when the target feeding instruction is valid, checks whether the target sequence index is the current sequence index in the target sequence index counter. If so, it controls the target watchdog module to perform a feeding operation, returns a target preset response sequence to the microcontroller unit, and updates the current sequence index in the target sequence index counter. The target sequence index is the sequence index in the feeding sequence instruction of the target feeding instruction. The target sequence index counter is the first or second sequence index counter corresponding to the target watchdog module, and the target watchdog module is the second or third watchdog module corresponding to the watchdog identifier. The target preset response sequence is a preset response sequence corresponding to a preset check sequence including the target sequence index.

[0023] On the other hand, updating the current sequence index in the target sequence index counter includes:

[0024] The current sequence index in the target sequence index counter is updated to the next sequence index according to a preset cyclic increment order; wherein, the preset cyclic increment order is the cyclic increment order of the n sequence indices in the n pairs of preset check sequences and preset response sequences.

[0025] In addition, the present invention also provides an application-specific integrated circuit, including: a watchdog circuit of the application-specific integrated circuit as described above.

[0026] The present invention provides a watchdog circuit for an application-specific integrated circuit (ASIC), comprising: a first watchdog module, a second watchdog module, a third watchdog module, a watchdog feed instruction processing module, and an abnormal state processing module; wherein, the first watchdog module is used to monitor the frequency relationship between the external clock input by the microcontroller unit of the host computer and the internal clock of the ASIC; the second watchdog module is a window-type watchdog architecture, and the third watchdog module is a timeout-type watchdog architecture; the watchdog feed instruction processing module is used to verify the legality of the target watchdog feed instruction sent by the microcontroller unit; if the target watchdog feed instruction is legal, it controls the target watchdog module to perform the watchdog feed operation; wherein, the target watchdog feed instruction is the watchdog feed instruction corresponding to the target watchdog module, and the target watchdog module is the second watchdog module or the third watchdog module; the abnormal state processing module is used to perform reset control on the ASIC and / or the microcontroller unit according to the abnormal signals of the first watchdog module, the second watchdog module, and the third watchdog module respectively.

[0027] As can be seen, this invention utilizes a first watchdog module to monitor the frequency relationship between the external clock input to the microcontroller unit of the host computer and the internal clock of the application-specific integrated circuit (ASIC). It utilizes a second and third watchdog module to monitor the correctness of different watchdog timing sequences, and a watchdog instruction processing module to monitor the legality of the watchdog instructions from the second and third watchdog modules. Through the collaborative work of these modules, comprehensive monitoring of clock synchronization, watchdog timing correctness, and instruction legality is achieved, covering the blind spots of single-dimensional monitoring in related technologies and improving the operational reliability of ASIC chips in embedded systems. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0029] Figure 1 This is a structural block diagram of a watchdog circuit for an application-specific integrated circuit provided in an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of the structure of a watchdog circuit for another application-specific integrated circuit provided in an embodiment of the present invention;

[0031] Figure 3 This is a structural diagram of a clock monitoring unit for a first watchdog module provided in an embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram illustrating an effective window of a second watchdog module and the generation of a watchdog feeding error, provided in an embodiment of the present invention.

[0033] Figure 5 This is a schematic diagram illustrating the counting and feeding mechanism of two built-in counters in a second watchdog module provided in an embodiment of the present invention.

[0034] Figure 6 This is a schematic diagram of feeding a dog in a third watchdog module provided in an embodiment of the present invention;

[0035] Figure 7 This is a schematic diagram of the watchdog circuit feeding process provided in an embodiment of the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Please refer to Figure 1 , Figure 1 This is a structural block diagram of a watchdog circuit for a dedicated integrated circuit provided in an embodiment of the present invention. The watchdog circuit includes: a first watchdog module 10, a second watchdog module 20, a third watchdog module 30, a watchdog feed command processing module 40, and an abnormal state processing module 50;

[0038] Among them, the first watchdog module 10 is used to monitor the frequency relationship between the external clock input of the microcontroller unit of the host computer and the internal clock of the application-specific integrated circuit; the second watchdog module 20 is a window-type watchdog architecture, and the third watchdog module 30 is a timeout-type watchdog architecture.

[0039] The watchdog instruction processing module 40 is used to verify the legality of the target watchdog instruction sent by the microcontroller unit; if the target watchdog instruction is legal, it controls the target watchdog module to perform the watchdog operation; wherein, the target watchdog instruction is the watchdog instruction corresponding to the target watchdog module, and the target watchdog module is the second watchdog module 20 or the third watchdog module 30.

[0040] The abnormal state handling module 50 is used to reset the application-specific integrated circuit and / or microcontroller unit according to the abnormal signals of the first watchdog module 10, the second watchdog module 20 and the third watchdog module 30.

[0041] It is understood that the first watchdog module 10 in this embodiment can serve as a clock synchronization monitoring unit, used to monitor the external clock (CLK_EXT, e.g., input from the microcontroller unit (MCU) of the host computer). Figure 2 The frequency relationship (i.e., clock synchronization) between the input clock of the host computer MCU and the internal clock (i.e., the internal reference clock) of the application-specific integrated circuit (ASIC) is defined as the correspondence between the frequencies of the external clock and the internal clock. This relationship is used to send a corresponding abnormal signal to the abnormal state handling module 50 when the frequency relationship is abnormal (e.g., the frequency change exceeds a threshold and / or the difference between the two frequencies exceeds a threshold). In other words, as... Figure 2As shown, the two input terminals of the first watchdog module 10 (watchdog 1) can be connected to the external clock output terminal of the MCU of the host computer and the internal clock output terminal of the application-specific integrated circuit (ASIC), respectively, to receive the two clock signals: the external clock input from the MCU of the host computer and the internal clock generated by the ASIC. The output terminal of the first watchdog module 10 can be connected to the input terminal of the abnormal state handling module 50 to send the abnormal signal of the first watchdog module 10 (such as...) to the abnormal state handling module 50. Figure 2 (overflow and underflow signals in the data).

[0042] Correspondingly, the specific structure of the first watchdog module 10 in this embodiment, that is, the specific method by which the first watchdog module 10 monitors the frequency relationship between the external clock and the internal clock, can be set by the designer according to the practical scenario and user needs. For example, the first watchdog module 10 can use a bidirectional counting mechanism to monitor the frequency relationship between the external clock and the internal clock to accurately detect the clock frequency offset. Compared with a single clock monitoring scheme (such as counting the external clock and the internal clock separately), it can significantly improve the clock synchronization reliability in heterogeneous systems. For example, the first watchdog module 10 may include: a bidirectional counter for cross-counting the external clock and the internal clock; if the count value corresponding to any monitored clock signal within a preset clock period is not within the corresponding pre-designed value range, an abnormal signal of the first watchdog module 10 is sent to the abnormal state processing module 50; wherein, the monitored clock signal includes the external clock and the internal clock.

[0043] Correspondingly, the bidirectional counter built into the first watchdog module 10 can cross-count two clock signals (i.e., external clock and internal clock), and the count value can be dynamically adjusted through the configuration register. The preset clock period can be a pre-set count value reset period, that is, when the count values ​​corresponding to both the external clock and the internal clock are within the pre-designed value range within the preset clock period, the count value can be reset; the preset clock period can be adjusted through programming. The pre-designed value range can be a preset threshold ± a preset percentage (e.g., 5%); when the count value corresponding to any monitoring clock signal is not within the corresponding pre-designed value range within the preset clock period, the bidirectional counter can generate an overflow or underflow signal, triggering the clock abnormality flag bit and sending an abnormal signal from the first watchdog module 10 to the abnormal state handling module 50.

[0044] The specific method by which the bidirectional counter performs cross-counting of the external and internal clocks can be set by the designer. For example, the bidirectional counter may include a first counter and a second counter. The first counter is used to update the count value corresponding to the internal clock when the rising edge of the external clock is detected. After each preset clock cycle, a clearing operation is performed and the count value before clearing corresponding to the internal clock is checked. If the count value before clearing corresponding to the internal clock is not within the preset value range, an abnormal signal of the first watchdog module 10 is sent to the abnormal state handling module 50. The second counter is used to update the count value corresponding to the external clock when the rising edge of the internal clock is detected. After each preset clock cycle, a clearing operation is performed and the count value before clearing corresponding to the external clock is checked. If the count value before clearing corresponding to the external clock is not within the preset value range, an abnormal signal of the first watchdog module 10 is sent to the abnormal state handling module 50.

[0045] For example, such as Figure 3 As shown, after power-on initialization, the first watchdog module 10 performs mutual frequency division (e.g., frequency reduction) and synchronization operations on the external clock (CLK_EXT) and internal clock (CLK_INT) respectively to facilitate subsequent cross-counting. The two built-in counters (i.e., the first counter and the second counter) of the first watchdog module 10 perform cross-counting of CLK_EXT and CLK_INT: when the rising edge of CLK_EXT arrives, CLK_INT is counted; when the rising edge of CLK_INT arrives, CLK_EXT is counted. Every T_CLR cycle (i.e., the preset clock cycle), the counter performs a clearing operation and checks the count value before clearing: if the count value exceeds the TH_CLK range (i.e., the pre-designed value range), the overflow (i.e., greater than the upper limit of the TH_CLK range) or underflow flag (i.e., less than the lower limit of the TH_CLK range) is set and sent to the abnormal state handling module 50.

[0046] The specific number and type of abnormal signals sent by the first watchdog module 10 to the abnormal state handling module 50 when the frequency relationship between the external clock and the internal clock changes can be set by the designer according to the practical scenario and user requirements. For example, the abnormal signal of the first watchdog module 10 can be a synchronization abnormal signal, or it can include overflow and underflow signals. This embodiment does not impose any restrictions on this.

[0047] It should be noted that the second watchdog module 20 in this embodiment can be a window-type watchdog architecture, that is, when the second watchdog module 20 receives the feeding signal corresponding to the feeding operation, if the count value is not within the valid window (i.e., the preset counting interval, such as...) Figure 3If the dog-feeding window time is specified, then the second watchdog module 20 (e.g., during the exception handling module 50) is sent to the exception handling module 50. Figure 2 Abnormal signals from the watchdog (2) in the system. For example... Figure 2 As shown, the counting input terminal of the second watchdog module 20 (watchdog 2) can be connected to the internal clock (CLK_INT) output terminal of the dedicated integrated circuit to use the internal clock as the counting clock for its internal counter, and count based on the internal clock; the feeding signal input terminal of the second watchdog module 20 can be connected to the first feeding signal output terminal of the feeding instruction processing module 40 to receive the feeding signal corresponding to the feeding operation sent by the feeding instruction processing module 40 (such as...). Figure 2 The output of the second watchdog module 20 can be connected to the input of the abnormal state handling module 50 to send an abnormal signal (such as the watchdog 2 feeding signal) to the abnormal state handling module 50. Figure 2 (overflow and underflow signals in the data).

[0048] Correspondingly, the specific structure of the second watchdog module 20 in this embodiment can be customized by the designer according to the practical scenario and user requirements. For example, the second watchdog module 20 may include a first increment counter, a low threshold register, and a high threshold register. Specifically, when the watchdog module 20 receives a watchdog signal corresponding to a watchdog feeding operation, if the count value of the first increment counter is not within a preset counting interval, it sends an exception signal of the second watchdog module 20 to the exception state handling module 50. The low threshold register is used to store the lower limit value of the preset counting interval, and the high threshold register is used to store the upper limit value of the preset counting interval. That is, the watchdog feeding signal can only effectively clear the first increment counter when it arrives within the interval COUNT_WIN∈[W_LOW, W_HIGH]. An underflow exception occurs before this interval, and an overflow exception occurs after this interval. COUNT_WIN can be the count value of the first increment counter. The interval [W_LOW, W_HIGH] can be the preset counting interval, where W_LOW and W_HIGH are the lower and upper limits of the preset counting interval, respectively.

[0049] Further, in this embodiment, the second watchdog module 20 can adopt a design of alternately clearing two counters to further enhance the accuracy of the watchdog feeding timing monitoring and reduce the risk of misjudgment caused by the abnormality of a single counter. That is to say, the first increment counter can include a third counter and a fourth counter; the third counter is used to clear when the number of times the second watchdog module 20 receives a watchdog feeding signal is odd; the fourth counter is used to clear when the number of times the second watchdog module 20 receives a watchdog feeding signal is even; when the second watchdog module 20 receives a watchdog feeding signal corresponding to a watchdog feeding operation, if the third counter or the fourth counter is not within a pre-designed counting range, it sends an abnormal signal of the second watchdog module 20 to the abnormal state processing module 50. For example, if a watchdog feeding instruction is received when the count value of the third counter or the fourth counter is less than W_LOW, an underflow abnormal signal is generated; if a watchdog feeding instruction is not received when the count value of the third counter or the fourth counter is greater than W_HIGH, an overflow abnormal signal is generated.

[0050] For example, as Figure 4 and Figure 5 shown, after the second watchdog module 20 is initialized, counter 1 (i.e., the third counter) starts incrementing from 0, and counter 2 (i.e., the fourth counter) remains 0 unchanged; when the count value reaches W_LOW, it enters the valid window, and when it reaches W_HIGH, it exits the valid window; after the watchdog feeding instruction processing module 40 receives the watchdog feeding instruction corresponding to the second watchdog module 20 sent by the MCU of the upper computer, after verifying that the watchdog feeding instruction is legal, it generates and sends a watchdog feeding signal corresponding to the watchdog feeding operation to the second watchdog module 20 (such as Figure 2 the watchdog 2 feeding signal in

[0051] ); the second watchdog module 20 clears the count value of counter 1 when receiving the watchdog feeding signal for the first time, and starts counter 2 incrementing from 0; clears the count value of counter 2 when receiving the watchdog feeding signal for the second time, and clears the count value of counter 1 again for the third time, and so on alternately; if a watchdog feeding signal is received when any count value in counter 1 and counter 2 is <W_LOW, an underflow abnormal signal is generated; if the corresponding watchdog feeding signal is not received when any count value in counter 1 and counter 2 is >W_HIGH, an overflow abnormality occurs, and the overflow or underflow flag is set correspondingly and sent to the abnormal state processing module 50.

[0052] Among them, the third watchdog module 30 in this embodiment can be an over-time watchdog architecture. That is, when the third watchdog module 30 receives the watchdog signal corresponding to the watchdog feeding operation, if the count value is greater than a pre-set threshold (i.e., a fixed threshold), it sends an abnormal signal of the third watchdog module 30 (such as the watchdog 3 in Figure 2 ) to the abnormal state processing module 50. As shown in Figure 2 , the counting input terminal of the third watchdog module 30 (watchdog 3) can be connected to the output terminal of the internal clock (CLK_INT) of the application-specific integrated circuit to use the internal clock as the counting clock of its internal counter and perform counting based on the internal clock; the watchdog signal input terminal of the third watchdog module 30 can be connected to the second watchdog signal output terminal of the watchdog feeding instruction processing module 40 to receive the watchdog signal corresponding to the watchdog feeding operation sent by the watchdog feeding instruction processing module 40 (such as the watchdog 3 feeding signal in Figure 2 ); the output terminal of the third watchdog module 30 can be connected to the input terminal of the abnormal state processing module 50 to send an abnormal signal of the third watchdog module 30 to the abnormal state processing module 50.

[0053] Correspondingly, for the specific structure of the third watchdog module 30 in this embodiment, it can be set by the designer according to the practical scenario and user requirements. For example, the third watchdog module 30 can include a second increment counter and a fixed threshold register; the third watchdog module 30 is specifically configured to, when receiving the watchdog signal corresponding to the watchdog feeding operation, if the count value of the second increment counter is greater than or equal to the fixed threshold stored in the fixed threshold register, send an abnormal signal of the third watchdog module 30 to the abnormal state processing module 50. That is to say, the watchdog signal needs to arrive when COUNT_FIX < T_FIX to effectively clear the second increment counter; when an effective watchdog instruction is not detected when COUNT_FIX ≥ T_FIX, an overflow abnormal signal (i.e., the abnormal signal of the third watchdog module 30) is generated; COUNT_FIX can be the count value of the second increment counter; T_FIX can be the fixed threshold.

[0054] For example, as shown in Figure 6 , after the third watchdog module 30 is initialized, the count value (COUNT_FIX) of the second increment counter starts to increase from 0; after the watchdog feeding instruction processing module 40 verifies the watchdog feeding instruction corresponding to the third watchdog module 30 sent by the MCU, it generates and sends a watchdog signal corresponding to the watchdog feeding operation to the third watchdog module 30 (such as the watchdog 3 feeding signal in Figure 2 ); if the watchdog signal is received when COUNT_FIX < T_FIX, the second increment counter is cleared; if no effective watchdog signal is received when COUNT_FIX reaches T_FIX, an overflow exception is generated, and the overflow flag is set correspondingly and sent to the abnormal state processing module 50.

[0055] It is understood that the watchdog feed instruction processing module 40 in this embodiment can verify the validity of the watchdog feed instructions sent by the MCU of the host computer to control the second watchdog module 20 to perform a watchdog feed operation and the watchdog feed instructions sent to control the third watchdog module 30 to perform a watchdog feed operation. When the watchdog feed instruction is valid, it controls the corresponding watchdog module (i.e., the second watchdog module 20 or the third watchdog module 30) to perform the watchdog feed operation. That is, the MCU of the host computer can send a watchdog feed instruction to the watchdog feed instruction processing module 40 to control the second watchdog module 20 to perform a watchdog feed operation, so that after the watchdog feed instruction processing module 40 verifies the validity of the watchdog feed instruction, it controls the second watchdog module 20 to perform the watchdog feed operation; the MCU of the host computer can also send a watchdog feed instruction to the watchdog feed instruction processing module 40 to control the third watchdog module 30 to perform a watchdog feed operation, so that after the watchdog feed instruction processing module 40 verifies the validity of the watchdog feed instruction, it controls the third watchdog module 30 to perform the watchdog feed operation.

[0056] Correspondingly, the specific method by which the watchdog instruction processing module 40 verifies the legality of a certain watchdog instruction (i.e., the target watchdog instruction) sent by the microcontroller unit can be set by the designer according to the practical scenario and user needs. For example, the target watchdog instruction may include a watchdog identifier and a fixed watchdog instruction. The watchdog instruction processing module 40 can determine that the target watchdog instruction is legal when the fixed watchdog instruction in the target watchdog instruction is a preset watchdog instruction, or when the fixed watchdog instruction is a preset watchdog instruction and the watchdog identifier is any preset identifier; otherwise, it determines that the target watchdog instruction is illegal. Among them, the watchdog identifier can be used to distinguish whether the instruction is used to control the watchdog operation of the second watchdog module 20 or the third watchdog module 30. That is, the preset identifier may include the identifier (such as address or ID code) corresponding to the second watchdog module 20 and the identifier corresponding to the third watchdog module 30.

[0057] Furthermore, the watchdog feeding instruction processing module 40 can adopt a multi-pair (i.e., n pairs) rotating check-response sequence mechanism. Compared with the fixed instruction watchdog feeding method, this can significantly reduce the risk of false triggering caused by random interference and improve the security of the watchdog feeding operation. For example, the watchdog feeding instruction processing module 40 includes a memory, a first sequence index counter, and a second sequence index counter. The memory is used to store n pairs of preset check sequences and preset response sequences. The preset check sequence includes a preset check instruction and a sequence index, and the preset response sequence includes a preset response instruction and a sequence index. The sequence indexes in each pair of preset check sequences and preset response sequences are the same, and the sequence indices in different pairs of preset check sequences are different. The first sequence index counter is used to store the current sequence index corresponding to the second watchdog module 20, and the second sequence index counter is used to store the current sequence index corresponding to the third watchdog module 30. n is a positive integer greater than or equal to 2.

[0058] The target watchdog instruction includes a watchdog identifier and a watchdog sequence instruction. The watchdog instruction processing module 40 is specifically used to, when the target watchdog instruction is valid, check whether the target sequence index is the current sequence index in the target sequence index counter; if so, it controls the target watchdog module to perform the watchdog operation and returns a target preset response sequence (such as...) to the microcontroller unit. Figure 2 The system returns a response sequence to the host MCU and updates the current sequence index in the target sequence index counter. The target sequence index is the sequence index in the watchdog feed instruction. The target sequence index counter is the first or second sequence index counter corresponding to the target watchdog module. The target watchdog module is the second watchdog module 20 or the third watchdog module 30 corresponding to the watchdog identifier. The target preset response sequence is the preset response sequence corresponding to the preset check sequence that includes the target sequence index. For example, when n is 8, the memory in the dog feeding instruction processing module 40 can store 8 pairs of preset check sequences (CHECK_WORD [0 to 7]) and preset response sequences (RESPONSE_WORD [0 to 7]), namely CHECK_WORD [0] and RESPONSE_WORD [0], ..., CHECK_WORD [7] and RESPONSE_WORD [7]; the count value (INDEX2, i.e., the current sequence index) stored in the first sequence index counter can be any value from 0 to 7; the count value (INDEX3, i.e., the current sequence index) stored in the second sequence index counter can be any value from 0 to 7; CHECK_WORD can be a preset check instruction, and RESPONSE_WORD can be a preset response instruction.

[0059] Correspondingly, when the target sequence index is not the current sequence index in the target sequence index counter, the dog-feeding instruction processing module 40 can send an exception signal (e.g., ...) to the exception state processing module 50. Figure 2 (Watchdog 2 sequence error signal or watchdog 3 sequence error signal in the watchdog). The abnormal state processing module 50 can be used to reset the application-specific integrated circuit and / or microcontroller unit according to the abnormal signals of the first watchdog module 10, the second watchdog module 20, the third watchdog module 30 and the watchdog feeding instruction processing module 40.

[0060] Correspondingly, the specific method for updating the current sequence index in the target sequence index counter, i.e., the specific looping method of the count values ​​in the first and second sequence index counters, can be set by the designer according to the practical scenario and user needs. For example, the current sequence index in the target sequence index counter can be updated to the next sequence index according to the preset cyclic incrementing order; where the preset cyclic incrementing order is the cyclic incrementing order of n sequence indices in the preset check sequence and preset response sequence.

[0061] For example, when n is 8, the memory in the watchdog feed instruction processing module 40 can be two independent register sequences: storing CHECK_WORD [0 to 7] and RESPONSE_WORD [0 to 7]; the watchdog feed instruction processing module 40 can maintain independent sequence index counters for watchdog 2 and watchdog 3 respectively: a first sequence index counter and a second sequence index counter, with an initial index value of 0 and a maximum value of 7; the watchdog feed instruction processing module 40 can distinguish whether the instruction controls the watchdog 2 or 3 feed operation based on the address (i.e., watchdog identifier) ​​in the target watchdog feed instruction sent by the MCU of the host computer; the MCU of the host computer sends CHECK_WORD [INDEXm] to the watchdog feed instruction processing module 40 to control the corresponding watchdog m (n=2 or 3); after receiving the corresponding watchdog feed, watchdog m returns RESPONSE_WORD [INDEXm], and the target sequence index counter (i.e., the first sequence index counter or the second sequence index counter) corresponding to watchdog m automatically increments: INDEXm=(INDEXm + 1) When INDEXm is 7, the value will be 0 after the next increment; when the sequence index (i.e. the target sequence index) in the received dog feed sequence instruction does not match the current sequence index (INDEXm) in the target sequence index counter, an instruction sequence error signal (i.e., the abnormal signal of the dog feed instruction processing module 40) is generated.

[0062] It should be noted that the abnormal state handling module 50 in this embodiment can be responsible for error counting and reset control. That is, the abnormal state handling module 50 can perform reset control on the dedicated integrated circuit and / or microcontroller unit based on the abnormal signals received from the first watchdog module 10, the second watchdog module 20, the third watchdog module 30, and the watchdog feeding command processing module 40, such as... Figure 2 As shown, the ASIC reset signal is output to control the reset of the dedicated integrated circuit, and a reset signal (host computer MCU reset signal) is output to the microcontroller unit to control the MCU reset.

[0063] Correspondingly, the specific method for error counting and reset control by the abnormal state handling module 50 in this step can be set by the designer according to the practical scenario and user needs. For example, the abnormal state handling module 50 can be specifically used to count the received abnormal signals; when the count value of the received abnormal signal is greater than the error count threshold, the application-specific integrated circuit and / or microcontroller unit is reset. In other embodiments, the abnormal state handling module 50 can also count different types of abnormal signals (such as abnormal signals sent by different modules) separately; when the count value of a certain type of abnormal signal is greater than the corresponding error count threshold, the corresponding processing operation (such as reset control) is triggered; so as to realize a hierarchical error response mechanism by using independent error counting and cumulative judgment logic, avoiding system overreaction caused by a single error, and realizing accurate error management. For example, the abnormal state handling module 50 may include three error counters (i.e., a first error counter, a second error counter, and a third error counter). The first error counter records the number of times abnormal signals sent by the first watchdog module 10 are received. The second error counter records the number of times abnormal signals sent by the second watchdog module 20 and the number of times sequence error signals of the second watchdog module 20 sent by the abnormal state handling module 50 are received. The third error counter records the number of times abnormal signals sent by the third watchdog module 30 and the number of times sequence error signals of the third watchdog module 30 sent by the abnormal state handling module 50 are received. The abnormal state handling module 50 may perform a reset control on the application-specific integrated circuit and / or microcontroller unit when the count value of any error counter exceeds the error count threshold. This embodiment does not impose any limitations on this.

[0064] Furthermore, in this embodiment, the abnormal state handling module 50 can determine whether to perform reset control based on the configuration parameter (RST_EN) in the reset enable configuration register. As described above, the process of resetting the dedicated integrated circuit and / or microcontroller unit when the count value of the received abnormal signal exceeds the error count threshold can include: when the count value of the received abnormal signal exceeds the error count threshold, detecting whether the configuration parameter in the reset enable configuration register is an enabled parameter; if yes, controlling the dedicated integrated circuit to reset and outputting a reset signal to the microcontroller unit; if no, the process can end to continue counting the received abnormal signals.

[0065] For example, the abnormal state handling module 50 may include an error counter and a reset enable configuration register; the abnormal state handling module 50 may trigger an error reset flag when the count value of the error counter is greater than 3; based on the error reset flag, it may detect the configuration parameters in the reset enable configuration register and decide whether to perform reset control on the dedicated integrated circuit and the microcontroller unit. If the configuration parameter is an enable parameter (such as 1), the dedicated integrated circuit and the microcontroller unit will be reset; if the configuration parameter is not an enable parameter (such as 1), the process will end and the dedicated integrated circuit and the microcontroller unit will not be reset.

[0066] For example, such as Figure 7As shown, the watchdog circuit's watchdog sequence verification process and exception handling process are as follows, including: 1) During initialization, INDEX2 and INDEX3 are both set to 0; 2) The host computer's MCU needs to send a CHECK_WORD [0] carrying the address for the first watchdog feed, i.e., a watchdog feed instruction; 3) The watchdog feed instruction processing module 40 will determine whether the instruction is applied to watchdog 2 (i.e., the second watchdog module 20) or watchdog 3 (i.e., the third watchdog module 30) based on the address carried by the watchdog feed instruction (i.e., the target watchdog feed instruction) sent by the host computer's MCU; 4) The watchdog feed instruction processing module 40 determines whether the watchdog feed sequence instruction is correct, i.e., whether it is equal to the preset CHECK_WORD. [0]; If an error occurs, the sequence error of watchdog 2 or 3 is set and output to the exception state handling module 50; If correct, the watchdog feeding operation is performed; 5) When the watchdog feeding instruction processing module 40 performs the watchdog 2 feeding operation, it determines whether the watchdog 2 counter is within the valid window. If not, an overflow or underflow error is generated and output to the exception state handling module 50; If it is, the watchdog is fed correctly and the counter is cleared; When the watchdog feeding instruction processing module 40 performs the watchdog 3 feeding operation, it determines whether the watchdog 3 counter is greater than the fixed threshold. If it is greater, an overflow error is generated and output to the exception state handling module 50; If it is not greater, the watchdog is fed correctly and the counter is cleared; 6) After the watchdog feeding is completed, INDEXm is incremented by 1, and the watchdog feeding instruction processing module 40 returns the target preset response sequence, such as RESPONSE_WORD [0]. Subsequent watchdog feedings need to send the corresponding CHECK_WORD in the INDEXm loop order. [INDEXm]; When INDEXm is 7, the value will be 0 after the next increment; If the transmission sequence does not match, an instruction error will be generated, and the error will be counted in the error counter of the corresponding watchdog; 7) The abnormal state handling module 50 monitors abnormal signals in real time, including: overflow and underflow errors of watchdog 1 (i.e., the first watchdog), overflow and underflow errors and sequence errors of watchdog 2 and overflow and sequence errors of watchdog 3; When any abnormal signal is detected, the corresponding error counter is incremented by 1; When the cumulative error count of any error counter is >3, if the configuration parameter in the reset enable configuration register is an enable parameter, the ASIC chip is reset and a reset signal is output to the MCU; After the system returns to normal, the error counter can be reset by writing clear command.

[0067] In this embodiment, the present invention utilizes a first watchdog module 10 to monitor the frequency relationship between the external clock input to the microcontroller unit of the host computer and the internal clock of the application-specific integrated circuit (ASIC). It utilizes a second watchdog module 20 and a third watchdog module 30 to monitor the correctness of different watchdog timing sequences, and a watchdog instruction processing module 40 to monitor the legality of the watchdog instructions from the second and third watchdog modules 20 and 30. Through the collaborative work of these modules, comprehensive monitoring of clock synchronization, watchdog timing correctness, and instruction legality is achieved, covering the blind spots of single-dimensional monitoring in related technologies and improving the operational reliability of ASIC chips in embedded systems.

[0068] Corresponding to the watchdog circuit embodiment above, this embodiment of the invention also provides an application-specific integrated circuit (ASIC). The ASIC described below and the watchdog circuit of the ASIC described above can be referred to in correspondence.

[0069] An application-specific integrated circuit (ASIC) includes a watchdog circuit for the ASIC as described in the above embodiments.

[0070] The application-specific integrated circuit provided in this embodiment can be an ASIC chip.

[0071] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the application-specific integrated circuits disclosed in the embodiments, since they correspond to the watchdog circuits disclosed in the embodiments, the description is relatively simple; relevant parts can be found in the method section.

[0072] The present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A watchdog circuit for a special purpose integrated circuit, characterized in that, include: The system includes a first watchdog module, a second watchdog module, a third watchdog module, a watchdog feeding command processing module, and an exception handling module. The first watchdog module is used to monitor the frequency relationship between the external clock input to the microcontroller unit of the host computer and the internal clock of the application-specific integrated circuit; the second watchdog module is a window-type watchdog architecture, and the third watchdog module is a timeout-type watchdog architecture. The watchdog feeding instruction processing module is used to verify the legality of the target watchdog feeding instruction sent by the microcontroller unit; if the target watchdog feeding instruction is legal, the module controls the target watchdog module to perform the watchdog feeding operation; wherein, the target watchdog feeding instruction is the watchdog feeding instruction corresponding to the target watchdog module, and the target watchdog module is the second watchdog module or the third watchdog module. The abnormal state handling module is used to perform reset control on the dedicated integrated circuit and / or the microcontroller unit according to the abnormal signals of the first watchdog module, the second watchdog module and the third watchdog module respectively; The first watchdog module includes: A bidirectional counter is used to cross-count the external clock and the internal clock; if the count value corresponding to any monitoring clock signal within a preset clock period is not within the corresponding preset value range, an abnormal signal of the first watchdog module is sent to the abnormal state processing module; wherein, the monitoring clock signal includes the external clock and the internal clock; The second watchdog module includes a first incrementing counter, a low threshold register, and a high threshold register. Specifically, when the watchdog module receives a feeding signal corresponding to the feeding operation, if the count value of the first incrementing counter is not within a preset counting interval, it sends an abnormal signal of the second watchdog module to the abnormal state handling module. The low threshold register stores the lower limit value of the preset counting interval, and the high threshold register stores the upper limit value of the preset counting interval. The third watchdog module includes a second incrementing counter and a fixed threshold register. Specifically, when the watchdog module receives the feeding signal corresponding to the feeding operation, if the count value of the second incrementing counter is greater than or equal to the fixed threshold stored in the fixed threshold register, the watchdog module sends an abnormal signal to the abnormal state handling module. The watchdog command processing module includes a memory, a first sequence index counter, and a second sequence index counter. The memory stores n pairs of preset check sequences and preset response sequences. Each preset check sequence includes a preset check instruction and a sequence index, and each preset response sequence includes a preset response instruction and a sequence index. The sequence indexes in each pair of preset check sequences and preset response sequences are the same, while the sequence indexes in different pairs of preset check sequences are different. The first sequence index counter stores the current sequence index corresponding to the second watchdog module, and the second sequence index counter stores the current sequence index corresponding to the third watchdog module. The target watchdog feeding instruction includes a watchdog identifier and a feeding sequence instruction. Specifically, the feeding instruction processing module, when the target feeding instruction is valid, checks whether the target sequence index is the current sequence index in the target sequence index counter. If so, it controls the target watchdog module to perform a feeding operation, returns a target preset response sequence to the microcontroller unit, and updates the current sequence index in the target sequence index counter. The target sequence index is the sequence index in the feeding sequence instruction of the target feeding instruction. The target sequence index counter is the first or second sequence index counter corresponding to the target watchdog module, and the target watchdog module is the second or third watchdog module corresponding to the watchdog identifier. The target preset response sequence is a preset response sequence corresponding to a preset check sequence including the target sequence index.

2. The watchdog circuit of the application-specific integrated circuit according to claim 1, characterized in that, The bidirectional counter includes a first counter and a second counter; The first counter is used to update the count value corresponding to the internal clock when the rising edge of the external clock is detected; after each preset clock cycle, a clearing operation is performed and the count value before clearing corresponding to the internal clock is detected; if the count value before clearing corresponding to the internal clock is not within the preset value range, an abnormal signal of the first watchdog module is sent to the abnormal state handling module. The second counter is used to update the count value corresponding to the external clock when the rising edge of the internal clock is detected; after each preset clock cycle, a clearing operation is performed and the count value before clearing corresponding to the external clock is detected; if the count value before clearing corresponding to the external clock is not within the preset value range, an abnormal signal of the first watchdog module is sent to the abnormal state handling module.

3. The watchdog circuit of the application-specific integrated circuit according to claim 1, characterized in that, The abnormal state processing module is specifically used to count the received abnormal signals; when the count value of the received abnormal signals is greater than the error count threshold, the dedicated integrated circuit and / or the microcontroller unit are reset.

4. The watchdog circuit of the application-specific integrated circuit according to claim 3, characterized in that, The step of resetting the dedicated integrated circuit and / or the microcontroller unit when the count value of the received abnormal signal exceeds the error count threshold includes: When the count of received abnormal signals exceeds the error count threshold, check whether the configuration parameter in the reset enable configuration register is an enabled parameter. If so, the dedicated integrated circuit is reset and a reset signal is output to the microcontroller unit.

5. The watchdog circuit of the application-specific integrated circuit according to claim 1, characterized in that, Updating the current sequence index in the target sequence index counter includes: The current sequence index in the target sequence index counter is updated to the next sequence index according to a preset cyclic increment order; wherein, the preset cyclic increment order is the cyclic increment order of the n sequence indices in the n pairs of preset check sequences and preset response sequences.

6. A special-purpose integrated circuit, characterized in that, include: The watchdog circuit of the application-specific integrated circuit as described in any one of claims 1 to 5.

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