Data processing method, processing component and server

Abstract

The invention discloses a data processing method, a processing assembly and a server, and the method comprises the steps: carrying out the periodic sampling of a plurality of groups of communication buses, obtaining the initial data corresponding to each group of communication buses, and storing the initial data in a target storage region, the initial data being the original protocol data transmitted by each group of communication buses, the storage subarea of the target storage area and the channel identifier of the communication bus have a corresponding relationship; in response to reading the initial data of the target storage area, converting the read initial data into decoded data with a channel identifier; and transmitting the decoded data to a processing module, wherein the processing module is used for processing the decoded data.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and more particularly to a data processing method, a processing component and a server. BACKGROUND

[0002] A server backplane is a key component inside a server, and is used to realize signal connection and data transmission between a mainboard and devices such as hard disks. For example, a server backplane can connect a host and backplane devices (such as hard disks) through a communication bus.

[0003] In a server backplane, a bus processing component (such as a CPLD, a complex programmable logic device) is usually used to sample a communication bus, so as to realize data transmission between a host and backplane devices. The bus processing component needs to process multiple groups of bus data at the same time, and each group needs a separate decoding module for decoding, which leads to a large amount of logic resource occupation of the bus processing component. If a large-scale bus processing component is used to solve the above problem, the system cost will be increased. SUMMARY

[0004] Therefore, the present application provides the following technical solutions:

[0005] A data processing method comprises the following steps:

[0006] Periodically sampling multiple groups of communication buses to obtain initial data corresponding to each group of communication buses, and storing the initial data into a target storage area, wherein the initial data is original protocol data transmitted by each group of communication buses, and a storage partition of the target storage area has a corresponding relationship with a channel identifier of a communication bus;

[0007] In response to reading the initial data of the target storage area, converting the read initial data into decoded data with a channel identifier;

[0008] Transmitting the decoded data to a processing module, wherein the processing module is used to process the decoded data.

[0009] Optionally, the step of periodically sampling multiple groups of communication buses to obtain initial data corresponding to each group of communication buses, and storing the initial data into a target storage area comprises the following steps:

[0010] According to a preset time division multiplexing mode, multiple groups of communication buses are sequentially sampled in turn at different time slices to obtain initial data corresponding to each group of communication buses, wherein each time slice corresponds to a sampling period of each group of communication buses;

[0011] store the initial data into a storage partition corresponding to the channel identifier in the target storage area according to the channel identifier corresponding to the time slice where the sampling is located; wherein each group of communication buses has a corresponding channel identifier; and the storage partitions of the target storage area have a corresponding relationship with the channel identifiers of the communication buses.

[0012] Optionally, the storage partitions in the target storage area represent divisions according to the channel identifiers corresponding to the communication buses, wherein the channel identifiers corresponding to the communication buses are obtained through a target register, and the target register stores the channel identifiers corresponding to the communication buses determined based on bus characteristics of the communication buses.

[0013] Optionally, in response to reading the initial data of the target storage area, the read initial data is converted into decoded data with a channel identifier, including:

[0014] reading a sampling sequence number corresponding to the current initial data of the sampling timing record;

[0015] querying a preset mapping table based on the sampling sequence number to determine a corresponding channel identifier, wherein the mapping table stores a one-to-one correspondence between the sampling sequence number and the channel identifier;

[0016] obtaining a communication bus attribute parameter matching the channel identifier, wherein the communication bus attribute parameter includes a slave address and a register address;

[0017] embedding the channel identifier and the bus attribute parameter into a protocol frame structure of the initial data to generate decoded data carrying the channel identifier; the protocol frame structure represents the format of the data when transmitted on the communication bus.

[0018] Optionally, the processing module is configured to process the decoded data, including: the processing module identifies the channel identifier in the decoded data; in response to the channel identifier in the decoded data matching a channel identifier preset by the processing module itself, activating the address information of the processing module to process the decoded data; and in response to the channel identifier in the decoded data not matching the channel identifier preset by the processing module itself, ignoring the decoded data.

[0019] Optionally, the storing of the initial data into the target storage area includes:

[0020] detecting a remaining storage space of a storage partition corresponding to the current communication bus in the target storage area;

[0021] if the remaining storage space meets the storage requirement of the initial data, writing the initial data into the remaining space according to the sampling timing;

[0022] if the remaining storage space does not meet the storage requirement of the initial data, determining a target storage sub-partition to be released based on a sampling timestamp of data in a storage partition of the target storage region;

[0023] after clearing the historical data of the target storage sub-partition, writing the initial data into the target storage sub-partition.

[0024] A processing assembly comprises:

[0025] a storage module configured to periodically sample a plurality of communication buses, obtain initial data corresponding to each of the communication buses, and store the initial data into a target storage region, wherein the initial data is original protocol data transmitted by each of the communication buses, and a storage partition of the target storage region has a corresponding relationship with a channel identifier of a communication bus;

[0026] a decoding module configured to, in response to reading the initial data from the target storage region, convert the read initial data into decoded data with a channel identifier;

[0027] a transmission module configured to transmit the decoded data to a processing module;

[0028] the processing module is configured to process the decoded data.

[0029] A server comprises a server backplane, at least one controlled device is arranged in the server backplane, and the controlled device is connected with the processing assembly through a plurality of communication buses;

[0030] The processing assembly is configured to periodically sample a plurality of communication buses, obtain initial data corresponding to each of the communication buses, and store the initial data into a target storage region, wherein the initial data is original protocol data transmitted by each of the communication buses, and a storage partition of the target storage region has a corresponding relationship with a channel identifier of a communication bus; in response to reading the initial data from the target storage region, the read initial data is converted into decoded data with a channel identifier; and the decoded data is transmitted to a processing module, and the processing module is configured to process the decoded data.

[0031] Optionally, the server further comprises a host;

[0032] The host is connected with the processing assembly, and is configured to initiate an access instruction to the processing assembly and receive a processing result fed back by the processing assembly.

[0033] Optionally, the processing module is an I2C slave module. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0035] Figure 1 A flow diagram of a data processing method provided by an embodiment of the present application;

[0036] Figure 2 A schematic diagram of data storage in a time division multiplexing mode provided by an embodiment of the present application;

[0037] Figure 3 A CPLD multipath I2C slave time division multiplexing architecture diagram provided by an embodiment of the present application;

[0038] Figure 4 An I2C slave module time division multiplexing channel data processing schematic diagram provided by an embodiment of the present application;

[0039] Figure 5 A structural schematic diagram of a processing component provided by an embodiment of the present application;

[0040] Figure 6 A structural schematic diagram of a server provided by an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of protection of the present application.

[0042] The terms "first" and "second" and the like in the present application are used to distinguish different objects, and are not used to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not set to the listed steps or units, but can include steps or units not listed.

[0043] The embodiment of the application provides a data processing method, which can be applied to a processing component (such as a CPLD, a complex programmable logic device) in a server backplane, and through time multiplexing processing mode, a plurality of communication buses are alternately sampled, and the sampled data is associated with a channel identifier, so that a single decoding module replaces a plurality of parallel communication slave modules, the logical resource occupation of the processing component and the hardware cost are reduced, and the integrity and real-time processing of the multi-channel communication bus data are ensured.

[0044] The application scenarios corresponding to the embodiment of the application include but are not limited to: data acquisition and control of a plurality of I2C (Inter-Integrated Circuit, a kind of serial communication bus protocol, used for intercommunication between chips) buses of a server backplane controlled device (such as a temperature sensor, a voltage monitoring chip and the like); data interaction of a plurality of bus peripherals in an industrial control field; centralized processing of multi-channel communication data in an embedded system and the like. Taking the application scenario of data acquisition and control of a plurality of I2C buses of a server backplane controlled device as an example, I2C communication is usually initiated and controlled by a master device (Master) (such as a CPU, a BMC), and one or more slave devices (Slave) (such as a sensor, a memory chip) respond. Usually, the host BMC needs to manage and monitor a plurality of hard disks (such as 8) on the backplane through the I2C bus, and each hard disk is an I2C slave device. The processing component CPLD is placed on the backplane and serves as a data transmission bridge between the host and the hard disk. In order to realize this function, the traditional method is that the engineer needs to program 8 independent I2C slave modules in the CPLD. Each I2C slave module is responsible for processing the communication of one I2C bus and interacting with one hard disk, which will make the CPLD logical resource occupation too high, and a plurality of same function I2C slave modules repeatedly consume a large number of programmable logic units (such as LUTs), resulting in low resource utilization. In addition, in order to accommodate all parallel modules, a larger and more expensive CPLD device must be selected, which significantly increases the hardware cost. In order to solve the above problems, the data processing method provided by the embodiment of the application uses a processing component (such as a CPLD) as a hardware platform, and uses an efficient I2C slave module with a label (channel identifier) to replace a plurality of parallel I2C slave modules, thereby solving the resource and cost problems caused by multi-channel I2C bus management.

[0045] Reference Figure 1 A flowchart of a data processing method provided by the embodiment of the application is shown in the figure, the method can be applied to a processing component such as a CPLD in a server backplane, and can include the following steps:

[0046] S101, periodically sample a plurality of communication buses, obtain initial data corresponding to each communication bus, and store the initial data to a target storage area.

[0047] S102, in response to reading the initial data of the target storage area, converting the read initial data into decoded data with channel identification.

[0048] S103, transmitting the decoded data to the processing module.

[0049] In step S101, the multiple groups of communication components refer to the communication buses on the server backplane connected to different control devices, which can include 8 groups of I2C buses, respectively connected to 8 different sensors. In the process of periodically sampling multiple communication buses, the initial data corresponding to each communication bus can be obtained. The initial data is the original protocol data transmitted by each communication bus, such as including the timing signal, level signal of I2C bus and the original monitoring data (such as binary signal corresponding to temperature value) output by the sensor. Then, the initial data is stored in the target storage area, and the storage partition of the target storage area has a corresponding relationship with the channel identification of the communication bus. For example, the target storage area can be a RAM (Random Access Memory, Random Access Memory) storage unit built-in CPLD, which is divided into multiple storage partitions according to the number of communication buses, and each partition corresponds to a group of communication buses one by one, such as channel identification 0 corresponding to the first group of I2C buses, and partition 0 corresponding to channel identification 0. In the embodiments of the present application, the channel identification can be a unique identity stored in the CPLD hard core storage unit in advance, which is bound to the physical connection order of each group of communication buses, such as the first group of buses binding identification 0, the second group binding identification 1, and so on.

[0050] For example, the CPLD samples 8 groups of I2C buses at a preset period (such as 1us / second), such as using a "polling sampling" method, sampling one group of buses each time, and circulating in turn (such as the first 1us samples the first group of buses, the second 1us samples the second group of buses, and so on. The eighth 1us samples the eighth group of buses); after sampling is completed, according to the channel identification corresponding to the current bus (such as sampling the third group of buses, the channel identification is 2), the initial data is written into the storage partition corresponding to the identification (such as partition 2) in RAM.

[0051] By setting the storage partition matching the channel identification of the communication bus in the target storage area, the initial data of multiple groups of communication buses can be stored in the corresponding partition during the storage stage, avoiding data confusion during subsequent interpretation, and at the same time, periodic sampling can obtain the state of the controlled device in real time, meeting the real-time demand of server monitoring hardware.

[0052] In step S102, the I2C slave state machine in the processing component (such as CPLD) actively reads initial data from the target storage area as needed, for example, when the host initiates a read operation request, or the state machine polls that the channel needs to process data, or the CPLD is preset at a period (such as 1 us / time synchronized with the sampling period). The I2C slave state machine reads the initial data from the target storage area. Then the read initial data is converted into decoded data with channel identification. The decoded data refers to digital signals conforming to the I2C protocol specification, including channel identification, slave address, register address, read-write data and other core information. Among them, the I2C slave state machine is a hardware logic unit inside the CPLD, which is used to read data in the target storage area and convert the decoded data according to the I2C protocol.

[0053] For example, when the CPLD needs to read the data of the third group of communication buses, the I2C slave state machine is triggered to read the initial data of the corresponding partition (such as partition 2) of the target storage area, such as "00110101". Then the channel identification 2 corresponding to the partition is called from the CPLD hard core, and the I2C protocol parameters (such as slave address 0x48 and register address 0x00) of the third group of buses are obtained. "Channel identification 2 + slave address 0x48 + register address 0x00 + data 00110101" is packaged into decoded data conforming to the I2C protocol frame format (such as protocol frame: 0x48 0x00 0x23 0x02, where 0x02 is the hexadecimal representation of channel identification). The initial data is converted into decoded data with channel identification, which not only ensures that the data format conforms to the I2C protocol specification, but also clearly indicates the data source through the channel identification, providing a data basis for the accurate matching of subsequent processing modules.

[0054] In step S103, the processing module refers to the I2C slave module corresponding to each group of communication buses, such as I2C slave module 1 corresponding to channel identification 0. Each processing module is preset with a unique channel identification. When receiving decoded data, the corresponding processing module can only reserve the decoded data matching its own channel identification, and then perform corresponding processing, such as performing read-write operation. For example, the processing module can upload temperature data to the host, or receive host instructions to control the sensor, etc.

[0055] For example, after transmitting the decoded data to all I2C slave modules, each slave module receives the data, first reads the channel identifier in the data: the processing module Slave3 (preset identifier 2) identifies that the identifier matches, activates its own slave address 0x48 and register address 0x00, parses the data “0x23” and confirms that it is temperature data, and then feeds back the data to the host; other slave modules (such as Slave1 and Slave2) identify that the identifier does not match, and directly ignore the data. In this process, the processing module filters the decoded data it needs based on the channel identifier, avoiding the waste of resources caused by multiple processing modules processing the same data at the same time, while ensuring that the data is only processed by the corresponding processing module, improving the reliability of communication.

[0056] The embodiment of the application provides a data processing method, which can periodically sample multiple communication buses, store the sampled original protocol data (i.e., initial data) in a target storage area according to channel identifiers, and then convert the initial data into decoded data with channel identifiers and distribute the decoded data to corresponding processing modules, thereby replacing the traditional multi-channel parallel processing architecture with a single processing link, significantly reducing the logical resource occupation of processing components such as CPLD, and making it possible to use low-cost and small-scale CPLD to implement multi-channel high-speed bus management while ensuring the real-time data transmission and effectively reducing the hardware cost.

[0057] The related features of the data processing method of the embodiment of the application will be described below in combination with corresponding application scenarios.

[0058] In some embodiments of the application, time division multiplexing (TDM) mode is used to realize multi-bus time-sharing sampling to ensure the order of sampling and storage. Correspondingly, the process of periodically sampling multiple communication buses to obtain initial data corresponding to each communication bus and storing the initial data in a target storage area can include:

[0059] According to a preset time division multiplexing mode, multiple communication buses are sequentially sampled in different time slices to obtain initial data corresponding to each communication bus. Based on the channel identifier corresponding to the time slice where the sampling is performed, the initial data is stored in a storage partition corresponding to the channel identifier in the target storage area.

[0060] Each time slice corresponds to a group of communication bus sampling periods. Each group of communication bus has a corresponding channel identifier, and the storage partition of the target storage area has a corresponding relationship with the channel identifier of the communication bus. The preset time division multiplexing mode means that the time is divided into time slices of fixed length, each time slice is allocated to a group of communication buses, and only the bus in the corresponding time slice samples data, such as 8us for 1 sampling period, which is divided into 8 time slices of 1us, time slice 0 corresponds to the first group of buses, time slice 1 corresponds to the second group of buses, and so on. The correspondence between the time slice identifier and the channel identifier (such as time slice 0 corresponding to channel identifier 0) can be pre-stored to ensure that the data sampled by each time slice can be accurately matched with the channel identifier. In the sampling stage, first, record the mapping table of the time slice and the channel identifier, and the timing control unit of the CPLD triggers the sampling in the time slice order, such as time slice 0 (0-1us): triggering the sampling module to sample the first group of buses, obtaining the initial data, and then determining the channel identifier 0 according to the mapping table, and writing the data into the RAM partition 0. Time slice 1 (1-2us): triggering the sampling module to sample the second group of buses, determining the channel identifier 1 according to the mapping table, and writing the data into the RAM partition 1; and so on, until the sampling and storage of the 8 groups of buses are completed in the 8 time slices.

[0061] For example, see Figure 2 which shows a schematic diagram of data storage in a time division multiplexing mode provided by an embodiment of the application, in Figure 2 which includes time slices T1, T2 and T3, and channels CH1, CH2 and CH3 corresponding to the communication buses, that is, each time slice corresponds to a channel. Partition 1 CH1, partition 2 CH2 and partition 3 CH3 are respectively the storage partitions allocated to each channel in the target storage area. In each preset time slice (T1, T2, T3...), the sampling logic unit of the CPLD collects the original protocol data (i.e. initial data) transmitted on the corresponding communication bus (CH1, CH2, CH3...), such as the level signal and its timing relationship including SDA (data line) and SCL (clock line). The time division multiplexing mechanism is used to cyclically sample each bus in time slice order, ensuring that only the data of one bus is collected at any time.

[0062] Based on the channel identifier corresponding to the time slice where the sampling is located, the data is stored in the dedicated storage partition (such as partition 1 corresponding to CH1, and partition 2 corresponding to CH2) strictly bound to the channel identifier in the target storage area (RAM). Each storage partition independently manages the data of the corresponding channel, ensuring that the data of each bus is isolated from each other in physical storage, avoiding mutual interference.

[0063] In this embodiment, the multi-bus conflict-free sampling is realized by adopting the time division multiplexing mode, avoiding data interference caused by simultaneous sampling of multiple groups of buses, and the identification logic of the sampling is reduced by mapping the time slice and the channel identifier, thereby reducing the resource consumption of the CPLD and other processing components.

[0064] In some embodiments of the present application, the storage partition in the target storage area represents a partition obtained according to the channel identifier corresponding to the communication bus, and the channel identifier corresponding to the communication bus is obtained through the target register. The target register stores the channel identifier corresponding to each communication bus determined based on the bus characteristics of the communication bus.

[0065] The target register can be a hard core storage unit (such as an EEPROM) of the CPLD content, which belongs to a non-volatile storage medium and does not lose data after power off. The bus characteristics of the communication bus refer to the physical connection characteristics (such as the hardware wiring sequence, bus interface number, etc.) of the communication bus, and can also be logical characteristics (such as the communication rate of the bus, the address range of the slave, etc.). In the application scenario where the number of communication buses is fixed, the channel identifier stored in the target register is a unique identifier corresponding to the communication bus determined according to a static preset mode. Specifically, during the production stage of the server, an engineer can assign a fixed channel identifier (such as identifier 0 for J1 and identifier 1 for J2, etc.) to each bus according to the physical connection sequence of the bus (such as the bus interface number J1 for the first group of buses and J2 for the second group of buses, etc.), and write the correspondence between the "bus interface number and channel identifier" into the target register; after the CPLD is started, the correspondence is directly read from the target register to determine the channel identifier of each bus.

[0066] In the application scenario where the number of communication buses changes dynamically, the channel identifier corresponding to the communication bus can be determined through a dynamic update mode. For example, during the initialization stage of the server, the host (BMC) scans the communication buses (such as detecting that 6 groups of I2C buses have connected devices) connected on the backboard, assigns a temporary channel identifier (such as identifiers 0-5 corresponding to the 6 groups of connected buses) to each bus according to the scanning result, and writes the correspondence between the "bus detection result and channel identifier" into the target register through a special instruction; when a new bus is connected or an old bus is disconnected, the host re-scans and updates the channel identifier in the target register to ensure that the identifier is uniquely matched with the current bus. In the embodiments of the present application, whether the communication bus is fixed or dynamically changed, the channel identifier matched with the communication bus can always be stored in the target register, and the non-volatile storage of the target register ensures that the channel identifier is not lost after power off, thereby reducing the initialization time after the server is restarted.

[0067] In some embodiments of the application, in response to reading the initial data of the target storage area, the process of converting the read initial data into decoded data with a channel identifier can include: reading the sampling sequence number corresponding to the current initial data of the sampling timing record; querying the preset mapping table based on the sampling sequence number to determine the corresponding channel identifier; obtaining the attribute parameters of the communication bus matching the channel identifier; embedding the channel identifier and bus attribute parameters into the protocol frame structure of the initial data to generate decoded data carrying the channel identifier.

[0068] The mapping table stores a one-to-one correspondence between the sampling sequence number and the channel identifier, for example, the mapping table stored in the CPLD can store the correspondence between the sampling sequence number, the channel identifier, and the bus attribute parameters. The communication bus attribute parameters include the slave address and the register address. For example, the sampling sequence number 3 corresponds to the channel identifier 3, which further corresponds to the slave address 0x4A and the register address 0x01. The sampling sequence number refers to the sampling sequence of each group of data recorded by the CPLD. For example, the sampling sequence number corresponding to the first sampling can be 0, and the sampling sequence number corresponding to the second sampling can be 1. That is, the sampling sequence number corresponds to a time slice of time division multiplexing. In the present application, the protocol frame structure represents the format of data transmission on the communication bus, which can refer to the data transmission format specified by the I2C protocol, which usually includes slave address bytes, register address bytes, and data bytes.

[0069] For example, when the I2C slave state machine reads the initial data of the RAM partition, it synchronously reads the sampling sequence number of the data recorded by the CPLD timing control unit (for example, when reading the data of partition 3, the sampling sequence number is 3). According to the number 3, the mapping table is queried to determine that the corresponding identifier is 3, and the bus attribute parameters are: slave address 0x4A, register address 0x01, etc. Then the channel identifier 3 (such as 0x03), the slave address 0x4A, the register address 0x01, and the initial data 01001100 (such as 0x4C) are encapsulated according to the I2C protocol frame structure to obtain the decoded data "0x4A 0x03 0x01 0x4C".

[0070] In some embodiments of the application, the processing module is configured to process the decoded data, including: the processing module identifies the channel identifier in the decoded data, and in response to the channel identifier in the decoded data matching the channel identifier preset by the processing module itself, activates the address information of the processing module to process the decoded data; and in response to the channel identifier in the decoded data not matching the channel identifier preset by the processing module itself, ignores the decoded data.

[0071] The processing module can refer to an I2C slave module. In an initialization stage, each I2C slave module writes a channel identifier corresponding to the I2C slave module into a register configured internally. For example, I2C slave module 1 is denoted as Slave 1, and the preset channel configured for Slave 1 is denoted as 0. I2C slave module 2 is denoted as Slave 2, and the preset channel configured for Slave 2 is denoted as 1. Further, the identifier is bound to a communication bus and a RAM storage partition. The processing module activates address information of the processing module refers to that the processing module calls a slave address and a register address bound to the channel identifier, which are preset internally (for example, the preset identifier 2 of the I2C slave module corresponds to the slave address 0x48 and the register address 0x00), and the address information is used to parse protocol data in decoded data. The processing module ignores the decoded data refers to that the processing module directly discards decoded data that does not match, and does not perform subsequent data processing, so as to avoid occupying logical resources of the processing module.

[0072] For example, if the channel identifier of the decoded data transmitted by the CPLD is 5 (corresponding to the processing module Slave 6), Slave 6 extracts the identifier 5, finds that the identifier 5 is consistent with the preset channel identifier 5 of Slave 6, activates the slave address 0x4C and the register address 0x03, parses the data field 0x3A (for example, corresponding to the voltage 12V), and feeds back to the host. Other modules (for example, Slave 4 and Slave 5) directly ignore the data because the identifiers do not match, and only Slave 6 performs processing. In the embodiment of the application, the channel identifier is carried in the decoded data, so that the processing module can effectively filter out the decoded data required by the processing module, without the need to increase an additional data detection module in the processing module, and the hardware cost of the processing module is reduced.

[0073] In order to further reduce the occupation of resources, in the embodiment of the application, the process of storing the initial data into the target storage area further includes: detecting a remaining storage space of a storage partition corresponding to the current communication bus in the target storage area; if the remaining storage space meets the storage requirement of the initial data, writing the initial data into the remaining storage space according to the sampling time sequence. If the remaining storage space does not meet the storage requirement of the initial data, determining a target storage sub-partition to be released based on a sampling timestamp of the storage partition data of the target storage area; and after clearing the historical data of the target storage sub-partition, writing the initial data into the target storage sub-partition.

[0074] The process of detecting the remaining storage space in the target storage area can be that the storage management unit of the CPLD monitors the used space and total space of each partition of the target storage area (such as RAM) in real time, and calculates the remaining storage space (for example, the total space of partition 0 is 1024 bytes, the used space is 980 bytes, and the remaining space is 44 bytes). The sampling timestamp represents that the CPLD will add a sampling timestamp to each piece of data when storing the initial data, and store the data and the timestamp in the partition at the same time. The target storage sub-area to be released refers to the storage partition corresponding to one or more groups of data with the earliest sampling time in the storage partition of the target storage area. For example, after the CPLD samples the initial data (such as 32 bytes) of the third group of buses, the storage management unit detects the remaining storage space of the partition 2 (channel identifier 2) corresponding to the data. If the remaining space is 40 bytes (greater than 32 bytes), the CPLD directly performs writing; if the remaining space is 25 bytes (less than 32 bytes), the CPLD triggers the space release process. The storage management unit reads the sampling timestamps of all data in the partition 2, sorts the timestamps, and determines the two pieces of data (each 16 bytes, a total of 32 bytes) with the earliest timestamps, and the corresponding storage sub-area is the "0x0000-0x001F address segment of partition 2". The storage management unit clears the old data in the target sub-area, releases 32 bytes of space, and then writes the newly sampled 32 bytes of initial data into the sub-area according to the sampling time sequence, and adds the current timestamp to the new data. In the embodiment of the present application, in the case that the remaining storage space of the target storage area is insufficient, the oldest data is preferentially cleared, the newer data is retained, and the occupation of the CPLD storage resource is reduced.

[0075] Referring to Figure 3 which shows a time-division multiplexing architecture diagram of a CPLD multi-channel I2C slave device provided by an embodiment of the present application. Figure 3In the specific embodiment, the CPLD is a complex programmable logic device, which is a multi-channel I2C data processing core, and realizes time division multiplexing, data storage and forwarding. I2C1 to I2C8 represent 8-channel I2C buses, which are used to connect different controlled devices (such as sensors, controllers, etc.) in the server to transmit hardware state data. The multi-channel I2C Slave time division multiplexer represents a multi-channel I2C slave time division multiplexer, which collects data on the 8-channel I2C bus in time slices, allocates internal resources of the CPLD according to time slices, and avoids bus conflicts. TDM_CHANNEL is a time division multiplexing channel identifier, which represents the original I2C bus corresponding to the current transmission data (for example, channel 0 corresponds to I2C1), and is used to distinguish different bus data. TDM_REG_ADDR represents a time division multiplexing register address, which records the internal register position of the controlled device (for example, the temperature data register address of the sensor). TDM_SVL_ADDR represents a time division multiplexing slave address, which stores the I2C slave device address of the current collected data (for example, the I2C address of the temperature sensor). TDM_WR_DATA represents time division multiplexing write data, which temporarily stores the hardware state data (such as the original code of the temperature value and the voltage value) read from the I2C bus. SLV_ACK_N represents the "acknowledge (ACK)" or "non-acknowledge (NACK)" response signal of the I2C slave module to the master request. RD_DATA represents read data, such as the CPLD processed data (such as the parsed temperature and voltage values) output to the server host and other upper modules. CPLD register Slave1-Slave8 (VPP / HP I2C Slave1-Slave8) represents 8 groups of I2C slave registers in the CPLD, which correspond to 8-channel I2C buses, and are used to temporarily store and parse the data transmitted on the corresponding bus. The slave address and register mapping relationship can be configured.

[0076] For example, 8-way I2C bus (I2C1-I2C8) in the server is connected to temperature sensors, voltage monitoring chips and other controlled devices respectively. The device timing sends hardware state data (such as temperature sensor reporting temperature code every 1us) through the I2C bus. The multi-way I2C slave time division multiplexer divides the CPLD internal resources according to time slices, such as assuming that I2C1-I2C8 are allocated 1us of collection window in turn. In the collection window of I2C1, the multiplexer connects I2C1 with the internal link of the CPLD to receive the temperature data on the bus; the next time slice switches to I2C2, and so on, to realize 8-way bus time division non-collision collection. The collected data is transmitted to the CPLD internal through the link, TDM_CHANNEL marks which way of I2C bus the data comes from (such as I2C3 corresponding channel identification is set to 3); TDM_SVL_ADDR records the I2C slave address of the bus connected device (such as temperature sensor address 0x48); TDM_REG_ADDR specifies the register position of the data in the controlled device (such as temperature data is stored in 0x00 register); TDM_WR_DATA temporarily stores the original data code (such as 0x25, corresponding to the actual temperature 37℃). These data are transmitted to the corresponding CPLD register Slave (such as the data of I2C3 is stored in CPLD register Slave3), that is, the corresponding Slave filters out the decoded data belonging to it according to its own preset channel identification. Then the Slave preliminarily analyzes the data according to the preset configuration (slave address, register mapping) to judge whether it is valid state information. If the CPLD register Slave analyzes the data normally, the processed data is output to the server host through RD_DATA for displaying hardware state, such as displaying "CPU temperature sensor (I2C1): 37℃" on the BMC interface. If the CPLD internal resource is busy (such as processing high priority task at the same time) or the data verification is abnormal (such as the length of the received data is not consistent), SLV_ACK_N signal is set, which is fed back to the multi-way I2C slave time division multiplexer. After receiving the signal, the multiplexer can trigger the "retry mechanism" (such as re-collecting the corresponding bus data at an interval of 0.05us), or mark the failure of this collection and record the log for fault troubleshooting.

[0077] It should be noted that the time values corresponding to the period, the sampling window and the time slice in the embodiments of the present application are only illustrative, and in specific, the setting of the time values needs to consider the actual application scenario and the corresponding line state, and the present application does not limit this.

[0078] Referring to Figure 4 , which shows a time division multiplexing channel data processing schematic diagram of an I2C slave module provided by an embodiment of the present application. In Figure 4 , the related character identification can be referred toFigure 3 The corresponding explanation content. Corresponding, Figure 4 REG_ADDR in the REG_ADDR indicates the register address (Register Address); WR_DATA indicates the write data (Write Data); SVL_ADDR indicates the slave address (Slave Address). Sel indicates a selection control signal module, which is used to determine the path switching of "time division multiplexed input (TDM_)" and "standard I2C signal (SVL_, RD_DATA, etc.)".

[0079] TDM_SVL_ADDR (time division multiplexed slave address), TDM_REG_ADDR (time division multiplexed register address), TDM_WR_DATA (time division multiplexed write data), TDM_CHANNEL (time division multiplexed channel) as input data, at the same time into I2C slave processing module (such as represented by I2C Slave x module). Among them, TDM_CHANNEL carries the channel identification Channel = x, which is used to confirm that these input data are the to-be-processed content of I2C Slave x channel, and realizes the matching of different channel data and slave in the time division multiplexing scenario. I2C Slave x internally detects the channel identification in TDM_CHANNEL, and when Channel = x is identified, it is determined that the current input data belongs to the processing range of the slave, and the subsequent data processing flow is activated; if the identification does not match, the data is temporarily stored or discarded to avoid interference of different channel data. I2C Slave x module parses the input TDM_SVL_ADDR into SVL_ADDR (slave address), TDM_REG_ADD into REG_ADDR (register address), and TDM_WR_DATA into WR_DATA (write data) to adapt to the I2C bus communication protocol.

[0080] If a write operation is performed, I2C Slave x finds the target slave or device according to SVL_ADDR, and sends REG_ADDR (register address) and WR_DATA (write data) out through the I2C bus. After sending, the response signal feedback from the outside is waited for: if the operation is successful, a positive response may be received; if there is an address error, bus conflict or other problems, SLV_ACK_N (slave negative response) will be received, at which time I2C Slave x needs to record the failure state, and can trigger subsequent processing such as retry, error reporting, etc. When a read operation is performed, I2C Slave x reads data from the target slave or register, generates RD_DATA (read data), and feeds back the data to the upper system or module through the module, for the scene of obtaining slave state, monitoring data, etc.

[0081] The embodiment of the present application adopts a time division multiplexing method, samples the multiple I2C buses with a 50MHz system clock of the CPLD, stores the sampled states into a RAM, and then reads the data in the RAM by an I2C slave state machine, converts the data into I2C decoding information with channel information, such as I2C slave addresses, register addresses, read / write data, and so on, and associates the information to other modules.

[0082] Using this mechanism, the CPLD logic resource occupation can be greatly saved, and a smaller scale CPLD can be used to realize the same function. Taking 8 groups of I2C as an example, the traditional method is to use one slave module for each group of I2C bus. For example, the logic resource occupation is: the resource of one module multiplied by 8, 97x8=776 LUTs (LUTs represent the logic resource occupation index); using the embodiment of the present application to parse 8 groups of I2C, the logic resource occupation is: 271 LUTs, which can save about 65% of the logic resource, and the CPLD cost can be saved by about 40%.

[0083] In the embodiment of the present application, a processing assembly is also provided, which is shown in Figure 5 The processing assembly comprises:

[0084] The storage module 501 is configured to periodically sample the multiple groups of communication buses, obtain initial data corresponding to each group of communication buses, and store the initial data into a target storage area, wherein the initial data is original protocol data transmitted by each group of communication buses, and the storage partitions of the target storage area have a corresponding relationship with channel identifiers of the communication buses.

[0085] The decoding module 502 is configured to convert the read initial data into decoding data with channel identifiers in response to reading the initial data of the target storage area.

[0086] The transmission module 503 is configured to transmit the decoding data to the processing module 504.

[0087] The processing module 504 is configured to process the decoding data.

[0088] In some embodiments of the present application, the storage module 501 comprises:

[0089] The sampling sub-module is configured to sequentially sample the multiple groups of communication buses in different time slices according to a preset time division multiplexing mode, and obtain initial data corresponding to each group of communication buses, wherein each time slice corresponds to a sampling period of each group of communication buses.

[0090] The storage submodule is configured to store the initial data into a storage partition corresponding to the channel identifier in the target storage region based on the channel identifier corresponding to the time slice where the sampling is located; each group of communication buses has a corresponding channel identifier; and the storage partitions of the target storage region have a corresponding relationship with the channel identifiers of the communication buses.

[0091] In some embodiments of the present application, the storage partitions in the target storage region represent divisions according to the channel identifiers corresponding to the communication buses; the channel identifiers corresponding to the communication buses are obtained through a target register; and the target register stores the channel identifiers corresponding to the communication buses determined based on the bus characteristics of the communication buses.

[0092] In some embodiments of the present application, the decoding module 502 includes:

[0093] The reading submodule is configured to read a sampling sequence number corresponding to the current initial data of the sampling time sequence record;

[0094] The determining submodule is configured to query a preset mapping table based on the sampling sequence number to determine a corresponding channel identifier, wherein the mapping table stores a one-to-one correspondence between the sampling sequence number and the channel identifier;

[0095] The obtaining submodule is configured to obtain a communication bus attribute parameter matching the channel identifier, wherein the communication bus attribute parameter includes a slave address and a register address;

[0096] The generating submodule is configured to embed the channel identifier and the bus attribute parameter into a protocol frame structure of the initial data to generate decoding data carrying the channel identifier; and the protocol frame structure represents the format of the data when transmitted on the communication bus.

[0097] In some embodiments of the present application, the processing module is specifically configured to:

[0098] identify the channel identifier in the decoding data; in response to the channel identifier in the decoding data matching a channel identifier preset in the processing module itself, activate the address information of the processing module itself to process the decoding data; and in response to the channel identifier in the decoding data not matching the channel identifier preset in the processing module itself, ignore the decoding data.

[0099] In some embodiments of the present application, the storing of the initial data into the target storage region includes:

[0100] detecting a remaining storage space of a storage partition corresponding to the current communication bus in the target storage region;

[0101] if the remaining storage space meets the storage requirement of the initial data, writing the initial data into the remaining space according to the sampling time sequence.

[0102] If the remaining storage space does not meet the storage requirement of the initial data, a target storage sub-partition to be released is determined based on the sampling time stamp of the data in the storage partition of the target storage region.

[0103] After the historical data of the target storage sub-partition is cleared, the initial data is written into the target storage sub-region.

[0104] It should be noted that the specific implementation of each module and sub-module in the embodiment can refer to the corresponding content in the foregoing, which will not be described in detail here.

[0105] In the embodiments of the present application, a server is also provided, which is shown in Figure 6 The server includes a server backplane 60, and the server backplane 60 is provided with at least one controlled device 601 (in Figure 6 three controlled devices are shown, and each controlled device is represented as “controlled device 601”), and the controlled device 601 is connected with a processing component 603 through a plurality of groups of communication buses 602.

[0106] The processing component 603 is configured to periodically sample the plurality of groups of communication buses, obtain initial data corresponding to each group of communication buses, and store the initial data into a target storage region, wherein the initial data is original protocol data transmitted by each group of communication buses, and the storage partition of the target storage region has a corresponding relationship with the channel identifier of the communication bus; in response to reading the initial data of the target storage region, the read initial data is converted into decoded data with a channel identifier; and the decoded data is transmitted to a processing module, and the processing module is configured to process the decoded data.

[0107] In the embodiments of the present application, the server backplane is a circuit board inside the server for connecting various hardware modules, and a plurality of groups of communication buses (such as 8 groups of I2C buses) are arranged on the circuit board and connected with the controlled device interface. The controlled device refers to a hardware device connected to the server backplane and needing to interact with the host through the communication bus, such as a temperature sensor (which can be used to monitor the backplane temperature), a voltage monitoring chip (which can be used to monitor the power supply voltage), a fan control module (such as controlling the speed of the cooling fan), etc.

[0108] In Figure 6On the basis of the illustrated server, the server can further include a host connected with the processing component, for initiating access instructions to the processing component and receiving processing results fed back by the processing component. The host refers to a master unit of the server, such as a BMC chip or a CPU, and has functions of instruction generation, data processing, display, etc. For example, the control command sent by the host to the processing component includes a data reading instruction (such as "read the third group of bus data"), a parameter configuration instruction (such as "modify the sampling period to 2us"), etc. The host is also used for receiving the processing results fed back by the processing component, wherein the processing results represent the final data (such as "channel 3: temperature 25℃") fed back by the processing module after data sampling, decoding and transmission, or the state information (such as "sampling period modification success") of the executed instruction.

[0109] On the basis of the foregoing embodiment, the processing module in the processing component is an I2C slave module, wherein the I2C slave module is a hardware module of the I2C protocol, has functions of slave address identification, data analysis and timing control, and forms an I2C bus network with the processing component and the controlled device as the processing module.

[0110] It should be noted that the specific implementation of the processing component in the embodiment can refer to the corresponding content in the foregoing text, which will not be described in detail here.

[0111] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts can be referred to the method part.

[0112] The skilled person can further realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed in the present text can be realized in electronic hardware, computer software or combination of the two. In order to clearly show the interchangeability of hardware and software, the composition and steps of each example have been described in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0113] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0114] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data processing method, comprising: Multiple communication buses are periodically sampled to obtain initial data corresponding to each communication bus, and the initial data is stored in a target storage area. The initial data is the original protocol data transmitted by each communication bus, and the storage partition of the target storage area corresponds to the channel identifier of the communication bus. In response to reading initial data from the target storage area, the read initial data is converted into decoded data with channel identifiers; The decoded data is transmitted to a processing module, which processes the decoded data.

2. The method according to claim 1, wherein periodically sampling multiple groups of communication buses to obtain initial data corresponding to each group of communication buses, and storing the initial data in the target storage area, comprises: According to the preset time-division multiplexing mode, multiple communication buses are sampled in turn at different time slices to obtain the initial data corresponding to each communication bus. Each time slice corresponds to the sampling period of a communication bus. Based on the channel identifier corresponding to the time slice in which the sampling occurs, the initial data is stored in the target storage area and the storage partition corresponding to the channel identifier; wherein, each communication bus has a corresponding channel identifier; the storage partition of the target storage area and the channel identifier of the communication bus have a corresponding relationship.

3. The method according to claim 2, wherein the storage partition representation in the target storage area is obtained by dividing according to the channel identifier corresponding to the communication bus, wherein, The target register is used to obtain the channel identifier corresponding to the communication bus. The target register stores the channel identifier corresponding to each communication bus, which is determined based on the bus characteristics of the communication bus.

4. The method according to claim 1, wherein converting the read initial data into decoded data with channel identifiers in response to reading the initial data of the target storage area comprises: Read the sampling sequence number corresponding to the current initial data in the sampling timing record; Based on the sampling sequence number, a preset mapping table is queried to determine the corresponding channel identifier, wherein the mapping table stores a one-to-one correspondence between the sampling sequence number and the channel identifier; Obtain communication bus attribute parameters that match the channel identifier, the communication bus attribute parameters including slave address and register address; The channel identifier and bus attribute parameters are embedded into the protocol frame structure of the initial data to generate decoded data carrying the channel identifier; The protocol frame structure represents the format of data transmitted on the communication bus.

5. The method according to claim 1, wherein the processing module is configured to process the decoded data, including: The processing module identifies the channel identifier in the decoded data; If the channel identifier in the decoded data matches the channel identifier preset by the processing module, the module activates its own address information to process the decoded data; if the channel identifier in the decoded data does not match the preset channel identifier, the decoded data is ignored.

6. The method according to claim 1, wherein storing the initial data in the target storage area comprises: Detect the remaining storage space of the storage partition in the target storage area that corresponds to the current communication bus; If the remaining storage space meets the storage requirements of the initial data, the initial data will be written into the remaining space according to the sampling time sequence; If the remaining storage space does not meet the storage requirements of the initial data, the target storage sub-partition to be released is determined based on the sampling timestamp of the data in the storage partition of the target storage area; After clearing the historical data of the target storage sub-partition, the initial data is written to the target storage sub-region.

7. A processing component, comprising: The storage module is used to periodically sample multiple communication buses to obtain initial data corresponding to each communication bus, and store the initial data in a target storage area. The initial data is the original protocol data transmitted by each communication bus, and the storage partition of the target storage area corresponds to the channel identifier of the communication bus. A decoding module is used to convert the read initial data into decoded data with channel identifiers in response to reading the initial data of the target storage area; The transmission module is used to transmit the decoded data to the processing module; The processing module is used to process the decoded data.

8. A server, comprising: A server backplane, wherein at least one controlled device is provided in the server backplane, and the controlled device is connected to the processing component through multiple sets of communication buses; The processing component is used to periodically sample multiple communication buses to obtain initial data corresponding to each communication bus, and store the initial data in a target storage area. The initial data is the original protocol data transmitted by each communication bus, and the storage partition of the target storage area corresponds to the channel identifier of the communication bus. In response to reading the initial data in the target storage area, the read initial data is converted into decoded data with channel identifier. The decoded data is transmitted to a processing module, which processes the decoded data.

9. The server according to claim 8, further comprising a host; The host is connected to the processing component and is used to send access commands to the processing component and receive processing results from the processing component.

10. The server according to claim 8, wherein the processing module is an I2C slave module.

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