A high-speed port ESD design method for reducing parasitic capacitance

Abstract

The application discloses a high-speed port ESD design method for reducing parasitic capacitance, relates to the technical field of high-speed interfaces, and comprises the following steps: obtaining the basic metal features of a high-speed interface ESD protection structure, wherein the high-speed interface ESD protection structure adopts high-layer metal; randomly setting via parameters of the high-speed interface ESD protection structure, wherein the via parameters include the number of vias and the coordinate parameters of all the vias; performing ESD prediction and parasitic capacitance prediction according to the via parameters and the basic metal features, obtaining tolerance parameters and parasitic capacitance; calculating ESD fitness according to the tolerance parameters and the parasitic capacitance, performing iterative optimization, obtaining optimal via parameters, and combining the basic metal features to serve as an ESD design result. The technical problems of large parasitic capacitance of the existing drawing method of the high-speed interface and the difficulty in balancing parasitic and current flow of the ESD current flow capacity of the existing drawing method are solved.

Description

Technical Field

[0001] This application relates to the field of high-speed interface technology, specifically to a high-speed port ESD design method for reducing parasitic capacitance. Background Technology

[0002] With the continuous development of high-speed interface technology, the importance of ESD protection for high-speed ports is becoming increasingly prominent. During high-speed signal transmission, ESD events can cause serious damage to circuits, thus requiring effective ESD protection structures. However, in traditional technologies, to enhance ESD current carrying capacity, multi-layer metal stacking with vias is typically used. This increases ESD current carrying capacity through parallel connections of multiple metal layers. However, each metal stack increases parasitic capacitance, making it difficult to balance parasitic capacitance and current carrying capacity. Summary of the Invention

[0003] This application provides a high-speed port ESD design method to reduce parasitic capacitance, solving the technical problems of large parasitic capacitance in existing high-speed interface designs and the difficulty in balancing parasitic capacitance and current carrying capacity in existing ESD designs.

[0004] The technical solution to the above-mentioned technical problems in this application is as follows:

[0005] In a first aspect, this application provides a high-speed port ESD design method for reducing parasitic capacitance, characterized in that the method includes:

[0006] The basic metal features of the high-speed interface ESD protection structure are obtained, wherein the high-speed interface ESD protection structure adopts a high-layer metal. The via parameters of the high-speed interface ESD protection structure are randomly set, including the number of vias and the coordinate parameters of all vias. Based on the via parameters and basic metal features, ESD prediction and parasitic capacitance prediction are performed to obtain tolerance parameters and parasitic capacitance. Based on the tolerance parameters and parasitic capacitance, the ESD fitness is calculated and iteratively optimized to obtain the optimal via parameters. These, combined with the basic metal features, serve as the ESD design result.

[0007] This application provides one or more technical solutions, which have at least the following technical effects or advantages:

[0008] This application provides a high-speed ESD design method to reduce parasitic capacitance. Compared to existing technologies, this application first uses high-layer metal to directly and uniformly connect to the bottom ESD device vias. This reduces the number of layers of the bottom metal, thus lowering parasitic capacitance. Furthermore, the greater distance between the high-layer metal and the bottom device / metal further reduces parasitic capacitance. Then, an innovative via design allows ESD current to directly and uniformly reach the device through the top metal, improving ESD current carrying capacity. This application employs a layout design method that effectively reduces parasitic capacitance while maintaining ESD current carrying capacity in the ESD routing design.

[0009] The above technical solution obtains the ESD protection structure of the high-speed interface, randomly sets via parameters, performs ESD and parasitic capacitance prediction, obtains tolerance parameters and parasitic capacitance, calculates ESD fitness, and performs iterative optimization to obtain the optimal via parameters. By using direct vias between the high-layer metal and the low-layer device without repetition of metal stacking, parasitic capacitance is reduced. Through special design of the via distribution, parasitic capacitance is further reduced while improving ESD current carrying capacity. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart illustrating a high-speed port ESD design method for reducing parasitic capacitance provided in an embodiment of this application. Detailed Implementation

[0012] This application provides a high-speed port ESD design method to reduce parasitic capacitance, addressing the technical problems of large parasitic capacitance in existing high-speed interface designs and the difficulty in balancing parasitic capacitance and current carrying capacity in existing ESD designs.

[0013] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0015] In the description of this application, the term "for example" is used to mean "used as an example, illustration, or description." Any embodiment described as "for example" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid unnecessarily obscuring the description of this application. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0016] Example 1, as Figure 1 As shown in the figure, this application provides a high-speed port ESD design method to reduce parasitic capacitance, including:

[0017] S10: Obtain the basic metal features of the high-speed interface ESD protection structure, wherein the high-speed interface ESD protection structure adopts a high-layer metal;

[0018] In this embodiment, the high-speed interface ESD protection structure uses a high-layer metal. Compared to the bottom-layer metal, the high-layer metal has a more regular and orderly distribution, thus being less affected by the complex wiring and devices at the bottom layer, providing a more stable foundation for subsequent via design and ESD current transmission. When obtaining the characteristics of the base metal, the dimensions of the high-layer metal must be accurately measured because the dimensional parameters directly affect the construction of the subsequent via design space and the ESD current transmission path.

[0019] Specifically, step S10 in the method includes:

[0020] Obtain the basic metal features of the high-speed interface ESD protection structure, wherein the high-speed interface ESD protection structure adopts a high-layer metal, and the basic metal features include the dimensions of the high-layer metal.

[0021] In this embodiment of the application, the basic metal features of the high-speed interface ESD protection structure are first obtained by searching the datasheets and technical documents of semiconductor manufacturers. The basic metal features include the dimensions of the high-layer metal.

[0022] Because of its inherent characteristics of "low parasitic capacitance, high load capacity, and high flexibility," the upper layer metal perfectly matches the core contradiction in high-speed scenarios: both discharging high-current ESD and avoiding interference with high-speed signals. Compared to the lower layer metal, the upper layer metal can control parasitic capacitance while ensuring ESD protection levels. For example, at HBM8kV and CDM500V, the upper layer metal controls parasitic capacitance to below 0.5pF and parasitic inductance to below 1nH, meeting the signal integrity requirements of high-speed interfaces such as USB4 and PCIe5.0. Therefore, the ESD protection structure for high-speed interfaces uses the upper layer metal.

[0023] Secondly, for high-layer metals, variations in their dimensions directly alter parasitic capacitance and inductance, thus affecting signal strength. For instance, excessively small high-layer metal dimensions violate design rules, leading to chip fabrication failures and unstable ESD protection performance; excessively large dimensions occupy more chip area, especially in multi-channel high-speed interfaces, significantly increasing the total area and raising chip costs. When acquiring basic metal characteristics, measurement tools and software, such as electron microscopes and 3D modeling software, are used to ensure that subsequent via space construction is based on accurate and complete data.

[0024] S20: Randomly set the via parameters of the high-speed interface ESD protection structure, wherein the via parameters include the number of vias and the coordinate parameters of all vias;

[0025] In this embodiment, the via parameters of the high-speed interface ESD protection structure are randomly set to provide diverse initial solutions for the subsequent optimization process. The via parameters include the number of vias and the coordinate parameters of all vias. Different combinations of the number of vias and the coordinate parameters of the vias will affect the performance of the ESD protection structure.

[0026] When setting the number of vias, consider the dimensions of the upper metal layers and the expected ESD current carrying capacity. If the number of vias is too small, the ESD current may not be able to be discharged effectively and in a timely manner, leading to device damage; if the number of vias is too large, it may increase parasitic capacitance and affect the transmission quality of high-speed signals.

[0027] When setting via coordinate parameters, a reasonable layout should be implemented within the via design space. The distribution of vias should be as uniform as possible, avoiding situations where local vias are too densely or sparsely distributed. For example, a random number generation method can be used to randomly generate the coordinates of the vias within the three-dimensional coordinate system of the via design space. Simultaneously, ensure that the generated via coordinates are within the effective range of the upper metal layer to prevent vias from exceeding the metal boundary and causing connection failure.

[0028] Specifically, step S20 in the method includes:

[0029] Based on the aforementioned basic metal characteristics, construct the via design space;

[0030] Within the via design space, via parameters are randomly set, including the number of vias and the coordinate parameters of all vias.

[0031] In this embodiment, a via design space is first constructed based on the obtained basic metal features to provide a range for the random setting of via parameters.

[0032] When randomly setting via parameters within a space, the size and shape of the upper metal layers should be considered. Too many vias may increase parasitic capacitance, while too few vias may affect ESD current carrying capacity. The coordinate parameters of all vias should also be reasonably distributed to avoid vias being too concentrated in a certain area, resulting in uneven current distribution and thus affecting the ESD protection effect.

[0033] Secondly, after randomly setting via parameters within the constructed via design space, preliminary screening and evaluation are conducted. By setting basic constraints, such as the minimum spacing between vias and the minimum distance between vias and metal edges, electrical performance problems caused by unreasonable via settings are avoided.

[0034] Finally, the number of vias is initially screened based on the dimensions of the upper metal layer and the expected ESD current carrying capacity, determining the range of via quantity. Within this range, the number of vias is randomly generated to ensure effective ESD current discharge and avoid excessive increase in parasitic capacitance.

[0035] Furthermore, after randomly setting the via parameters, preliminary screening and verification of the parameters are necessary. For example, check whether the spacing between vias meets the design rules to avoid problems such as short circuits caused by excessively small via spacing. Through such preliminary screening, invalid calculations in subsequent prediction and optimization processes can be reduced, improving the efficiency of the algorithm.

[0036] For the initial evaluation of via coordinate parameters, check whether the generated via coordinates meet the above constraints. If not, regenerate via coordinates randomly until the conditions are met.

[0037] Furthermore, based on the aforementioned basic metal characteristics, a via design space is constructed, including:

[0038] Based on the high-level metal scale features within the basic metal features, a three-dimensional spatial coordinate system for via setting is constructed.

[0039] The three-dimensional spatial coordinate system is used as the via design space.

[0040] In this embodiment, after obtaining the basic features of the high-level metal within the basic metal features, a three-dimensional spatial coordinate system for feasible via placement is constructed based on the high-level metal dimensional features. A three-dimensional Cartesian coordinate system is established with the geometric center of the high-level metal as the origin and the length, width, and height directions of the high-level metal as the coordinate axes.

[0041] Using the constructed three-dimensional coordinate system as the via design space provides a clear range and constraints for the random setting of via parameters. Within the via design space, the existence of vias must not only consider their role in guiding ESD current, but also their impact on high-speed signal transmission.

[0042] The location and number of vias affect the transmission path and characteristic impedance of high-speed signals, thus impacting signal integrity. For example, vias placed too close to high-speed signal lines may introduce additional parasitic capacitance and inductance, leading to increased signal reflection and attenuation. Therefore, when setting via parameters within the via design space, both ESD protection and high-speed signal transmission requirements must be considered comprehensively.

[0043] S30: Based on the via parameters and the characteristics of the base metal, perform ESD prediction and parasitic capacitance prediction to obtain the tolerance parameters and parasitic capacitance.

[0044] In this embodiment, ESD prediction and parasitic capacitance prediction are performed based on via parameters and base metal characteristics. By inputting the parameters into the ESD performance predictor during ESD prediction and parasitic capacitance prediction, more accurate tolerance parameters and parasitic capacitances can be obtained.

[0045] The ESD performance predictor is trained based on experimental data and theoretical models, and can simulate the conduction process of ESD current in protective structures and the generation mechanism of parasitic capacitance. During the prediction process, the material properties of the upper metal layers, the specific parameters of the vias, and their interactions are considered.

[0046] The tolerance parameters reflect the performance of the ESD protection structure when subjected to ESD impact, including indicators such as maximum withstand current and withstand time, and are used to evaluate whether the protection structure can effectively protect high-speed interfaces from ESD damage.

[0047] Parasitic capacitance is a key factor affecting the quality of high-speed signal transmission. Excessive parasitic capacitance can lead to signal attenuation and distortion, impacting the performance of high-speed interfaces. Accurately predicting tolerance parameters and parasitic capacitance provides crucial information for subsequent optimization processes.

[0048] Specifically, step S30 in the method includes:

[0049] Obtain an ESD performance predictor, wherein the ESD performance predictor includes an ESD prediction network and a capacitance prediction network;

[0050] The via parameters and base metal characteristics are input into the ESD performance predictor, and the output yields the tolerance parameters and parasitic capacitance.

[0051] In this embodiment of the application, an ESD performance predictor is first obtained, which includes an ESD prediction network and a capacitance prediction network.

[0052] The ESD prediction network is built based on experimental data and theoretical analysis of a large number of ESD events. It simulates the conduction path, current distribution, thermal effects and electrical stress effects on the protective structure of ESD current under different via parameters and base metal characteristics, thereby accurately predicting ESD tolerance parameters.

[0053] The capacitance prediction network uses electromagnetic field theory and numerical calculation methods, combined with the geometry and physical properties of high-layer metals and vias, to predict the size of parasitic capacitance.

[0054] By inputting via parameters and base metal characteristics into the ESD performance predictor, the ESD prediction network calculates the shunting effect of vias at different locations and in different numbers on the ESD current, as well as the influence of the size and material of the upper metal on current conduction, based on the input parameters.

[0055] For example, when there are a large number of vias and they are evenly distributed, the ESD current can be conducted more quickly from the upper layer metal to the lower layer ESD device, thereby improving the withstand current and withstand time. At the same time, the capacitance prediction network takes into account the interaction between the vias and the upper layer metal, the lower layer metal, and the surrounding dielectric to calculate the specific value of the parasitic capacitance.

[0056] The ESD performance predictor includes:

[0057] Based on historical ESD design test data, we collected the sample via parameter set and the sample basic metal feature set, as well as the sample tolerance parameter set and sample parasitic capacitance set obtained from the test.

[0058] Based on machine learning, an ESD prediction network and a capacitance prediction network were constructed.

[0059] Using the sample via parameter set and sample basic metal feature set as input data, and the sample tolerance parameter set and sample parasitic capacitance set as supervision data, respectively, the ESD prediction network and capacitance prediction network are trained, and an ESD performance predictor is obtained after convergence.

[0060] In this embodiment, the neural network possesses powerful nonlinear mapping capabilities, enabling it to learn the potential relationships between via parameters and basic metal features of samples, as well as between the prediction network and the capacitance prediction network, from complex historical data. This application trains an ESD performance predictor based on the neural network. Iterative training using ESD design test data from a valid historical dataset yields a converged ESD performance predictor.

[0061] For example, iterative training of the ESD performance predictor can be achieved through the following technical path:

[0062] First, data preparation involves collecting the sample via parameter set and the sample basic metal feature set, as well as the sample tolerance parameter set and sample parasitic capacitance set obtained from the test.

[0063] Secondly, regarding model construction, based on machine learning, the number of nodes in the input layer equals the dimension of the input features. For example, if there are 10 features in total, such as the via parameters and the basic metal features of the sample, then the input layer contains 10 nodes. Set 1-3 hidden layers, and adjust the number of nodes in each layer through experiments, such as 64, 32, etc. The activation function is ReLU. The number of nodes in the output layer equals the number of predicted targets. For example, if only the time consumption is predicted, then there is 1 node; if both the time consumption and energy consumption are predicted, then there are 2 nodes. The output layer generally does not use an activation function and directly outputs continuous values.

[0064] Finally, for model training, the sample tolerance parameter set and sample parasitic capacitance set are used as supervision labels. The Adam optimizer and mean squared error (MSE) loss function are used to construct the training framework. The batch size is set to 32 and the total number of training rounds is 50. An early stopping mechanism (patience=5) is introduced. When the validation set loss does not decrease for 5 consecutive rounds, the training process is automatically terminated, and the trained ESD performance predictor is obtained. This effectively avoids model overfitting and ensures that the model reaches a convergent state. The trained ESD performance predictor can provide reliable model support for subsequent location prediction.

[0065] S40: Based on the tolerance parameters and parasitic capacitance, calculate the ESD fitness and perform iterative optimization to obtain the optimal via parameters. Combine these with the basic metal characteristics to obtain the ESD design result.

[0066] In this embodiment, the ESD fitness is calculated based on the tolerance parameters and parasitic capacitance. ESD fitness is an important indicator for measuring the overall performance of ESD protection structures.

[0067] First, a fitness function is constructed by assigning different weights to the tolerance parameter and parasitic capacitance according to actual needs. For example, to emphasize ESD protection performance, the weight of the tolerance parameter is appropriately increased. In this application, the weight of the tolerance parameter is set to 0.6, and the weight of the parasitic capacitance is 0.4.

[0068] Then, the ESD fitness is calculated based on the weights and iteratively optimized to obtain the optimal via parameters. Combined with the basic metal characteristics, this is taken as the optimal design result for ESD.

[0069] Specifically, step S40 in the method includes:

[0070] Obtain preset tolerance parameters and preset parasitic capacitance;

[0071] The ratio of the tolerance parameter to the preset tolerance parameter is calculated, and the ratio of the preset parasitic capacitance to the parasitic capacitance is calculated. The weighted calculation yields the ESD fitness.

[0072] Continue to randomly set via parameters, calculate ESD fitness, and perform iterative optimization. After the iterative optimization is completed, obtain the optimal via parameters with the highest ESD fitness, and combine them with the basic metal features as the ESD design result.

[0073] In this embodiment, preset tolerance parameters and preset parasitic capacitance are obtained. Then, based on the trained ESD performance predictor, the via parameters and basic metal features are input into the ESD performance predictor, and the tolerance parameters and parasitic capacitance are output.

[0074] Calculate the ratio of the tolerance parameter to the preset tolerance parameter, and the ratio of the preset parasitic capacitance to the parasitic capacitance, and then calculate the weighted average to obtain the ESD fitness. Tolerance parameter ratio = tolerance parameter / preset tolerance parameter; parasitic capacitance ratio = preset parasitic capacitance / parasitic capacitance.

[0075] For example, suppose the parameters of a USB4 interface ESD protection structure are: preset voltage tolerance parameter =8kV, preset parasitic capacitance =0.5pF; Actual voltage withstand parameter X=9kV, actual parasitic capacitance C=0.4pF; The withstand parameter ratio is calculated as follows: =9 / 8=1.25 → Upper limit normalized to 1; Parasitic capacitance ratio parameter calculated as follows =0.5 / 0.4=1.25→Upper limit normalized to 1; Then calculate fitness: 1×0.6+1×0.4=1, which means the fitness is optimal.

[0076] If the actual parameter is X=6kV =6 / 8=0.75; C=0.6pF, =0.5 / 0.6≈0.83;

[0077] Fitness calculation: 0.75×0.6+0.83×0.4≈0.45+0.33=0.78, which is less than 1, indicating that the tolerance parameters need to be optimized.

[0078] After obtaining the ESD fitness, iterative optimization is performed to obtain the optimal via parameters. An intelligent optimization algorithm is employed; taking a genetic algorithm as an example, randomly set via parameters are first used as the initial population, with each combination of via parameters corresponding to an individual. Then, the individuals in the population are evaluated based on the calculated ESD fitness; individuals with higher fitness have a higher probability of survival and reproduction.

[0079] In each iteration, a new population is generated through operations such as selection, crossover, and mutation. The selection operation selects some individuals with high fitness values ​​to enter the next generation; the crossover operation exchanges genes between selected individuals to produce new individuals; and the mutation operation randomly modifies some genes of the new individuals to increase the diversity of the population.

[0080] During the iteration process, the above operations are repeated until the termination condition is met. The termination condition is reaching a preset number of iterations, or the fitness value no longer showing significant improvement in a number of consecutive iterations. After the iterative optimization is completed, the via parameters corresponding to the individual with the highest fitness are the optimal via parameters.

[0081] Finally, the optimal via parameters are combined with the characteristics of the underlying metal to arrive at the ESD design result. This approach considers both the characteristics of the upper-layer metal and, by optimizing the via parameters, effectively controls parasitic capacitance while ensuring ESD protection capabilities, thus meeting the requirements of high-speed interfaces for ESD protection and signal integrity.

[0082] In summary, the embodiments of this application have at least the following technical effects:

[0083] This application provides a high-speed interface ESD design method to reduce parasitic capacitance. Compared with existing technologies, this application first uses high-layer metal to directly and uniformly connect vias to the bottom ESD device. This reduces the number of layers of bottom metal, thus lowering parasitic capacitance. Furthermore, the greater distance between the high-layer metal and the bottom device / metal further reduces parasitic capacitance. Then, an innovative via design allows ESD current to directly and uniformly reach the device through the top metal, improving ESD current carrying capacity. This application employs a layout design method that effectively reduces parasitic capacitance while maintaining ESD current carrying capacity in the ESD routing design. Through the above technical solution, by obtaining the high-speed interface ESD protection structure, randomly setting via parameters, performing ESD and parasitic capacitance prediction, obtaining tolerance parameters and parasitic capacitance, calculating the ESD fitness, and iteratively optimizing to obtain the optimal via parameters. By using direct vias between the high-layer metal and the bottom device without repetitive metal stacking, parasitic capacitance is reduced. By specially designing the via distribution, parasitic capacitance is further reduced while simultaneously improving ESD current carrying capacity.

[0084] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this specification. Additionally, the processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are possible or may be advantageous.

[0085] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0086] This specification and accompanying drawings are merely illustrative examples of this application and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Therefore, if such modifications and modifications fall within the scope of this application and its equivalents, this application intends to include such modifications and modifications.

Claims

1. A high-speed port ESD design method for reducing parasitic capacitance, characterized in that, The method includes: Obtain the basic metal features of the high-speed interface ESD protection structure, in which the high-speed interface ESD protection structure adopts a high-layer metal direct via to the bottom layer ESD device; The via parameters of the high-speed interface ESD protection structure are randomly set, wherein the via parameters include the number of vias and the coordinate parameters of all vias; Based on the via parameters and the characteristics of the base metal, ESD prediction and parasitic capacitance prediction are performed to obtain the tolerance parameters and parasitic capacitance. Based on the tolerance parameters and parasitic capacitance, the ESD fitness is calculated and iteratively optimized to obtain the optimal via parameters. Combined with the basic metal characteristics, this is used as the ESD design result.

2. The high-speed port ESD design method for reducing parasitic capacitance according to claim 1, characterized in that, Obtain the basic metallic features of the high-speed interface ESD protection structure, including: Obtain the basic metal features of the high-speed interface ESD protection structure, wherein the high-speed interface ESD protection structure adopts a high-layer metal, and the basic metal features include the dimensions of the high-layer metal.

3. The high-speed port ESD design method for reducing parasitic capacitance according to claim 1, characterized in that, The via parameters of the high-speed interface ESD protection structure are randomly set, wherein the via parameters include the number of vias and the coordinate parameters of all vias, including: Based on the aforementioned basic metal characteristics, construct the via design space; Within the via design space, via parameters are randomly set, including the number of vias and the coordinate parameters of all vias.

4. The high-speed port ESD design method for reducing parasitic capacitance according to claim 3, characterized in that, Based on the aforementioned basic metal characteristics, a via design space is constructed, including: Based on the high-level metal scale features within the basic metal features, a three-dimensional spatial coordinate system for via setting is constructed. The three-dimensional spatial coordinate system is used as the via design space.

5. The high-speed port ESD design method for reducing parasitic capacitance according to claim 1, characterized in that, Based on the via parameters and base metal characteristics, ESD prediction and parasitic capacitance prediction are performed to obtain tolerance parameters and parasitic capacitance, including: Obtain an ESD performance predictor, wherein the ESD performance predictor includes an ESD prediction network and a capacitance prediction network; The via parameters and base metal characteristics are input into the ESD performance predictor, and the output yields the tolerance parameters and parasitic capacitance.

6. The high-speed port ESD design method for reducing parasitic capacitance according to claim 5, characterized in that, Obtain an ESD performance predictor, including: Based on historical ESD design test data, we collected the sample via parameter set and the sample basic metal feature set, as well as the sample tolerance parameter set and sample parasitic capacitance set obtained from the test. Based on machine learning, an ESD prediction network and a capacitance prediction network were constructed. Using the sample via parameter set and sample basic metal feature set as input data, and the sample tolerance parameter set and sample parasitic capacitance set as supervision data, respectively, the ESD prediction network and capacitance prediction network are trained, and an ESD performance predictor is obtained after convergence.

7. The high-speed port ESD design method for reducing parasitic capacitance according to claim 1, characterized in that, Based on the tolerance parameters and parasitic capacitance, the ESD fitness is calculated and iteratively optimized to obtain the optimal via parameters. These parameters, combined with the basic metal characteristics, serve as the ESD design result, including: Obtain preset tolerance parameters and preset parasitic capacitance; The ratio of the tolerance parameter to the preset tolerance parameter is calculated, and the ratio of the preset parasitic capacitance to the parasitic capacitance is calculated. The weighted calculation yields the ESD fitness. Continue to randomly set via parameters, calculate ESD fitness, and perform iterative optimization. After the iterative optimization is completed, obtain the optimal via parameters with the highest ESD fitness, and combine them with the basic metal features as the ESD design result.

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