Intelligent storage chip high and low temperature testing device and testing optimization method

Abstract

This invention discloses an intelligent high and low temperature testing device and testing optimization method for memory chips, belonging to the field of memory chip testing technology. The device includes: a testing unit for constructing a cold and hot testing environment for the memory chip under test; a power supply unit for providing DC power to each unit; a management unit for real-time monitoring of environmental data and uploading it to a data acquisition and analysis server, and for closed-loop control of environmental data in conjunction with test commands; an excitation generator for generating and sending test excitations to the memory chip under test according to test commands, recording test data and feeding it back to the data acquisition and analysis server; and a data acquisition and analysis server for predicting faults in the memory chip under test based on real-time environmental data and test data using an AI model, optimizing test command parameters or memory chip FTL algorithm parameters, generating dynamically controlled test commands, and issuing them. This invention enables accurate testing and optimization of memory chips under extreme temperature environments.

Description

Technical Field

[0001] This invention relates to the field of memory chip testing technology, and in particular to an intelligent high and low temperature testing device and testing optimization method for memory chips. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] As electronic technology develops towards higher integration and higher reliability, the operational stability of chips and storage products under extreme environments (such as high and low temperatures, thermal shock) has become a key performance indicator. Ensuring the reliability of chips and storage products in harsh environments has become one of the key focuses of the industry, especially in fields with stringent temperature requirements such as automobiles and aerospace.

[0004] Traditional high and low temperature testing of chips relies on large high and low temperature test chambers or thermal shock devices. These devices have significant drawbacks: First, they are bulky, energy-intensive, and have low energy efficiency. Second, the temperature control method is based on overall environmental temperature control, resulting in a slow temperature response and several minutes required for switching between hot and cold temperatures. This leads to a lengthy testing process and makes it impossible to achieve precise local temperature control for individual chips, thus failing to meet the needs of precision testing. Third, the testing mode is singular, making it impossible to conduct tests on multiple types of chips in parallel, resulting in low testing efficiency. Furthermore, it can only simulate the environment and lacks coordination with the test stimulus, failing to truly simulate the performance of chips under workload.

[0005] Furthermore, the testing requirements for modern storage products extend beyond ambient temperature control. They must also incorporate online debugging based on actual workloads to realistically simulate the product's operation in extreme environments. Traditional testing methods are typically static and passive, lacking intelligent optimization of the testing process and deep analysis of test data, making it difficult to monitor the storage product's operational status and performance in real time. While existing AI-based chip testing devices can optimize testing processes (such as power-on sequence and pin detection) through deep learning, they do not delve into the internal algorithmic level of the chip under test. For example, regarding the FTL (Flash Translation Layer) algorithm in storage chips, current testing methods cannot dynamically adjust FTL algorithm parameters in conjunction with temperature changes, leading to significant deviations between test results and the chip's actual operating conditions, making it difficult to detect potential faults under extreme temperatures. Moreover, traditional devices lack closed-loop data analysis capabilities, failing to utilize test data for fault prediction and algorithm iterative optimization, requiring manual intervention and exhibiting low automation. Summary of the Invention

[0006] To address the shortcomings of the existing technologies, this invention provides an intelligent high and low temperature testing device and testing optimization method for memory chips. This device can meet the precise testing needs of modern chips and memory products in extreme temperature environments, and solves the problems of traditional high and low temperature testing equipment being large in size, high in energy consumption, low in testing efficiency, and unable to perform real-time adaptive optimization of the internal algorithms of the chip under test.

[0007] In a first aspect, the present invention provides an intelligent high and low temperature testing device for memory chips.

[0008] An intelligent high and low temperature testing device for memory chips, comprising:

[0009] The test unit is used to construct a hot and cold test environment for the memory chip under test;

[0010] The power supply unit is used to provide DC power to each unit;

[0011] The management unit is used to detect environmental data in real time and upload it to the data acquisition and analysis server, while also controlling the environmental data in a closed loop in conjunction with test commands.

[0012] The excitation generator is used to generate and send test excitations to the memory chip under test according to the test instructions, record test data and feed it back to the data acquisition and analysis server;

[0013] The management unit and the excitation generator are connected to the data acquisition and analysis server via a network interface. The data acquisition and analysis server is used to predict the faults of the memory chip under test based on real-time environmental data and test data, and optimize the test command parameters or memory chip FTL algorithm parameters, generate dynamic control test commands, and send them to the management unit and the excitation generator.

[0014] In a further technical solution, the test unit supports multi-layer stacking, including a semiconductor cold plate, an ADN8835 chip, a thermistor, thermally conductive materials, and a heat dissipation device.

[0015] The ADN8835 chip is connected to the PWM module of the management unit and the power supply unit respectively. It has a built-in PID control algorithm to adjust the power supply current of the semiconductor cold chip according to the received PWM control signal to achieve closed-loop temperature control.

[0016] The semiconductor cold plate contacts the memory chip under test through a thermally conductive material and switches between cooling and heating based on the Peltier effect to create a cold and hot test environment for the memory chip under test.

[0017] The thermistor is embedded inside the thermally conductive material and is used to detect the contact temperature of the chip under test in real time.

[0018] In a further technical solution, the management unit includes an embedded MCU, which integrates multiple PWM modules, ADC modules, and IO modules;

[0019] The PWM module is connected to the ADN8835 chip of the test unit and is used to output pulse width modulation signals to control the temperature of the test unit.

[0020] The ADC module is connected to the thermistor of the test unit and is used to collect real-time temperature data;

[0021] The IO module is connected to the heat dissipation device of the test unit and is used to control the start and stop of the heat dissipation device.

[0022] In a further technical solution, the excitation generator includes an FPGA board or an embedded Linux operating system board;

[0023] The FPGA board is used for testing non-general interface chips. It forms a control interface based on logic circuits, receives test commands from the data acquisition and analysis server through the network interface of the FPGA, tests the chip under test through the control interface, and uploads the test data to the data acquisition and analysis server.

[0024] The embedded Linux operating system board is used for testing general interface chips, automatically generating standardized test stimuli, recording test data, and feeding it back to the data acquisition and analysis server.

[0025] A further technical solution, the data acquisition and analysis server, includes:

[0026] The control module is used to send dynamic temperature control commands to the management unit according to the preset temperature curve;

[0027] The test control logic module is used to send test stimulus parameters to the stimulus generator;

[0028] The data acquisition and analysis module is used to receive environmental data uploaded by the management unit and test data uploaded by the excitation generator, and to perform data preprocessing to generate metadata;

[0029] The deep learning model includes a CNN model, a Transformer model, and a reinforcement learning unit. The CNN model is used to extract the correlation features between temperature and chip performance. The Transformer model is used to analyze multi-dimensional time series data of temperature and chip performance to identify fault modes. The reinforcement learning unit is used to dynamically optimize the FTL algorithm parameters or test instruction parameters of the chip under test.

[0030] Further technical solutions include excitation parameter data such as environmental data and FTL algorithm parameter data;

[0031] The environmental data includes the temperature profile, power consumption data, and voltage fluctuations of each chip.

[0032] The FTL algorithm parameter data includes Flash erase / write timing parameters or DDR4 timing parameters; wherein, the Flash erase / write timing parameters include erase voltage, programming pulse width, and number of erase / write cycles, and the DDR4 timing parameters include CAS latency, row precharge time, and row activation time;

[0033] The test data includes chip performance data and FTL operation-related metrics data. The chip performance data includes latency, error rate, and throughput, while the FTL operation-related metrics data includes write amplification factor, erase / write frequency, address remapping times, mapping table update density, GC trigger time distribution, and bad block growth trend.

[0034] A further technical solution, the workflow of the deep learning model, is as follows:

[0035] A pre-training dataset is constructed using historical test data; the pre-training dataset contains chip performance data and fault data under different temperature ranges and different test stimuli.

[0036] A temperature-performance mapping model is established by learning features from a pre-trained dataset using a CNN model.

[0037] During different high and low temperature tests, based on the real-time received temperature data and test data, the temporal characteristics of the data are analyzed using the Transformer model. Combined with the temperature-performance mapping relationship model, abnormal data points are identified, and the time and cause of the fault are determined.

[0038] Based on the analysis results of the Transformer model, a reinforcement learning algorithm is used, combined with a preset optimization objective, to generate parameter adjustment instructions for the chip under test and send them to the excitation generator. The preset optimization objective is to maximize the chip throughput performance while minimizing the chip error rate performance.

[0039] Secondly, the present invention provides an intelligent method for high and low temperature testing and optimization of memory chips.

[0040] A method for optimizing high and low temperature testing of intelligent memory chips, implemented based on the aforementioned intelligent high and low temperature testing device for memory chips, includes:

[0041] The chip under test is bonded to the semiconductor cold plate of the test unit using a thermally conductive material, and the number of test units and stacked layers are configured according to the test requirements.

[0042] Select either offline or online working mode. In offline mode, the temperature curve and excitation parameters are set and test tasks are issued through the management unit. In online mode, test tasks are issued by the data acquisition and analysis server. The test tasks include test instructions.

[0043] The management unit controls the power supply unit to start, the PWM module outputs a pulse width modulation signal to the ADN8835 chip of the test unit to drive the semiconductor cold plate to reach the target temperature, and the ADC module collects temperature data in real time and performs closed-loop temperature control.

[0044] The excitation generator sends test excitations to the chip under test according to the test instructions and records the test data;

[0045] The management unit and the excitation generator upload environmental data and test data to the data acquisition and analysis server. They optimize test command parameters or storage chip FTL algorithm parameters through deep learning models, generate dynamically controlled test commands, and issue them.

[0046] Based on the testing requirements, the above process is iterated repeatedly to complete high and low temperature cycling and thermal shock tests, and output test reports and FTL algorithm optimization schemes.

[0047] Thirdly, the present invention also provides an electronic device, comprising: a memory for storing executable instructions; and a processor for implementing the above-mentioned intelligent storage chip high and low temperature test optimization method when executing the executable instructions stored in the memory.

[0048] Fourthly, the present invention also provides a computer-readable storage medium storing executable instructions, which, when executed by a processor, implement the above-described intelligent storage chip high and low temperature test optimization method.

[0049] The above one or more technical solutions have the following beneficial effects:

[0050] 1. This invention proposes an intelligent high and low temperature testing device and testing optimization method for memory chips, which can adapt to the precise testing needs of modern chips and memory products in extreme temperature environments. The device includes a management unit, a testing unit, a power supply unit, and an excitation generator. The management unit uses an embedded MCU to realize multi-module collaborative control and data uploading. The testing unit uses a semiconductor cold plate as the core and combines it with an ADN8835 chip to achieve precise temperature control over a wide temperature range of -55℃ to 125℃. The excitation generator generates customized test stimuli through an FPGA or embedded Linux architecture. Each unit is linked with a data acquisition and analysis server. The test data is analyzed using AI models such as CNN, Transformer, and reinforcement learning strategies in the server to achieve FTL algorithm optimization, parameter optimization, and fault prediction for memory chips. This enables lower energy consumption and higher efficiency multi-channel parallel reliable testing of memory chip performance, which can be widely used in the reliability testing of memory chips in the automotive, aerospace, and other fields.

[0051] 2. The device proposed in this invention features embedded, low-power, modular, and intelligent characteristics, enabling it to provide rapid and accurate high and low temperature environments and thermal shock conditions for storage chips (such as Flash and DDR) or products. It also integrates AI algorithms to adaptively optimize the test process, control parameters, and operating strategies. By integrating a temperature control system and an operational load excitation module, it achieves integrated testing capabilities for environmental simulation and functional verification, significantly improving test efficiency and accuracy. Its miniaturized design and distributed architecture are suitable for diverse parallel testing needs, offering significant advantages in energy consumption control, algorithm adjustability, and data closed-loop analysis. It can effectively evaluate and improve the reliability and lifespan of chips under extreme environments.

[0052] 3. The device proposed in this invention possesses powerful secondary development capabilities, enabling deep integration of test stimuli and environmental stimuli. For storage products such as DDR chips, Flash chips, and hard drives, which require read / write stimuli to be sent by a host or embedded controller to verify their operating status under harsh environments, this device supports the addition of a Field Programmable Gate Array (FPGA) chip or an embedded operating system (such as Linux). It allows for direct porting of the controller or the construction of a test environment, intelligently generating and applying test stimuli. This achieves the integration, flexibility, and miniaturization of the test environment and test stimuli, greatly improving the realism and effectiveness of the test.

[0053] 4. The device proposed in this invention possesses network collaboration and data acquisition capabilities. Through an excitation generator, it directly uploads test excitation data, experimental data, and environmental data to a data acquisition and analysis server in real time. The server can utilize advanced deep learning models such as CNN and Transformer to intelligently learn and analyze massive amounts of data, uncovering potential performance bottlenecks and failure modes. Based on the network testing mechanism and AI-driven real-time feedback, the system can intelligently optimize the task processing mechanism of the storage controller, deeply consider the robustness of the storage algorithm under harsh environments, simulate and predict failure scenarios, thereby achieving high-quality adaptive optimization of the FTL control algorithm and significantly improving the reliability and lifespan of the product under extreme conditions.

[0054] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0055] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0056] Figure 1 This is an assembly environment diagram of the intelligent storage chip high and low temperature testing device proposed in this embodiment of the invention;

[0057] Figure 2 This is an assembly logic architecture diagram of the intelligent high and low temperature testing device for memory chips proposed in an embodiment of the present invention;

[0058] Figure 3 This is a schematic diagram of the structure of the intelligent high and low temperature testing device for memory chips proposed in an embodiment of the present invention;

[0059] Figure 4 This is a schematic diagram of the test unit in the device proposed in the embodiment of the present invention;

[0060] Figure 5 This is a flowchart of the intelligent storage chip high and low temperature testing and optimization method proposed in the embodiments of the present invention;

[0061] Figure 6 This is a flowchart illustrating the data acquisition and analysis server training method in an embodiment of the present invention. Detailed Implementation

[0062] It should be noted that the following detailed descriptions are exemplary and are intended only to describe specific embodiments and to provide further explanation of the invention, and are not intended to limit the scope of exemplary embodiments of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0063] Example 1

[0064] To meet the precise testing requirements of modern chips and memory products in extreme temperature environments, this embodiment proposes a miniaturized, low-power, and intelligent high and low temperature testing device for memory chips by integrating embedded design, semiconductor cold wafers, modular structure, online debugging, and the integration of testing devices and test stimuli, while deeply incorporating artificial intelligence technology. Figure 1 As shown, the assembly environment requirements of this device are displayed from the perspective of functional division. That is, the test device is placed in a normal temperature environment, and multiple test devices are connected to the data acquisition and analysis server through switch / router equipment. The test device has a management unit, a power supply unit, an excitation generator and multiple test units.

[0065] The system comprises the following components: a testing unit responsible for maintaining test conditions, constructing an accurate and controllable hot and cold test environment for the memory chip under test; a power supply unit providing stable DC power to each unit, which can be expanded according to the number of testing units; a management unit controlling the power supply unit and the testing unit, monitoring the working status and environmental data of the testing units in real time and uploading them to the data acquisition and analysis server (which performs AI analysis and optimization), and simultaneously controlling the environmental data in a closed loop based on test commands; and a stimulus generator providing test cases for the device under test, generating and sending test stimuli to the memory chip under test according to test commands to activate the device under test into a working or load state, while recording test data and feeding it back to the data acquisition and analysis server.

[0066] In addition, the management unit and the stimulus generator are connected to a data acquisition and analysis server via a network interface. This server is used to predict the faults of the memory chip under test based on real-time environmental data and test data, using an AI model, and to optimize test command parameters or memory chip FTL algorithm parameters. It then generates dynamically adjustable test commands and sends them to the management unit and the stimulus generator. In other words, this server can control and intelligently schedule the testing equipment in real time, and collect multi-dimensional data during the testing process (including environmental information, stimulus data, and test data). Combined with the control commands under test (or test commands), it uses a deep learning model for intelligent analysis and algorithm optimization to achieve intelligent assessment and predictive maintenance of storage product quality.

[0067] Specifically, such as Figure 2 As shown, the test unit, management unit, excitation generator, power supply unit, and data acquisition and analysis server in the test device are described in detail. The management unit and excitation generator are both connected to the data acquisition and analysis server via a network topology, with the data acquisition and analysis server acting as the server and the management unit and excitation generator acting as clients.

[0068] (1) The test unit is the core component of this device, such as Figure 3 and Figure 4 As shown, each test setup consists of multiple test units. For example, a test setup can be configured with multiple (1 to 16) test units. The test units can be stacked to improve the cooling / heating efficiency and enhance the testing capabilities. The test unit mainly includes: a semiconductor cold plate, an ADN8835 chip, a thermistor, thermally conductive materials, and a heat dissipation device. This unit is controlled by a management unit and powered by a power supply unit, working in conjunction with an excitation generator to perform tests on the chip under test.

[0069] Specifically, the ADN8835 chip is the driver control chip for the semiconductor cold plate (a full-bridge rectifier circuit can also be used as an alternative). It is connected to the PWM module of the management unit and the power supply unit. It is controlled by the PWM of the management unit and uses the built-in PID (proportion integration differentiation) function and the intelligent adjustment of the management unit. That is, according to the received PWM control signal, it controls the frequency and pulse width to adjust the power supply current of the semiconductor cold plate, thereby controlling the cooling / heating capacity of the semiconductor cold plate. This achieves precise and adaptive PID closed-loop control of the semiconductor cold plate temperature, adjusts the output drive capability of the power supply unit, and ensures fast temperature response and high-precision stability.

[0070] The semiconductor cold plate contacts the memory chip under test (MDT) via a thermally conductive material, which transfers the heat generated by the semiconductor cold plate to the MDT. Preferably, the test cells can also be stacked using a thermally conductive material.

[0071] The thermistor is embedded in the thermally conductive material. The management unit detects the temperature of the thermistor through the ADC (Analog to Digital Converter) interface. It is responsible for monitoring temperature changes together with the ADN8835 chip. The management unit will perform temperature calibration and compensation based on real-time temperature information and AI model to ensure the ultimate accuracy of temperature control.

[0072] The heat dissipation device is used to quickly release the ineffective energy consumption of the semiconductor cold plate. Generally, it refers to rapidly releasing the heat energy from the hot stage while the cold stage is in cooling mode, thereby improving the working efficiency of the semiconductor cold plate and extending its lifespan. The heat dissipation device is controlled by a management unit. In this embodiment, a DC fan is used to dissipate heat from the semiconductor cold plate, and its start / stop is controlled by a switch, thus extending the equipment's lifespan.

[0073] (2) The management unit is based on a general-purpose industrial-grade MCU, composed of embedded MCUs, and has multiple PWM modules, ADC modules, and IO modules, and supports the TCP / IP protocol. This embodiment uses, but is not limited to, the STM32F407 series MCU, which can support up to 16 test units. The management unit can work offline or be controlled by a data acquisition and analysis server to receive dynamic control commands generated by the AI ​​model, thereby realizing intelligent temperature control and status adjustment of the test units.

[0074] The PWM module connects to the ADN8835 chip in the test unit, controlling the chip to output a pulse-modulated signal by adjusting the frequency and pulse width, thereby achieving fast and accurate PID closed-loop control of the test environment temperature. The ADC module connects to the thermistor in the test unit, detecting the real-time status of the test unit (such as temperature data) to ensure the test temperature remains in a steady state. The IO module connects to the heat dissipation device of the test unit, controlling its start and stop, and controlling the DC fan to dissipate heat from the test unit, improving the device's lifespan. The management unit collects temperature timing data and other relevant environmental parameters (such as power consumption and voltage fluctuation data collected in real time using the ADC sensor) and uploads them to the data acquisition and analysis server via a network interface for further intelligent analysis and decision support by the deep learning model.

[0075] Through the above design, this device utilizes a thermoelectric cooler (TEC) based on the Peltier effect to achieve cooling / heating, generating a wide industrial temperature range of -40℃ to 85℃. Through multi-layer stacking technology, this range can be extended to a military-grade temperature range of -55℃ to 125℃. It features high energy efficiency, zero pollution, and small size. By combining a microcontroller with a pulse width modulation (PWM) module and a TEC control circuit, the DC power supply direction can be rapidly switched, thereby precisely and dynamically controlling the heating and cooling levels of the TEC and achieving rapid and stable temperature control of the contact surface. A thermistor is installed on the TEC contact surface, and the microcontroller measures the real-time temperature via an analog-to-digital converter (ADC), forming a high-precision temperature closed-loop control. The real-time temperature is displayed through a display module, achieving millimeter-level precise temperature control. Compared to traditional cooling / heating methods, semiconductor cold chips offer safer low-voltage power supply. Their small area, low power consumption, and high energy efficiency contact-based heat transfer method can directly affect chips or storage products, significantly improving power conversion efficiency and the accuracy and response speed of environmental control.

[0076] Furthermore, each independent thermal testing unit of the device consists of a PWM module, an ADC module, a semiconductor chip unit module, and related circuitry. The semiconductor module features a detachable design and supports multi-layer stacking to enhance temperature output capabilities. The testing units are isolated by insulation material to ensure the stability and independence of the measurement units. Each experimental testing device can simultaneously perform 1 to 16 independent tests. This modular architecture overcomes the testing efficiency bottleneck caused by the long overall cooling / heating time of traditional temperature chambers or shock devices, allowing multiple experimental modes such as high temperature, low temperature, and thermal shock to be performed simultaneously on the same device. This significantly improves testing efficiency and resource utilization. Simultaneously, it possesses excellent robustness and durability, and supports rapid replacement of damaged modules, greatly simplifying maintenance.

[0077] (3) The stimulus generator adopts a CPU+FPGA hardware architecture, has a network interface, and supports the Linux operating system. This embodiment uses, but is not limited to, the ZYNQ 7100 series FPGA. The stimulus generator mainly sends test stimuli to the chip under test through the stimulus controller. The stimulus controller generally refers to the controller that controls the chip under test, such as the DDR controller, NandFlash controller, and non-general high-speed interface. It can use the hardware resources built into the ZYNQ 7100, or it can use its FPGA resources to develop or expand the corresponding interface circuits. The stimulus generator obtains the intelligent test instructions and parameters of the data acquisition and analysis server through the network port driver of the Linux operating system, calls the corresponding controller driver, sends test stimuli, and applies them to the chip under test, realizing the automated and intelligent generation of test stimuli.

[0078] Furthermore, the excitation generator is an onboard module. Onboard design ensures high-speed signal quality and simplifies and improves wiring reliability. The excitation generator can intelligently generate test stimuli for different types of chips through logic reconfiguration and AI algorithm-driven operation. Excitation generators are divided into two categories: FPGA boards or embedded Linux operating system boards. Non-general-purpose interface chips can use FPGA boards, implementing the control interface through logic circuits. They receive intelligent test commands and parameters from the data acquisition and analysis server via the FPGA's network interface, perform tests on the chip under test through the control interface, and send the test data results to the data acquisition and analysis server. General-purpose interface chips can use standard controllers with embedded Linux operating system boards to automatically and intelligently generate test stimuli for testing the chip under test, sending test commands and test data to the data acquisition and analysis server via the network interface.

[0079] The excitation generator sends test stimuli according to the interface required by the chip under test. For example, NandFlash memory chips generally use a NandFlash controller; memory chips generally use a DDR controller; NorFlash / SRAM generally use SPI, I2C, or other interfaces (collectively referred to as FMC interfaces); eMMC / SD / TF / UFS memory chips correspond to different communication interfaces. The excitation generator can be controlled offline, that is, test parameters can be set through the embedded Linux operating system of the ZYNQ 7100, or it can be remotely controlled and have AI-driven test strategies distributed by a data acquisition and analysis server via a network interface.

[0080] (3) The data acquisition and analysis server controls the management unit and the excitation generator through a network interface. It consists of a control module, a test control logic module, a data acquisition and analysis module, and a deep learning model. The test device has network connectivity. The data acquisition and analysis server can control and intelligently monitor the excitation generator and test unit in real time through network connection. The management unit has off-network control functionality, i.e., it can perform constant temperature tests, and it can also be interconnected with the data acquisition and analysis server through the network interface to receive dynamic adjustment control commands sent by the server, thereby realizing adaptive optimization of the test process.

[0081] Specifically, the control module is responsible for controlling the testing device, generally used to issue dynamic temperature control commands to the management unit according to a preset temperature curve, and implement dynamic real-time adjustments; the test control logic module is responsible for controlling the excitation generator, issuing test excitation parameters to the excitation generator in network mode, testing the chip under test and acquiring test data; the data acquisition and analysis module acquires environmental status data from the management unit, control and feedback test data from the excitation generator, and the FTL algorithm of the chip under test, etc., and performs data preprocessing to form metadata that can be learned and analyzed; the deep learning model, including CNN, Transformer, reinforcement learning models, etc., is the core of the server, mainly providing services to the development end, performing intelligent learning and parameter tuning based on multi-source metadata, especially optimizing FTL algorithm parameters and data management methods in harsh environments, improving the robustness of storage products such as solid-state drives, USB flash drives, eMMC NAND flash memory, SD cards, TF cards, and UFS NAND flash memory. This embodiment supports CNN algorithms and Transformer models, and can be extended to support other advanced machine learning algorithms, such as reinforcement learning for test strategy optimization, or transfer learning for small sample fault diagnosis. For example, for storage chips that are prone to bad blocks, such as NandFlash, NorFlash, EMMC, SD, TF, UFS and other environmentally sensitive chips, this module can predict the time of failure, analyze the root cause of failure, and intelligently optimize the robustness of the control algorithm based on AI models, thereby realizing predictive maintenance and intelligent fault diagnosis.

[0082] Furthermore, the workflow of a deep learning model is as follows:

[0083] A pre-training dataset was constructed using historical test data; this pre-training dataset contains chip performance data and fault data under different temperature ranges and different test stimuli.

[0084] A temperature-performance mapping model is established by learning features from a pre-trained dataset using a CNN model.

[0085] During different high and low temperature tests, based on the real-time received temperature data and test data, the temporal characteristics of the data are analyzed using the Transformer model. Combined with the temperature-performance mapping relationship model, abnormal data points are identified, and the time and cause of the fault are determined.

[0086] Based on the analysis results of the Transformer model, a reinforcement learning algorithm is used, combined with a preset optimization objective, to generate parameter adjustment instructions for the chip under test and send them to the excitation generator. The preset optimization objective is to maximize the chip throughput performance while minimizing the chip error rate performance.

[0087] In the above process, the excitation parameter data includes environmental data and FTL algorithm parameter data. The environmental data includes the temperature profile, power consumption data, voltage fluctuations, etc. of each chip. The FTL algorithm parameter data includes Flash erase / write timing parameter data or DDR4 timing parameter data. Among them, the Flash erase / write timing parameters include erase voltage, programming pulse width, erase / write count, etc., and the DDR4 timing parameters include CAS latency, row precharge time, row activation time, etc.

[0088] The test data includes chip performance data and FTL operation-related metrics data. Chip performance data includes latency, error rate, throughput, etc., while FTL operation-related metrics data includes write amplification factor, erase / write frequency, address remapping times, mapping table update density, GC trigger time distribution, bad block growth trend, etc.

[0089] (4) Power supply unit, used to provide stable DC power to each unit, and can be expanded according to the number of test units. In this embodiment, the power supply unit uses 12V~24V power supply, the power consumption of a single test unit is between 50W and 200W, and the maximum power consumption of 16 channels at full load is about 3200W. Compared with traditional temperature chamber equipment (generally using 220V or 380V power supply, with power consumption between 6000W and 7500W), this device can effectively convert energy, achieve a higher energy efficiency ratio, and adopt a compact design to reduce space occupation. Moreover, the device does not require environmental cooling time and can achieve rapid heating and cooling through electrode switching of semiconductor cold plates, which greatly improves the testing efficiency.

[0090] The device proposed in this embodiment replaces traditional high and low temperature test chambers and chip testing systems. This device features embedded design, low power consumption, modularity, and intelligence, providing rapid and accurate high and low temperature environments and thermal shock conditions for memory chips (such as Flash and DDR) or other products. It also integrates AI algorithms to adaptively optimize the test process, control parameters, and operating strategies. By integrating a temperature control system and an operational load excitation module, this device achieves integrated testing capabilities for environmental simulation and functional verification, significantly improving testing efficiency and accuracy. Its miniaturized design and distributed architecture are suitable for diverse parallel testing needs, offering significant advantages in energy consumption control, algorithm adjustability, and data closed-loop analysis. It can effectively evaluate and improve the reliability and lifespan of chips under extreme environments.

[0091] Example 2

[0092] This embodiment provides an intelligent high and low temperature testing and optimization method for memory chips, implemented based on the intelligent high and low temperature testing device for memory chips proposed in Embodiment 1. Figure 5As shown, the working process is mainly completed through the collaboration of the management unit, the excitation generator, and the data acquisition and analysis server, and specifically includes the following steps:

[0093] Step S1: Bond the chip under test to the semiconductor cold plate of the test unit using a thermally conductive material, and configure the number of test units and stacking layers according to the test requirements.

[0094] Step S2: Select offline or online working mode. In offline mode, the temperature curve and excitation parameters are set and the test task is issued through the management unit. In online mode, the test task is issued by the data acquisition and analysis server. The test task includes test instructions.

[0095] Step S3: The management unit controls the power supply unit to start, the PWM module outputs a pulse width modulation signal to the ADN8835 chip of the test unit, driving the semiconductor cold plate to reach the target temperature, and the ADC module collects temperature data in real time and performs closed-loop temperature control.

[0096] Step S4: The excitation generator sends test excitations to the chip under test according to the test instructions and records the test data.

[0097] Step S5: In online mode, the management unit and the excitation generator upload environmental data and test data to the data acquisition and analysis server. They optimize test command parameters or storage chip FTL algorithm parameters through a deep learning model, generate dynamically controlled test commands, and issue them.

[0098] Step S6: Iterate the above process according to the test requirements to complete the high and low temperature cycle and thermal shock tests, and output the test report and FTL algorithm optimization scheme.

[0099] Specifically, the management unit has two startup methods: offline mode and online mode. The excitation generator also has two control methods: offline mode and online mode. The tested environment is determined by the test unit, which is mainly determined by the semiconductor cold plate. The test unit is controlled by the management unit. The data acquisition and analysis server can not only serve as a control module, but also as an intelligent analysis and optimization module during or after the test process. It is used to identify the quality of the tested object, predict faults, and optimize algorithms.

[0100] In offline mode, there is no need to connect to a data acquisition and analysis server. Instead, the management unit parameters are set locally, and the excitation generator is set through the embedded Linux operating system. The temperature environment and test excitation strategy are set, and the Linux operating system of the excitation generator records the temperature environment and test excitation strategy.

[0101] In online mode, a data acquisition and analysis server needs to be connected, and the management unit and stimulus generator are configured through the server's network interface. Compared to offline mode, online mode is easier to automate and batch test, and can monitor and intelligently adjust the test status in real time through AI models, acquiring multi-dimensional and environmental data during the test process to achieve adaptive optimization and fault early warning.

[0102] In this embodiment, the test results in both online and offline modes are displayed on the LCD screen of the testing device. Meanwhile, in online mode, detailed data and AI analysis results can be visualized and deeply analyzed on the data acquisition and analysis server.

[0103] The deep learning training and algorithm optimization described above will be introduced in more detail. For example... Figure 6 As shown, the data acquisition and analysis server has pre-trained data. The metadata of the pre-trained data consists of test data from the stimulus generator and environmental data from the management unit, arranged in a time series. Deep learning models such as CNN and Transformer perform initial model construction and feature learning based on the pre-trained data, and then optimize the parameters based on real-time data. The real-time data has the same structure as the pre-trained data. Figure 2 The data acquisition and analysis module processes the data and mixes it with pre-trained data to dynamically adjust the algorithm as training data. Through multiple rounds of iteration and reinforcement learning, the algorithm model is continuously optimized and intelligently replaces the existing algorithm, thereby continuously improving testing efficiency and product reliability.

[0104] Based on the above AI model design, intelligent parameter tuning and fault prediction for Flash / DDR4 memory can be achieved. Specifically, intelligent tuning of key operating parameters for Flash memory chips or DDR4 memory chips, and prediction of potential faults, are achieved as follows:

[0105] First, test scenarios were set up and multi-dimensional data was collected. The goal was to optimize the erase / program timing parameters of Flash chips or the read / write latency parameters of DDR4 chips, ensuring optimal performance and reliability even under extreme high and low temperature environments. Multiple Flash / DDR4 chips under test were connected to the test device via test units. A series of preset high and low temperature cycling test curves were set using a management unit and a stimulus generator, such as a temperature shock from -40°C to 85°C. The stimulus generator continuously applied read and write stress tests to the chips, simulating actual workloads.

[0106] During the testing process, the management unit collects environmental parameters such as temperature curves, power consumption data, and voltage fluctuations of each chip in real time. At the same time, the excitation generator accurately records the performance and reliability indicators such as latency, success rate, error count (such as ECC error rate and bad block generation rate) and internal register status of each read and write operation as test data. This multi-dimensional, high-frequency timing data is uploaded to the data acquisition and analysis server in real time.

[0107] The server pre-stores a large amount of multimodal pre-trained data generated from historical tests and simulations, covering Flash / DDR4 performance and failure modes under different batches, temperature conditions, and operating parameters (i.e., excitation parameters). A Transformer model is used for feature extraction and correlation analysis of the time-series data to identify the complex nonlinear relationships between environmental parameters, operating parameters, chip performance, and failures. Simultaneously, a reinforcement learning (RL) agent is introduced for online policy generation and parameter optimization.

[0108] During training, the Transformer model first uses pre-trained data for supervised learning, learning a predictive model of chip performance under specific temperatures and operating parameters. In actual testing, real-time acquired data serves as "environmental feedback" for the RL (Reinforcement Learning) agent. The RL agent dynamically adjusts the Flash erase / write timing parameters sent by the stimulus generator based on the current environment (e.g., temperature, applied test stimuli) and the chip's real-time performance (e.g., latency, error rate). These parameters include erase voltage, programming pulse width, erase / write cycles, and DDR4 timing parameters such as CAS Latency (CL, column address strobe delay), RowPrecharge Time (tRP), and Row Active Time (tRAS). The goal of the RL agent is to maximize chip performance (e.g., throughput) while minimizing the error rate and extending its lifespan, thereby finding the optimal parameter combination at different temperature points.

[0109] Furthermore, intelligent tuning and adaptive parameter optimization were performed during the experiment. During high and low temperature cycling, as the temperature changed, the AI ​​model predicted the optimal Flash / DDR4 operating parameters based on real-time temperature and chip feedback, and sent these parameters to the excitation generator in real time via the network interface. For example, when the temperature increased, the AI ​​might intelligently fine-tune the Flash programming pulse width or the CL value of the DDR4 to compensate for the impact of temperature on the internal circuitry, ensuring that performance did not degrade or the error rate did not increase.

[0110] As another implementation method, anomaly detection and early warning are performed during the experiment. The Transformer model continuously analyzes the real-time data stream and intelligently identifies anomalies that deviate significantly from the normal behavior pattern, such as: data read failure, sudden increase in erase / write latency at a specific temperature, rapid increase in ECC error rate, or irregular jitter in DDR4 read / write latency. Once these anomalies are detected, an early warning is immediately triggered, and an attempt is made to analyze the root cause, such as whether it is a problem caused by a specific temperature range or a defect in a certain parameter combination.

[0111] As another implementation method, during the experiment, Remaining Lifetime (RUL) prediction is performed based on experimental data. Specifically, an AI model is trained by combining the chip's cumulative operating time, temperature exposure history, error rate trends, etc. After unsupervised training, the AI ​​model is used to predict or extrapolate the chip's remaining effective lifetime or the critical point for bad blocks to occur. This is of great value for chip quality identification, reliability assessment, and early elimination of defective products.

[0112] Through the aforementioned intelligent tuning mechanism, this embodiment can enable the Flash / DDR4 chip to automatically find the optimal operating parameters in a complex temperature-changing environment without human intervention. It can also achieve early fault prediction and intelligent intervention that are difficult to achieve with traditional methods, significantly improving the overall quality and robustness of storage products.

[0113] Because the manufacturing process of FLASH / DDR4 chips will result in different batches, different wafer yields, and different levels of bare dies (single bare die), the required parameters of the chips will also differ. Through the aforementioned intelligent optimization mechanism, this embodiment can automatically adjust parameters (such as erase count, latency, voltage boost, etc.) of the Flash / DDR4 chip in complex temperature-changing environments without human intervention to find the optimal operating parameters. This improves the yield of low-quality memory chips and enhances the overall quality and robustness of memory products. Moreover, the above method can also achieve early fault prediction and intelligent intervention that are difficult to achieve with traditional methods, ensuring the safety of the test chips and avoiding unnecessary damage.

[0114] Preferably, the FTL algorithm of the storage product is dynamically optimized for high and low temperature conditions, and failure prediction and fault handling are performed, including:

[0115] First, the test environment and simulated workload were set up. Multiple NandFlash chips with different FTL parameter strategies (such as mapping strategy, erase trigger threshold, GC algorithm, etc.) were selected and connected to the system through the test unit. Based on the set high and low temperature cycle (such as -40°C to 85°C), the excitation generator continuously generated intensive IO operations such as read, write, update, GC (Garbage Collection), and erase to simulate the behavior characteristics of FTL in the actual running scenario.

[0116] Secondly, multi-dimensional data and modeling parameters were collected. During testing, ambient temperature, current, voltage, and power consumption were continuously collected, while FTL operation-related metrics were recorded in real time, including write amplification factor (WA), erase / write frequency, address remapping count, mapping table update density, GC trigger time distribution, and bad block growth trend. These data constitute a complete multi-dimensional input feature set.

[0117] Next, the neural network is trained and feature weights are learned. Using the aforementioned features as input, a performance prediction model based on a multilayer perceptron (MLP) is constructed. The target output includes I / O latency, ECC error rate, chip temperature rise sensitivity, and the impact of the FTL algorithm on lifespan. The model is trained using supervised learning, utilizing historical test results and labels, and cross-validated to enhance generalization ability.

[0118] Secondly, clustering-based FTL behavior pattern analysis and configuration optimization are performed. Clustering algorithms such as K-Means or DBSCAN are used to cluster the operating behavior of different FTL configurations under the temperature dimension, extracting the parameter combination features corresponding to the optimal behavior cluster. Based on the clustering results, the current state of the chip under test is categorized and matched, and the system recommends the FTL parameter set closest to the optimal cluster for switching or fine-tuning.

[0119] Next, real-time parameter fine-tuning occurs. Upon receiving the recommended parameter combination, the test device automatically adjusts FTL strategy parameters, including but not limited to GC trigger threshold, mapping method (page-level / block-level), write buffer size, and WL strategy, to achieve the optimal performance point under the current temperature environment. The entire process requires no manual intervention, achieving adaptive adjustment of the FTL strategy.

[0120] Finally, abnormal behavior is detected and failure trends are predicted. By combining time-series anomaly detection methods (such as sliding window with LSTM autoencoder or threshold-based multivariate control chart method), the system can issue early warnings when FTL performance changes abruptly (such as a sudden increase in WA, a sudden change in GC frequency, or write latency jitter). The AI ​​model can also combine historical behavior with current temperature distribution trends to predict the probability of FTL-related failures and remaining service life.

[0121] By combining neural network regression prediction and unsupervised clustering analysis, the FTL algorithm optimization method described above can accurately identify FTL performance differences and provide optimization suggestions in multi-chip, multi-temperature, and multi-strategy combination environments, significantly improving the reliability and lifespan utilization of storage products under complex temperature control conditions.

[0122] Example 3

[0123] This embodiment provides an electronic device, including: a memory for storing executable instructions; and a processor for executing the executable instructions stored in the memory to implement the method provided in this embodiment.

[0124] Example 4

[0125] This embodiment also provides a computer-readable storage medium storing executable instructions, which, when executed by a processor, will cause the processor to execute the method described above in this embodiment.

[0126] The steps involved in Embodiments 2 to 4 above correspond to those in Embodiment 1. For specific implementation details, please refer to the relevant description section of Embodiment 1. The term "computer-readable storage medium" should be understood as a single medium or multiple media including one or more instruction sets; it should also be understood as including any medium capable of storing, encoding, or carrying an instruction set for execution by a processor and enabling the processor to perform any of the methods in this invention.

[0127] Those skilled in the art will understand that the modules or steps of the present invention described above can be implemented using general-purpose computer devices. Optionally, they can be implemented using computer-executable program code, thereby allowing them to be stored in a storage device for execution by a computer device, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. The present invention is not limited to any particular combination of hardware and software.

[0128] The above description is only a preferred embodiment of the present invention. Although the specific implementation of the present invention has been described in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that, based on the technical solution of the present invention, various modifications or variations that can be made by those skilled in the art without creative effort are still within the scope of protection of the present invention.

Claims

1. An intelligent storage chip high and low temperature testing device, characterized in that, include: The test unit is used to construct a hot and cold test environment for the memory chip under test; The power supply unit is used to provide DC power to each unit; The management unit is used to detect environmental data in real time and upload it to the data acquisition and analysis server, while also controlling the environmental data in a closed loop in conjunction with test commands; The excitation generator is used to generate and send test excitations to the memory chip under test according to the test instructions, record test data and feed it back to the data acquisition and analysis server; The management unit and the excitation generator are connected to the data acquisition and analysis server through a network interface. The data acquisition and analysis server is used to predict the fault of the memory chip under test based on real-time environmental data and test data, and optimize the test command parameters or memory chip FTL algorithm parameters, generate dynamic control test commands and send them to the management unit and the excitation generator. The data acquisition and analysis server includes: The control module is used to send dynamic temperature control commands to the management unit according to the preset temperature curve; The test control logic module is used to send test stimulus parameters to the stimulus generator; The data acquisition and analysis module is used to receive environmental data uploaded by the management unit and test data uploaded by the excitation generator, and to perform data preprocessing to generate metadata; The deep learning model includes a CNN model, a Transformer model, and a reinforcement learning unit. The CNN model is used to extract the correlation features between temperature and chip performance. The Transformer model is used to analyze multi-dimensional time series data of temperature and chip performance to identify fault modes. The reinforcement learning unit is used to dynamically optimize the FTL algorithm parameters or test instruction parameters of the chip under test. Excitation parameter data includes environmental data and FTL algorithm parameter data; The environmental data includes the temperature profile, power consumption data, and voltage fluctuations of each chip. The FTL algorithm parameter data includes Flash erase / write timing parameters or DDR4 timing parameters. The Flash erase / write timing parameters include erase voltage, programming pulse width, and number of erase / write cycles. The DDR4 timing parameters include CAS latency, row precharge time, and row activation time. The test data includes chip performance data and FTL operation-related metrics data. The chip performance data includes latency, error rate, and throughput, while the FTL operation-related metrics data includes write amplification factor, erase / write frequency, address remapping times, mapping table update density, GC trigger time distribution, and bad block growth trend. 2.The intelligent storage chip high and low temperature test device of claim 1, wherein, The test unit supports multi-layer stacking, including semiconductor cold plate, ADN8835 chip, thermistor, thermal conductive material and heat dissipation device; The ADN8835 chip is connected to the PWM module of the management unit and the power supply unit respectively. It has a built-in PID control algorithm to adjust the power supply current of the semiconductor cold chip according to the received PWM control signal to achieve closed-loop temperature control. The semiconductor cold plate contacts the memory chip under test through a thermally conductive material and switches between cooling and heating based on the Peltier effect to create a cold and hot test environment for the memory chip under test. The thermistor is embedded inside the thermally conductive material and is used to detect the contact temperature of the chip under test in real time.

3. The intelligent high and low temperature testing device for memory chips as described in claim 1, characterized in that, The management unit includes an embedded MCU, which integrates multiple PWM modules, ADC modules, and IO modules. The PWM module is connected to the ADN8835 chip of the test unit and is used to output pulse width modulation signals to control the temperature of the test unit. The ADC module is connected to the thermistor of the test unit and is used to collect real-time temperature data; The IO module is connected to the heat dissipation device of the test unit and is used to control the start and stop of the heat dissipation device.

4. The intelligent high and low temperature testing device for memory chips as described in claim 1, characterized in that, The excitation generator includes an FPGA board or an embedded Linux operating system board; The FPGA board is used for testing non-general interface chips. It forms a control interface based on logic circuits, receives test commands from the data acquisition and analysis server through the network interface of the FPGA, tests the chip under test through the control interface, and uploads the test data to the data acquisition and analysis server. The embedded Linux operating system board is used for testing general interface chips, automatically generating standardized test stimuli, recording test data, and feeding it back to the data acquisition and analysis server.

5. The intelligent high and low temperature testing device for memory chips as described in claim 1, characterized in that, The workflow of the deep learning model is as follows: A pre-training dataset is constructed using historical test data; the pre-training dataset contains chip performance data and fault data under different temperature ranges and different test stimuli. A temperature-performance mapping model is established by learning features from a pre-trained dataset using a CNN model. During different high and low temperature tests, based on the real-time received temperature data and test data, the temporal characteristics of the data are analyzed using the Transformer model. Combined with the temperature-performance mapping relationship model, abnormal data points are identified, and the time and cause of the fault are determined. Based on the analysis results of the Transformer model, a reinforcement learning algorithm is used, combined with a preset optimization objective, to generate parameter adjustment instructions for the chip under test and send them to the excitation generator. The preset optimization objective is to maximize the chip throughput performance while minimizing the chip error rate performance.

6. A method for high and low temperature testing and optimization of intelligent memory chips, characterized in that, Based on the intelligent high and low temperature testing device for memory chips according to any one of claims 1-5, it includes: The chip under test is bonded to the semiconductor cold plate of the test unit using a thermally conductive material, and the number of test units and stacked layers are configured according to the test requirements. Select either offline or online working mode. In offline mode, the temperature curve and excitation parameters are set and test tasks are issued through the management unit. In online mode, test tasks are issued by the data acquisition and analysis server. The test tasks include test instructions. The management unit controls the power supply unit to start, the PWM module outputs a pulse width modulation signal to the ADN8835 chip of the test unit to drive the semiconductor cold plate to reach the target temperature, and the ADC module collects temperature data in real time and performs closed-loop temperature control. The excitation generator sends test excitations to the chip under test according to the test instructions and records the test data; The management unit and the excitation generator upload environmental data and test data to the data acquisition and analysis server. They optimize test command parameters or storage chip FTL algorithm parameters through deep learning models, generate dynamically controlled test commands, and issue them. Based on the testing requirements, the above process is iterated repeatedly to complete high and low temperature cycling and thermal shock tests, and output test reports and FTL algorithm optimization schemes.

7. An electronic device, characterized in that, include: Memory, used to store executable instructions; The processor, when executing executable instructions stored in the memory, implements the intelligent storage chip high and low temperature testing method of claim 6.

8. A computer-readable storage medium, characterized in that, It stores executable instructions, which, when executed by the processor, implement the intelligent storage chip high and low temperature testing method of claim 6.

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