Airtight packaging method for flip chip and packaged chip
By etching half-grooves and silicon pillars on a silicon-based adapter board, evaporating solder and gold layers, and using a hot-pressing process to mount the chip, the problem of chip hermeticity not being proportional to package size is solved, achieving hermetic packaging with high reliability and small package area.
Patent Information
- Application Number
- CN202511312124.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-15
- Publication Date
- 2025-12-19
AI Technical Summary
In existing technologies, the hermeticity of chips is not directly proportional to the package size. How can we improve the hermeticity of flip chips while minimizing the package area?
Half-grooves and silicon pillars are etched on a silicon-based adapter using dry etching, solder and a ring-shaped gold layer are deposited by vapor deposition, and the chip is flip-chip mounted on the half-grooves using a hot-pressing process. Finally, molding compound is used for encapsulation.
This technology improves chip airtightness and reliability while reducing packaging area, preventing external moisture and dust from entering, extending chip life, and ensuring reliable operation in harsh environments.
Smart Images
Figure CN121171902A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor packaging, and in particular to a flip chip hermetic packaging method and a packaged chip. BACKGROUND
[0002] With the development of communication technology, higher requirements are put forward for the size, performance and reliability of electronic components. Flip chip technology has rapidly developed due to its high I / O density, short transmission path and compatibility with high frequency scenarios. Current flip chip technology uses bare chips or plastic packaged chips as the upper flip chip, and uses chip wafers or low thermal expansion PCBs as the lower substrate. After flip, the whole is plastic encapsulated. This method has low resistance to water vapor and high failure risk in long-term service. Using ceramic or metal tubes to hermetically seal the flip chip will greatly increase the package size, losing the area advantage of flip chip. In the prior art, the hermeticity of the chip is not proportional to the package size. How to achieve hermetic packaging of flip chips with the smallest size is the direction of continuous efforts in the industry. SUMMARY
[0003] The present application provides a flip chip hermetic packaging method and a packaged chip to solve the problem that the hermeticity of the chip is not proportional to the package size in the prior art.
[0004] In a first aspect, the present application provides a flip chip hermetic packaging method, comprising:
[0005] A dry etching method is used to etch a predetermined number of half grooves on the top surface of the silicon adapter board, the predetermined number being the number of chips to be packaged, and each half groove containing a plurality of silicon pillars corresponding to the chip function points or contact points of the corresponding chip;
[0006] Solder is evaporated around each half groove and on the top end of each silicon pillar, and a ring-shaped gold layer is electroplated around each chip to be packaged.
[0007] A predetermined hot pressing process parameter is set, and a hot pressing process is used to flip and install each chip to be packaged on the corresponding half groove, and plastic encapsulation is performed using plastic encapsulation material.
[0008] In a second aspect, the present application provides a packaged chip, which is prepared by the flip chip hermetic packaging method of the first aspect.
[0009] The application provides a flip chip airtight packaging method and a packaged chip. A dry etching method is used to etch a preset number of half grooves on the top surface of a silicon-based adapter board, the preset number being the number of chips to be packaged, and each half groove contains a plurality of silicon columns corresponding to the chip function points or contact points of the corresponding chip. Solder is evaporated around each half groove and on the top end of each silicon column, and a ring-shaped gold layer is electroplated on the periphery of each chip to be packaged. A preset hot pressing process parameter is set, and a hot pressing process is used to flip mount each chip to be packaged on the corresponding half groove, and plastic sealing material is used for plastic sealing. The application evaporates solder around each half groove and on the top end of each silicon column, and when the hot pressing process is used to flip mount the chip on the corresponding half groove, the molten solder can form firm welding points, which not only ensures good electrical connection between the chip and the silicon-based adapter board, but also provides reliable mechanical fixation. Meanwhile, the ring-shaped gold layer electroplated on the periphery of the chip further enhances the bonding strength of the chip and the surrounding structure, so that the entire packaging can still maintain the structural integrity and stability when facing mechanical vibration, impact and other external environmental changes. Furthermore, the step of using plastic sealing material for plastic sealing provides effective airtight protection for the entire packaging structure. The airtight packaging can prevent external moisture, dust, chemicals and the like from entering the packaging interior, avoids damage to the chip caused by these factors such as corrosion and short circuit, thereby prolonging the service life of the chip and ensuring reliable operation of the chip in various harsh environments. BRIEF DESCRIPTION OF DRAWINGS
[0010] In order to more clearly illustrate the technical solutions in the application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.
[0011] Figure 1 is a flowchart of the flip chip airtight packaging method provided by the embodiments of the application;
[0012] Figure 2 is a side structure schematic diagram of the silicon-based adapter board provided by the embodiments of the application;
[0013] Figure 3 is a BGA pad structure schematic diagram provided by the embodiments of the application;
[0014] Figure 4 is a radio frequency connection solder setting schematic diagram provided by the embodiments of the application;
[0015] Figure 5 is a hot pressing process curve schematic diagram provided by the embodiments of the application;
[0016] Figure 6Figure 1 is a structural schematic diagram of a packaged chip provided by an embodiment of the present application.
[0017] In the figure, 1 is a silicon-based adapter plate, 2 is plastic sealing material, 3 is a heat dissipation cold plate, 4-6 are chips, 11 is a half slot, 12 is a BGA pad, 13 is a TSV hole, 14 is an insulating layer, and 15 is evaporated solder. DETAILED DESCRIPTION
[0018] In the following description, specific details are set forth, such as particular system configurations, techniques, etc., in order to provide a thorough understanding of the present application. However, persons skilled in the art will understand that the present application can be practiced without these specific details. In other instances, well-known structures, devices, circuits, and methods have not been described in detail in order to avoid obscuring the present application.
[0019] In order to make the purpose, technical scheme and advantages of the present application clearer, specific embodiments will be described below with reference to the accompanying drawings.
[0020] To solve the problem that the air tightness of a chip is not proportional to the packaging size in the prior art, the present application provides a flip chip air tight packaging method, which realizes improving the self air tightness of multiple flip chips in the case of minimizing the packaging area.
[0021] Figure 1 The implementation flowchart of the flip chip air tight packaging method provided by an embodiment of the present application is described in detail as follows.
[0022] In step 101, a dry etching method is used to etch a preset number of half slots on the top surface of a silicon-based adapter plate, the preset number being the number of chips to be packaged, and each half slot contains multiple silicon pillars corresponding to the chip function points or contact points of the corresponding chip.
[0023] In the embodiment of the present application, after determining the number of chips to be packaged (i.e., the preset number), a dry etching method is used to etch a preset number of half slots on the top surface of a silicon-based adapter plate. Since multiple chip function points and contact points exist on each chip, a dry etching method is also used to etch a corresponding number of silicon pillars in each half slot etched on the silicon-based adapter plate according to the positions of the chip function points and contact points of the corresponding chip.
[0024] The area of each half slot covers the corresponding chip pattern, thereby providing an air tight cavity for each flip chip.
[0025] In the embodiment of the present application, the depth of the half slot is smaller than the thickness of the silicon-based adapter plate, but the depth of the half slot is deep enough, which can be set to 100 μm, and the bottom of the half slot has no metal plating layer, thereby avoiding the influence on the performance of radio frequency chips.
[0026] As an example, referring to Figure 2 As shown, 1 is a silicon interposer, and 11 is a half slot. When the number of chips to be packaged is 4, corresponding half slots 11 are etched on the top surface of the silicon interposer 1 according to the size of each chip by using a dry etching method, and a silicon column corresponding to the chip function point and the grounding point of the corresponding chip is etched in each half slot (the silicon column is not shown in Figure 2 ).
[0027] The embodiment of the present application etches a half slot corresponding to the number of chips to be packaged on the top surface of the silicon interposer by using a dry etching method, and each half slot contains a plurality of silicon columns corresponding to the chip function point or the grounding point. This precise etching process can ensure that the chip and the interposer are highly accurately matched, the silicon column is accurately matched with the chip function point or the grounding point, greatly improves the reliability of electrical connection, reduces interference and loss in the process of signal transmission, and thus improves the overall performance of the chip.
[0028] In addition, the pre-set number of half slots in the embodiment of the present application can be flexibly adjusted according to the packaging requirements of different chips, and can adapt to the packaging requirements of various types and different sizes of chips, has strong universality and adaptability, reduces the development cost and time of the packaging process, and improves the flexibility and production efficiency of the production line.
[0029] In a possible implementation, the back surface of the silicon interposer is provided with a BGA pad; after the pre-set number of half slots are etched on the top surface of the silicon interposer by using a dry etching method, the method can further include:
[0030] The position of each silicon column is found on the BGA pad, and a TSV hole is etched for each silicon column to realize the interconnection between the top surface and the back surface of the silicon interposer.
[0031] Optionally, since the BGA is a key conductive area for connecting the BGA packaged device and the printed circuit board (PCB) in electronic packaging technology, the design thereof directly affects signal transmission, heat dissipation performance and welding reliability, therefore, referring to Figure 2 As shown, the back surface of the silicon interposer 1 is provided with a BGA pad 12, that is, the surface metal trace is made by photolithography and electroplating, and the lead pad (i.e., the BGA pad 12) on the back surface of the silicon interposer, and the structure of the BGA pad is shown in Figure 3As shown, from bottom to top, there are, in sequence, a silicon-based adapter plate, a bridge metal layer, a solder resist layer, a nickel layer, and a thin gold layer. In order to avoid damage to the solder resist layer due to pressure and friction during assembly of the chip, the solder resist layer is made to be below the BGA pad. In order to avoid micro cracks between the BGA pad and the solder resist layer due to process factors and to improve the width of the process window, the BGA pad structure is set to a structure in which the nickel pad presses the solder resist, and the size A is set to a range of 20 μm to 40 μm. For example, the size A can be 20 μm, 25 μm, 30 μm, or 38 μm, and is set according to actual requirements.
[0032] Then, referring to Figure 2 The position of each silicon column is found on the BGA pad 12, and a TSV hole 13 is etched for each silicon column by a dry etching method, so as to realize double-sided communication of the silicon-based adapter plate 1 and ensure the air tightness of the packaged chip. Then, the TSV hole is filled with copper by electroplating, and the planarity of the electroplating is ensured by a CMP process.
[0033] The embodiment of the present application can form a good air-tight structure and effectively prevent external gas from entering the inside of the chip. This is very important for some chips that are sensitive to environmental gas, such as some sensor chips and optoelectronic devices, and can ensure that the performance of the chip is not affected by changes in the composition of external gas and humidity, and that the chip can work normally in various complex environments.
[0034] In a possible implementation, after a preset number of half grooves are etched on the top surface of the silicon-based adapter plate by the dry etching method, the method can further include:
[0035] An oxidation layer is made on the etched silicon-based adapter plate by high-temperature baking, and is used as an insulating layer of the metal wiring and the silicon-based adapter plate. For example, referring to Figure 2 As shown, 14 is an insulating layer.
[0036] In step 102, solder is evaporated around each half groove and on the top end of each silicon column, and a ring-shaped gold layer is electroplated on the periphery of each chip that needs to be packaged.
[0037] In the embodiment of the present application, after the half grooves and the silicon columns are etched on the top surface of the silicon-based adapter plate, and before flip-chip mounting is performed, solder is evaporated around each half groove and on the top end of each silicon column on the top surface of the silicon-based adapter plate by an evaporation process, so as to ensure good air tightness and avoid short circuit caused by too much solder.
[0038] In this embodiment, the vapor-deposited solder is composed of Au80Sn20 (i.e., gold-tin solder), and its shape can be square or a closed ring. If it is a closed ring, the width of the sealing ring can be designed to be 80μm. To prevent solder splashing during heating, the solder at signal function points (i.e., chip function points or ground points) is designed as a non-closed ring, as detailed in the following reference. Figure 4 As shown, the solder width A is designed to be 50μm, the opening width B is designed to be 25μm, the outer ring diameter C is designed to be 200μm, and the distance D between the solder and the TSV hole is designed to be 70μm.
[0039] For example, refer to Figure 2 15 is the vapor-deposited solder. After the silicon-based adapter board 1 is etched, the vapor-deposited solder 15 (i.e., Au80Sn20) is prepared on the periphery of each half-groove 11 on the silicon-based adapter board 1 and on the top of each silicon pillar in each half-groove 11 by vapor deposition process.
[0040] Then, a ring-shaped gold layer is electroplated around each chip that needs to be packaged.
[0041] In this embodiment, solder is deposited around each half-groove and at the top of the silicon pillar. This design makes the electrical connection between the chip and the adapter board more stable. The solder provides good conductivity, reduces contact resistance, further optimizes signal transmission quality, and reduces energy loss. This is especially important for chips with high-frequency and high-speed signal transmission, as it helps to improve the chip's operating frequency and stability.
[0042] Furthermore, this embodiment of the application, through the design and fabrication of slots in the silicon interposer and the shape of the solder, enables the hermetically sealed packaging of multiple chips onto the silicon interposer after flip-chip bonding. This flip-chip method achieves hermetically sealed bare chip flip-chip bonding, reduces package size, and increases package reliability.
[0043] In one possible implementation, before depositing solder around the perimeter of each half-groove and at the tip of each silicon pillar, the method may further include:
[0044] Plasma cleaning is performed on the vapor-deposited solder.
[0045] Optionally, in this embodiment of the application, before welding via vapor deposition, the gold-tin solder raw material and the annular gold layer need to be plasma cleaned. The plasma cleaning parameters are: 180W, 120s.
[0046] In step 103, preset hot pressing process parameters are set, and each chip to be packaged is flip-chip mounted on the corresponding half-groove using the hot pressing process, and then encapsulated using molding compound.
[0047] In the embodiment of the present application, after the solder is evaporated around each half slot and the top of each silicon column, and the peripheral gold layer of each chip to be packaged is electroplated, the silicon-based adapter plate and the chips to be packaged are placed in a flip welding machine, preset thermal compression process parameters are set, and the flip-chip mounting of each chip to be packaged on the corresponding half slot is performed by using the thermal compression process. Then, in order to protect each exposed chip (i.e., the back of each chip is exposed after flip-chip mounting), the back of the chip is molded with plastic packaging material to achieve protection of the chip.
[0048] The thermal compression process in the embodiment of the present application, combined with the preset thermal compression process parameters, can accurately control the connection pressure and temperature between the chip and the adapter plate, and ensure the consistency and stability of the welding quality. At the same time, the process steps of electroplating a peripheral gold layer around the chip and evaporating solder on the half slot and the silicon column help to improve the reliability and success rate of welding, reduce welding defects such as false welding and short circuit, thereby improving the overall production yield and reducing production costs. In addition, the flip-chip mounting method and the design of the half slot make the connection between the chip and the adapter plate more compact, reducing the packaging size. This compact packaging structure is conducive to integrating more chips in a limited space, improving the integration of electronic products, and meeting the development trend of miniaturization and thinness of modern electronic products.
[0049] In a possible implementation, the preset thermal compression process parameters include temperature, the temperature peak of the temperature is higher than the melting point of the evaporated solder, the temperature rising rate of the temperature is 5℃ / s-10℃ / s, and the holding time of the temperature ranges from 8s to 10s.
[0050] In a possible implementation, the preset thermal compression process parameters include pressure, and the calculation formula of the pressure is:
[0051] F=(1N / mm 2 ~2N / mm 2 )*S
[0052] Wherein, F is the pressure, and S is the solder area of the evaporated solder.
[0053] Optionally, in the embodiment of the present application, the preset thermal compression process parameters include two parts, which are temperature and pressure respectively. The thermal compression process curve corresponding to the preset thermal compression process parameters is shown in FIG. 2, which includes a temperature curve and a pressure curve respectively. Figure 5
[0054] The temperature peak is set higher than the melting point of the evaporation solder (Au80Sn20, and its melting point is 280℃). In the embodiment, the temperature peak is set at 310℃. In addition, considering the high density of the chip interconnection and the small array solder spacing, the solder diffusion needs to be reduced during the flip welding process. Therefore, the temperature rising rate is controlled at 5-10℃ / s, and the temperature holding time is set at 8-10s.
[0055] It should be noted that the whole process is carried out in a formic acid environment.
[0056] For example, when the chip is flip welded on the corresponding half groove, the temperature is raised at a rate of 8℃ / s in a formic acid environment, and the temperature is maintained for 10s.
[0057] In order to make the welding surface contact sufficient, the pressure needs to be calculated according to the solder area. The welding pressure peak calculation formula is:
[0058] F=(1N / mm 2 ~2N / mm 2 )*S
[0059] Wherein, F is the pressure, and S is the solder area of the evaporation solder.
[0060] It should be noted that the pressure should be applied before the temperature is raised.
[0061] Moreover, once the gold-tin solder is fused and welded with the gold layer of the welding surface, the increase of the gold content will cause the melting point of the formed alloy to rise. At this time, after adjusting the hot pressing process curve to an appropriate temperature, it can be ensured that the subsequent chip process after flip avoids the remelting of the solder bumps of the chip which has been flip welded. The appropriate pressure of the hot pressing process curve makes the silicon-based adapter plate and the chip flip process fully contact, and the gold-tin solder around the half groove forms a sealing ring.
[0062] In a possible implementation, before the plastic encapsulation is performed by using the plastic encapsulating material, the method can further include:
[0063] When there is a chip that needs to be cooled, a heat dissipation cold plate is attached to the back of the chip that needs to be cooled by using an adhesive material.
[0064] Optionally, after the flip is completed, for the chip that needs to be cooled, a heat dissipation cold plate is attached to the back of the chip that needs to be cooled by using an adhesive material. The adhesive material is high-thermal-conductivity nano-silver glue.
[0065] It should be noted that in order to ensure that the size of the packaged chip is small enough, it is required that the height of the heat dissipation cold plate is consistent with the height of the plastic encapsulating material, so as to avoid the increase of the size of the packaged chip due to the excessive height of the heat dissipation cold plate or the plastic encapsulating material.
[0066] The application provides a flip chip airtight packaging method, which comprises the following steps: etching a preset number of half grooves on the top surface of a silicon-based adapter plate by using a dry etching method, wherein the preset number is the number of chips to be packaged, and each half groove contains a plurality of silicon columns corresponding to the chip function points or grounding points of the corresponding chip; evaporating solder around each half groove and on the top end of each silicon column, and electroplating a ring-shaped gold layer on the periphery of each chip to be packaged; setting preset hot-pressing process parameters, and using a hot-pressing process to flip and install each chip to be packaged on the corresponding half groove, and then using plastic sealing material to perform plastic sealing.
[0067] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the application.
[0068] The following is an embodiment of the application for packaging chips, and for details not described in detail, reference can be made to the corresponding method embodiments described above.
[0069] Figure 2 A structure diagram of a packaged chip prepared by using the flip chip airtight packaging method is shown, and only parts related to the embodiment of the application are shown for the convenience of description, and the details are as follows:
[0070] As shown in Figure 6 , the packaged chip comprises a silicon-based adapter plate 1, plastic sealing material 2, a heat dissipation cold plate 3 and chips 4-6. The chips 4-6 are flip-chip sealed and installed on the top surface of the silicon-based adapter plate 1, the heat dissipation cold plate 3 is bonded to the back surface of the chip 6 with high power dissipation requirement, and the plastic sealing material 2 is used to protect the back surface of the chips 4-6. The height of the plastic sealing material 2 is flush with the height of the heat dissipation cold plate 3.
[0071] The application provides a packaged chip, which is prepared by the flip chip airtight packaging method as described above, and the specific preparation method is as follows: a preset number of half grooves are etched on the top surface of a silicon-based adapter plate by using a dry etching method, the preset number is the number of chips to be packaged, and each half groove contains a plurality of silicon columns corresponding to the chip function points or grounding points of the corresponding chip; solder is evaporated on the periphery of each half groove and the top end of each silicon column, and a ring-shaped gold layer is electroplated on the periphery of each chip to be packaged; preset hot pressing process parameters are set, the hot pressing process is used to flip mount each chip to be packaged on the corresponding half groove, and plastic sealing material is used for plastic sealing.
[0072] The above description and the above embodiments are only used to illustrate the technical solutions of the application, rather than limit the application; although the application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and the modification or replacement does not make the essence of the corresponding technical solution deviate from the spirit and scope of the technical solutions of the embodiments of the application.
Claims
1. A flip-chip hermetic packaging method, characterized by, The application relates to a flip-chip airtight packaging method. A preset number of half grooves are etched on the top surface of a silicon-based adapter plate by using a dry etching method, the preset number is the number of chips to be packaged, each half groove contains a plurality of silicon columns corresponding to the chip function points or contact points of the corresponding chip; Solder is evaporated on the periphery of each half groove and the top end of each silicon column, and a ring-shaped gold layer is electroplated on the periphery of each chip to be packaged; Preset hot-pressing process parameters are set, each chip to be packaged is flip-chip mounted on the corresponding half groove by using a hot-pressing process, and plastic sealing material is used for plastic sealing.
2. The flip-chip hermetic packaging method of claim 1, wherein, The preset hot-pressing process parameters include temperature, the temperature peak of the temperature is higher than the melting point of the evaporated solder, the temperature rising rate of the temperature is 5-10 DEG C / s, and the holding time of the temperature ranges from 8s to 10s.
3. The flip-chip hermetic packaging method of claim 2, wherein, The preset hot-pressing process parameters include pressure, and the calculation formula of the pressure is: F = (1 N / mm 2 ~ 2 N / mm 2 )* S Wherein, F is the pressure, and S is the solder area of the evaporated solder.
4. The flip-chip hermetic packaging method of claim 1, wherein, The back surface of the silicon-based adapter plate is provided with a BGA pad; after the preset number of half grooves are etched on the top surface of the silicon-based adapter plate by using the dry etching method, the method further comprises: The position of each silicon column is found on the BGA pad, and a TSV hole is etched for each silicon column to realize the interconnection between the top surface and the back surface of the silicon-based adapter plate.
5. The flip-chip hermetic packaging method of claim 4, wherein, The material of the BGA pad is nickel gold; The TSV hole is filled with electroplated copper.
6. The flip-chip hermetic packaging method of claim 1, wherein, Before the solder is evaporated on the periphery of each half groove and the top end of each silicon column, the method further comprises: The evaporated solder is subjected to plasma cleaning.
7. The flip-chip hermetic packaging method of claim 1, wherein, Before the plastic sealing material is used for plastic sealing, the method further comprises: When there is a chip to be cooled, a heat dissipation cold plate is bonded to the back surface of the chip to be cooled by using bonding material to cool the chip to be cooled.
8. The flip-chip hermetic packaging method of claim 7, wherein, The bonding material is high-thermal-conductivity nano-silver glue, and the height of the plastic sealing material is consistent with the height of the heat dissipation cold plate.
9. The flip-chip hermetic packaging method of claim 1, wherein, The evaporated solder is Au80Sn20.
10. A packaged chip, comprising: The packaged chip is prepared by using the flip-chip airtight packaging method according to any one of claims 1 to 9.