Dielectric layer preparation method, semiconductor device preparation method and semiconductor device

Abstract

The invention discloses a dielectric layer preparation method, a semiconductor device preparation method and a semiconductor device, and relates to the technical field of semiconductor manufacturing. The dielectric layer preparation method comprises the following steps: depositing fluorosilicate glass on a metal layer of a wafer to form a first dielectric layer; depositing undoped silica glass on the first dielectric layer to form a second dielectric layer; and depositing a silicon-rich oxide on the second dielectric layer to form a third dielectric layer. Through the above technical means, high-energy ion bombardment and electric field breakdown are effectively resisted by using the compact structures and high dielectric strength of the undoped silica glass and the silicon-rich oxide, and the gate oxide breakdown risk caused by charge accumulation is reduced by using the pure insulator characteristic of the undoped silica glass and the weak conductivity of the silicon-rich oxide to evacuate charges. The problem that the performance and the yield of the semiconductor device are influenced by PID is obviously improved, and a favorable guarantee is provided for long-term normal work and prolonging of the service life of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a dielectric layer manufacturing method, a semiconductor device manufacturing method, and a semiconductor device. BACKGROUND

[0002] In the manufacturing process of a semiconductor integrated circuit chip, plasma is widely used in process steps such as dry etching, chemical vapor deposition, and sputtering. Although plasma processes are efficient and have high precision, the high-energy charged particles (ions, electrons) and strong electric field environment of plasma can cause the following problems: 1. The charged particles in the plasma can accumulate electric charges on the surface of the chip or the insulating layer (such as the gate oxide layer) to form a local high electric field. Once the electric field exceeds the breakdown strength of the material, the insulating layer will be broken down (such as the gate oxide layer breakdown), causing permanent damage; 2. Metal interconnection structures or conductors in the plasma environment can act as an "antenna" to collect and amplify electric charges, causing the gate oxide layer connected to these structures to bear excessive voltage stress. In small-size devices (such as nanoscale transistors), the gate oxide layer is extremely thin (a few nanometers), and is more likely to be broken down; 3. High-energy ions in the plasma directly bombard the surface of the chip, which can damage the crystal structure or introduce defects (such as silicon lattice damage), affecting the electrical properties of the device. These device damage or material damage caused by plasma processes are collectively referred to as Plasma Induced Damage (PID). PID can cause the performance of the chip to decrease (such as threshold voltage drift and increased leakage current caused by gate oxide layer damage), reduce reliability (accelerate device aging over time), and reduce yield (part of the chips are directly disabled due to damage during the manufacturing process). As an insulating material layer between two adjacent metal layers in a semiconductor device, the dielectric layer can prevent the upper layer of charges from transferring to the lower layer, thereby preventing the gate oxide layer from accumulating too much charge and causing damage to the gate oxide layer.

[0003] In the prior art, the preparation process of the dielectric layer includes first depositing a fluorosilicon glass material using a HDP (High Density Plasma) chemical vapor deposition process, then depositing a fluorosilicon glass material using a PE (Plasma Enhanced) chemical vapor deposition process, and finally depositing an undoped silicon glass to form a dielectric layer with a three-layer structure. However, after the semiconductor device is prepared, the failure rate of the semiconductor device is calculated through the PID test, and the failure rate is relatively high. Therefore, the existing dielectric layer preparation process cannot effectively improve the performance and yield of the semiconductor device. SUMMARY

[0004] The application provides a medium layer preparation method, a semiconductor device preparation method and a semiconductor device, which replace the fluorosilicon glass of the second layer with undoped silicon glass and replace the undoped silicon glass of the last layer with silicon-rich oxide, utilize the dense structure and high dielectric strength of the undoped silicon glass and the silicon-rich oxide to effectively resist high-energy ion bombardment and electric field breakdown, utilize the pure insulator property of the undoped silicon glass and the weak conductivity of the silicon-rich oxide to disperse charges and reduce the risk of gate oxide layer breakdown caused by charge accumulation, significantly improve the performance and yield of the semiconductor device, and provide favorable guarantee for long-term normal operation and service life of the device.

[0005] In a first aspect, the application provides a medium layer preparation method, comprising: depositing fluorosilicon glass on a metal layer of a wafer to form a first medium layer; depositing undoped silicon glass on the first medium layer to form a second medium layer; depositing silicon-rich oxide on the second medium layer to form a third medium layer.

[0006] Optionally, the step of depositing fluorosilicon glass on the metal layer of the wafer to form the first medium layer comprises: depositing fluorosilicon glass on the metal layer of the wafer by a high-density plasma chemical vapor deposition process to form the first medium layer.

[0007] Optionally, the step of depositing undoped silicon glass on the first medium layer to form the second medium layer comprises: depositing undoped silicon glass on the first medium layer by a plasma-enhanced chemical vapor deposition process to form the second medium layer.

[0008] Optionally, before the step of depositing silicon-rich oxide on the second medium layer to form the third medium layer, the method further comprises: polishing the second medium layer by a mechanical polishing process.

[0009] Optionally, the thickness of the first medium layer is 6000 Å, the thickness of the second medium layer is 9600 Å, and the thickness of the third medium layer is 2000 Å.

[0010] Optionally, before the step of depositing fluorosilicon glass on the metal layer of the wafer to form the first medium layer, the method further comprises: depositing silicon-rich oxide on the metal layer to form a metal sealing layer, and the thickness of the metal sealing layer is less than the thickness of the third medium layer.

[0011] Optionally, before the step of depositing silicon-rich oxide on the metal layer to form the metal sealing layer, the method further comprises: in the case where the metal layer is made of copper material, depositing tantalum nitride on the metal layer to form a first adhesion layer.

[0012] Optionally, after the third dielectric layer is formed by depositing silicon-rich oxide on the second dielectric layer, the method further comprises: In the case where the metal layer is made of copper, a second adhesion layer is formed by depositing tantalum nitride on the third dielectric layer.

[0013] In a third aspect, the present application provides a semiconductor device manufacturing method, which comprises the dielectric layer manufacturing method as described in the first aspect.

[0014] In a third aspect, the present application provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method as described in the second aspect.

[0015] In the present application, a first dielectric layer is formed by depositing fluorosilicate glass on the metal layer of the wafer, a second dielectric layer is formed by depositing undoped silicon glass on the first dielectric layer, and a third dielectric layer is formed by depositing silicon-rich oxide on the second dielectric layer. By the above technical means, three dielectric layers are formed above the metal layer, the third dielectric layer is located at the top of the dielectric layers and is made of silicon-rich oxide, the high-density amorphous structure of the silicon-rich oxide can effectively resist high-energy ion bombardment in the plasma, reduce physical damage of the third dielectric layer to the lower dielectric layer and the metal layer, and dissipate local charges by the weak conductivity of the silicon-rich oxide, so as to prevent excessive accumulation of charges and reduce the risk of gate oxide breakdown caused by high electric field. The second dielectric layer is located in the middle of the dielectric layers and is made of undoped silicon glass, the mechanical strength of the undoped silicon glass is lower than that of the silicon-rich oxide but higher than that of the fluorosilicate glass, which can effectively resist high-energy ion bombardment through the silicon-rich oxide, reduce physical damage of the second dielectric layer to the lower dielectric layer and the metal layer, the undoped silicon glass is a pure insulator, the charge trap density is low, and the charges are not easy to accumulate on the surface, thereby reducing the risk of gate oxide breakdown caused by high electric field. After the charges and high-energy ions are dispersed and protected by the second dielectric layer and the third dielectric layer, only a small part of them fall on the first dielectric layer, and even if the first dielectric layer is made of fluorosilicate glass with low mechanical strength and slightly high conductivity, it can withstand high-energy ion bombardment. Therefore, the optimized dielectric layer structure can resist high-energy ion bombardment and external electric field pressure, reduce the risk of gate oxide breakdown caused by charge accumulation, and significantly improve the performance and yield of the semiconductor device, thereby providing favorable guarantee for long-term normal operation and service life of the device. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a normal distribution diagram of failure rates of various structures in a conventional CMOS under different reference currents provided by an embodiment of the present application; Figure 2 is a flowchart of a dielectric layer manufacturing method provided by an embodiment of the present application; Figure 3is a structural schematic diagram of a wafer before a medium layer is deposited according to an embodiment of the present application; Figure 4 is a structural schematic diagram of a wafer after a first medium layer is formed according to an embodiment of the present application; Figure 5 is a structural schematic diagram of a wafer after a metal sealing layer and a first medium layer are formed according to an embodiment of the present application; Figure 6 is a structural schematic diagram of a wafer after a second medium layer is formed according to an embodiment of the present application; Figure 7 is a structural schematic diagram of a wafer after a third medium layer is formed according to an embodiment of the present application; Figure 8 is a normal distribution diagram of failure rates of various structures in an optimized CMOS under different reference currents according to an embodiment of the present application; Figure 9 is a structural schematic diagram of a wafer after a second metal layer is formed according to an embodiment of the present application; Figure 10 is a structural schematic diagram of a wafer after a metal sealing layer is formed above the second metal layer according to an embodiment of the present application; In the figure, 11, first metal layer; 12, first medium layer; 13, metal sealing layer; 14, second medium layer; 15, third medium layer; 16, second adhesive layer; 17, second metal layer; 18, first adhesive layer. DETAILED DESCRIPTION

[0017] In order to make the objectives, technical solutions and advantages of the present application clearer, the following further describes specific embodiments of the present application with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application. In addition, it should be noted that, for the convenience of description, only parts related to the present application are shown in the drawings and not all contents. Before discussing the example embodiments in more detail, it should be mentioned that some example embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations can be implemented in parallel, concurrently or simultaneously. In addition, the order of the operations can be rearranged. The process can be terminated when the operations are completed, but can also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0018] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a particular order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the objects before and after are in an "or" relationship.

[0019] In a more common existing implementation, the preparation process of the dielectric layer includes first depositing fluorosilicon glass material by using HDP (High Density Plasma) chemical vapor deposition process, then depositing fluorosilicon glass material by using PE (Plasma Enhanced) chemical vapor deposition process, and finally depositing undoped silicon glass to form a dielectric layer with a three-layer structure. When the above dielectric layer preparation process is applied to the preparation link of CMOS, after the metal layer of CMOS is deposited, the dielectric layer above the metal layer is made by using the above dielectric layer preparation process, then a metal layer is deposited, and after the last metal layer is deposited, the preparation of CMOS is completed. In the preparation of multiple CMOSs, PID testing can be performed on multiple CMOSs to obtain test results. When performing PID testing, the leakage current of CT, V1, V2, V3, V4 and Acc Via area of the device is mainly detected. When the current value of the leakage current intersects with the reference current by 20%, it is confirmed that the corresponding structure fails. Among them, CT is the contact hole between the first metal layer and the silicon substrate, V1 is the structure layer from the second metal layer to the first metal layer, V2 is the structure layer from the third metal layer to the second metal layer, V3 is the structure layer from the fourth metal layer to the third metal layer, V4 is the structure layer from the fifth metal layer to the fourth metal layer, and Acc Via area is the structure layer from the fifth metal layer to the first metal layer. Figure 1 is the normal distribution diagram of the failure rate of each structure in the conventional CMOS under different reference currents provided by the embodiment of the present application. Among them, PV18X_CT area_1x, PV18X_V1_1x, PV18X_V2_1x, PV18X_V3_1x, PV18X_V4_1x and PV18X_Acc Via area_1x respectively correspond to the normal distribution of the failure rate of CT, V1, V2, V3, V4 and Acc Via area. As Figure 1As shown, the failure rates of the Acc Via area exceed 5% under most of the set reference currents, which do not meet the PID test requirements. Table 1 is a result table of the PID test of the conventional CMOS provided by the embodiment of the present application.

[0020]

[0021] Table 1 The left side of Table 1 is the structure of the CMOS, and the right side of Table 1 is the failure rate of the same row structure when the reference current is 0.1 μA. As shown in Table 1, the failure rates of V4 and the Acc Via area are both greater than 5%, which do not meet the PID test requirements. Therefore, from Table 1 and Figure 1 It can be seen that the semiconductor device prepared by using the above-mentioned medium layer preparation method will cause the leakage current to increase due to the PID, and once the leakage current exceeds 20% of the reference current, the semiconductor device will fail. The failure rate of the Acc Via area of the semiconductor device is as high as 29% after the PID test, which seriously affects the yield and preparation efficiency of the semiconductor device, and the semiconductor device that passes the test cannot guarantee its performance. Therefore, the existing medium layer preparation process cannot effectively improve the performance and yield of the semiconductor device.

[0022] To solve the above-mentioned problems, the embodiment provides a medium layer preparation method, a semiconductor device preparation method and a semiconductor device, so as to replace the fluorosilicon glass of the second layer with the undoped silicon glass and replace the undoped silicon glass of the last layer with the silicon-rich oxide, use the dense structure and high dielectric strength of the undoped silicon glass and the silicon-rich oxide to effectively resist high-energy ion bombardment and electric field breakdown, use the pure insulator property of the undoped silicon glass and the weak conductivity of the silicon-rich oxide to disperse charges to reduce the risk of gate oxide layer breakdown caused by charge accumulation, improve the performance and yield of the semiconductor device, and provide favorable guarantee for long-term normal work and life of the device.

[0023] Figure 2 A flowchart of a medium layer preparation method provided by the embodiment of the present application is given. As shown in the figure, the medium layer preparation method comprises the following steps. Figure 2 S110, depositing fluorosilicon glass on the metal layer of the wafer to form a first medium layer 12.

[0024] The metal layer can be any metal layer in the semiconductor device except the last metal layer. The embodiment takes the preparation of the medium layer on the first metal layer 11 as an example for description. For example, Figure 3 is a structure schematic diagram of the wafer before depositing the medium layer provided by the embodiment of the present application. As shown in the figure, Figure 3 ​As shown in the process of preparing CMOS (Complementary Metal Oxide Semiconductor) on a wafer, a P-type substrate and an N-type substrate are provided, N-type impurities are injected in the middle of the P-type substrate to form an N-type well (N-Well), and P-type impurities are injected in the N-type P-type substrate to form a P-type well (P-Well). Then, high-concentration P-type impurities are injected on both sides of the P-type substrate to form P+ diffusion layers, which can serve as source and drain and form PN junctions with the N-Well in the middle. High-concentration N-type impurities are injected on both sides of the N-type P-type substrate to form N+ diffusion layers, which can serve as source and drain and form PN junctions with the P-Well in the middle. Then, a gate oxide layer and a polysilicon layer are formed above the P-Well and the N-Well. A layer of silicon dioxide is attached to the polysilicon sidewall as a sidewall insulating layer, and then cobalt metal is deposited above the source, drain and gate. After the cobalt metal reacts with the polysilicon, cobalt silicide is formed. A pre-metal dielectric layer (PMD) is deposited above the wafer, a contact hole is formed in the pre-metal dielectric layer, and a first metal layer 11 is deposited on the pre-metal dielectric layer. The first metal layer 11 is connected to the gate or drain through the contact hole.

[0025] Figure 4 Figure 1 is a schematic diagram of a wafer after a first dielectric layer 12 is formed according to an embodiment of the present application. As shown in the figure, a fluorine-silicon glass (FSG) is deposited on the first metal layer 11, covering the first metal layer 11 and the area not covered by the first metal layer 11. The fluorine-silicon glass above and around the first metal layer 11 forms the first dielectric layer 12. Due to the deposition of fluorine-silicon glass in the area not covered by the first metal layer 11, the height of the fluorine-silicon glass in this area is lower than that in the other areas, resulting in a high-low undulating surface of the first dielectric layer 12. Figure 4

[0026] Optionally, the fluorine-silicon glass can be deposited on the metal layer of the wafer to form the first dielectric layer 12 by a high-density plasma chemical vapor deposition process. High-density plasma chemical vapor deposition (HDP-CVD) is an advanced semiconductor manufacturing process that can be used for gap filling. The fluorine-silicon glass is precisely deposited in the gap formed by the first metal layer 11, so that the fluorine-silicon glass completely wraps the first metal layer 11, improving the preparation accuracy of the first dielectric layer 12.

[0027] ​In one embodiment, a silicon-rich oxide can be deposited on the metal layer to form a metal sealing layer 13 before the first dielectric layer 12 is formed, and the thickness of the metal sealing layer 13 is less than the thickness of the third dielectric layer 15. For example, the metal layer is prone to be oxidized and reduced by air when exposed to air, and thus corroded. To prevent the metal layer from being exposed to air, a silicon-rich oxide can be deposited on the metal layer to form a thin metal sealing layer 13 before the dielectric layer is formed, and the thickness of the metal sealing layer 13 can be 300 angstroms. The metal sealing layer 13 can reduce the PID damage, but its main function is to prevent the metal layer from being corroded by air.

[0028] In this embodiment, Figure 5 is a schematic diagram of the structure of a wafer after the metal sealing layer 13 and the first dielectric layer 12 are formed according to an embodiment of the present application. As shown in Figure 5 , after the metal sealing layer 13 is formed, fluorine silicon glass can be deposited on the metal sealing layer 13 to form the first dielectric layer 12.

[0029] S120, undoped silicon glass is deposited on the first dielectric layer 12 to form the second dielectric layer 14.

[0030] For example, Figure 6 is a schematic diagram of the structure of a wafer after the second dielectric layer 14 is formed according to an embodiment of the present application. As shown in Figure 6 , undoped glass (USG) is deposited on the first dielectric layer 12, and the undoped glass is deposited on the raised areas and the recessed areas of the first dielectric layer 12 to form the second dielectric layer 14 that completely covers the first dielectric layer 12.

[0031] To ensure the flatness of the upper surface of the second dielectric layer 14, the second dielectric layer 14 is ground flat after the second dielectric layer 14 is formed, so that the third dielectric layer 15 can be deposited subsequently.

[0032] Optionally, the undoped silicon glass is deposited on the first dielectric layer 12 to form the second dielectric layer 14 by a plasma-enhanced chemical vapor deposition process. The plasma-enhanced chemical vapor deposition process (PE-CVD) is a thin film deposition process, and the plasma-enhanced chemical vapor deposition process can be performed at a relatively low temperature. The thermal stability of the fluorine silicon glass of the first dielectric layer 12 is poor, and the fluorine atoms may escape at a high temperature, causing material degradation (e.g., increased porosity and k value drift). Therefore, to adapt to the temperature-sensitive substrate (the first dielectric layer 12), the plasma-enhanced chemical vapor deposition process is selected to deposit the undoped silicon glass to form the second dielectric layer 14.

[0033] S130, silicon-rich oxide is deposited on the second dielectric layer 14 to form the third dielectric layer 15.

[0034] Exemplary, Figure 7 is a structure schematic diagram of wafer after forming the third dielectric layer 15 provided by the embodiment of the present application. As shown in the figure, the second dielectric layer 14 is covered by the third dielectric layer 15 formed by depositing silicon-rich oxide (SRO) on the smooth upper surface of the second dielectric layer 14. The first dielectric layer 12, the second dielectric layer 14 and the third dielectric layer 15 can be used as the interlayer dielectric layer between metal layers to effectively reduce the capacitive coupling between metal lines. Figure 7 As described above, the second dielectric layer 14 is covered by the third dielectric layer 15 formed by depositing silicon-rich oxide (SRO) on the smooth upper surface of the second dielectric layer 14. The first dielectric layer 12, the second dielectric layer 14 and the third dielectric layer 15 can be used as the interlayer dielectric layer between metal layers to effectively reduce the capacitive coupling between metal lines.

[0035] Table 2 is a comparison table of PID resistance of fluorosilicate glass, undoped silicon glass and silicon-rich oxide provided by the embodiment of the present application.

[0036]

[0037] Table 2 As shown in Table 2, from the perspective of material density and mechanical strength, FSG has a low-k structure due to the doping of fluorine (F) atoms, and there are more pores inside, resulting in loose material and low mechanical strength, which is easy to cause defects under plasma bombardment. USG is undoped silicon dioxide, which has a dense structure and high mechanical strength, and can effectively resist high-energy ion bombardment in plasma and reduce physical damage (such as microcracks or material peeling). The silicon content of SRO is higher than that of traditional silicon dioxide (USG), forming a more dense amorphous structure, which can effectively resist high-energy ion bombardment in plasma and reduce physical damage (such as surface roughening or microcracks).

[0038] From the perspective of charge accumulation and electrical conductivity, the fluorine doping of FSG can introduce additional charge traps, and the electrical conductivity of low-k materials is slightly higher, which is more likely to accumulate charges in the plasma environment, aggravating the antenna effect, resulting in overvoltage damage to the gate oxide layer connected to the interconnection line. As a pure insulator, USG has stable insulation performance and low charge trap density, and charges are not easy to accumulate on the surface or interface in the plasma process, reducing the risk of gate oxide layer breakdown caused by high electric field. The presence of excess silicon in SRO introduces weak electrical conductivity (such as through silicon nanoclusters or defect states), which helps to dissipate local charges and reduce the risk of gate oxide layer breakdown caused by surface charge accumulation. In a high-temperature or plasma environment, fluorine atoms in FSG may escape, leading to material degradation (such as increased porosity, k value drift), and even reacting with metal interconnection materials, aggravating the damage.

[0039] From the perspective of thermal and chemical stability, fluorine atoms in FSG may escape at high temperatures or in plasma environments, leading to material degradation (e.g., increased porosity, k value drift), and even reactions with metal interconnect materials, exacerbating damage. USG has excellent thermal stability and is less likely to decompose or release gas during high-temperature processes (e.g., annealing, etching), maintaining the integrity of the insulating layer. The deposition of SRO requires precise control of the silicon-oxygen ratio, with a relatively narrow process window, which may increase manufacturing costs and difficulty.

[0040] From the perspective of process compatibility and interface characteristics, the low-k characteristics of FSG require more complex process control (e.g., low-power plasma), but its porous structure may allow plasma to penetrate to the underlying structure, increasing the risk of damage to sensitive devices (e.g., gates). USG, as a mature process material, is more compatible with subsequent metal deposition, etching, and other steps, with a wide process window, allowing optimization of plasma parameters (e.g., power, frequency) to reduce damage. SRO may have poor adhesion to certain metals, requiring the additional introduction of an adhesion layer, increasing process complexity.

[0041] From the perspective of electric field breakdown resistance, FSG has a lower dielectric strength (about 5-8 MV / cm) due to its porous structure, making it prone to breakdown due to local electric field concentration during plasma processes, leading to permanent damage. USG has a higher dielectric strength (about 10 MV / cm) and can withstand higher electric fields without being broken down. SRO has a very high dielectric strength (about 12-15 MV / cm) and can withstand very high electric fields without being broken down.

[0042] Based on the characteristics of the FSG, USG and SRO, it can be summarized that the FSG is easy to be damaged in the PID sensitive area due to its porosity, fluorine doping side effects and low dielectric strength; the USG improves the anti-plasma damage ability in an all-round way due to its dense structure, high mechanical strength, low charge trap density and high thermal stability; the SRO can more effectively inhibit charge accumulation and physical damage due to its high density, weak conductivity and excellent thermal stability. Based on this, the third dielectric layer 15 is prepared by SRO in the embodiment, the high-density amorphous structure of SRO is used to effectively resist the high-energy ion bombardment in the plasma, reduce the physical damage of itself and the underlying dielectric layer and metal layer, and the weak conductivity of SRO is used to dissipate local charges, prevent excessive charge accumulation and reduce the risk of gate oxide layer breakdown caused by high electric field. The second dielectric layer 14 is prepared by USG, the second dielectric layer 14 is in the middle of the dielectric layer, although its mechanical strength is lower than that of SRO, it can effectively resist the high-energy ion bombardment through the silicon-rich oxide, reduce the physical damage of itself and the underlying dielectric layer and metal layer, the charge trap density of the second dielectric layer 14 is relatively low, and the charge is not easy to accumulate on the surface, thereby reducing the risk of gate oxide layer breakdown caused by high electric field. The first dielectric layer 12 is prepared by FSG, after the charge and high-energy ions are dispersed and protected by the second dielectric layer 14 and the third dielectric layer 15, only a small part of them fall on the first dielectric layer 12, even if the first dielectric layer 12 adopts FSG with low mechanical strength and slightly high conductivity, it can withstand high-energy ion bombardment and external electric field pressure, and reduce the risk of gate oxide layer breakdown caused by charge accumulation. After the charge is dispersed through the dielectric layers, a small electric field is applied to the gate oxide layer, which effectively reduces the risk of gate oxide layer breakdown, the dielectric layer above resists the high-energy ion bombardment, effectively reduces the damage caused by PID to the semiconductor device, improves the performance and yield of the semiconductor device, and provides favorable protection for the long-term normal work and life of the device.

[0043] Optionally, the thickness of the first dielectric layer 12 is 6000 Å, the thickness of the second dielectric layer 14 is 9600 Å, and the thickness of the third dielectric layer 15 is 2000 Å. As can be seen from the above, the process complexity of SRO, FSG and USG is from high to low, so the thickness of the third dielectric layer 15 is the lowest, so as to effectively resist high-energy ion bombardment and disperse charges while reducing process complexity, the thickness of the second dielectric layer 14 is the highest, so as to prepare a relatively thick second dielectric layer 14 with the simplest preparation process, so as to effectively improve the reliability of the dielectric layer while not increasing the process complexity too much, and the thickness of the first dielectric layer 12 is medium, and the process complexity is medium, and only a thickness that can play a basic protection role is prepared. The thicknesses of the first dielectric layer 12, the second dielectric layer 14 and the third dielectric layer 15 are set after measuring the process complexity and performance of SRO, FSG and USG, so as to effectively improve the performance and reliability of the semiconductor device while not increasing the process complexity too much.

[0044] In the preparation of CMOS, the leakage current of CT, V1, V2, V3, V4 and cc Via area of CMOS is also detected respectively, so as to test the PID of CMOS. Figure 8 is the normal distribution diagram of the failure rate of each structure of the optimized CMOS under different reference currents provided by the embodiment of the application. PV18X_CT area_1x, PV18X_V1_1x, PV18X_V2_1x, PV18X_V3_1x, PV18X_V4_1x and PV18X_Cumulativa Via_3_10x correspond to the normal distribution of the failure rate of CT, V1, V2, V3, V4 and Acc Via area respectively. Figure 1 and Figure 8 After the improvement of the dielectric layer, the failure rate of V4 and Acc Via area is significantly reduced under the same reference current, the anti-PID capability of the optimized CMOS is significantly improved, thereby improving the reliability, performance and yield of the CMOS. More obviously, Table 3 is the result table of the PID test of the optimized CMOS provided by the embodiment of the application.

[0045]

[0046] Table 3 The right side of Table 3 is the failure rate of the structure in the same row when the reference current is 0.1 μA. As shown in Table 3, the failure rate of CT, V1, V2, V3, V4 and Acc Via area is equal to 0%, that is, no CMOS failure is found due to PID damage, and the PID test requirement is passed. After the optimization of the dielectric layer, each layer of the CMOS can pass the PID test, thereby effectively improving the yield and preparation efficiency of the CMOS.

[0047] After the formation of the third dielectric layer 15, a metal material can be deposited above the third dielectric layer 15 to form a metal layer. Since the adhesion of SRO to copper is poor, in order to avoid the interface separation of the third dielectric layer 15 and the metal layer above, in the case that the metal layer adopts copper material, tantalum nitride is deposited on the third dielectric layer 15 to form a second adhesion layer 16. Then, copper material is deposited above the second adhesion layer 16 to form a second metal layer 17. In the case that RSO is deposited above the metal layer to serve as a metal sealing layer 13, if the metal layer adopts copper material, the interface separation between the metal sealing layer 13 and the metal layer below will also occur. In this regard, in the case that the metal layer adopts copper material, tantalum nitride is deposited on the metal layer to form a first adhesion layer 18. Figure 9 is the structure schematic diagram of the wafer after the formation of the second metal layer provided by the embodiment of the application. As Figure 9As shown, the third dielectric layer 15 is formed with a second adhesive layer 16, and the second adhesive layer 16 is formed with a second metal layer 17. After the copper material is deposited on the second adhesive layer 16 to form the second metal layer 17, the tantalum nitride is deposited on the second metal layer 17 to form the first adhesive layer 18.

[0048] Figure 10 is a schematic diagram of the structure of the wafer after the metal sealing layer is formed on the second metal layer. As shown, after the copper material is deposited on the second adhesive layer 16 to form the second metal layer 17, the tantalum nitride is deposited on the second metal layer 17 to form the first adhesive layer 18, and then the RSO is deposited on the first adhesive layer 18 to form the metal sealing layer 13 of the second metal layer 17. After that, the first dielectric layer 12, the second dielectric layer 14 and the third dielectric layer 15 can be formed on the metal sealing layer 13 layer by layer to serve as the interlayer dielectric layer between the second metal layer 17 and the third metal layer. Figure 10

[0049] It should be noted that the first metal layer 11 is also formed with a first adhesive layer 18 to adhere the first metal layer to the metal sealing layer 13, but Figure 10 The first adhesive layer 18 on the first metal layer 11 is not shown.

[0050] After the last metal layer is formed on the last interlayer dielectric layer, the preparation of the semiconductor device is completed. Since the first dielectric layer 12, the second dielectric layer 14 and the third dielectric layer 15 are arranged between two adjacent metal layers, the second dielectric layer 14 and the third dielectric layer 15 can effectively block the high-energy ion bombardment from the upper metal layer and disperse the charge of the upper metal layer, preventing the accumulated charge of the multi-layer metal layer from forming a high electric field on the gate oxide layer, reducing the risk of the gate oxide layer being broken down by a high electric field, and effectively improving the yield and performance of the semiconductor device.

[0051] On the basis of the above-mentioned embodiments, the semiconductor device preparation method provided by the embodiments of the present application comprises the dielectric layer preparation method described in the above-mentioned embodiments. For example, the semiconductor device preparation method comprises preparing a structure before the first layer interlayer dielectric layer is prepared through the substrate preparation process and the metal layer preparation process. The prepared structure can refer to Figure 3 After that, the first dielectric layer 12, the second dielectric layer 14 and the third dielectric layer 15 are sequentially deposited on the first metal layer 11 based on the dielectric layer preparation method provided in the above-mentioned embodiments to form the first layer interlayer dielectric layer, and the second metal layer 17 is deposited on the first layer interlayer dielectric layer. Then, the first dielectric layer 12, the second dielectric layer 14 and the third dielectric layer 15 are sequentially deposited on the second metal layer 17 based on the dielectric layer preparation method provided in the above-mentioned embodiments to form the second layer interlayer dielectric layer, and so on. After the last metal layer is deposited on the last layer interlayer dielectric layer, the preparation of the semiconductor device is completed.​

[0052] On the basis of the above-mentioned embodiments, the semiconductor device is prepared by using the semiconductor device preparation method described in the above-mentioned embodiments. Referring to Figure 9 or Figure 10 The first dielectric layer 12, the second dielectric layer 14, and the third dielectric layer 15 are sequentially stacked between the two adjacent metal layers in the semiconductor device. Since the first dielectric layer 12, the second dielectric layer 14, and the third dielectric layer 15 are arranged between the two adjacent metal layers, the second dielectric layer 14 and the third dielectric layer 15 can effectively block the high-energy ion bombardment from the upper metal layer and dissipate the charge of the upper metal layer, prevent the high electric field formed by the accumulated charge of the multi-layer metal layer on the gate oxide layer, and reduce the risk of breakdown of the gate oxide layer caused by the high electric field, thereby effectively improving the yield and performance of the semiconductor device.

[0053] In summary, the dielectric layer preparation method, the semiconductor device preparation method, and the semiconductor device provided in the embodiments of the present application can form three layers of dielectric layers above the metal layer, the third dielectric layer 15 is located at the top of the dielectric layer and is made of silicon-rich oxide, which has a high-density amorphous structure to effectively resist high-energy ion bombardment in the plasma, reduce physical damage to the lower dielectric layer and metal layer, and dissipate local charge by using the weak conductivity of the silicon-rich oxide to prevent excessive accumulation of charge and reduce the risk of breakdown of the gate oxide layer caused by a high electric field. The second dielectric layer 14 is located in the middle of the dielectric layer and is made of undoped silicon glass, which has a lower mechanical strength than silicon-rich oxide but a higher mechanical strength than fluorosilicon glass, which can effectively resist high-energy ion bombardment through the silicon-rich oxide, reduce physical damage to the lower dielectric layer and metal layer, and the undoped silicon glass is a pure insulator with a low charge trap density, so the charge is not easy to accumulate on the surface, thereby reducing the risk of breakdown of the gate oxide layer caused by a high electric field. After the charge and high-energy ions are dissipated and protected by the second dielectric layer 14 and the third dielectric layer 15, only a small part of them fall on the first dielectric layer 12, which can withstand high-energy ion bombardment even if the first dielectric layer 12 is made of fluorosilicon glass with low mechanical strength and slightly higher conductivity. Therefore, the optimized dielectric layer structure can resist high-energy ion bombardment and external electric field pressure, reduce the risk of breakdown of the gate oxide layer caused by charge accumulation, and significantly improve the performance and yield of the semiconductor device, thereby providing a favorable guarantee for the long-term normal operation and service life of the device.

[0054] The above merely describes the preferred embodiments of the present application and the technical principles applied. The present application is not limited to the specific embodiments herein, and various obvious changes, modifications and replacements made by those skilled in the art without departing from the scope of the present application shall not be excluded. Therefore, although the present application is described in more detail through the above embodiments, the present application is not limited to the above embodiments, and more other equivalent embodiments can be included without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

Claims

1. A method for preparing a dielectric layer, characterized in that, include: Fluorosilicone glass is deposited on the metal layer of the wafer to form the first dielectric layer; An undoped silicon glass is deposited on the first dielectric layer to form a second dielectric layer; A silicon-rich oxide layer is deposited on the second dielectric layer to form a third dielectric layer.

2. The method for preparing a dielectric layer according to claim 1, characterized in that, The deposition of fluorosilicone glass on the metal layer of the wafer to form a first dielectric layer includes: Fluorosilicone glass is deposited on the metal layer of a wafer to form the first dielectric layer using a high-density plasma chemical vapor deposition process.

3. The method for preparing a dielectric layer according to claim 1, characterized in that, The step of depositing undoped silicon glass on the first dielectric layer to form the second dielectric layer includes: An undoped silicon glass is deposited on the first dielectric layer using a plasma-enhanced chemical vapor deposition process to form a second dielectric layer.

4. The method for preparing a dielectric layer according to claim 1, characterized in that, Before depositing silicon-rich oxide on the second dielectric layer to form the third dielectric layer, the process further includes: The second dielectric layer is smoothed by a mechanical grinding process.

5. The method for preparing a dielectric layer according to claim 1, characterized in that, The thickness of the first dielectric layer is 6000 Å, the thickness of the second dielectric layer is 9600 Å, and the thickness of the third dielectric layer is 2000 Å.

6. The method for preparing a dielectric layer according to claim 1, characterized in that, Before depositing fluorosilicone glass on the metal layer of the wafer to form the first dielectric layer, the process also includes: A silicon-rich oxide is deposited on the metal layer to form a metal sealing layer, the thickness of which is less than the thickness of the third dielectric layer.

7. The method for preparing a dielectric layer according to claim 6, characterized in that, Prior to depositing silicon-rich oxide on the metal layer to form a metal sealing layer, the method further includes: When the metal layer is made of copper, tantalum nitride is deposited on the metal layer to form a first adhesion layer.

8. The method for preparing a dielectric layer according to claim 1, characterized in that, After depositing silicon-rich oxide on the second dielectric layer to form the third dielectric layer, the process further includes: When the metal layer is made of copper, tantalum nitride is deposited on the third dielectric layer to form a second adhesion layer.

9. A method for fabricating a semiconductor device, characterized in that, Includes the method for preparing the dielectric layer as described in any one of claims 1-8.

10. A semiconductor device, characterized in that, It was prepared using the semiconductor device fabrication method as described in claim 9.

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