Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided. For example, a semiconductor device may include: a substrate; an interposer at least partially on a first surface of the substrate facing the first direction; a first semiconductor chip on a first surface of the interposer facing the first direction; a second semiconductor chip at least partially on the first surface of the interposer, the second semiconductor chip being spaced apart from the first semiconductor chip in a second direction crossing the first direction; a mixed diamond thermal interposer at least partially on a first surface of the first semiconductor chip facing the first direction or at least partially on a first surface of the second semiconductor chip facing the first direction, where the mixed diamond thermal interposer includes diamond particles within a metal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure can relate to semiconductor devices, and more particularly to semiconductor devices including, for example, hybrid diamond thermal interposers. BACKGROUND

[0002] There is an industry demand for semiconductor devices having a high number of inputs and outputs (I / O), high bandwidth, low latency, high power efficiency, small form factor (footprint), and the like. Due to the large amount of power required for integration of logic dies and high bandwidth memory (HBM) packages, there is an urgent need for thermal performance improvement for high performance advanced packages.

[0003] By improving the thermal performance of semiconductor devices (e.g., high performance devices such as high performance advanced packages), the semiconductor devices can be effectively cooled and the lifetime of the products can be increased. SUMMARY

[0004] Embodiments of the present disclosure can address the above-mentioned problems and / or other problems.

[0005] According to some example embodiments of the present disclosure, semiconductor devices (e.g., semiconductor packages) having improved thermal performance can be provided.

[0006] According to some example embodiments of the present disclosure, semiconductor devices (e.g., semiconductor packages) including hybrid diamond thermal interposers can be provided for high performance applications (e.g., networking, artificial intelligence (AI), high performance computing (HPC), mobile, wearable, and the like) and can be configured as advanced packages.

[0007] According to some example embodiments of the present disclosure, semiconductor devices (e.g., semiconductor packages) having improved thermal performance without sacrificing mechanical integrity of the semiconductor devices can be provided.

[0008] According to some example embodiments of the present disclosure, hybrid diamond thermal interposers integrated with thermal interface materials (TIMs) having high thermal conductivity can be provided, which can significantly improve thermal performance while enabling semiconductor devices (e.g., semiconductor packages) to have a high level of mechanical integrity (e.g., during thermal cycling).

[0009] According to some example embodiments of the present disclosure, semiconductor devices requiring and having high thermal performance, such as, for example, system in package (SIP), flip chip packages, advanced wafer and panel level packages, and other high performance packages can be provided.

[0010] According to some example embodiments of the present disclosure, a semiconductor device can include a substrate; an interposer at least partially on a first surface of the substrate facing a first direction; a first semiconductor chip at least partially on a first surface of the interposer facing the first direction; a second semiconductor chip at least partially on the first surface of the interposer, the second semiconductor chip spaced apart from the first semiconductor chip in a second direction crossing the first direction; and a hybrid diamond thermal interposer at least partially on a first surface of the first semiconductor chip facing the first direction or at least partially on a first surface of the second semiconductor chip facing the first direction, wherein the hybrid diamond thermal interposer includes diamond particles within a matrix.

[0011] According to some example embodiments of the present disclosure, a semiconductor device can include an interposer; a first semiconductor chip at least partially on a first surface of the interposer facing a first direction, wherein the first semiconductor chip is a logic chip; a second semiconductor chip at least partially on the first surface of the interposer, the second semiconductor chip spaced apart from the first semiconductor chip in a second direction crossing the first direction, wherein the second semiconductor chip includes a high bandwidth memory (HBM); and a hybrid diamond thermal interposer at least partially on a first surface of the first semiconductor chip facing the first direction, wherein the hybrid diamond thermal interposer includes diamond particles within a metal.

[0012] According to some example embodiments of the present disclosure, a method of manufacturing a semiconductor device can include providing an intermediate semiconductor device including a substrate; an interposer at least partially on a first surface of the substrate facing a first direction; a first semiconductor chip at least partially on a first surface of the interposer facing the first direction; and a second semiconductor chip at least partially on the first surface of the interposer, the second semiconductor chip spaced apart from the first semiconductor chip in a second direction crossing the first direction. The method can further include providing a hybrid diamond thermal interposer at least partially on a first surface of the first semiconductor chip facing the first direction or at least partially on a first surface of the second semiconductor chip facing the first direction, wherein the hybrid diamond thermal interposer includes diamond particles within a metal. BRIEF DESCRIPTION OF DRAWINGS

[0013] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, and

[0014] Figure 1 shows a schematic enlarged cross-sectional view of a hybrid diamond thermal interposer according to an example embodiment of the present disclosure;

[0015] Figure 2Aschematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0016] Figure 2B schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure; Figure 2A schematic enlarged view of part A of FIG. 1;

[0017] Figure 3 schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0018] Figure 4 schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0019] Figure 5 schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0020] Figure 6A schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0021] Figure 6B schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0022] Figure 7 schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0023] Figure 8A schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0024] Figure 8B schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0025] Figure 9 schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0026] Figure 10 schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0027] Figure 11 schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0028] Figure 12 flowchart of a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure;

[0029] Figure 13 schematic cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure; Figure 12an intermediate semiconductor device formed in operations of a method of

[0030] Figure 14 shows a semiconductor device according to an example embodiment of the present disclosure. Figure 12 an intermediate semiconductor device formed in operations of a method of

[0031] Figure 15 shows a semiconductor device according to an example embodiment of the present disclosure. Figure 12 an intermediate semiconductor device formed in operations of a method of

[0032] Figure 16 shows a semiconductor device according to an example embodiment of the present disclosure. Figure 12 an intermediate semiconductor device formed in operations of a method of

[0033] Figure 17 shows a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The embodiments of the present disclosure described herein are example embodiments, and thus the present disclosure is not limited thereto and can be implemented in various other forms. Each of the embodiments provided in the following description does not exclude one or more features of another embodiment provided herein or not provided herein but consistent with the present disclosure. For example, even if the content described in a particular example embodiment is not described in a different example embodiment, the content can be understood as being related or combined with the different example embodiment, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of principles, aspects, examples, and embodiments of the present disclosure are intended to encompass structural and functional equivalents. In addition, these equivalents should be understood as not only including currently known equivalents but also including equivalents to be developed in the future, that is, all means that perform the same function regardless of their structure.

[0035] It will be understood that when an element, component, layer, pattern, structure, region, or the like (hereinafter referred to as "element") of a semiconductor device (or semiconductor package) is referred to as being "on", "connected to", or "coupled to" another element of the semiconductor device, it can be directly on, directly connected to, or directly coupled to the other element, or an intervening element can exist. In contrast, when an element of a semiconductor device is referred to as being "directly on", "directly connected to", or "directly coupled to" another element of the semiconductor device, there is no intervening element. Throughout the present disclosure, the same reference numerals refer to the same elements.

[0036] For ease of description, spatially relative terms such as "up", "over", "above", "upward", "down", "below", "lower", "left", "right", "downward", "upward", "center", "intermediate", etc., can be used herein for the purpose of describing the orientation of one element relative to another element(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the semiconductor device in use or operation in addition to the orientations depicted in the figures. For example, if a semiconductor device in the figures is turned over, elements described as being "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the term "below" can encompass both an orientation of above and below. The semiconductor device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As another example, elements described as "left" and "right" can be "right" and "left" when the device or structure including the elements is turned over. Similarly, the terms "lower" and "upper" can be used herein to describe elements related to the vertical orientation of the aforementioned or other elements unless explicitly stated otherwise. As such, the terms "lower" and "upper" can be used herein interchangeably with the terms "first" and "second" to describe one element from another in the same context in which the aforementioned terms are used unless explicitly stated otherwise.

[0037] It will be understood that, although the terms "first", "second", "third", "fourth", "fifth", "sixth" etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the scope of the present disclosure.

[0038] As used herein, such as the expression "at least one of", when preceding a list of elements, modifies the entire list of elements and does not modify the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. As used herein, the term "same" or "equal" when comparing dimensions of two or more elements can encompass dimensions that are "substantially the same" or "substantially equal".

[0039] When a component is described as "on" another component, it can be "partly on" or "fully on" the other component. That is, the component can be "at least partially on" the other component.

[0040] It will also be understood that, when a method of manufacturing a device or structure is described, unless otherwise indicated herein, it can include additional steps or operations that are not expressly disclosed in the specification. For example, steps or operations that are well known in the art or otherwise not necessary for the understanding of the subject matter can not be described in detail.

[0041] Many of the example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments (and intermediate structures) of the example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the disclosure. Furthermore, the figures can not be drawn to scale, and the dimensions of the layers and regions can be exaggerated or minimised for the sake of clarity and illustration.

[0042] For the sake of brevity, conventional elements, structures, or layers (including connection pads, adhesive layers, isolation layers, barrier metal patterns, seed layers, etc.) included in semiconductor packages can or can not be described in detail herein. For example, when these structural elements are irrelevant to certain features of embodiments, descriptions of certain connection pads of semiconductor chips connected to solder balls or bumps in semiconductor packages can be omitted herein. Also, when materials forming well-known structural elements are irrelevant to certain features of embodiments, descriptions of these materials can be omitted herein. Herein, the term "connected" between two structures or elements can refer to an electrical connection between them. For example, a connection between semiconductor chips, semiconductor packages, and / or semiconductor devices can refer to an electrical connection of the respective two or more elements to each other. The terms "coupled" and "connected" can have the same meaning and can be used interchangeably herein. Also, the term "isolated" between two structures or elements refers to an electrical insulation or electrical separation between them. For example, wire patterns being isolated from each other can mean that the wire patterns are not electrically connected to each other.

[0043] In the following, reference is made to Figures 1 to 17 Various non-limiting example embodiments of the disclosure are described.

[0044] The use of hybrid diamond thermal interposers integrated with thermal interface materials (TIMs) having high thermal conductivity can significantly improve thermal performance without sacrificing the mechanical integrity of the package. For example, reference is made below to Figure 1 A hybrid diamond thermal interposer 90 is described.

[0045] Figure 1A schematic enlarged cross-sectional view showing a hybrid diamond thermal interlayer 90 is shown in accordance with an example embodiment of the present disclosure.

[0046] Referring to Figure 1 A hybrid diamond thermal interlayer 90 can be provided, which can be a thermal interlayer including a hybrid diamond structure. The hybrid diamond thermal interlayer 90 can include a hybrid diamond layer 92 and an outer layer 96.

[0047] The hybrid diamond layer 92 can include a diamond skeleton 93 and a metal matrix 95 (also referred to as metal) within and around the diamond skeleton 93. The diamond skeleton 93 can include diamond particles 94 (also referred to as diamond filler) within the metal matrix 95. The metal matrix 95 can be within the diamond skeleton 93 so as to surround the diamond particles 94. In accordance with some example embodiments of the present disclosure, the metal matrix 95 can include or consist of at least one metal such as, for example, silver (Ag), copper (Cu), and the like.

[0048] The outer layer 96 can surround at least a portion of the hybrid diamond layer 92. For example, the outer layer 96 can be on one or more (e.g., some or all) of a top surface, a bottom surface, and side surfaces (e.g., four side surfaces) of the hybrid diamond layer 92. For example, the outer layer 96 can be plated onto one or more (e.g., some or all) of a top surface, a bottom surface, and side surfaces (e.g., four side surfaces) of the hybrid diamond layer 92.

[0049] The outer layer 96 can include, for example, a first outer layer 97 and a second outer layer 98. The first outer layer 97 can be directly on one or more (e.g., some or all) of a top surface, a bottom surface, and side surfaces (e.g., four side surfaces) of the hybrid diamond layer 92 so as to surround at least a portion of the hybrid diamond layer 92. The second outer layer 98 can also be on one or more (e.g., some or all) of a top surface, a bottom surface, and side surfaces (e.g., four side surfaces) of the hybrid diamond layer 92 so as to surround at least a portion of the hybrid diamond layer 92. For example, the second outer layer 98 can be directly on an outer surface of the first outer layer 97 such that the first outer layer 97 is between the second outer layer 98 and the hybrid diamond layer 92.

[0050] For example, the first outer layer 97 can be plated onto one or more (e.g., some or all) of a top surface, a bottom surface, and side surfaces (e.g., four side surfaces) of the hybrid diamond layer 92, and the second outer layer 98 can be plated onto an outer surface of the first outer layer 97. In accordance with some example embodiments of the present disclosure, the first outer layer 97 can include or consist of, for example, nickel (Ni), and the second outer layer 98 can include or consist of, for example, gold (Au).

[0051] According to some example embodiments of the present disclosure, the hybrid diamond thermal interposer 90 (e.g., the hybrid diamond layer 92) can not include any organic material.

[0052] Referring to Table 1 below, the thermal conductivity of the hybrid diamond (e.g., the hybrid diamond layer 92) can be about 600 W / m-K, while the thermal conductivity of silicon (Si) can be about 200 W / m-K. In other words, the thermal conductivity of the hybrid diamond (e.g., the hybrid diamond layer 92) can be about three times the thermal conductivity of silicon (Si). Accordingly, by disposing the hybrid diamond (e.g., the hybrid diamond thermal interposer 90 including the hybrid diamond layer 92) on top of silicon (Si) and / or on top of an HBM package, the thermal performance of a semiconductor device (e.g., an advanced package) can be improved.

[0053] Table 1: Example Properties

[0054]

[0055] Additionally, referring to Table 1 above, the coefficient of thermal expansion (CTE) value of the hybrid diamond (e.g., the hybrid diamond layer 92) can be about 10 ppm / °C, while the CTE value of silicon (Si) can be about 3 ppm / °C and the CTE value of copper (e.g., a copper heat spreader (HS)) can be about 18 ppm / °C. Accordingly, when using a thermal interposer (e.g., the hybrid diamond thermal interposer 90) according to some example embodiments of the present disclosure between a silicon (Si) die (e.g., a semiconductor chip) and a copper (Cu) heat spreader, the mechanical integrity of a semiconductor device (e.g., a semiconductor package) can be maintained. This is because using a thermal interposer material with an intermediate CTE value can result in low thermal mechanical stress in the semiconductor device (e.g., the semiconductor package).

[0056] In comparison to a thermal interposer (e.g., the hybrid diamond thermal interposer 90) according to some example embodiments of the present disclosure, a low-quality TIM can harden or leak (e.g., crack, delaminate, outgas, etc.) over time, resulting in increased thermal resistance, which in turn can result in overheating or premature failure of a high-performance device.

[0057] The risk of cracking or leaking of a TIM can be mitigated by the reduced CTE mismatch between a thermal interposer (e.g., the hybrid diamond thermal interposer 90) and a heat spreader according to some example embodiments of the present disclosure. Accordingly, the reliability of a TIM can be improved over the entire lifetime of a device according to some example embodiments of the present disclosure.

[0058] According to some example embodiments of the present disclosure, a thermal interposer (e.g., hybrid diamond thermal interposer 90) can be provided that includes a metal matrix (e.g., metal matrix 95, which can include, for example, silver or copper) in a diamond skeleton (e.g., diamond skeleton 93) and can not include any organic material. Thus, even at high temperatures (e.g., about 400 °C), the combination of the metal matrix (e.g., metal matrix 95) and the diamond skeleton (e.g., diamond skeleton 93) can adhere well to an outer layer (e.g., outer layer 96, which can include a plated nickel layer and / or a gold layer) without blistering. Thus, there is a low risk of thermal resistance at the interface of the hybrid diamond layer (e.g., hybrid diamond layer 92).

[0059] According to some example embodiments of the present disclosure, a hybrid diamond thermal interposer (e.g., hybrid diamond thermal interposer 90) can be implemented in semiconductor devices, such as, for example, high power devices and high performance advanced packages.

[0060] Reference is made below to Figures 2A to 9 Examples of semiconductor devices according to some example embodiments of the present disclosure are described. Figure 2A and Figures 3 to 9 Schematic cross-sectional views of semiconductor devices according to some example embodiments of the present disclosure are shown. Figure 2B Schematic enlarged views of portions A of Figure 2A are shown.

[0061] Reference is made below to Figures 2A to 6B Semiconductor devices can be provided that can be advanced packages. For example, semiconductor devices can include 2.5D architectures. For example, Figures 2A to 6B Semiconductor devices of

[0062] For example, reference is made to Figures 2A to 2B Semiconductor devices 1A can be provided. Semiconductor devices 1A can include, for example, a first lower redistribution layer 10, a substrate 20, a first upper redistribution layer 30, a second lower redistribution layer 40, an interposer 50, a second upper redistribution layer 60, a first semiconductor chip 70, at least one second semiconductor chip 80 (or semiconductor device), and a hybrid diamond thermal interposer 90.

[0063] The first lower redistribution layer 10 can be configured to electrically connect components above and / or below the first lower redistribution layer 10. For example, the first lower redistribution layer 10 can be configured to electrically connect the substrate 20 above the first lower redistribution layer 10 to one or more first bumps 112 below the first lower redistribution layer 10.

[0064] A top surface of the first lower redistribution layer 10 can be on a bottom surface of the substrate 20. For example, the top surface of the first lower redistribution layer 10 can be in direct contact with the bottom surface of the substrate 20. The one or more first bumps 112 can be on a bottom surface of the first lower redistribution layer 10. For example, the one or more first bumps 112 can be in direct contact with the bottom surface of the first lower redistribution layer 10. According to some example embodiments of the present disclosure, the one or more first bumps 112 can be external bumps configured to electrically connect the semiconductor device 1A to at least one external component. The one or more first bumps 112 can be, for example, ball grid array (BGA) solder balls.

[0065] Referring to Figure 2B , the first lower redistribution layer 10 can include at least one dielectric layer 12 and at least one connecting element (e.g., a metallic element) configured to electrically connect components above and / or below the first lower redistribution layer 10. For example, the at least one connecting element can include an upper metal layer 16 and a lower metal layer 14 at an upper surface and a lower surface, respectively, of the at least one dielectric layer 12. The at least one connecting element can also include at least one via within the at least one dielectric layer 12 that electrically connects the upper metal layer 16 and the lower metal layer 14 together.

[0066] The substrate 20 can be configured to electrically connect components above and / or below the substrate 20. For example, the substrate 20 can be configured to electrically connect the first upper redistribution layer 30 above the substrate 20 to the first lower redistribution layer 10 below the substrate 20. According to some example embodiments of the present disclosure, the substrate 20 can be an organic substrate. For example, the substrate 20 can be a substrate that primarily includes an organic material. For example, the substrate 20 can be a BT core substrate that includes bismaleimide triazine (BT). According to some example embodiments of the present disclosure, the substrate 20 can be a glass substrate or a ceramic substrate. For example, the substrate 20 can be a substrate that primarily includes a ceramic or a glass. According to some example embodiments of the present disclosure, the substrate 20 can include at least one connecting element (e.g., a metallic element) configured to electrically connect components above and / or below the substrate 20.

[0067] The first upper redistribution layer 30 can be configured to electrically connect components above and / or below the first upper redistribution layer 30. For example, the first upper redistribution layer 30 can be configured to electrically connect one or more second bumps 114 (see Figure 2B ) above the first upper redistribution layer 30 to the substrate 20 below the first upper redistribution layer 30.

[0068] A bottom surface of the first upper redistribution layer 30 can be on a top surface of the substrate 20. For example, the bottom surface of the first upper redistribution layer 30 can be in direct contact with the top surface of the substrate 20. The one or more second bumps 114 can be on a top surface of the first upper redistribution layer 30. For example, the one or more second bumps 114 can be in direct contact with the top surface of the first upper redistribution layer 30. The one or more second bumps 114 can be, for example, C4 solder bumps. According to some example embodiments of the present disclosure, the one or more second bumps 114 can be surrounded in at least one horizontal direction by an underfill 115 on (e.g., in direct contact with) an upper surface of the first upper redistribution layer 30.

[0069] Referring to Figure 2B The first upper redistribution layer 30 can include at least one dielectric layer 32 and at least one connecting element (e.g., metallic element) configured to electrically connect components above and / or below the first upper redistribution layer 30. For example, the at least one connecting element can include an upper metal layer 36 and a lower metal layer 34 at an upper surface and a lower surface, respectively, of the at least one dielectric layer 32. The at least one connecting element can also include at least one via within the at least one dielectric layer 32, the at least one via electrically connecting the upper metal layer 36 and the lower metal layer 34 together.

[0070] The second lower redistribution layer 40, the interposer 50, and the second upper redistribution layer 60 can be provided on (e.g., above) the combination of the first lower redistribution layer 10, the substrate 20, and the first upper redistribution layer 30.

[0071] The second lower redistribution layer 40 can be configured to electrically connect components above and / or below the second lower redistribution layer 40. For example, the second lower redistribution layer 40 can be configured to electrically connect the interposer 50 above the second lower redistribution layer 40 to the one or more second bumps 114 below the second lower redistribution layer 40.

[0072] A top surface of the second lower redistribution layer 40 can be on a bottom surface of the interposer 50. For example, the top surface of the second lower redistribution layer 40 can be in direct contact with the bottom surface of the interposer 50. The one or more second bumps 114 can be on a bottom surface of the second lower redistribution layer 40. For example, the one or more second bumps 114 can be in direct contact with the bottom surface of the second lower redistribution layer 40.

[0073] Referring to Figure 2BThe second lower redistribution layer 40 can include at least one dielectric layer 42 and at least one connecting element (e.g., a metallic element) configured to electrically connect components above and / or below the second lower redistribution layer 40. For example, the at least one connecting element can include an upper metal layer 46 and a lower metal layer 44 at upper and lower surfaces of the at least one dielectric layer 42, respectively. The at least one connecting element can also include at least one via within the at least one dielectric layer 42 that electrically connects the upper metal layer 46 and the lower metal layer 44 together.

[0074] The interposer 50 can be configured to electrically connect components above and / or below the interposer 50. For example, the interposer 50 can be configured to electrically connect the second upper redistribution layer 60 above the interposer 50 to the second lower redistribution layer 40 below the interposer 50. According to some example embodiments of the present disclosure, the interposer 50 can be an organic interposer. For example, the interposer 50 can be an interposer that primarily includes an organic material 54. According to some example embodiments of the present disclosure, the interposer 50 can be a 2.5D interposer.

[0075] According to some example embodiments of the present disclosure, the interposer 50 can include at least one connecting element configured to electrically connect components above and / or below the interposer 50. For example, the interposer 50 can include at least one via 53 (e.g., at least one through via) and / or at least one bridge die 58.

[0076] The at least one via 53 can be configured to electrically connect at least one component above the interposer 50 (e.g., the second upper redistribution layer 60) to at least one component below the interposer 50 (e.g., the second lower redistribution layer 40). The at least one via 53 can extend from a top surface of the interposer 50 through the organic material 54 to a bottom surface of the interposer 50. As shown, Figure 2A The at least one via 53 can include, for example, a metallic material.

[0077] The at least one bridge die 58 can be configured to electrically connect two or more components above the interposer 50 together. The at least one bridge die 58 can be at least partially surrounded by the organic material 54 in at least one horizontal direction. As shown, Figure 2AAs shown, two bridge die 58 can be provided, although embodiments of the present disclosure are not limited thereto. According to some example embodiments of the present disclosure, one of the bridge die 58 can be configured to electrically connect one of the second semiconductor chips 80 and the first semiconductor chip 70 together through the second upper redistribution layer 60, and can overlap the one of the second semiconductor chips 80 and the first semiconductor chip 70. In addition, another of the bridge die 58 can be configured to electrically connect another of the second semiconductor chips 80 and the first semiconductor chip 70 together through the second upper redistribution layer 60, and can overlap the another of the second semiconductor chips 80 and the first semiconductor chip 70. However, embodiments of the present disclosure are not limited thereto.

[0078] The second upper redistribution layer 60 can be configured to electrically connect components above and / or below the second upper redistribution layer 60. For example, the second upper redistribution layer 60 can be configured to electrically connect one or more third bumps 116 above the second upper redistribution layer 60 to the interposer 50 below the second upper redistribution layer 60.

[0079] A bottom surface of the second upper redistribution layer 60 can be on a top surface of the interposer 50. For example, the bottom surface of the second upper redistribution layer 60 can be in direct contact with the top surface of the interposer 50. The one or more third bumps 116 can be on a top surface of the second upper redistribution layer 60. For example, the one or more third bumps 116 can be in direct contact with the top surface of the second upper redistribution layer 60. The one or more third bumps 116 can be, for example, microsolder bumps.

[0080] Referring to Figure 2B The second upper redistribution layer 60 can include at least one dielectric layer 62 and at least one connecting element (e.g., metallic element) configured to electrically connect components above and / or below the second upper redistribution layer 60. For example, the at least one connecting element can include an upper metal layer 66 and a lower metal layer 64 at an upper surface and a lower surface, respectively, of the at least one dielectric layer 62. The at least one connecting element can also include at least one via within the at least one dielectric layer 62, the at least one via electrically connecting the upper metal layer 66 and the lower metal layer 64 together.

[0081] The first semiconductor chip 70 and the at least one second semiconductor chip 80 can be provided on (e.g., above) a combination of the second lower redistribution layer 40, the interposer 50, and the second upper redistribution layer 60.

[0082] According to some example embodiments of the present disclosure, as Figure 2AAs shown, the first semiconductor chip 70 can be between at least two of the second semiconductor chips 80 in a horizontal direction, although embodiments of the present disclosure are not limited thereto. Multiple sets of third bumps 116 can be provided respectively under the first semiconductor chip 70 and the at least one second semiconductor chip 80 to electrically connect thereto. For example, the first semiconductor chip 70 can be electrically connected to a first set of third bumps 116 under the first semiconductor chip 70, one of the second semiconductor chips 80 can be electrically connected to a second set of third bumps 116 under the one of the second semiconductor chips 80, and another of the second semiconductor chips 80 can be electrically connected to a third set of third bumps 116 under the another of the second semiconductor chips 80. Through the multiple sets of third bumps 116, the first semiconductor chip 70 and the at least one second semiconductor chip 80 can be electrically connected to the second upper redistribution layer 60. According to some example embodiments of the present disclosure, each set of third bumps 116 can be surrounded by a respective underfill 117 in at least one horizontal direction, the respective underfill 117 being on (e.g., in direct contact with) a top surface of the second upper redistribution layer 60.

[0083] Through the electrical connection to the second upper redistribution layer 60, the first semiconductor chip 70 and / or the at least one second semiconductor chip 80 can be further electrically connected to one or more of (e.g., some or all of) the interposer 50 (e.g., the vias 53 and / or the bridge die 58), the second lower redistribution layer 40, the second bumps 114, the first upper redistribution layer 30, the substrate 20, the first lower redistribution layer 10, and the first bumps 112. According to some example embodiments of the present disclosure, the first semiconductor chip 70 can be electrically connected to the at least one second semiconductor chip 80 through the third bumps 116 and one or more of the second upper redistribution layer 60, the interposer 50 (e.g., the vias 53 and / or the bridge die 58), the second lower redistribution layer 40, the second bumps 114, the first upper redistribution layer 30, the substrate 20, the first lower redistribution layer 10, and the first bumps 112. For example, the first semiconductor chip 70 can be electrically connected to the at least one second semiconductor chip 80 through the third bumps 116, the second upper redistribution layer 60, and the bridge die 58 of the interposer 50.

[0084] According to some example embodiments of the present disclosure, the first semiconductor chip 70 can be a logic die (e.g., a logic chip), and each of the second semiconductor chips 80 can be a memory chip (e.g., an HBM). According to some example embodiments of the present disclosure, a logic die (e.g., a logic chip) can have much higher power requirements than a memory chip (e.g., an HBM).

[0085] According to some example embodiments of the present disclosure, the metal pad 102 can be provided (e.g., deposited) on a top surface of the first semiconductor chip 70. For example, a bottom surface of the metal pad 102 can be in direct contact with the top surface of the first semiconductor chip 70. A shape of the metal pad 102 in a plan view can correspond to (e.g., be the same as) a shape of the first semiconductor chip 70 in a plan view. For example, side surfaces of the metal pad 102 and the first semiconductor chip 70 can be coplanar with each other, although example embodiments of the present disclosure are not limited thereto. The metal pad 102 can be configured to form a metal solder joint between a semiconductor chip (e.g., the first semiconductor chip 70) and the hybrid diamond thermal interposer 90. According to some example embodiments of the present disclosure, the metal pad 102 can include at least one layer of metal. For example, the at least one layer of the metal pad 102 can include: (a) a layer of nickel (Ni) and a layer of gold (Au); (b) a layer of titanium (Ti), a layer of nickel-vanadium (Ni-V), and a layer of palladium (Pd); (c) a layer of titanium (Ti), a layer of nickel-vanadium (Ni-V), and a layer of gold (Au); (d) a layer of titanium (Ti), a layer of nickel-vanadium (Ni-V), and a layer of copper (Cu); (e) and the like. According to some example embodiments of the present disclosure, the at least one layer of the metal pad 102 can be formed on the first semiconductor chip 70 by a sputtering process.

[0086] According to some example embodiments of the present disclosure, the first TIM 104 can be provided on a top surface of the metal pad 102. For example, a bottom surface of the first TIM 104 can be in direct contact with the top surface of the metal pad 102. Further, a top surface of the first TIM 104 can be in direct contact with a bottom surface of the hybrid diamond thermal interposer 90 (e.g., a bottom surface of the second outer layer 98 of the outer layer 96 on the bottom surface of the hybrid diamond layer 92). A shape of the first TIM 104 in a plan view can correspond to (e.g., be the same as) a shape of the metal pad 102 and / or the hybrid diamond thermal interposer 90 in a plan view. For example, side surfaces of the first TIM 104, the metal pad 102, and / or the hybrid diamond thermal interposer 90 can be coplanar with each other, although example embodiments of the present disclosure are not limited thereto. The first TIM 104, together with the metal pad 102, can be configured to form a metal solder joint between a semiconductor chip (e.g., the first semiconductor chip 70) and the hybrid diamond thermal interposer 90. According to some example embodiments of the present disclosure, the first TIM 104 can include any type of solder material, including but not limited to SAC (SnAgCu) alloy, Sn5Sb alloy, and low melting temperature solder (e.g., eutectic 42Sn58Bi alloy, eutectic 48Sn52In alloy, and the like).

[0087] According to some example embodiments of the present disclosure, the molding material 106 can be provided on (e.g., in direct contact with) the second upper redistribution layer 60. For example, the molding material 106 can surround the third bump 116, the underfill 117, the first semiconductor chip 70, the at least one second semiconductor chip 80, the metal pad 102, the first TIM 104, and the hybrid diamond thermal interposer 90 in at least one horizontal direction. For example, the molding material 106 can be in direct contact with side surfaces of the underfill 117, side surfaces of the first semiconductor chip 70, side surfaces of the at least one second semiconductor chip 80, side surfaces of the metal pad 102, side surfaces of the first TIM 104, and side surfaces of the hybrid diamond thermal interposer 90.

[0088] According to some example embodiments of the present disclosure, a shape of the molding material 106 in a plan view can correspond to (e.g., be the same as) a shape of the second upper redistribution layer 60 in a plan view. For example, side surfaces of the molding material 106 and side surfaces of the second upper redistribution layer 60 can be coplanar with each other, although example embodiments of the present disclosure are not limited thereto. According to some example embodiments of the present disclosure, an upper surface of the at least one second semiconductor chip 80 and an upper surface of the hybrid diamond thermal interposer 90 can be exposed from the molding material 106. For example, the upper surface of the at least one second semiconductor chip 80 and the upper surface of the hybrid diamond thermal interposer 90 can be coplanar with an upper surface of the molding material 106.

[0089] According to some example embodiments of the present disclosure, a semiconductor chip cap 108 can be provided on a top surface of the first upper redistribution layer 30. For example, the semiconductor chip cap 108 can include a plurality of capacitors surrounding the second lower redistribution layer 40, the interposer 50, and the second upper redistribution layer 60 in at least one horizontal direction.

[0090] According to some example embodiments of the present disclosure, a stiffener ring 120 can be provided on a top surface of the first upper redistribution layer 30. For example, the stiffener ring 120 can be attached to an outer side of the top surface of the first upper redistribution layer 30 by an adhesive 122.

[0091] According to some example embodiments of the present disclosure, one or more (e.g., some or all) of the first lower redistribution layer 10, the substrate 20, the first upper redistribution layer 30, the second lower redistribution layer 40, the interposer 50, the second upper redistribution layer 60, the first semiconductor chip 70, the at least one second semiconductor chip 80, the hybrid diamond thermal interposer 90, the molding material 106, the semiconductor chip cap 108, and the stiffener ring 120 can have a rectangular shape (e.g., a square shape) in a plan view, although example embodiments of the present disclosure are not limited thereto.

[0092] Referring to Figure 3 A semiconductor device IB can be provided. The semiconductor device IB can be similar to the semiconductor device IA described above with reference to Figures 2A to 2B , except that, for example, a heat spreader 130 can be provided instead of the stiffener ring 120. Thus, repeated description of the semiconductor device IB can be omitted.

[0093] The heat spreader 130 can be configured to spread heat from components such as, for example, the first semiconductor chip 70 and the at least one second semiconductor chip 80. For example, the heat spreader 130 can be provided on a top surface of the first upper redistribution layer 30. For example, the heat spreader 130 can be attached to an outer side of the top surface of the first upper redistribution layer 30 by an adhesive 122. The heat spreader 130 can extend perpendicularly from the outer side of the top surface of the first upper redistribution layer 30 to a level higher than the top surface of the at least one second semiconductor chip 80 and the top surface of the hybrid diamond thermal interposer 90, and can extend horizontally so as to be above (e.g., in an overlapping manner) the top surface of the at least one second semiconductor chip 80 and the top surface of the hybrid diamond thermal interposer 90. According to some example embodiments of the present disclosure, the heat spreader 130 can be configured as a lid of the semiconductor device IB. According to some example embodiments of the present disclosure, the heat spreader 130 can be made of a metal (e.g., copper). According to some example embodiments of the present disclosure, the heat spreader 130 can be coated with at least one metal (e.g., nickel (Ni) and / or gold (Au)).

[0094] According to some example embodiments of the present disclosure, a second TIM 140 can be provided on the top surface of the at least one second semiconductor chip 80 and the top surface of the hybrid diamond thermal interposer 90, respectively, so as to attach the top surface of the at least one second semiconductor chip 80 and the top surface of the hybrid diamond thermal interposer 90 to the portion of the heat spreader 130 above which they are located. Optionally, a second TIM 140A (see Figure 8B ) can be provided as a continuous layer extending over the top surface of the at least one second semiconductor chip 80 and the top surface of the hybrid diamond thermal interposer 90, so as to attach the top surface of the at least one second semiconductor chip 80 and the top surface of the hybrid diamond thermal interposer 90 to the portion of the heat spreader 130 above which they are located. Thus, heat from the first semiconductor chip 70 can be transferred to the heat spreader 130 through the hybrid diamond thermal interposer 90 and the second TIM 140 (or the second TIM 140A) thereon, and heat from the at least one second semiconductor chip 80 can be transferred to the heat spreader 130 through the at least one second TIM 140 (or the second TIM 140A) thereon.

[0095] According to some example embodiments of the present disclosure, the second TIM 140 (or the second TIM 140A) can include, for example, a liquid metal (e.g., gallium (Ga)) or a liquid-like metal (e.g., a Ga-In alloy), graphite, a thermal grease, etc.

[0096] Referring to Figure 4 , a semiconductor device 1C can be provided. The semiconductor device 1C can be similar to the semiconductor device 1B described above with reference to Figure 3 , except that, for example, a plurality of metal pads 102, a plurality of first TIMs 104, and a plurality of hybrid diamond thermal interlayers 90 can be provided. Thus, repeated description of the semiconductor device 1C can be omitted.

[0097] As shown in Figure 4 , the metal pads 102, the first TIMs 104, and the hybrid diamond thermal interlayers 90 of each group can be provided on a top surface of each of the first semiconductor chip 70 and the at least one second semiconductor chip 80. For example, the metal pads 102 can additionally be provided on a top surface of each second semiconductor chip 80, the first TIMs 104 can be provided on such metal pads 102, and the hybrid diamond thermal interlayers 90 can be provided on such first TIMs 104, thereby being bonded to the second semiconductor chip 80 through such metal pads 102 and such first TIMs 104. Thus, heat from the first semiconductor chip 70 can be transferred to the heat spreader 130 through the hybrid diamond thermal interlayer 90 and the second TIM 140 (or the second TIM 140A) thereon, and heat from each second semiconductor chip 80 can be transferred to the heat spreader 130 through the hybrid diamond thermal interlayer 90 and the second TIM 140 (or the second TIM 140A) thereon.

[0098] According to some example embodiments of the present disclosure, the heat spreader 130 can be omitted, and a reinforcement ring 120 (see Figure 2A ) can be provided.

[0099] Referring to Figure 5 , a semiconductor device 1D can be provided. The semiconductor device 1D can be similar to the semiconductor device 1A described above with reference to Figures 2A to 2B , except that, for example, an interlayer 50A can be provided instead of the interlayer 50, the second lower redistribution layer 40, and the second upper redistribution layer 60. Thus, repeated description of the semiconductor device 1D can be omitted.

[0100] According to some example embodiments of the present disclosure, the interlayer 50A can be a silicon interlayer. For example, the interlayer 50A can mainly include silicon, rather than an organic material. According to some example embodiments of the present disclosure, the interlayer 50A can be a 2.5D interlayer.

[0101] The interposer 50A can be configured to electrically connect components above and / or below the interposer 50A. For example, the interposer 50A can be configured to electrically connect the third bump 116 above the interposer 50A to the second bump 114 below the interposer 50A (see Figure 2A ).

[0102] According to some example embodiments of the present disclosure, the interposer 50A can include at least one connecting element (e.g., a metal element) configured to electrically connect components above and / or below the interposer 50A. For example, the interposer 50A can include an upper metal layer and a lower metal layer at the upper surface and the lower surface of the interposer 50A, respectively. The at least one connecting element can also include at least one via (e.g., a through via) within the interposer 50A that electrically connects the upper metal layer and the lower metal layer together.

[0103] According to some example embodiments of the present disclosure, the semiconductor device 1D can include a heat spreader 130 (see Figure 3 ) and a second TIM 140, instead of the stiffener ring 120, such that the semiconductor device 1E is similar to the semiconductor device 1B (see Figure 3 ), except for including the interposer 50A, for example.

[0104] Referring to Figures 6A to 6B , a semiconductor device 1E can be provided. Figures 6A to 6B A schematic cross-sectional view of the semiconductor device 1E according to example embodiments of the present disclosure is shown.

[0105] The semiconductor device 1E can be similar to the semiconductor device 1D described above with reference to Figure 5 , except that a plurality of third bumps 116A can be provided instead of the plurality of third bumps 116 and the underfill 117, for example. Further, referring to Figure 6A , the molding material 106 can be omitted. Accordingly, repeated descriptions of the semiconductor device 1E can be omitted.

[0106] According to some example embodiments of the present disclosure, the third bump 116A can be a hybrid copper bond, for example. For example, each of the first semiconductor chip 70 and the second semiconductor chip 80 can be directly bonded to the interposer 50A via the third bump 116A (e.g., a hybrid copper bond). For example, each of the first semiconductor chip 70 and the second semiconductor chip 80 can be directly bonded to the interposer 50A via a hybrid copper bond (HCB). The hybrid copper bond can include an embedded metal (e.g., copper) portion bonded together and a dielectric (e.g., SiOx) portion bonded together.

[0107] According to example embodiments of the present disclosure, the above description with reference to Figures 6A to 6BThe described configuration (including the third bumps 116A) can also be implemented, for example, on the semiconductor device 1C described above with reference to Figures 2A to 5 in the described embodiments.

[0108] Referring to Figure 7 , a semiconductor device 1F can be provided. The semiconductor device 1F can be similar to the semiconductor device 1D described above with reference to Figure 5 , except that, for example, a plurality of metal pads 102, a plurality of first TIMs 104, and a plurality of hybrid diamond thermal interlayers 90 can be provided. In addition, a heat spreader 130 and a second TIM 140 can be provided instead of the stiffener ring 120. Accordingly, repeated descriptions of the semiconductor device 1F can be omitted.

[0109] For example, the metal pads 102, the first TIMs 104, the hybrid diamond thermal interlayers 90, and the second TIMs 140 of each group can be provided on the top surface of each of the first semiconductor chip 70 and the at least one second semiconductor chip 80 in a similar manner as described above with reference to Figure 4 . Accordingly, repeated descriptions of the semiconductor device 1F can be omitted.

[0110] According to some example embodiments of the present disclosure, the heat spreader 130 can be omitted, and the stiffener ring 120 (see Figure 5 ) can be provided.

[0111] Referring to Figures 8A to 8B , a semiconductor device 1G can be provided. Figures 8A to 8B A schematic cross-sectional view of the semiconductor device 1G according to example embodiments of the present disclosure is shown.

[0112] The semiconductor device 1G can be similar to the semiconductor device 1F described above with reference to Figure 7 , except that, for example, a plurality of third bumps 116A can be provided instead of the plurality of third bumps 116 and the underfill 117. In addition, referring to Figure 8A , the molding material 106 can be omitted. Accordingly, repeated descriptions of the semiconductor device 1G can be omitted. As described above, the third bumps 116A can be, for example, hybrid copper bonds. Accordingly, repeated descriptions of the third bumps 116A can be omitted.

[0113] According to some example embodiments of the present disclosure, referring to Figure 8BThe second TIM 140A can be provided as a continuous layer extending over the upper surface of the first semiconductor chip 70, the upper surface of one or more (e.g., some or all) of the second semiconductor chips 80, and the upper surface of the molding material 106. For example, the second TIM 140A can be provided as a continuous layer extending over the upper surface of each of the one or more (e.g., some or all) of the second semiconductor chips 80 and the hybrid diamond thermal interlayers 90 on the first semiconductor chip 70, and over the upper surface of the molding material 106. For example, the second TIM 140A can be in direct contact with the upper surface of the outer layer 96 of each hybrid diamond thermal interlayer 90, and over the upper surface of the molding material 106.

[0114] According to example implementations of the present disclosure, in plan view, the second TIM 140A can have the same shape as the molding material 106, the side surfaces of the second TIM 140A and the side surfaces of the molding material 106 can be coplanar with each other.

[0115] According to example implementations of the present disclosure, the configurations described above with reference to Figures 8A to 8B may also be implemented in the implementations described above with reference to Figure 7 .

[0116] According to example implementations of the present disclosure, the configurations described above with reference to Figure 8B may also be implemented in other implementations of the present disclosure including the molding material 106 (e.g., the implementations shown in Figure 2A , Figures 3 to 5 , Figure 6B and Figure 7 ).

[0117] Referring to Figures 9 to 11 , a semiconductor device can be provided having a flip chip ball grid array (BGA) configuration. Figures 9 to 11 The semiconductor device of Figures 9 to 11 may be configured for high power applications. In describing the implementations of Figures 1 to 8B , descriptions that are repetitive of the descriptions given above with respect to may be omitted.

[0118] Figure 9 For example, referring to , a semiconductor device 1H can be provided.

[0119] Figure 2AThe semiconductor device 1A shown can not include the second semiconductor chip 80, and can not include the second lower redistribution layer 40, the interposer 50, and the second upper redistribution layer 60, compared to the semiconductor device 1A. For example, the first semiconductor chip 70 can be mounted on and electrically connected to the first upper redistribution layer 30 by the second bump 116B, without the second lower redistribution layer 40, the interposer 50, and the second upper redistribution layer 60.

[0120] According to some example embodiments of the present disclosure, the second bump 116B can be a C4 solder bump. According to some example embodiments of the present disclosure, the second bump 116B can be surrounded by an underfill 117A in at least one horizontal direction, the underfill 117A being on (e.g., in direct contact with) a top surface of the first upper redistribution layer 30. According to some example embodiments of the present disclosure, the semiconductor chip capacitor 109 can be provided on a bottom surface of the first lower redistribution layer 10.

[0121] According to some example embodiments of the present disclosure, a stiffener ring 120A can be provided on a top surface of the first upper redistribution layer 30. For example, the stiffener ring 120A can be attached to an outer side of the top surface of the first upper redistribution layer 30 by an adhesive 122A. According to some example embodiments of the present disclosure, the stiffener ring 120A can have a rectangular shape (e.g., a square shape) in a plan view, although example embodiments of the present disclosure are not limited thereto.

[0122] Referring to Figure 10 A semiconductor device 1I can be provided. The semiconductor device 1I can be similar to the semiconductor device 1H described above with reference to Figure 9 except that, for example, a heat spreader 130A can be provided instead of the stiffener ring 120A. Thus, repeated description of the semiconductor device 1I can be omitted.

[0123] The heat spreader 130A can be configured to spread heat from components such as, for example, the first semiconductor chip 70. For example, the heat spreader 130A can be provided on a top surface of the first upper redistribution layer 30. For example, the heat spreader 130A can be attached to an outer side of the top surface of the first upper redistribution layer 30 by an adhesive 122A. As Figure 10 shown, the heat spreader 130A can extend perpendicularly from an outer side of the top surface of the first upper redistribution layer 30 to a level higher than a top surface of the hybrid diamond thermal interposer 90, and can extend horizontally so as to be above (e.g., in an overlapping manner) the top surface of the hybrid diamond thermal interposer 90. Thus, heat from the first semiconductor chip 70 can be transferred to the heat spreader 130A through the hybrid diamond thermal interposer 90 and the second TIM 140 thereon. According to some example embodiments of the present disclosure, the heat spreader 130A can be configured as a lid of the semiconductor device 1I.

[0124] According to some example embodiments of the present disclosure, the heat spreader 130A can be made of a metal (e.g., copper (Cu)). According to some example embodiments of the present disclosure, the heat spreader 130A can be coated with at least one metal (e.g., nickel (Ni) and / or gold (Au)). According to some example embodiments of the present disclosure, the heat spreader 130A can have a rectangular shape (e.g., a square shape) in a plan view, although example embodiments of the present disclosure are not limited thereto.

[0125] Referring to Figure 11 A semiconductor device 1J can be provided. The semiconductor device 1J can be similar to the semiconductor device 11 described above with reference to Figure 10 except that, for example, a heat spreader 130B can be provided instead of the heat spreader 130A. Thus, repeated description of the semiconductor device 1J can be omitted.

[0126] The heat spreader 130B can have a shape different from that of the heat spreader 130A. For example, the heat spreader 130B can include a first horizontal portion 132, an inclined portion 134, and a second horizontal portion 136.

[0127] The first horizontal portion 132 can extend in a horizontal direction over the adhesive 122A toward the first semiconductor chip 70 and the hybrid diamond thermal interposer 90. The inclined portion 134 can be directly connected to the first horizontal portion 132 and can extend from the first horizontal portion 132 in an inclined direction (horizontally and vertically) toward and over the first semiconductor chip 70 and the hybrid diamond thermal interposer 90. The second horizontal portion 136 can be directly connected to the inclined portion 134, can extend horizontally over a top surface of the hybrid diamond thermal interposer 90, and can be connected to the hybrid diamond thermal interposer 90 by a second TIM 140.

[0128] According to some example embodiments of the present disclosure, the heat spreader 130B can be made of a metal (e.g., copper). According to some example embodiments of the present disclosure, the heat spreader 130B can be coated with at least one metal (e.g., nickel (Ni) and / or gold (Au)). According to some example embodiments of the present disclosure, the heat spreader 130B can have a rectangular shape (e.g., a square shape) in a plan view, although example embodiments of the present disclosure are not limited thereto.

[0129] According to some example embodiments of the present disclosure, referring to Figures 12 to 16 A method 200 of manufacturing a semiconductor device (e.g., the semiconductor devices 1A to 1G) can be provided.

[0130] Figure 12A flowchart of a method 200 of manufacturing a semiconductor device according to an example embodiment of the present disclosure is shown. Figures 13 to 14 An intermediate semiconductor device formed in the operations of the method 200 is shown for explanation of the above reference Figures 2A to 4 The manufacture of the semiconductor devices 1A-1C described above is referenced. Figures 15 to 16 An intermediate semiconductor device formed in the operations of the method 200 is shown for explanation of the above reference Figures 5 to 8B The manufacture of the semiconductor devices 1D-1G described above is referenced.

[0131] Reference is made to Figure 12 , the method 200 can include providing an intermediate semiconductor device (operation 210) and providing at least one hybrid diamond thermal interposer on at least one semiconductor die of the intermediate semiconductor device (operation 220). The method 200 can also include attaching a stiffener ring to the intermediate semiconductor device (operation 230) or attaching a heat sink to the intermediate semiconductor device (operation 240).

[0132] Reference is made to Figure 13 and Figure 15 , the operation 210 can include providing an intermediate semiconductor device (e.g., the intermediate semiconductor device 301A or the intermediate semiconductor device 301B). According to some embodiments of the present disclosure, the operation 210 can include manufacturing an intermediate semiconductor device (e.g., the intermediate semiconductor device 301A or the intermediate semiconductor device 301B).

[0133] For example, reference is made to Figure 13 , the operation 210 can include forming, assembling together, and / or electrically connecting together any number of components of the intermediate semiconductor device, including, for example, the first lower redistribution layer 10, the substrate 20, the first upper redistribution layer 30, the second lower redistribution layer 40, the interposer 50, the second upper redistribution layer 60, the first semiconductor die 70, the at least one second semiconductor die 80, the at least one metal pad 102, the at least one first TIM 104, the semiconductor die capacitor 108, the bumps (e.g., the first bump 112, the second bump 114, the third bump 116, and / or the third bump 116A), the underfill (e.g., the underfill 115 and / or the underfill 117), and / or the molding material (e.g., the molding material 106). Reference is made to Figure 15 , the operation 210 can include forming, assembling, and / or electrically connecting the interposer 50A instead of the interposer 50. To form the semiconductor devices 1H-1J described above with reference to Figures 9 to 11 , the intermediate semiconductor device provided by the operation 210 can not include, for example, the second semiconductor die 80, the second lower redistribution layer 40, the interposer 50, and the second upper redistribution layer 60.

[0134] According to some example embodiments of the present disclosure, operation 210 can include providing (e.g., sputtering) a metal pad 102 on at least one semiconductor chip (e.g., the first semiconductor chip 70 and / or the at least one second semiconductor chip 80) and providing a first TIM 104 on the at least one metal pad 102 on the at least one semiconductor chip (e.g., the first semiconductor chip 70 and / or the at least one second semiconductor chip 80).

[0135] Referring to Figure 14 and Figure 16 , operation 220 can include providing at least one hybrid diamond thermal interposer 90 on at least one semiconductor chip (e.g., the first semiconductor chip 70 and / or the at least one second semiconductor chip 80) of the intermediate semiconductor device. For example, the hybrid diamond thermal interposer 90 can be provided on the first semiconductor chip 70, with the metal pad 102 and the first TIM 104 between the hybrid diamond thermal interposer 90 and the first semiconductor chip 70. However, embodiments of the present disclosure are not limited thereto. For example, referring to Figure 4 , a plurality of hybrid diamond thermal interposers 90 can be provided on a plurality of semiconductor chips (e.g., the first semiconductor chip 70 and the at least one second semiconductor chip 80), respectively, with respective metal pads 102 and respective first TIMs 104 therebetween.

[0136] For example, operation 220 can include attaching the at least one hybrid diamond thermal interposer 90 to the at least one semiconductor chip (e.g., the first semiconductor chip 70 and / or the at least one second semiconductor chip 80) by at least one metal solder joint formed by the at least one metal pad 102 and the at least one first TIM 104.

[0137] Referring to Figure 2A , Figure 5 , Figures 6A to 6B and Figure 9 , operation 230 can include attaching a stiffener ring (e.g., the stiffener ring 120 or the stiffener ring 120A) to the intermediate semiconductor device. For example, the stiffener ring (e.g., the stiffener ring 120 or the stiffener ring 120A) can be attached to the first upper redistribution layer 30 by an adhesive (e.g., the adhesive 122 or the adhesive 122A).

[0138] Referring to Figures 3 to 4 , Figure 7 , Figures 8A to 8B and Figures 10 to 11Operation 230 can include attaching a heat spreader (e.g., heat spreader 130, heat spreader 130A, or heat spreader 130B) to the intermediate semiconductor device. For example, the heat spreader (e.g., heat spreader 130, heat spreader 130A, or heat spreader 130B) can be attached to the first upper redistribution layer 30 by an adhesive (e.g., adhesive 122 or adhesive 122A).

[0139] According to some example embodiments of the present disclosure, operation 230 can further include attaching a heat spreader (e.g., heat spreader 130, heat spreader 130A, or heat spreader 130B) to a top surface of the at least one hybrid diamond thermal interlayer 90 provided in operation 220. For example, operation 230 can further include attaching a heat spreader (e.g., heat spreader 130, heat spreader 130A, or heat spreader 130B) to a top surface of the at least one hybrid diamond thermal interlayer 90 by at least one second TIM 140 (or second TIM 140A) on each hybrid diamond thermal interlayer 90.

[0140] According to some example embodiments of the present disclosure, one or more (e.g., some or all) of the second semiconductor chips 80 can be memory devices 80A, and / or a plurality of first semiconductor chips 70 can be provided. For example, the second semiconductor chips 80 of the example embodiments described above with reference to Figures 1 to 16 The second semiconductor chips 80 of the example embodiments described above with reference to Figure 17 may be memory devices 80A as described below with reference to

[0141] Figure 17 A schematic plan view of a first semiconductor chip 70 and a memory device 80A of a semiconductor device according to example embodiments of the present disclosure is shown. Example configurations of the memory device 80A and the first semiconductor chip 70 are described below with reference to Figure 17

[0142] Reference is made to Figure 17 ​One or more (e.g., some or all) of the memory devices 80A may include a bufferless logic die 82A and at least one stack 84A of a plurality of semiconductor chips 86A stacked vertically on the upper surface of the bufferless logic die 82A. Each stack 84A of the plurality of semiconductor chips 86A may be referred to as a “tower”. According to some exemplary embodiments of this disclosure, each memory device 80A may be an HBM, and each of the plurality of semiconductor chips 86A may be, for example, an HBM dual in-line memory module (DIMM).

[0143] like Figure 17 As shown, each memory device 80A may include two stacks 84A of semiconductor chips 86A on a bufferless logic die 82A. That is, one or more (e.g., some or all) of the memory devices 80A may be configured as a dual-tower HBM comprising two towers of semiconductor chips 86A. However, embodiments of this disclosure are not limited thereto. For example, one or more (e.g., some or all) of the memory devices 80A may comprise only one stack 84A (or tower) of semiconductor chips 86A or three or more stacks 84A (or towers) of semiconductor chips 86A.

[0144] like Figure 17 As shown, for each of the memory devices 80A, the stack 84A can be arranged relative to each other and the first semiconductor chip 70 in the X direction. However, embodiments of this disclosure are not limited to this. For example, for one or more (e.g., some or all) of the memory devices 80A, the stack 84A can be arranged relative to each other in any other horizontal direction (e.g., the Y direction perpendicular to the X direction) while being arranged relative to the first semiconductor chip 70 in the X direction. According to an example embodiment, each memory device 80A can be arranged on a second redistribution layer 60 (see...). Figures 2A to 4 ) or intermediary layer 50A (see Figures 5 to 8B At the same vertical height on ).

[0145] like Figure 17 As shown, two first semiconductor chips 70 can be provided. However, embodiments of this disclosure are not limited to this. For example, only a single first semiconductor chip 70 may be provided, or three or more first semiconductor chips 70 may be provided. Figure 17 As shown, a plurality of first semiconductor chips 70 may be arranged relative to each other in the Y direction. However, embodiments of this disclosure are not limited thereto. For example, one or more (e.g., some or all) of the first semiconductor chips 70 may be arranged relative to each other in any other horizontal direction (e.g., the X direction). According to an example embodiment, each first semiconductor chip 70 may be arranged on a second redistribution layer 60 (see Figures 2A to 4 ) or intermediary layer 50A (seeFigures 5 to 8B at the same vertical height on the same vertical plane.

[0146] According to some example embodiments of the present disclosure, an advanced package with improved thermal performance can be provided without sacrificing the mechanical integrity of the advanced package.

[0147] According to some example embodiments of the present disclosure, a hybrid diamond thermal interposer (e.g., hybrid diamond thermal interposer 90) integrated with a TIM (e.g., first TIM 104 and / or second TIM 140 (or second TIM 140A)) with high thermal conductivity can be provided, thereby significantly improving thermal performance without sacrificing the mechanical integrity of the package.

[0148] According to some example embodiments of the present disclosure, a semiconductor package (e.g., advanced package) can be provided. The semiconductor package can include at least one semiconductor chip (e.g., first semiconductor chip 70 and / or at least one second semiconductor chip 80), a heat spreader, two thermal interface materials, and a thermal interposer (e.g., hybrid diamond thermal interposer 90). The thermal interposer (e.g., hybrid diamond thermal interposer 90) can be configured to spread heat and can include a hybrid diamond (e.g., hybrid diamond layer 92) that includes a metal matrix (e.g., metal matrix 95) in a diamond skeleton (e.g., diamond skeleton 93) and can not include an organic material. The hybrid diamond (e.g., hybrid diamond layer 92) can be coated with, for example, at least one layer (e.g., outer layer 96 that includes, for example, a nickel (Ni) layer and a gold (Au) layer).

[0149] According to some example embodiments of the present disclosure, the semiconductor package can be or include a system-in-package (SIP), flip-chip package, advanced wafer- and panel-level package, and other high-performance package that requires high thermal performance.

[0150] According to some example embodiments of the present disclosure, a semiconductor device with any package architecture that requires and has high thermal performance can be provided. The semiconductor device can include a hybrid diamond thermal interposer implemented in the package architecture.

[0151] According to some example embodiments of the present disclosure, a method (e.g., method 200) of manufacturing a semiconductor device (e.g., semiconductor devices 1A-1J) can be provided.

[0152] According to some example embodiments of the present disclosure, a hybrid diamond thermal interposer (e.g., hybrid diamond thermal interposer 90) that includes Ag-diamond and / or Cu-diamond can be provided.

[0153] The present disclosure is presented to enable a person having ordinary skill in the art to make and use the disclosure and to incorporate it in the context of particular applications. Although the foregoing is directed to particular examples, other and further examples can be devised without departing from the scope of the disclosure.

[0154] Various modifications and other implementations of what is described here can be utilized without departing from the spirit of the disclosure. The generic principles defined herein can be applied to a wide range of implementations. Thus, the disclosure is not intended to be limited to the examples presented, and is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0155] In the description provided herein, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without necessarily being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present disclosure.

[0156] Unless specifically stated otherwise, all features disclosed herein can be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, each feature disclosed herein is one example only of a generic series of equivalent or similar features.

[0157] Various features are described in the present disclosure with reference to the accompanying drawings. It should be noted that the drawings are merely meant to facilitate the description of the features. They are not intended as an exhaustive description of the disclosure or as a limitation on the scope of the present disclosure. In addition, the examples shown need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so expressly stated or described.

[0158] Furthermore, any element of claim that is not specifically recited in the claim as an "means for" performing a specified function should not be construed as a "means plus function" claim as "means for" performing a specified function. In particular, the use of "step of" or "act of" in the claims hereof is not intended to invoke 35 U.S.C. § 112(f) under 35 U.S.C. § 101.

[0159] If used, the description words "left," "right," "front," "back," "top," "bottom," "forward," "reverse," "clockwise," and "counter clockwise" are used only for convenience, and are not intended to imply any particular fixed direction. Instead, they are used to reflect relative positions and / or orientations between various parts of an object.

[0160] Although implementations have been described in relation to circuit functionality, implementations of the present disclosure are not limited thereto. Possible implementations can be implemented in a single integrated circuit, in a multi-chip module, in a single card, in a system on a chip, or in a multi-card circuit assembly. As will be apparent to those of ordinary skill in the art, the various implementations can also be implemented as part of a larger system. Such implementations can be used in conjunction with, for example, a digital signal processor, a microcontroller, a field programmable gate array, an application specific integrated circuit, or a general purpose computer.

[0161] For the sake of brevity, conventional elements of a semiconductor device can be described in detail herein or can not be described in detail herein. However, even if an element is described as or shown in a semiconductor device in the present disclosure, the element can not be included in the claimed semiconductor device unless the element is recited as included in the claimed semiconductor device. Also, when a specific method for deposition or etching is mentioned or not mentioned herein for use in manufacturing a semiconductor device, it will be understood that a conventional method for such deposition or etching can be applied to the corresponding step of manufacturing the semiconductor device.

[0162] Although non-limiting example implementations have been described above in connection with the drawings, modifications and changes thereto can become apparent to those of ordinary skill in the art without departing from the scope of the present disclosure.

[0163] This application is based on and claims priority to U.S. Provisional Application No. 63 / 661,294, filed on June 18, 2024, and U.S. Application No. 19 / 085,797, filed on March 20, 2025, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A semiconductor device comprising: a substrate; an interposer at least partially on a first surface of the substrate facing a first direction; a first semiconductor chip at least partially on a first surface of the interposer facing the first direction; a second semiconductor chip at least partially on the first surface of the interposer, the second semiconductor chip spaced apart from the first semiconductor chip in a second direction crossing the first direction; and a hybrid diamond thermal interposer at least partially on a first surface of the first semiconductor chip facing the first direction or at least partially on a first surface of the second semiconductor chip facing the first direction, wherein the hybrid diamond thermal interposer comprises diamond particles within a metal.

2. The semiconductor device of claim 1, wherein the first semiconductor chip comprises a logic chip and the second semiconductor chip comprises a memory chip.

3. The semiconductor device of claim 1, wherein the hybrid diamond thermal interposer is at least partially on the first surface of the first semiconductor chip.

4. The semiconductor device of claim 1, wherein the hybrid diamond thermal interposer is at least partially on the first surface of the second semiconductor chip.

5. The semiconductor device of claim 1, wherein the hybrid diamond thermal interposer is at least partially on the first surface of the first semiconductor chip, wherein the semiconductor device further comprises a further hybrid diamond thermal interposer at least partially on the first surface of the second semiconductor chip, and wherein the further hybrid diamond thermal interposer comprises diamond particles within a metal.

6. The semiconductor device of claim 1, further comprising a first thermal interface material (TIM) between the hybrid diamond thermal interposer and the first surface of the first semiconductor chip or the first surface of the second semiconductor chip.

7. The semiconductor device of claim 1, further comprising: a first thermal interface material (TIM) between the hybrid diamond thermal interposer and the first surface of the first semiconductor chip or the first surface of the second semiconductor chip; and a metal pad between the first TIM and the first surface of the first semiconductor chip or the first surface of the second semiconductor chip.

8. The semiconductor device of claim 1, further comprising: a first thermal interface material (TIM) between the hybrid diamond thermal interposer and the first surface of the first semiconductor chip or the first surface of the second semiconductor chip; and a second TIM at least partially on a first surface of the hybrid diamond thermal interposer facing the first direction.

9. The semiconductor device of claim 1, further comprising: a first thermal interface material (TIM) between the hybrid diamond thermal interposer and the first surface of the first semiconductor chip or the first surface of the second semiconductor chip; and a metal pad between the first TIM and the first surface of the first semiconductor chip or the first surface of the second semiconductor chip. ​ ​ ​ a second TIM at least partially on a first surface of the hybrid diamond thermal interposer facing the first direction, wherein the first TIM comprises a solder material, the second TIM comprises Ga, a Ga-In alloy, graphite, or a thermal grease.

10. The semiconductor device of claim 1, further comprising: a first thermal interface material (TIM) between the hybrid diamond thermal interposer and the first surface of the first semiconductor chip or the first surface of the second semiconductor chip; a second TIM at least partially on a first surface of the hybrid diamond thermal interposer facing the first direction; and a heat spreader at least partially on the first surface of the substrate and extending in the first direction and the second direction to overlap the hybrid diamond thermal interposer in the first direction, wherein the heat spreader is connected to the hybrid diamond thermal interposer through the second TIM.

11. The semiconductor device of claim 1, wherein the substrate comprises an organic substrate.

12. The semiconductor device of claim 1, wherein the interposer comprises an organic interposer.

13. The semiconductor device of claim 1, wherein the interposer comprises a silicon interposer.

14. A semiconductor device, comprising: an interposer; a first semiconductor chip at least partially on a first surface of the interposer facing a first direction, wherein the first semiconductor chip comprises a logic chip; a second semiconductor chip at least partially on the first surface of the interposer, the second semiconductor chip spaced apart from the first semiconductor chip in a second direction that intersects the first direction, wherein the second semiconductor chip comprises a high bandwidth memory (HBM); and a hybrid diamond thermal interposer at least partially on a first surface of the first semiconductor chip facing the first direction, wherein the hybrid diamond thermal interposer comprises diamond particles within a metal.

15. The semiconductor device of claim 14, further comprising a first thermal interface material (TIM) between the hybrid diamond thermal interposer and the first surface of the first semiconductor chip.

16. The semiconductor device of claim 15, further comprising a metal pad between the first TIM and the first surface of the first semiconductor chip.

17. The semiconductor device of claim 15, further comprising: a metal pad between the first TIM and the first surface of the first semiconductor chip; and a second TIM at least partially on a first surface of the hybrid diamond thermal interposer facing the first direction.

18. The semiconductor device of claim 15, further comprising: a metal pad between the first TIM and the first surface of the first semiconductor chip; a second TIM at least partially on a first surface of the hybrid diamond thermal interposer facing the first direction; a substrate, wherein the interposer is at least partially on a first surface of the substrate facing the first direction; and a heat spreader at least partially on the first surface of the substrate and extending in the first direction and the second direction to overlap the hybrid diamond thermal interposer in the first direction, wherein the heat spreader is connected to the hybrid diamond thermal interposer through the second TIM. a heat spreader at least partially on the first surface of the substrate and extending in the first direction and the second direction so as to overlap the hybrid diamond thermal interlayer in the first direction, wherein the heat spreader is connected to the hybrid diamond thermal interlayer by the second TIM.

19. The semiconductor device of claim 15, further comprising: a metal pad between the first TIM and the first surface of the first semiconductor chip; a second TIM at least partially on a first surface of the hybrid diamond thermal interlayer facing the first direction; a substrate, wherein the interlayer is at least partially on a first surface of the substrate facing the first direction; a heat spreader at least partially on the first surface of the substrate and extending in the first direction and the second direction so as to overlap the hybrid diamond thermal interlayer in the first direction; and a further hybrid diamond thermal interlayer at least partially on a first surface of the second semiconductor chip facing the first direction, wherein the heat spreader is connected to the hybrid diamond thermal interlayer by the second TIM, and wherein the further hybrid diamond thermal interlayer comprises diamond particles within a metal.

20. A method of manufacturing a semiconductor device, the method comprising: providing an intermediate semiconductor device, the intermediate semiconductor device comprising: a substrate; an interlayer at least partially on a first surface of the substrate facing a first direction; a first semiconductor chip at least partially on a first surface of the interlayer facing the first direction; and a second semiconductor chip at least partially on the first surface of the interlayer, the second semiconductor chip being spaced apart from the first semiconductor chip in a second direction crossing the first direction; and providing a hybrid diamond thermal interlayer at least partially on a first surface of the first semiconductor chip facing the first direction or at least partially on a first surface of the second semiconductor chip facing the first direction, wherein the hybrid diamond thermal interlayer comprises diamond particles within a metal.

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