Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The present disclosure provides a semiconductor device capable of reducing resistance between a semiconductor element and a lead. A semiconductor device (100) is provided with: a semiconductor element (30); a first metal layer (16) electrically connected to the semiconductor element (30); a bonding layer (20) bonded to the first metal layer (16), the bonding layer (20) being a sintered metal or a solder; a lead wire (24) bonded to the bonding layer (20); and a second metal layer (22) provided in a first hole penetrating the bonding layer (20) and electrically connecting the first metal layer (16) and the lead (24).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] A semiconductor device is known in which a semiconductor chip is mounted on a base portion, the semiconductor chip is covered with an insulating layer, and a wiring electrically connected to the semiconductor chip is provided on the insulating layer, the wiring being electrically connected to a terminal portion (for example, Patent Literature 1)

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Laid-Open No. 2023-133676

[0006] It is considered to use a bonding layer to bond a lead wire, which is a terminal electrically connected to a semiconductor element, to a wiring. However, the conductivity of the bonding layer is low, and thus the electrical resistance between the semiconductor element and the lead wire becomes high. SUMMARY

[0007] An object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof in which the electrical resistance between a semiconductor element and a lead wire can be reduced.

[0008] An embodiment of the present disclosure is a semiconductor device including: a semiconductor element; a first metal layer electrically connected to the semiconductor element; a bonding layer bonded to the first metal layer, the bonding layer being a sintered metal or a solder; a lead wire bonded to the bonding layer; and a second metal layer provided in a first hole that penetrates the bonding layer, the second metal layer electrically connecting the first metal layer and the lead wire.

[0009] A manufacturing method of a semiconductor device according to an embodiment of the present disclosure includes: forming a bonding layer on a first metal layer electrically connected to a semiconductor element, the bonding layer being a sintered metal or a solder; bonding a lead wire to the bonding layer; and forming a second metal layer in a first hole that penetrates the bonding layer, the second metal layer electrically connecting the first metal layer and the lead wire.

[0010] EFFECT OF THE INVENTION

[0011] According to the present disclosure, the electrical resistance between a semiconductor element and a lead wire can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a cross-sectional view of a semiconductor device of a first embodiment.

[0013] Figure 2 is a cross-sectional view of a semiconductor device of a comparative example.

[0014] Figure 3 This is a circuit diagram of the semiconductor device according to the second embodiment.

[0015] Figure 4A This is a top view of the semiconductor device according to the second embodiment.

[0016] Figure 4B yes Figure 4A A-A sectional view.

[0017] Figure 5A This is a top view of the area near the bonding layer in the second embodiment.

[0018] Figure 5B yes Figure 5A A-A sectional view.

[0019] Figure 6 This is a cross-sectional view of another example near the bonding layer in the second embodiment.

[0020] Figure 7A This is a top view illustrating the manufacturing method of the semiconductor device according to the second embodiment.

[0021] Figure 7B yes Figure 7A A-A sectional view.

[0022] Figure 8 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0023] Figure 9A This is a top view illustrating the manufacturing method of the semiconductor device according to the second embodiment.

[0024] Figure 9B yes Figure 9A A-A sectional view.

[0025] Figure 10 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0026] Figure 11 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0027] Figure 12 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0028] Figure 13A This is a top view illustrating the manufacturing method of the semiconductor device according to the second embodiment.

[0029] Figure 13B yes Figure 13A A-A sectional view.

[0030] Figure 14A This is a top view illustrating the manufacturing method of the semiconductor device according to the second embodiment.

[0031] Figure 14B yes Figure 14A A-A sectional view.

[0032] Figure 15A This is a top view illustrating the manufacturing method of the semiconductor device according to the second embodiment.

[0033] Figure 15B yes Figure 15A A-A sectional view.

[0034] Figure 16 yes Figure 15B A magnified view of the area near the bonding layer.

[0035] Figure 17A This is a top view illustrating the manufacturing method of the semiconductor device according to the second embodiment.

[0036] Figure 17B yes Figure 17A A-A sectional view.

[0037] Figure 18 yes Figure 17B A magnified view of the area near the bonding layer.

[0038] Figure 19A This is a top view illustrating the manufacturing method of the semiconductor device according to the second embodiment.

[0039] Figure 19B yes Figure 19A A-A sectional view.

[0040] Figure 20 yes Figure 19B A magnified view of the area near the bonding layer.

[0041] Explanation of reference numerals in the attached figures

[0042] 10: Base;

[0043] 12, 18: Insulation layer;

[0044] 12A, 20A (first hole), 24A (second hole): Holes;

[0045] 14: Via;

[0046] 16 (first metal layer), 16A, 16B, 22 (second metal layer), 22A (third metal layer): metal layers;

[0047] 17A, 17B, 17C (second wiring), 17D, 17E, 17F (first wiring): Partial;

[0048] 20: Bonding layer;

[0049] 21: Conductive paste;

[0050] 24, 24B (output lead), 24C (input lead): Leads;

[0051] 30: Semiconductor components;

[0052] 31, 36: substrate;

[0053] 32, 33, 34, 37, 38, 39, 42, 43: Electrodes;

[0054] 35, 35A, 35B: Passive components;

[0055] 40: Electronic components;

[0056] 41: Main body;

[0057] 50, 52: Matching circuit;

[0058] 54: Mask layer;

[0059] 54A: Opening;

[0060] 100, 102, 110: Semiconductor devices. Detailed Implementation

[0061] [Description of embodiments of this disclosure]

[0062] First, the implementation plan disclosed herein will be listed for illustration.

[0063] (1) An embodiment of the present disclosure is a semiconductor device comprising: a semiconductor element; a first metal layer electrically connected to the semiconductor element; a bonding layer bonded to the first metal layer, the bonding layer being a sintered metal or solder; a lead bonded to the bonding layer; and a second metal layer disposed in a first hole penetrating the bonding layer, electrically connecting the first metal layer to the lead. This reduces the resistance between the first metal layer and the lead, thereby improving the characteristics of the semiconductor device.

[0064] (2) In (1) above, the conductivity of the second metal layer may also be higher than that of the bonding layer. This reduces the resistance between the first metal layer and the lead.

[0065] (3) In (1) or (2) above, the bonding layer may also be a sintered metal containing resin. This reduces the resistance between the first metal layer and the leads, even when the conductivity of the bonding layer is low.

[0066] (4) In any of (1) to (3) above, the lead wire may have a second hole penetrating the lead wire, and when viewed from the stacking direction of the second metal layer and the lead wire, the second hole overlaps with the first hole. Thus, the first hole can be formed.

[0067] (5) In (4) above, the first hole may be smaller than the second hole when viewed from the stacking direction, and the semiconductor device may have a third metal layer disposed on the bonding layer within the second hole, thereby electrically connecting the second metal layer to the lead. Thus, the second metal layer can be electrically connected to the lead.

[0068] (6) In any of (1) to (5) above, the semiconductor device may also include: a conductive substrate on which the semiconductor element is mounted; and an insulating layer disposed on the substrate to cover the semiconductor element, wherein the first metal layer is disposed on the upper surface of the insulating layer. This improves performance.

[0069] (7) In (6) above, the semiconductor device may also include electronic components disposed on the insulating layer and electrically connected to the leads or the semiconductor element. This enables miniaturization.

[0070] (8) In (6) or (7) above, the semiconductor device may also include a passive element mounted on the substrate, the leads including an input lead and an output lead, the semiconductor element having a transistor that amplifies a high-frequency signal input to the input lead and outputs the amplified high-frequency signal from the output lead, the first metal layer including a first wiring electrically connecting the input lead to the transistor and a second wiring electrically connecting the output lead to the transistor, and the passive element having a capacitor electrically connected to the first wiring or the second wiring. This improves high-frequency characteristics.

[0071] (9) In any of (1) to (7) above, the semiconductor element may also process high-frequency signals. This improves high-frequency characteristics.

[0072] (10) An embodiment of this disclosure is a method for manufacturing a semiconductor device, the method comprising the following steps: forming a bonding layer on a first metal layer electrically connected to a semiconductor element, the bonding layer being a sintered metal or solder; bonding a lead to the bonding layer; and forming a second metal layer electrically connecting the first metal layer and the lead in a first hole penetrating the bonding layer. This allows the formation of a second metal layer electrically connecting the first metal layer and the lead. Consequently, the resistance between the first metal layer and the lead can be reduced, and the characteristics of the semiconductor device can be improved.

[0073] (11) In (10) above, the lead may also have a second hole penetrating the lead, and the method of manufacturing the semiconductor device includes the following steps: after the step of bonding the lead and before the step of forming the second metal layer, forming a first hole in the bonding layer that is connected to the second hole and penetrates the bonding layer. Thus, the first hole can be formed.

[0074] [Details of the embodiments of this disclosure]

[0075] Hereinafter, specific examples of semiconductor devices and manufacturing methods of the present disclosure according to embodiments will be described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is illustrated by the claims and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0076] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment. The stacking direction of the bonding layer 20 and the lead 24, which is the thickness direction of the substrate 10, is designated as the Z direction; the arrangement direction of the lead 24 is designated as the X direction; and the direction orthogonal to both the X and Z directions is designated as the Y direction. Figure 1 As shown, the semiconductor device 100 includes a substrate 10, an insulating layer 12, an insulating layer 18, a via 14, a metal layer 16, a bonding layer 20, a metal layer 22, a lead 24, a semiconductor element 30, a passive element 35, and an electronic component 40.

[0077] Semiconductor element 30 and passive element 35 are mounted on substrate 10. Semiconductor element 30 has substrate 31, electrode 32 and electrode 33 disposed on the upper surface of substrate 31, and electrode 34 disposed on the lower surface of substrate 31. Passive element 35 has electrode 37 and electrode 38 disposed on the upper surface of substrate 36, and electrode 39 disposed on the lower surface of substrate 36. Electrode 34 and electrode 39 are bonded to substrate 10, for example, using a conductive bonding layer.

[0078] An insulating layer 12 is disposed on a substrate 10 to cover semiconductor element 30 and passive element 35. Vias 14 penetrate the insulating layer 12 and are electrically connected to electrodes 32 and 33 of the semiconductor element 30 and electrodes 37 and 38 of the passive element 35. A metal layer 16 is disposed on the insulating layer 12. The metal layer 16 is electrically connected to electrodes 32 and 33 of the semiconductor element 30 and electrodes 37 and 38 of the passive element 35 via the vias 14. An electronic component 40 is mounted on the metal layer 16. The electronic component 40 has a body 41, electrodes 42 and 43. Electrodes 42 and 43 are disposed on the surface of the body. Electrodes 42 and 43 are bonded to the metal layer 16, for example, using a conductive bonding layer.

[0079] A bonding layer 20 is bonded to a metal layer 16. A lead 24 is bonded to a bonding layer 20. The bonding layer 20 has a hole 20A extending through the bonding layer 20 in the Z direction. A metal layer 22 is disposed within the hole 20A, electrically connecting the metal layer 16 and the lead 24. An insulating layer 18 is disposed on an insulating layer 12 to cover the metal layer 16, the bonding layer 20, a portion of the lead 24, and the electronic component 40. A portion of the lead 24 extends from and is exposed from the insulating layer 18 in the X direction.

[0080] At least the upper surface of the substrate 10 is conductive. The substrate 10 is, for example, a metal plate such as a copper plate, copper, molybdenum, or a copper laminate. Insulating layers 12 and 18 are, for example, resins such as epoxy resin. Vias 14, metal layers 16 and 22 are, for example, metal layers such as copper layers. The bonding layer 20 is sintered metal or solder. The sintered metal is, for example, conductive paste formed by sintering conductive pastes such as silver paste, copper paste, gold paste, or gold-tin paste. The solder is, for example, tin-silver-copper solder, tin-silver solder, or gold-tin solder. The lead 24 is, for example, a copper-based material or an iron-based material.

[0081] Semiconductor element 30 is a semiconductor chip, such as a transistor with a FET (Field Effect Transistor). Substrate 31 is, for example, a semiconductor substrate. Electrodes 32, 33, and 34 are, for example, metal layers such as gold, copper, or aluminum.

[0082] Passive component 35 is a passive chip, such as a capacitor or inductor. Substrate 36 is a dielectric substrate, such as an alumina substrate or a barium titanate substrate. Electrodes 37, 38, and 39 are, for example, metal layers such as gold, copper, aluminum, or nickel. Electronic component 40 is, for example, a discrete chip capacitor, chip inductor, or chip resistor.

[0083] (Comparison method)

[0084] Figure 2 This is a cross-sectional view of a semiconductor device in a comparative manner. For example... Figure 2 As shown, in the semiconductor device 110 of the comparison mode, the metal layer 22 is not provided in the bonding layer 20.

[0085] As with the semiconductor device 110 of the comparative embodiment, a bonding layer 20 is used to bond the lead 24 to the metal layer 16. The bonding layer 20 has low conductivity. For example, with respect to sintered metal formed by sintering conductive paste, the conductivity is, for example, 0.1 × 10⁻⁶. 6 S / m up to 30×10 6 S / m. Regarding the solder, the conductivity is, for example, 6 × 10⁻⁶. 6 S / m to 9×10 6S / m. Therefore, the resistance between lead 24 and metal layer 16 increases, and the resistance between lead 24 and semiconductor element 30 increases. As a result, the characteristics of semiconductor device 110 deteriorate.

[0086] (Description of the first embodiment)

[0087] According to the first embodiment, a metal layer 22 (second metal layer) is disposed within a hole 20A (first hole) penetrating the bonding layer 20, electrically connecting the metal layer 16 (first metal layer) to the lead 24. Thus, by electrically connecting the metal layer 16 and the lead 24 with the metal layer 22, the resistance between the metal layer 16 and the lead 24 can be reduced, thereby improving the characteristics of the semiconductor device 100.

[0088] The conductivity of metal layer 22 is higher than that of bonding layer 20. This reduces the resistance between metal layer 16 and lead 24. For example, when copper is used as metal layer 22, its conductivity is approximately 65 × 10⁻⁶. 6 S / m. The conductivity of the metal layer 22 can be set to more than twice the conductivity of the bonding layer 20, or more than five times the conductivity of the bonding layer 20. When the conductivity of the bonding layer 20 is too low, the resistance between the metal layer 16 and the lead 24 will increase. From this point of view, the conductivity of the metal layer 22 can also be less than 10,000 times the conductivity of the bonding layer 20.

[0089] Solder melts above its melting point, so the bonding layer 20 may melt during the mounting of the semiconductor device 100. Therefore, sintered metal can be used as the bonding layer 20. The sintered metal contains resins such as epoxy resin after curing. For example, when the bonding layer 20 is formed using a conductive paste containing silver-coated copper powder, the resin content in the bonding layer 20 is 8% to 10% by mass, and the silver-coated copper powder content is 90% to 92% by mass. Furthermore, when other conductive pastes are used, the resin content in the bonding layer 20 is 14% to 16% by mass, and the silver-coated copper powder content is 84% ​​to 86% by mass.

[0090] Thus, when the bonding layer 20 contains resin, the conductivity of the bonding layer 20 decreases. Therefore, by providing the metal layer 22, the resistance between the metal layer 16 and the lead 24 can be reduced. The resin in the bonding layer 20 is, for example, 1% by mass or more, or 5% by mass or more. Furthermore, the resin in the bonding layer 20 is, for example, 30% by mass or less, or 20% by mass or less.

[0091] The semiconductor element 30 is mounted on a conductive substrate 10. By mounting the semiconductor element 30 on the conductive substrate 10, the conductive substrate 10 can be used as a heat sink. This improves heat dissipation. From the viewpoint of heat dissipation, the thickness of the conductive substrate 10 is, for example, 1 mm or more. When bonding wires are used in the electrical connection between the semiconductor element 30 and the passive element 35 or the terminal portion, an inductive component is added, thereby degrading the high-frequency characteristics. Furthermore, the current capacity cannot be increased. Therefore, as in Patent Document 1, the terminal portion and the base are formed from the same metal plate, and the metal layer 16 on the insulating layer 12 is used to make the electrical connection between the semiconductor element 30 and the passive element 35 or the terminal portion. This improves the high-frequency characteristics. Furthermore, the current capacity can be increased. However, the terminal portion is electrically connected from the lower surface of the semiconductor device. This requires the use of leads to make the electrical connection from the side of the semiconductor device. When it is desired to electrically connect the lead 24 to the metal layer 16, as in the comparative semiconductor device 110, a bonding layer 20, such as sintered metal or solder, is used to connect the metal layer 16 to the lead 24. However, the bonding layer 20 has low conductivity, thus degrading high-frequency characteristics. Furthermore, it cannot increase current capacity. Therefore, by using the metal layer 22, high-frequency characteristics can be improved. Furthermore, current capacity can be increased. Thus, the characteristics of the semiconductor device can be improved.

[0092] Electronic component 40 is mounted on insulating layer 12 and electrically connected to lead 24 or semiconductor element 30. Thus, electronic component 40 can be mounted above semiconductor element 30 and passive element 35, thereby enabling miniaturization of semiconductor device 100.

[0093] (Second Implementation)

[0094] The second embodiment is an example of using a semiconductor device in an amplification device. Figure 3 This is a circuit diagram of the semiconductor device according to the second embodiment. (Example) Figure 3 As shown, the semiconductor device 102 includes an input terminal Tin, an output terminal Tout, a matching circuit 50, a matching circuit 52, and a transistor Q1.

[0095] A high-frequency signal is input to the input terminal Tin. In the case where the semiconductor device 102 is used as a power amplifier in a mobile communication base station, the frequency of the high-frequency signal is, for example, 0.5 GHz or higher and 20 GHz or lower.

[0096] Matching circuit 52 includes lines L3, L4, L5, capacitor C2, and capacitor C3. Lines L3 to L5 are connected in series between the gate of transistor Q1 and the input terminal Tin. Capacitor C2 is shunt-connected at the node between lines L3 and L4. Capacitor C3 is shunt-connected at the node between lines L4 and L5. Matching circuit 52 matches the impedance when viewed from the input terminal Tin towards matching circuit 52 with the impedance when viewed from matching circuit 52 towards transistor Q1.

[0097] Transistor Q1 is a FET, having a source (S), a drain (D), and a gate (G). The source (S) is grounded and supplied with a reference potential, such as ground. The gate (G) is electrically connected to the input terminal Tin via matching circuit 52. The drain (D) is electrically connected to the output terminal Tout via matching circuit 50. Transistor Q1 amplifies the high-frequency signal input to the gate (G) and outputs the amplified high-frequency signal to the drain (D).

[0098] Matching circuit 50 includes lines L1 and L2, and capacitor C1. Lines L1 and L2 are connected in series between the drain D of transistor Q1 and the output terminal Tout. Capacitor C1 is shunt to the node between lines L1 and L2. Matching circuit 50 matches the impedance from transistor Q1 to matching circuit 50 with the impedance from matching circuit 50 to output terminal Tout. Output terminal Tout outputs the amplified high-frequency signal from transistor Q1.

[0099] Figure 4A This is a top view of the semiconductor device according to the second embodiment. Figure 4B yes Figure 4A A-A sectional view. Figure 4A The insulating layer 18 is not shown; instead, semiconductor element 30, passive element 35A, passive element 35B, and via 14 are shown in dashed lines.

[0100] like Figure 4A and Figure 4B As shown, in the semiconductor device 102, semiconductor element 30, passive element 35A and passive element 35B are mounted on substrate 10. Figure 3 Transistor Q1 is disposed on semiconductor element 30. Electrodes 33, 32 and 34 are electrically connected to gate G, drain D and source S, respectively.

[0101] An electrode 37 is provided on the upper surface of passive component 35A. Electrode 37 and electrode 39, separated by substrate 36, form capacitor C1. Electrode 37 and electrode 38 are provided on the upper surface of passive component 35B. Electrode 37 and electrode 39, separated by substrate 36, form capacitor C2. Electrode 38 and electrode 39, separated by substrate 36, form capacitor C3.

[0102] Metal layer 16 has portions 17A to 17F. Portion 17A is for bonding lead 24B. Portion 17C is for connecting electrode 32 of semiconductor element 30 via via 14. Portion 17B connects portion 17A and portion 17C. Portion 17F is for bonding lead 24C. Portion 17D is for connecting electrode 33 of semiconductor element 30 via via 14. Portion 17E connects portion 17D and portion 17F. Multiple portions 17B are arranged in the Y direction, and multiple portions 17E are arranged in the Y direction.

[0103] Part 17B forms lines L1 and L2. Part 17E forms lines L3 to L5. The number, length, and width of parts 17B and 17E can be appropriately set in a way that the desired high-frequency characteristics are obtained from lines L1 to L5.

[0104] Lead 24B, electrically connected to portion 17A, forms output terminal Tout. Lead 24C, electrically connected to portion 17F, forms input terminal Tin. Leads 24B and 24C have a hole 24A that passes through leads 24B and 24C in the Z direction.

[0105] Transistor Q1 is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). When transistor Q1 is a GaN HEMT, substrate 31 is, for example, a silicon carbide substrate. When the transistor is an LDMOS, substrate 31 is, for example, a silicon substrate.

[0106] Figure 5A This is a top view of the area near the bonding layer in the second embodiment. Figure 5B yes Figure 5A A-A sectional view. In Figure 5A The figure shows metal layer 16, bonding layer 20, lead 24B, hole 20A and hole 24A.

[0107] like Figure 5A and Figure 5BAs shown, a metal layer 16 is provided on the insulating layer 12. A bonding layer 20 bonds the metal layer 16 to the lead 24B. The bonding layer 20 has a through hole 20A in the Z direction. A metal layer 22 is embedded in the through hole 20A. The lead 24B has a through hole 24A in the Z direction. When viewed from the Z direction, the through hole 24A is larger than the through hole 20A, and the through hole 24A is connected to the through hole 20A. A portion of the bonding layer 20 extends into the through hole 24A, and a portion of the through hole 20A is disposed within the bonding layer 20 in the through hole 24A. A metal layer 22A is provided on the surfaces of the bonding layer 20 and the lead 24B. An insulating layer 18 is provided on the insulating layer 12 to cover the metal layer 16, the bonding layer 20, and the lead 24B.

[0108] The thickness of substrate 10 is, for example, 800 μm to 1400 μm. The thickness of insulating layer 12 is, for example, 100 μm to 300 μm. The thickness of metal layer 16 is, for example, 35 μm to 45 μm. The thickness of bonding layer 20 is, for example, 1 μm to 50 μm. The thickness of lead 24 is, for example, 80 μm to 200 μm. The thickness of insulating layer 18 is, for example, 1000 μm to 3000 μm. The width of insulating layer 18 in the X and Y directions is, for example, 5 mm to 20 mm. The thickness of metal layer 22A is, for example, 8 μm to 35 μm. The diameter (width) of hole 20A is, for example, 100 μm to 400 μm. The diameter (width) of hole 24A is, for example, 140 μm to 500 μm.

[0109] Figure 6 This is a cross-sectional view of another example near the bonding layer in the second embodiment. Figure 5A A-A sectional view. For example... Figure 6 As shown, the metal layer 22 can also be disposed on the side and bottom surfaces of the hole 24A, instead of in the center of the hole 24A. Other configurations are the same as... Figure 5B Same, explanation omitted.

[0110] (Manufacturing method of the second embodiment)

[0111] Figure 7A to Figure 20 This is a diagram illustrating a method for manufacturing a semiconductor device according to the second embodiment. Figure 7A This is a top view illustrating a method for manufacturing a semiconductor device according to the second embodiment. Figure 7B yes Figure 7A A-A sectional view. For example... Figure 7A and Figure 7BAs shown, a semiconductor element 30, a passive element 35A, and a passive element 35B are mounted on a substrate 10. Electrodes 32 and 33 extend in the Y direction. Multiple electrodes 37 and 38 are arranged in the Y direction. In the passive element 35B, electrodes 37 and 38 are arranged in the X direction. A conductive bonding layer is used in mounting the semiconductor element 30, passive element 35A, and passive element 35B. The conductive bonding layer is, for example, a conductive paste, and the semiconductor element 30, passive element 35A, and passive element 35B are mounted on the substrate 10 with the conductive paste in between. Subsequently, the conductive paste is sintered to form the conductive bonding layer by heat treatment.

[0112] Figure 8 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment. (e.g.) Figure 8 As shown, an insulating layer 12 is formed on the substrate 10 to cover semiconductor element 30, passive element 35A, and passive element 35B. The insulating layer 12 can be formed, for example, using lamination or compression molding. The insulating layer 12 is then cured by heat treatment. Planarization can also be achieved by grinding the upper surface of the insulating layer 12.

[0113] Figure 9A This is a top view illustrating a method for manufacturing a semiconductor device according to the second embodiment. Figure 9B yes Figure 9A A-A sectional view. For example... Figure 9A and Figure 9B As shown, holes 12A are formed in the insulating layer 12. The holes 12A are formed, for example, by laser irradiation. The holes 12A expose the upper surfaces of electrodes 32, 33, 37, and 38 from the insulating layer 12. Multiple holes 12A connected to electrodes 32 and 33 are arranged in the Y direction. Three holes 12A are connected to electrode 37, and one hole 12A is connected to electrode 38. The number of holes 12A connected to each electrode 32, 33, 37, and 38, as well as the planar shape of the holes 12A, can be appropriately set.

[0114] Figure 10 to Figure 12 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment. (e.g.) Figure 10 As shown, a desmearing process is performed to remove resin residue from when the hole 12A was formed. A via 14 is formed in the hole 12A using a chemical plating method, and a metal layer 16A is formed on the upper surface of the insulating layer 12.

[0115] Next, as Figure 11As shown, a mask layer 54 is formed on the metal layer 16A. The mask layer 54 is, for example, a photosensitive resin layer, formed using a lamination method. Exposure and development are performed to form the opening 54A. Then, as... Figure 12 As shown, metal layer 16A is used as a seed layer, and metal layer 16B is formed in the opening 54A by electroplating.

[0116] Figure 13A This is a top view illustrating a method for manufacturing a semiconductor device according to the second embodiment. Figure 13B yes Figure 13A A-A sectional view. For example... Figure 13A and Figure 13B As shown, mask layer 54 is peeled off. Metal layer 16A is removed using metal layer 16B as a mask. Then, metal layers 16A and 16B are collectively represented as metal layer 16. Multiple vias 14 connected to electrode 32 are connected to portion 17C. Multiple vias 14 connected to electrode 33 are connected to portion 17D. Vias 14 connected to electrode 37 of passive element 35A are connected to portion 17B. Vias 14 connected to electrodes 37 and 38 of passive element 35B are connected to portion 17E.

[0117] Figure 14A This is a top view illustrating a method for manufacturing a semiconductor device according to the second embodiment. Figure 14B yes Figure 14A A-A sectional view. For example... Figure 14A and Figure 14B As shown, conductive paste 21 is formed on portions 17A and 17F of the metal layer 16 using a printing method.

[0118] Figure 15A This is a top view illustrating a method for manufacturing a semiconductor device according to the second embodiment. Figure 15B yes Figure 15A A-A sectional view. Figure 16 yes Figure 15B A magnified view of the area near the bonding layer 20. (See image below.) Figure 15A , Figure 15B as well as Figure 16 As shown, leads 24B and 24C are attached to conductive paste 21 such that holes 24A of lead 24B and 24A of lead 24C are located on conductive paste 21. Leads 24B and 24C are, for example, metal foils, pre-processed into the desired shape. Leads 24B and 24C are connected to the frame of the metal foil via connecting rods. Thus, leads 24B and 24C can be attached to conductive paste 21 as a single unit. At this time, leads 24B and 24C are pressed into conductive paste 21, thereby... Figure 16 In this way, conductive paste 21 is introduced into at least a portion of the hole 24A. Then, the conductive paste 21 is sintered by heat treatment to form the bonding layer 20.

[0119] Figure 17A This is a top view illustrating a method for manufacturing a semiconductor device according to the second embodiment. Figure 17B yes Figure 17A A-A sectional view. Figure 18 yes Figure 17B A magnified view of the area near the bonding layer 20. (See image below.) Figure 17A , Figure 17B as well as Figure 18 As shown, a hole 20A penetrating the bonding layer 20 is formed through the bonding layer 20 via a hole 24A. The hole 20A is formed by irradiating the hole 24A with a laser. The size of the hole 20A when viewed from the Z direction is smaller than the size of the hole 24A when viewed from the Z direction. The hole 20A exposes the surfaces of portions 17A and 17F of the metal layer 16. In portion 17A, a column of multiple holes 20A and 24A arranged in the Y direction is provided, but multiple columns of multiple holes 20A and 24A arranged in the Y direction can also be provided in the X direction.

[0120] Figure 19A This is a top view illustrating a method for manufacturing a semiconductor device according to the second embodiment. Figure 19B yes Figure 19A A-A sectional view. Figure 20 yes Figure 19B A magnified view of the area near the bonding layer 20. (See image below.) Figure 19A , Figure 19B as well as Figure 20 As shown, a metal layer 22 is formed within the hole 20A. Electroplating is used to form the metal layer 22. By electroplating, a metal layer 22A is formed on the bonding layer 20 and the surfaces of leads 24B and 24C. This metal layer 22A uses the same material as the metal layer 22. Lead 24B is electrically connected to the metal layer 22 through the metal layer 22A provided on the upper surface of the bonding layer 20 within the hole 24A.

[0121] Next, electronic components 40 are mounted on the metal layer 16 (see reference). Figure 1 ), then, as Figure 4A and Figure 4B An insulating layer 18 is formed in this way. The insulating layer 18 is formed, for example, using a transfer molding method. Then, monolithization is achieved by cutting the connecting rods of the connecting leads. Through the above processes, the semiconductor device 102 of the second embodiment is manufactured.

[0122] According to the second embodiment, such as Figure 14A and Figure 14B Thus, a bonding layer 20 is formed on the metal layer 16 (first metal layer) electrically connected to the semiconductor element 30. This bonding layer 20 is either sintered metal or solder. Figure 15A to Figure 16In this way, leads 24B and 24C are bonded to the bonding layer 20. Figure 19A to Figure 20 In this way, a metal layer 22 (second metal layer) is formed through the bonding layer 20, electrically connecting the metal layer 16 to the leads 24B and 24C. Thus, a metal layer 22 electrically connecting the metal layer 16 to the leads 24B and 24C can be formed.

[0123] After the process of bonding leads 24B and 24C and before the process of forming metal layer 22, such as Figure 17A to Figure 18 Thus, a hole 20A is formed in the bonding layer 20, which is connected to and penetrates the hole 24A (the second hole). Therefore, leads 24B and 24C are bonded to the bonding layer 20, and after the bonding layer 20 is cured, the hole 20A is formed. When the hole 20A is thus formed, when viewed from the Z direction (the stacking direction of the bonding layer 20 and leads 24B and 24C), the hole 24A overlaps with the hole 20A.

[0124] like Figure 5B and Figure 6 Thus, when viewed from the Z direction, hole 20A is smaller than hole 24A, and metal layer 22A (third metal layer) is disposed on bonding layer 20 inside hole 24A, electrically connecting metal layer 22 to lead 24B. A third metal layer is provided. Therefore, metal layer 22 and metal layer 22A can electrically connect metal layer 16 to lead 24B.

[0125] As a second embodiment, a semiconductor element 30 that processes high-frequency signals has been described as an example, but the semiconductor element 30 may not process high-frequency signals. In the case of the semiconductor element 30 that processes high-frequency signals, the high-frequency characteristics deteriorate when the resistance between the leads 24B and 24C and the semiconductor element 30 is high. As with the semiconductor device 102 of the second embodiment, when a semiconductor element 30 for processing high-frequency signals is provided, a metal layer 22 can be provided. This improves the high-frequency characteristics.

[0126] Semiconductor element 30 has a transistor Q1 that amplifies a high-frequency signal input to lead 24C (input lead) and outputs the amplified high-frequency signal from lead 24B (output lead). Portions 17A to 17C in metal layer 16 include a second wiring electrically connecting lead 24B to the transistor. Portions 17D to 17F in metal layer 16 include a first wiring electrically connecting lead 24C to the transistor. Passive elements 35A and 35B have capacitors C1 to C3 electrically connected to portions 17B and 17E, respectively. Thus, it is possible to... Figure 3Transistor Q1, along with matching circuits 50 and 52, are mounted on substrate 10. In high-frequency amplifier circuits, reducing the resistance between leads 24B and 24C and semiconductor element 30 is important to improve high-frequency characteristics. Therefore, metal layer 22 can be provided. In particular, reducing the resistance between leads 24B and 24C and semiconductor element 30 is crucial in high-frequency amplifier circuits with output power of 10W or higher.

[0127] The embodiments disclosed herein should be considered exemplary and not limiting in all respects. The scope of this disclosure is not as foregoing, but as set forth in the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: Semiconductor components; A first metal layer is electrically connected to the semiconductor element; A bonding layer is bonded to the first metal layer, wherein the bonding layer is a sintered metal or solder; Lead wires are bonded to the bonding layer; as well as A second metal layer is disposed within a first hole penetrating the bonding layer, electrically connecting the first metal layer to the lead.

2. The semiconductor device according to claim 1, wherein, The conductivity of the second metal layer is higher than that of the bonding layer.

3. The semiconductor device according to claim 1 or 2, wherein, The bonding layer is a sintered metal containing resin.

4. The semiconductor device according to claim 1 or 2, wherein, The lead wire has a second hole through it. When viewed from the stacking direction of the second metal layer and the lead, the second hole overlaps with the first hole.

5. The semiconductor device according to claim 4, wherein, When viewed from the stacking direction, the first hole is smaller than the second hole. The semiconductor device includes a third metal layer disposed on the bonding layer within the second hole, which electrically connects the second metal layer to the lead.

6. The semiconductor device according to claim 1 or 2, comprising: A conductive substrate on which the semiconductor element is mounted; and An insulating layer is disposed on the substrate to cover the semiconductor element, and a first metal layer is disposed on the upper surface of the insulating layer.

7. The semiconductor device according to claim 6, wherein, The semiconductor device includes electronic components disposed on the insulating layer and electrically connected to the leads or the semiconductor element.

8. The semiconductor device according to claim 6, wherein, The semiconductor device includes passive components mounted on the substrate. The leads include input leads and output leads. The semiconductor element has a transistor that amplifies a high-frequency signal input to the input lead and outputs the amplified high-frequency signal from the output lead. The first metal layer includes a first wiring that electrically connects the input lead to the transistor and a second wiring that electrically connects the output lead to the transistor. The passive element has a capacitor electrically connected to the first wiring or the second wiring.

9. The semiconductor device according to claim 1 or 2, wherein, The semiconductor element processes high-frequency signals.

10. A method for manufacturing a semiconductor device, comprising the following steps: A bonding layer is formed on a first metal layer that is electrically connected to a semiconductor element, the bonding layer being a sintered metal or solder; Bonding the leads to the bonding layer; and A second metal layer is formed within a first hole penetrating the bonding layer to electrically connect the first metal layer to the lead.

11. The method of manufacturing a semiconductor device according to claim 10, wherein, The lead wire has a second hole through it. The method of manufacturing the semiconductor device includes the following steps: after the step of bonding the leads and before the step of forming the second metal layer, forming a first hole in the bonding layer that is connected to the second hole and penetrates the bonding layer.

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