Semiconductor device including imprined die pad

Abstract

A semiconductor device including an embossed die pad includes a die pad having a top surface and a bottom surface, and a semiconductor die mounted on the top surface of the die pad. The bottom surface of the die pad includes an unimprinted region and at least two imprinted edge regions. The die pad includes an unembossed connection strip disposed between two embossed edge regions of the bottom surface. An area of the top surface is larger than an area of an unimprinted region of the bottom surface.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices including an embossed die pad and associated manufacturing methods. BACKGROUND

[0002] A semiconductor device can include a die pad for mounting a semiconductor die, wherein a size of the die pad can be determined by a footprint compatibility requirement. Accordingly, a mounting surface of the die pad can be limited to a specific mounting area, such that only semiconductor dies reaching a specific size can be mounted on the die pad. In view of the above, it can be desirable to provide a die pad and a semiconductor device having a sufficient mounting area while satisfying an existing footprint compatibility requirement. Further, it can be desirable to provide a simple and cost-effective method for manufacturing the die pad and the semiconductor device. SUMMARY

[0003] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a die pad including a top surface and a bottom surface. The semiconductor device further includes a semiconductor die mounted on the top surface of the die pad. The bottom surface of the die pad includes an unembossed region and at least two embossed edge regions. The die pad includes an unembossed connecting strip arranged between the two embossed edge regions of the bottom surface. An area of the top surface is greater than an area of the unembossed region of the bottom surface.

[0004] Another aspect of the present disclosure relates to a method. The method includes a step of providing a metal panel. The method further includes a step of forming a plurality of first openings in the metal panel to form a lead frame panel including a plurality of die pads arranged in a row, wherein two adjacent die pads are separated by two first openings arranged side by side and connected by a connecting strip between the two first openings. The method further includes a step of embossing edge regions of a bottom surface of the die pads, wherein a material of the die pads is pressed into regions of the first openings. The method further includes a step of forming a plurality of second openings at locations of the plurality of first openings to remove the material pressed into the regions of the first openings, wherein each second opening is wider than the first openings, wherein the two adjacent die pads are still connected by the connecting strip.

[0005] Another aspect of the present disclosure relates to a method. The method includes a step of providing a leadframe panel including a plurality of die pads arranged in a plurality of rows. Each die pad includes a top surface and a bottom surface. The bottom surface of each die pad includes a stamped edge region and an unstamped region. An area of the top surface is greater than an area of the unstamped region of the bottom surface. The method further includes a step of mounting a plurality of semiconductor dies on the top surfaces of the die pads. The method further includes a step of attaching a plurality of clips on top of the semiconductor dies. The method further includes a step of performing an encapsulation process, wherein a plurality of strips are formed from an encapsulation material, wherein each strip encapsulates a row of die pads. The method further includes a step of singulating the plurality of strips into a plurality of semiconductor packages. BRIEF DESCRIPTION OF DRAWINGS

[0006] Devices and methods according to the present disclosure are described in more detail below based on the drawings. The elements of the drawings are not necessarily to scale relative to each other. Like designations can designate corresponding similar parts. The technical features of the various illustrated examples can be combined unless they are mutually exclusive, and / or can be selectively omitted if not necessary for describing.

[0007] Figures 1A-1C Different views of a die pad 100 that can be included in a semiconductor device according to the present disclosure are shown.

[0008] Figure 2A And Figure 2B Different views of a semiconductor device 200 according to the present disclosure are shown.

[0009] Figure 3A And Figure 3B Different views of a semiconductor device 300 according to the present disclosure are shown.

[0010] Figure 4 A flowchart of a method according to the present disclosure is shown.

[0011] Figures 5A-5E A method according to the present disclosure is schematically shown.

[0012] Figure 6 A flowchart of a method according to the present disclosure is shown.

[0013] Figures 7A-7F A method for manufacturing a semiconductor device 700 according to the present disclosure is schematically shown. DETAILED DESCRIPTION

[0014] In the following detailed description, reference is made to the accompanying drawings, which illustrate, by way of example, certain aspects of the disclosure. In this regard, directional terminology, such as "top," "bottom," "front," "back," etc., can be used with reference to the orientation of the described drawings. Because components of the described devices can be positioned in a number of different orientations, the directional terminology can be used for purposes of illustration and is in no way limiting. Other aspects can be utilized and structural or logical changes can be made without departing from the concept of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0015] Reference is now made to Figures 1A-1C FIGS. 1-3, different views of a die pad 100 that can be included in a semiconductor device in accordance with the present disclosure are shown. Note that, for example, in conjunction with Figures 5A-5E An exemplary method for fabricating one or more of such die pads is shown and described. The die pad 100 can include or be made of a metal or metal alloy. For example, the die pad 100 can include a core material that includes at least one of copper, a copper alloy, aluminum, an aluminum alloy, etc. Optionally, the die pad 100 can be plated with at least one plating material that can include, for example, at least one of nickel, nickel-phosphorous, nickel-nickel-phosphorous, copper, silver, etc. The plating material can cover the entire die pad 100 (or its core material) or only selected portions thereof. It should be appreciated that the core material and plating material of the die pad 100 can depend on the type of semiconductor die that is to be mounted on the die pad 100 and / or the material of the electrical connection elements (e.g., wires, ribbons, clips, etc.) that are to be connected to the die pad 100.

[0016] The die pad 100 can include a top surface 10 and an opposing bottom surface 12. The bottom surface 12 of the die pad 100 can include an un-embossed region 16 and at least two embossed edge regions 14. The thickness of the embossed edge regions 14 can be less than the thickness of the un-embossed region 16 when measured in a direction perpendicular to the top surface 10 or the bottom surface 12 (i.e., in the z-direction). In the illustrated example, the bottom surface 12 can include an exemplary number of three embossed edge regions 14A-C. In further examples, the number of embossed edge regions 14 can be two or even higher than three. In the illustrated example, the un-embossed region 16 is disposed between the three embossed edge regions 14A-C. In other examples, the un-embossed region 16 can be disposed between two embossed edge regions 14 or even higher than three. In the illustrated example, the die pad 100 includes a core material that includes at least one of copper, a copper alloy, aluminum, an aluminum alloy, etc. Optionally, the die pad 100 can be plated with at least one plating material that can include, for example, at least one of nickel, nickel-phosphorous, nickel-nickel-phosphorous, copper, silver, etc. Figure 1CIn the exemplary top view of the bottom surface 12 shown, the bottom surface 12 of the die pad 100 may include a first imprinted edge region 14A disposed on the lower side of the die pad 100 and a second imprinted edge region 14B disposed on the upper side of the die pad 100 opposite to the lower side. In the illustrated case, each of the imprinted edge regions 14A and 14B may have a substantially rectangular shape. In other examples, the shape or form of the imprinted edge regions 14 may be different. In an exemplary embodiment, the bottom surface 12 may have only two imprinted regions 14A and 14B, while Figure 1C The region 14C shown can be an unprinted region, that is, its thickness can be the same as that of the unprinted region 16.

[0017] The bottom surface 12 of the die pad 100 may optionally include a surface disposed on Figure 1C The third imprinted edge region 14C is located on the right side of the die pad 100 and connects the lower and upper sides of the die pad 100. In the illustrated example, the third imprinted edge region 14C may extend along the entire right side of the die pad 100 and partially along the lower and upper sides of the die pad 100. Therefore, the third imprinted edge region 14C may have a left-opening letter "U" shape. The imprinted edge regions 14A to 14C may be separated by portions of the unimprinted region 16.

[0018] Since the bottom surface 12 of the die pad 100 may include imprinted edge regions 14A to 14C (while the top surface 10 does not), the area of ​​the top surface 10 can be larger than the area of ​​the unimprinted region 16 of the bottom surface 12. In the illustrated example, the imprinted edge regions 14A to 14C may surround the unimprinted region 16 on three sides of the die pad 100. In another example, the die pad 100 may not necessarily include a third imprinted edge region 14C; that is, the imprinted edge regions 14A and 14B may be arranged on two opposite sides of the die pad 100, while the other two sides of the die pad 100 may not have imprinted edge regions.

[0019] When measured in the z-direction, the thickness of the imprinted edge regions 14A to 14C can range from about 60% to about 90% of the thickness of the unimprinted region 16 (and more specifically, from about 85% to about 90%). In other words, when measured in the z-direction, the imprinting depth can range from about 10% to about 40% of the thickness of the unimprinted region 16 (and more specifically, from about 10% to about 15%). The dimension d of the first imprinted edge region 14A, measured in the y-direction, is... A The size can range from about 0.2 mm to about 0.6 mm. The dimension d of the second imprinted edge region 14B, measured in the y-direction. B It can be similar to size d AThe dimension d of the third imprinted edge region 14C, measured in the x-direction. C The dimensions can range from about 0.4 mm to about 0.8 mm. All three dimensions can be varied depending on footprint requirements and / or stamping processes. Optionally, larger areas in regions 14A to 14C can improve the stability of the molding compound disposed beneath them.

[0020] The die pad 100 may include at least one unprinted connecting strip 18 disposed between two imprinted edge regions 14 on the bottom surface 12. During the manufacture of the semiconductor device, the connecting strip may be configured to mechanically connect adjacent die pads of the lead frame panel (as in...). Figures 5A-5E (As can be seen in the method described). In the illustrated example, the die pad 100 may include a first connecting strip 18A disposed between a first imprinted edge region 14A and a third imprinted edge region 14C, and a second connecting strip 18B disposed between a second imprinted edge region 14B and a third imprinted edge region 14C. The imprinted edge regions 14A to 14C may surround the unimprinted region 16 on three sides of the die pad 100, excluding the locations of the unimprinted connecting strips 18A and 18B.

[0021] from Figure 1C As can be seen in the exemplary view of the bottom surface 12 shown, each of the connecting strips 18A and 18B may include a first segment 20A having a first width w1 measured in the x-direction and a second segment 20B having a second width w2, less than the first width w1, measured in the x-direction. The first segment 20A of the corresponding connecting strip 18 may be arranged within the area (or occupied area) of the top surface 10, while the second segment 20B of the corresponding connecting strip 18 may extend beyond the area of ​​the top surface 10. The dimension d of the first segment 20A of the first connecting strip 18A arranged between the two embossed edge regions 14A and 14C is [not specified in the original text]. TB It can be equal to the size d A This can also be applied to the first section 20A of the second connecting strip 18B and dimension d. B .

[0022] The die pad 100 may optionally include an opening 22 that extends in the z-direction from the top surface 10 through the die pad 100 to the bottom surface 12. In the illustrated example, the opening 22 may have a rectangular shape. In other examples, the shape of the opening 22 may be different and may be circular, round, elliptical, quadratic, etc. The bottom surface 12 of the die pad 100 may include an imprinted area 24 surrounding the opening 22.

[0023] Now for reference Figure 2A and Figure 2BDifferent views of a semiconductor device 200 according to this disclosure are shown. The semiconductor device 200 may include components that can be used with… Figures 1A-1C The die pad 100 is similar to or the same as the die pad 100 in the semiconductor device 200. The semiconductor device 200 may also include one or more semiconductor dies 26 mounted on the top surface 10 of the die pad 100 and one or more electrical connection elements 28 connected to the semiconductor die 26.

[0024] Typically, the semiconductor dies described herein can be manufactured from elemental semiconductor materials (e.g., Si) or from wide-bandgap semiconductor materials or compound semiconductor materials (e.g., SiC, GaN, SiGe, GaAs). Semiconductor dies can be of any type and can include integrated circuits with active and / or passive electronic components. Integrated circuits can be designed as logic integrated circuits, analog integrated circuits, mixed-signal integrated circuits, power integrated circuits, memory circuits, integrated passive devices, etc. Note that throughout this specification, the terms "die," "semiconductor die," "chip," and "semiconductor chip" are used interchangeably.

[0025] Specifically, semiconductor die 26 can be a power semiconductor die. In this context, the term "power semiconductor die" can refer to a semiconductor die that provides at least one of high voltage blocking or high current carrying capacity. A power semiconductor die can be configured to handle high currents, such as a maximum current value of several amperes (e.g., 10 A) or a maximum current value of up to or exceeding 100 A. Similarly, the voltage associated with such current values ​​can range from a few volts to tens or hundreds or even thousands of volts, such as, for example, about 1200 V, about 1600 V, about 2400 V, etc. Power semiconductor dies can be used in any kind of power application, such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), half-bridge circuits, power modules including gate drivers, etc. For example, a power semiconductor die can include, or be part of, a power device, such as a power MOSFET, an LV (Low Voltage) power MOSFET, a power IGBT (Insulated Gate Bipolar Transistor), a power diode, a superjunction power MOSFET, etc.

[0026] In the example shown, the semiconductor device 200 may include an exemplary number of two electrically connected elements 28A and 28B implemented as clamps. The clamps 28A and 28B may comprise, or may be made of, metal or metal alloy. The core material and / or plating material of the clamps 28A and 28B may be similar to or equivalent to bonding. Figures 1A-1CThe die pad 100 in the diagram describes the material. A first clamp 28A may contact one or more electrical contacts of the semiconductor die 26 disposed on the top surface of the semiconductor die 26, and may exemplary include a single lead or pin 30A. Similarly, a second clamp 28B may contact one or more electrical contacts of the semiconductor die 26 disposed on the top surface of the semiconductor die 26, and may include an exemplary number of three leads or pins 30B.

[0027] In a non-limiting example, the semiconductor die 26 may include or correspond to a power transistor having a drain electrode disposed on the bottom surface of the top surface 10 of the semiconductor die 26 facing the die pad 100, and a source electrode and a gate electrode disposed on the top surface of the semiconductor die 26 facing away from the top surface 10 of the die pad 100. In the case of a vertical power transistor, the drain electrode may be electrically connected to the die pad 100, the source electrode may be electrically connected to the second clamp 28B, and the gate electrode may be electrically connected to the first clamp 28A. Therefore, the electrodes of the power transistor may be accessible via the die pad 100 and leads 30A, 30B.

[0028] Now for reference Figure 3A and Figure 3B Different views of a semiconductor device 300 according to this disclosure are shown. The semiconductor device 300 may include... Figure 2A and Figure 2B The semiconductor device 200 includes some or all of the features of the semiconductor device 200. The semiconductor device 300 may include an encapsulation material 32 that at least partially encapsulates the die pad 100, the semiconductor die 26, and the clamps 28A, 28B. For example, the encapsulation material 32 may include at least one of epoxy resin, filled epoxy resin, glass fiber filled epoxy resin, imide, thermoplastic, thermosetting polymer, polymer blend, compression compound, molding compound, etc., or may be made from at least one of these. Various techniques (e.g., at least one of compression molding, injection molding, powder molding, liquid molding, patterning molding, etc.) may be used to encapsulate the components in the encapsulation material 32. In the example shown, the encapsulation material 32 may form an encapsulation having a bottom surface 34, an opposing top surface 36, and a side surface 38 connecting the bottom surface 34 and the top surface 36. The semiconductor device 300 may also be referred to as a semiconductor package.

[0029] The unprinted area 16 of the die pad 100 may not be covered by the encapsulating material 32, while the printed edge areas 14A to 14C of the die pad 100 may be at least partially covered by the encapsulating material 32. In the example shown, the printed edge areas 14A to 14C may be completely covered by the encapsulating material 32, and therefore in Figure 3BNot visible in the view. The unprinted area 16 of the die pad 100 and the bottom surface 34 of the encapsulation material 32 can be substantially coplanar, i.e., they can be arranged in a common plane. One or more side surfaces 38 of the encapsulation material 32 can be arranged substantially perpendicular to the bottom surface 34 and the top surface 36 of the encapsulation material 32. In the example shown, the side surfaces 38 of the encapsulation material 32 can be arranged in the xz plane, while the bottom surface 34 and the top surface 36 of the encapsulation material 32 can be arranged in the xy plane.

[0030] Each of the connecting strips 18A and 18B may be at least partially covered by the encapsulating material 32. In the example shown, the bottom surface 40 and side surface 42 of the respective connecting strip 18 may not be covered by the encapsulating material 32. The side surface 38 of the encapsulating material 32 and the side surface 42 of the connecting strip 18 may be substantially coplanar, i.e., they may be arranged in a common plane. In the example shown, the side surface 42 of the respective connecting strip 18 may be arranged in the xz plane.

[0031] The semiconductor device 300 and other semiconductor devices according to the present invention described herein can be superior to conventional semiconductor devices. Typically, the area of ​​the bottom surface of a die pad can be determined by footprint compatibility requirements. Furthermore, in many conventional semiconductor devices, the area of ​​the top surface of a die pad can correspond to the area of ​​the bottom surface of the die pad, thus potentially limiting the mounting surface of the die pad to a specific mounting area. Therefore, only semiconductor dies of a specific size can be arranged on the die pads of a conventional semiconductor device. In contrast, the bottom surface 12 of the die pad 100 can include imprinted edge regions 14A to 14C, such that the area of ​​the top surface 10 can be larger than the area of ​​the unimprinted region 16 of the bottom surface 12. The semiconductor device can thus simultaneously provide a compatible footprint and a larger mounting area for the semiconductor die. In a non-limiting example, the die pad of a conventional semiconductor device may only accommodate dies with dimensions up to approximately 6.39 mm. 2 The semiconductor die is the size of a chip, while the semiconductor device according to the present invention can provide up to 10.5 mm. 2 The installation area is approximately 64.3% larger than that of conventional installations.

[0032] Now for reference Figure 4 A flowchart of a method according to the present disclosure is shown. The method is described in a general manner to qualitatively illustrate aspects of the present disclosure. The method can be used to manufacture a semiconductor device according to the present disclosure. In particular, the method can be applied to the manufacture of, for example, semiconductor devices... Figures 1A-1C One or more die pads are shown. It should be understood that this method may include other aspects. For example, the method can be extended by combining any aspects described in conjunction with other examples provided herein. For example, the method can be extended by combining... Figures 5A-5EThe methods described in the document can be extended to any aspect.

[0033] In step 44, a metal panel may be provided. In step 46, a plurality of first openings may be formed in the metal panel to form a lead frame panel including a plurality of die pads. The plurality of die pads may be arranged in a row, wherein two adjacent die pads may be separated by two side-by-side first openings and connected by a connecting strip between the two first openings. In step 48, the edge region of the bottom surface of the die pads may be embossed, wherein material of the die pads may be pressed into the region of the first opening. In step 50, a plurality of second openings may be formed at the locations of the plurality of first openings to remove material pressed into the region of the first opening, wherein each second opening may be wider than the first opening, and two adjacent dies may still be connected by the connecting strip.

[0034] Now for reference Figures 5A-5E This describes another method according to the present disclosure. Figures 5A-5E The method in [the text] can be at least partially regarded as [the method]. Figure 4 A more detailed version of the method described in [the document]. For example, Figures 5A-5E The method described can be used to manufacture Figures 1A-1C The die pad in the middle is 100.

[0035] exist Figure 5A The device may provide a metal panel (or metal sheet) 52. The metal panel 52 may include, or may be made of, a metal or metal alloy. For example, the metal panel 52 may include a core material, which includes at least one of copper, copper alloy, aluminum, aluminum alloy, etc. Optionally, the metal panel 52 may be plated with at least one plating material, which may include, for example, at least one of nickel, nickel-phosphorus, nickel-nickel-phosphorus, copper, silver, etc. Figure 5A The steps in can correspond to Figure 4 Step 44 in the process.

[0036] exist Figure 5B In this configuration, multiple first openings 56 can be formed in the metal panel 52 to form the leadframe panel 54. For example, material at the location of the first openings 56 can be removed by a cutting process. In the illustrated example, the first openings 56 are indicated by shaded areas. The resulting leadframe panel 54 may include a peripheral frame 60 and multiple rows of die pads 58 connected to the opposite side of the peripheral frame 60. In the illustrated case, for simplicity, only one row of die pads 58 extending in the y-direction and including an exemplary number of three die pads 58 is shown. In practice, the leadframe panel 54 may include multiple rows of die pads 58 arranged side-by-side, wherein the number of die pads included in a row can be greater than three, for example, up to several dozen.

[0037] Dies 58 arranged in the same row of die pads 58 can be connected via connecting strips 18. In this respect, adjacent die pads 58 can be separated by two side-by-side first openings 56A, 56B and connected by a connecting strip 18 between the two first openings 56A, 56B. Dies 58 in a row of die pads 58 may include two connecting strips 18 arranged on opposite sides of the die pads 58. The innermost and outermost die pads 58 can be connected to the outer frame 60 via connecting strips 18 and to adjacent die pads 58 via opposing connecting strips 38. Other die pads 58 in a row can be connected to two adjacent die pads 58 in that row of die pads 58 via two opposing connecting strips 18. Figure 5B The steps in can correspond to Figure 4 Step 46 in the process.

[0038] exist Figure 5C In the process, the lead frame panel 54 can be imprinted using an imprinting tool. During the imprinting process, the punch of the imprinting tool can move toward the lead frame panel 54 in the z-direction and at least partially imprint the lead frame panel 54. Material 62 of the die pad 58 can be imprinted into one or more regions of the first openings 56A to 56C. In the illustrated example, the material 62 imprinted into the first opening 56 and the region of the die pad 58 from which the material originates are indicated by shaded areas. After performing the imprinting process, each die pad 58 may include imprinted edge regions 14A to 14C and an unimprinted region 16 on its bottom surface 12. The imprinted and unimprinted regions of the die pad 58 can be similar to those previously combined. Figures 1A-1C The corresponding area described. Figure 5C The steps in can correspond to Figure 4 Step 48 in the process.

[0039] exist Figure 5D In this process, multiple second openings 64 can be formed at the locations of multiple first openings 56A to 56C to remove material 62 pressed into the regions of the first openings 56A to 56C. For example, this can be achieved through methods similar to... Figure 5B The material 62 is removed by a cutting process. Specifically, each second opening 64 may be wider than one of the associated first openings 56A to 56C. Note that when the material 62 is removed by the cutting process, at least a portion of the imprinted edge regions 14A to 14C is retained. Furthermore, the cutting process does not necessarily affect the connecting strip 18, because after the cutting process is performed, two adjacent cores 58 remain connected by the connecting strip 18. Figure 5D The steps in can correspond to Figure 4 Step 50 in the process.

[0040] exist Figure 5E The text shows the execution process.Figure 5D The arrangement structure after the cutting process. Dies 58 can still be connected by connecting strips 18. The sidewall of each die pad 58 can be substantially perpendicular to the bottom surface 12 of the corresponding die pad 58, and the sidewall can be without material 62. Each manufactured die pad 58 can be similar to... Figures 1A-1C The die pad 100 in the die pad 100 may include some or all of the features of the die pad 100 as described above. Specifically, the connecting strip 18 may be unembossed and disposed between two embossed edge regions of the bottom surface 12. When viewed along the z-direction, the connecting strip 18 may include a first segment having a first width and a second segment having a second width less than the first width. The corresponding first segment of the connecting strip 18 may be disposed within the area of ​​the top surface 10 of the die pad 18, and the second segment of the connecting strip 18 may extend beyond the area of ​​the top surface 10.

[0041] Now for reference Figure 6 A flowchart of a method according to this disclosure is shown. The method is described in a general manner to qualitatively illustrate aspects of this disclosure. As previously stated, this method can be used to manufacture a semiconductor device. It should be understood that the method may include additional aspects. For example, the method can be extended by incorporating any aspects described in conjunction with other examples described herein.

[0042] In step 66, a lead frame panel comprising multiple die pads arranged in multiple rows can be provided. Each die pad may include a top surface and a bottom surface. The bottom surface of each die pad may include an imprinted edge region and an unimprinted region. The area of ​​the top surface may be larger than the area of ​​the unimprinted region of the bottom surface. In step 68, multiple semiconductor dies may be mounted on the top surface of the die pads. In step 70, multiple clamps may be attached to the top of the semiconductor dies. In step 72, an encapsulation process may be performed, wherein multiple strips made of encapsulation material may be formed, wherein each strip may encapsulate one row of die pads. In step 74, the multiple strips may be individualized into multiple semiconductor packages.

[0043] Now for reference Figures 7A-7F Another method according to this disclosure is described, which can be at least partially similar to... Figure 6 The methods used in [the context]. For example... Figures 7A-7F The method described can be used to manufacture Figure 2A and Figure 2B as well as Figure 3A and Figure 3B One or more of the semiconductor devices 200 and 300 in the semiconductor device.

[0044] exist Figure 7AA lead frame panel 54 may be provided, comprising a plurality of die pads 58 arranged in multiple rows. Semiconductor dies 26 may be disposed on the mounting surfaces of the die pads 58. The lead frame panel 54 may include a peripheral frame 60, wherein the multiple rows of die pads 58 may be connected to opposite sides of the peripheral frame 60. The multiple rows of die pads 58 may be partially separated by gaps 76. Enlarged details of the lead frame panel 54 are shown in dashed rectangles. From this detail, it can be seen that... Figure 7A The multi-row die pad 58 in the middle can be similar to Figure 5E The multi-row die pads 58 shown are previously combined. Figures 5A-5E The relevant features are described and referenced herein. Specifically, each die pad 58 may include a top surface 10 and a bottom surface 12, wherein the bottom surface 12 may include imprinted edge regions 14A to 14C and unimprinted regions 16. The area of ​​the top surface 10 may be larger than the area of ​​the unimprinted regions 16 of the bottom surface 12. Figure 7A The steps in can correspond to Figure 6 Steps 66 and 68 in the text.

[0045] In another step (not shown), the clamp may be attached to and electrically connected to the semiconductor die 26. This step may correspond to Figure 6 Step 70. For example, the fixture can be similar to a combination. Figure 2A and Figure 2B The described fixtures are 28A and 28B. Specifically, the fixtures can be configured as a batch fixture frame comprising multiple fixtures 28A and 28B. Such a batch fixture frame can be arranged in gaps 76, and the included fixtures can be attached to semiconductor dies 26 arranged on both sides of the respective gaps 76. In the illustrated example, four batch fixture frames can be arranged in four gaps 76, such that all semiconductor dies 26 can be electrically coupled to a configuration similar to... Figure 2A and Figure 2B The clamp.

[0046] In another step (not shown), a reflow process can be performed to attach a batch jig frame or fixture to the semiconductor die 26. Additionally, optional flux cleaning and plasma cleaning processes can be performed.

[0047] In another step (not shown), an encapsulation process can be performed. This step can correspond to... Figure 6 Step 72. For example, multiple strips made of encapsulating material can be formed in the molding process, wherein each molded strip can encapsulate a row of die pads. Alternatively, a post-molding curing (PMC) process can be performed.

[0048] In another step (not shown), one or more barrier strips of the arrangement can be cut. Barrier strips can be used in lead frame design to facilitate molding or encapsulation operations and further provide support for the leads. In this regard, barrier strips can be arranged between adjacent leads. During the encapsulation operation, the barrier strips can be configured to act as clamping surfaces for the edges of the die-cutting tool and as barriers to prevent molding material from leaking or splashing from the die-cutting tool onto the leads. After the encapsulation operation, the barrier strips can be removed, allowing the leads to be physically and / or electrically monomerized depending on their respective functions.

[0049] In another step (not shown), at least one of the deburring or plating processes may be performed.

[0050] In another step (not shown), the leads of clamps 28A and 28B may be trimmed and / or formed.

[0051] exist Figure 7B The image shows an arrangement structure processed by the previously described steps, but rotated 180 degrees. This arrangement structure may include multiple encapsulation elements arranged in rows, wherein each element may include a die pad, a semiconductor die, and a fixture. An arrangement structure comprising multiple strips made of encapsulation material can be individualized into multiple semiconductor devices (or semiconductor packages). Exemplary individualization of the arrangement structure is indicated by dashed lines.

[0052] exist Figures 7C-7F In the middle, it is shown that by Figure 7B Different views of the semiconductor device 700 obtained through a single-process manufacturing process. Specifically, the semiconductor device 700 may include... Figure 3A and Figure 3B Some or all of the features of the semiconductor device 300 in the prior art. Previously combined Figure 3A and Figure 3B These characteristics are described and referenced here.

[0053] Example

[0054] In the following description, semiconductor devices and methods according to the present invention are illustrated by way of example.

[0055] Example 1 is a semiconductor device comprising: a die pad including a top surface and a bottom surface; and a semiconductor die mounted on the top surface of the die pad, wherein the bottom surface of the die pad includes an unprinted area and at least two printed edge areas, wherein the die pad includes an unprinted connecting strip disposed between the two printed edge areas on the bottom surface, and wherein the area of ​​the top surface is larger than the area of ​​the unprinted area on the bottom surface.

[0056] Example 2 is a semiconductor device according to Example 1, wherein, in a top view of the bottom surface, the connecting strip includes a first segment having a first width and a second segment having a second width less than the first width.

[0057] Example 3 is a semiconductor device according to Example 2, wherein, in a top view of the bottom surface: a first segment of the connecting strip is arranged within the area of ​​the top surface, and a second segment of the connecting strip extends beyond the area of ​​the top surface.

[0058] Example 4 is a semiconductor device according to any of the preceding examples, further comprising: an encapsulation material that at least partially encapsulates the die pads and the semiconductor die, wherein an unimprinted area on the bottom surface is not covered by the encapsulation material.

[0059] Example 5 is a semiconductor device according to Example 4, wherein: the imprinted edge region of the bottom surface is at least partially covered by encapsulation material, and the connecting strip is at least partially not covered by encapsulation material.

[0060] Example 6 is a semiconductor device according to Example 4 or 5, wherein the unprinted area on the bottom surface and the bottom surface of the encapsulating material are substantially coplanar.

[0061] Example 7 is a semiconductor device according to any one of Examples 4 to 6, wherein the side surface of the encapsulating material is arranged substantially perpendicular to the bottom surface and the top surface of the encapsulating material.

[0062] Example 8 is a semiconductor device according to any one of Examples 4 to 7, wherein the side surfaces of the encapsulating material and the connecting strip are substantially coplanar.

[0063] Example 9 is a semiconductor device according to any of the preceding examples, wherein at least two imprinted edge regions surround an unimprinted region on either side or more sides of a die pad.

[0064] Example 10 is a semiconductor device according to any of the preceding examples, wherein at least two imprinted edge regions surround an unimprinted area on two or more sides of the die pad, excluding the location of the connector strip.

[0065] Example 11 is a semiconductor device according to any of the preceding examples, wherein the bottom surface of the die pad includes a first imprinted edge region disposed on a first side of the die pad and a second imprinted edge region disposed on a second side of the die pad opposite to the first side.

[0066] Example 12 is a semiconductor device according to Example 11, wherein the bottom surface of the die pad includes a third imprinted edge region disposed on a third side of the die pad, the third side of the die pad connecting the first side and the second side of the die pad.

[0067] Example 13 is a semiconductor device according to any one of Examples 2 to 12, wherein the size of a first segment of a connecting strip arranged between two imprinted edge regions is equal to the size of the two imprinted edge regions.

[0068] Example 14 is a semiconductor device according to any of the preceding examples, wherein the thickness of the imprinted edge region is in the range of 60% to 90% of the thickness of the unimprinted region.

[0069] Example 15 is a method comprising: providing a metal panel; forming a plurality of first openings in the metal panel to form a lead frame panel including a plurality of die pads, wherein the plurality of die pads are arranged in a row, wherein two adjacent die pads are separated by two side-by-side first openings and connected by a connecting strip between the two first openings; embossing an edge region of the bottom surface of the die pads, wherein material of the die pads is pressed into the region of the first openings; and forming a plurality of second openings at the locations of the plurality of first openings to remove material pressed into the region of the first openings, wherein each second opening is wider than the first opening, wherein two adjacent die pads are still connected by the connecting strip.

[0070] Example 16 is based on the method of Example 15, wherein the connecting strip is unembossed and is arranged between two embossed edge areas on the bottom surface.

[0071] Example 17 is based on the method of Example 15 or 16, wherein at least a portion of the imprinted edge region is retained when the material pressed into the region of the first opening is removed.

[0072] Example 18 is a method according to any one of Examples 15 to 17, wherein, after forming a plurality of second openings: the sidewall of each die pad is substantially perpendicular to the bottom surface of the corresponding die pad, and the sidewall is not pressed into the area of ​​the first opening.

[0073] Example 19 is a method according to any one of Examples 15 to 18, wherein: the lead frame panel includes a peripheral frame and multiple rows of die pads, wherein the multiple rows of die pads are connected to opposite sides of the peripheral frame, and the die pads arranged in the same row of die pads are connected via connecting strips.

[0074] Example 20 is based on the method of Example 19, wherein: a die pad in a row of die pads includes two connecting strips arranged on opposite sides of the die pad, and the die pad is connected to two adjacent die pads in a row of die pads via the two connecting strips.

[0075] Example 21 is a method according to any one of Examples 15 to 20, wherein, in a top view of the bottom surface, the connecting strip includes a first segment having a first width and a second segment having a second width less than the first width.

[0076] Example 22 is based on the method of Example 21, wherein, in a top view of the bottom surface: a first segment of the connecting strip is arranged within the area of ​​the top surface, and a second segment of the connecting strip extends beyond the area of ​​the top surface.

[0077] Example 23 is a method comprising: providing a leadframe panel including a plurality of die pads arranged in multiple rows, wherein: each die pad includes a top surface and a bottom surface, the bottom surface of each die pad includes an imprinted edge region and an unimprinted region, and the area of ​​the top surface is greater than the area of ​​the unimprinted region of the bottom surface; mounting a plurality of semiconductor dies on the top surface of the die pads; attaching a plurality of clamps to the top of the semiconductor dies; performing an encapsulation process, wherein a plurality of strips made of encapsulation material are formed, wherein each strip encapsulates a row of die pads; and individualizing the plurality of strips into a plurality of semiconductor packages.

[0078] As used in this specification, the terms “connection,” “coupling,” “electrical connection,” and / or “electrical coupling” do not necessarily mean that the elements must be directly connected or coupled together. Intermediate elements may be provided between “connection,” “coupling,” “electrical connection,” or “electrical coupling” elements.

[0079] Furthermore, the terms "above" and "on" used herein to refer to a material layer, for example, formed or located "above" or "on" a surface of an object, may be used to indicate that the material layer may be "directly" located (e.g., formed, deposited, etc.) on the implied surface (e.g., in direct contact with the implied surface). The terms "above" and "on" used herein to refer to a material layer, for example, formed or located "above" or "on" a surface, may also be used to indicate that the material layer may be "indirectly" located (e.g., formed, deposited, etc.) on the implied surface, for example, with one or more additional layers arranged between the implied surface and the material layer.

[0080] Furthermore, with regard to the terms “having,” “containing,” “comprising,” “with,” or variations thereof used in the specific embodiments or claims, these terms are intended to be inclusive in a manner similar to the term “comprising.” That is, as used herein, the terms “having,” “containing,” “comprising,” “with,” “including,” etc., are open-ended terms that indicate the presence of the stated element or feature but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles “a” and “said” are intended to include both plural and singular forms.

[0081] Furthermore, the word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as superior to other aspects or designs. Rather, the use of the word "exemplary" is intended to present the concept in a specific manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise stated, "X adopts A or B" is intended to mean any natural inclusive arrangement, as is clear from the context. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the foregoing instances. Furthermore, the article "a" as used in this application and the appended claims can generally be interpreted as meaning "one or more," unless otherwise stated or clearly pointed to from the context in the singular form. In addition, at least one of A and B generally means A or B, or both A and B.

[0082] This document describes apparatus and methods for manufacturing an apparatus. Comments made in conjunction with the described apparatus also apply to the corresponding methods, and vice versa. For example, if specific components of the apparatus are described, the corresponding method for manufacturing the apparatus may include the step of providing the components in an appropriate manner, even if such steps are not explicitly described or illustrated in the accompanying drawings.

[0083] Although this disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to those skilled in the art, at least in part, based on reading and understanding of the description and drawings. This disclosure includes all such modifications and modifications and is limited only by the concept of the appended claims. In particular, regarding the various functions performed by the aforementioned components (e.g., elements, resources, etc.), unless otherwise stated, the terminology used to describe such components is intended to correspond to any component that performs the specified function of the described component (e.g., functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary embodiments of this disclosure shown herein. Furthermore, while specific features of this disclosure may have been disclosed with respect to only one of several embodiments, such features may be combined with one or more other features of other embodiments if they may be desirable and advantageous for any given or particular application.

Claims

1. A semiconductor device, comprising: The die pads (58, 100) include the top surface (10) and the bottom surface (12); as well as A semiconductor die (26) mounted on the top surface (10) of the die pads (58, 100), The bottom surface (12) of the die pads (58, 100) includes an unprinted area (16) and at least two printed edge areas (14). The imprinted edge region (14C) of the bottom surface (12) extends continuously along multiple sides of the die pads (58, 100). The die pads (58, 100) include unprinted connecting strips (18) arranged between two imprinted edge regions (14) on the bottom surface (12), and The area of ​​the top surface (10) is greater than the area of ​​the unprinted area (16) of the bottom surface (12).

2. The semiconductor device according to claim 1, wherein, In a top view of the bottom surface (12), the connecting strip (18) includes a first segment (20A) having a first width and a second segment (20B) having a second width less than the first width.

3. The semiconductor device according to claim 2, wherein, In the top view of the bottom surface: The first section (20A) of the connecting strip (18) is arranged within the area of ​​the top surface (10), and The second section (20B) of the connecting strip (18) extends beyond the area of ​​the top surface (10).

4. The semiconductor device according to any one of the preceding claims, further comprising: Encapsulation material (32) at least partially encapsulates the die pads (58, 100) and the semiconductor die (26), wherein the unprinted area (16) of the bottom surface (12) is not covered by the encapsulation material (32).

5. The semiconductor device according to claim 4, wherein: The embossed edge region (14) of the bottom surface (12) is at least partially covered by the encapsulating material (32), and The connecting strip (18) is at least partially not covered by the encapsulating material (32).

6. The semiconductor device according to claim 4 or 5, wherein, The unprinted area (16) of the bottom surface (12) and the bottom surface (34) of the encapsulating material (32) are substantially coplanar.

7. The semiconductor device according to any one of claims 4 to 6, wherein, The side surface (38) of the encapsulating material (32) is arranged to be substantially perpendicular to the bottom surface (34) and the top surface (36) of the encapsulating material (32).

8. The semiconductor device according to any one of claims 4 to 7, wherein, The side surface (38) of the encapsulating material (32) and the connecting strip (18) are substantially coplanar.

9. The semiconductor device according to any one of the preceding claims, wherein, The at least two imprinted edge regions (14) surround the unimprinted region (16) on both or more sides of the die pads (58, 100).

10. The semiconductor device according to any one of the preceding claims, wherein, The at least two imprinted edge regions (14) surround the unimprinted region (16) on two or more sides of the die pad (58, 100) other than the location of the connecting strip (18).

11. The semiconductor device according to any one of the preceding claims, wherein, The bottom surface (12) of the die pad (58, 100) includes a first imprinted edge region (14A) disposed on a first side of the die pad (58, 100) and a second imprinted edge region (14B) disposed on a second side of the die pad (58, 100) opposite to the first side.

12. The semiconductor device according to claim 11, wherein, The bottom surface (12) of the die pad (58, 100) includes a third imprinted edge region (14C) disposed on the third side of the die pad (58, 100), the third side of the die pad (58, 100) connecting the first side and the second side of the die pad (58, 100).

13. The semiconductor device according to any one of claims 2 to 12, wherein, The size of the first segment (20A) of the connecting strip (18) arranged between the two embossed edge regions (14) is equal to the size of the two embossed edge regions (14).

14. The semiconductor device according to any one of the preceding claims, wherein, The thickness of the embossed edge region (14) is in the range of 60% to 90% of the thickness of the unembossed region (16).

15. A method comprising: A lead frame panel (54) is provided, the lead frame panel (54) including a plurality of die pads (58) arranged in multiple rows, wherein: Each die pad (58) includes a top surface (10) and a bottom surface (12). The bottom surface (12) of each die pad (58) includes an unprinted area (16) and at least two printed edge areas (14). The imprinted edge region (14C) of the bottom surface (12) extends continuously along multiple sides of the die pads (58, 100). Each die pad (58, 100) includes an unprinted connecting strip (18) disposed between two imprinted edge regions (14) on the bottom surface (12), and The area of ​​the top surface (10) is larger than the area of ​​the unprinted area (16) of the bottom surface (12); Multiple semiconductor dies (26) are mounted on the top surface (10) of the die pad (58); Multiple clamps (28) are attached to the top of the semiconductor die (26); The encapsulation process is performed, wherein multiple strips made of encapsulation material (32) are formed, wherein each strip encapsulates a row of die pads (58); and The multiple strips are individually packaged into multiple semiconductor packages.

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