Semiconductor device and layout structure with multiple semiconductor devices

Abstract

The invention provides a semiconductor device and a layout structure with a plurality of semiconductor devices, the semiconductor device comprises an active region, the active region comprises a polycrystalline electrode and a source electrode metal layer, a first contact hole is arranged between the source electrode metal layer and the polycrystalline electrode, and a second contact hole is arranged between the source electrode metal layer and the polycrystalline electrode. And connecting the source electrode polycrystal with the source electrode metal layer through the first contact hole. According to the semiconductor device provided by the invention, the polycrystalline electrode is connected with the source electrode metal layer through the first contact hole, so that stray capacitance between the grid electrode and the drain electrode of the device is reduced, an RC absorption network between the drain electrode and the source electrode of the device is added, and the switching efficiency and the anti-electromagnetic interference capability of the device are optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a semiconductor device and a layout structure having a plurality of semiconductor devices. BACKGROUND

[0002] Insulated gate field effect transistor (MOSFET) is a commonly used switch in modern times, and its core function is to control the current between the source and the drain by using the gate voltage to realize switching, amplification, signal processing and other functions. Because it has the advantages of fast switching speed, low power consumption, easy-to-drive gate, small driving power, high input impedance and fast frequency response, it is widely used in various power systems.

[0003] At present, in the medium and high voltage range, MOSFET devices with super junction structure are usually used, for example: in LLC resonant topology structure, power factor correction (PFC) and flyback circuit, MOSFET devices with super junction structure are used as switches, so that the MOSFET devices are in a fast switching state. The current and voltage in the circuit structure will change sharply in a short time, which will cause great electromagnetic interference to other components of the circuit, reduce the reliability of the circuit operation, and reduce the service life of the overall circuit. SUMMARY

[0004] The present application provides a semiconductor device and a layout structure having a plurality of semiconductor devices to solve the problem of large electromagnetic interference and low circuit reliability of the above-mentioned semiconductor device with super structure when the device is in a fast switching state.

[0005] The present application provides a semiconductor device, comprising:

[0006] The semiconductor device includes an active region, the active region includes a polycrystalline electrode and a source metal layer, and part of the source metal layer is connected to part of the polycrystalline electrode through a first contact hole.

[0007] In an embodiment of the present application, the semiconductor device comprises:

[0008] A drain structure comprising a front surface and a back surface arranged opposite to each other;

[0009] A drift region super junction structure arranged on the front surface of the drain structure;

[0010] The active region includes a source region structure and the polycrystalline electrode, the source region structure is arranged on the side of the drift region super junction structure away from the drain structure, and the polycrystalline electrode is located inside the source region structure.

[0011] In an embodiment of the present application, the drift region super junction structure comprises:

[0012] a second conductivity type drift region disposed on a front side of the drain structure, the second conductivity type drift region including a plurality of first pillar regions therein;

[0013] a first conductivity type drift region disposed in the first pillar regions.

[0014] In an embodiment of the present disclosure, the source structure includes:

[0015] a first conductivity type body region disposed on a side of the first pillar regions away from the drain structure, and covering the first conductivity type drift region;

[0016] a second conductivity type source region disposed in the first conductivity type body region;

[0017] a first conductivity type ohmic contact region disposed in the first conductivity type body region, and between two of the second conductivity type source regions;

[0018] a source metal layer disposed on a side of the first conductivity type ohmic contact region away from the drain structure, and covering the first conductivity type ohmic contact region and part of the second conductivity type source regions.

[0019] In an embodiment of the present disclosure, the poly electrode includes:

[0020] an insulating medium layer disposed on a side of the second conductivity type drift region away from the drain structure, and covering part of the second conductivity type drift region, the first conductivity type body region, and part of the second conductivity type source regions;

[0021] a source poly disposed on a side of the insulating medium layer away from the drain structure, and the insulating medium layer wrapping the source poly, the first contact hole being disposed on a side of the source poly away from the drain structure, such that the source metal layer covers part of the source poly;

[0022] a gate poly disposed on a side of the insulating medium layer away from the drain structure, and the insulating medium layer wrapping the gate poly.

[0023] In an embodiment of the present disclosure, an extension direction of the first conductivity type drift region is parallel or orthogonal to an extension direction of the gate poly.

[0024] The application also provides a layout structure with a plurality of semiconductor devices, the layout structure comprising the semiconductor device as described above, and comprising a first contact hole, a second contact hole, a source poly, and a gate poly, the first contact hole being a connection region of a source metal layer and the source poly, the second contact hole being a connection region of the source metal layer and a second-conductivity-type source region and a first-conductivity-type ohmic, the first contact hole being located between and parallel to two adjacent second contact holes, the two adjacent second contact holes being parallel to each other and having the same length, the length of the first contact hole being smaller than that of the second contact hole, the poly material between the source poly and the gate poly being disconnected, and the start points of the plurality of first contact holes being located on the same cross section and each first contact hole having the same length.

[0025] In an embodiment of the application, two adjacent second contact holes on the same straight line are separated by the gate poly, and the gate poly is arranged on the side of the second contact hole away from the first contact hole.

[0026] In an embodiment of the application, the first contact hole is arranged at the opposite ends of the second contact hole.

[0027] In an embodiment of the application, the second contact holes on the same straight line are continuous, and the first contact hole is arranged on the side of the second contact hole away from the first contact hole or the gate poly is arranged on the side of the second contact hole away from the first contact hole.

[0028] The application provides a semiconductor device and a layout structure with a plurality of semiconductor devices, the semiconductor device comprising: a semiconductor device comprising an active region, the active region comprising a poly electrode and a source metal layer, a first contact hole being arranged between the source metal layer and the poly electrode, and the source poly being connected to the source metal layer through the first contact hole. The semiconductor device provided by the application connects the poly electrode to the source metal layer through the first contact hole, which not only reduces the parasitic capacitance between the gate and the drain of the device, but also increases the RC absorption network between the drain and the source of the device, and optimizes the switching efficiency and the anti-electromagnetic interference capability of the device; since the main voltage resistance of the device is a super-junction structure, the disconnection of the poly electrode is located at the top of the body region, and the voltage resistance characteristics of the device are not affected. BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application. It is to be expressly understood that the drawings are included solely for purposes of illustration and that they are not to be construed as limiting the application. It is to be further expressly understood that the description, together with the drawings, makes apparent to those skilled in the art various modifications and variations of the application which, however, may not be covered by the appended claims.

[0030] In the drawings:

[0031] Figure 1 A first layout structure of a semiconductor device in the prior art;

[0032] Figure 2 A cross-sectional view of the semiconductor device along A-A' of the first layout structure in the prior art;

[0033] Figure 3 A second layout structure of a semiconductor device in the prior art;

[0034] Figure 4 A third layout structure of a semiconductor device in the prior art;

[0035] Figure 5 (a) A first layout structure of a semiconductor device with multiple semiconductor devices in an embodiment of the present application;

[0036] Figure 5 (b) A cross-sectional view of the first layout structure of the semiconductor device along B-B' in an embodiment of the present application;

[0037] Figure 6 A layout structure area division of a semiconductor device in an embodiment of the present application;

[0038] Figure 7 A second layout structure of a semiconductor device with multiple semiconductor devices in an embodiment of the present application;

[0039] Figure 8 A third layout structure of a semiconductor device with multiple semiconductor devices in an embodiment of the present application

[0040] Figure 9 (a) A fourth layout structure of a semiconductor device with multiple semiconductor devices in an embodiment of the present application;

[0041] Figure 9 (b) A cross-sectional view of the fourth layout structure of the semiconductor device with multiple semiconductor devices along B-B' in an embodiment of the present application;

[0042] Figure 10 A fifth layout structure of a semiconductor device with multiple semiconductor devices in an embodiment of the present application.

[0043] Reference numerals: 1-Drain metal layer; 2-Drain region of the second conductivity type; 3-Drift region of the second conductivity type; 4-Drift region of the first conductivity type; 5-Body region of the first conductivity type; 6-Source region of the second conductivity type; 7-Ohmic contact region of the first conductivity type; 8-Insulating dielectric layer; 91-Source polycrystalline; 92-Gate polycrystalline; 10-Source metal layer; CT1-First contact hole; CT2-Second contact hole. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0045] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0047] As described in the background section, in the medium and high voltage range, MOSFET devices with superjunction structures are commonly used, such as in LLC resonant topologies, power factor correction (PFC) circuits, and flyback circuits. Using MOSFET devices with superjunction structures as switches causes the MOSFET devices to be in a fast switching state. The current and voltage within the circuit structure will change drastically in a short time, which will generate significant electromagnetic interference to other components of the circuit, reduce the reliability of circuit operation, and reduce the overall lifespan of the circuit.

[0048] In the prior art, a traditional first layout structure diagram with multiple semiconductor devices is shown as follows: Figure 1 As shown, along Figure 1 The A-A' cross-section was dissected to obtain the following results: Figure 2The cross-sectional schematic diagram of the semiconductor device shown; the conventional structure of semiconductor device in the process of fast switching, generate serious electromagnetic interference, affect the stability of the circuit. Need to explain, such as Figures 3-4 As shown, the length and connection of the gate polysilicon in the active region of the conventional semiconductor device can be adjusted according to the setting of the source metal layer.

[0049] To solve the above problems, as shown in Figure 5 (b), the present application provides a semiconductor device, the semiconductor device includes an active region (Active Region), the active region (Active Region) includes a polysilicon electrode and a source metal layer 10, part of the source metal layer 10 is connected with part of the polysilicon electrode through a first contact hole (CT1).

[0050] Specifically, as shown in Figure 5 (a), Figure 5 (a) shows a first layout structure of the semiconductor device provided by the present application, along Figure 5 The B-B' cross section in (a) is dissected to obtain the cross-sectional view of the semiconductor device as shown in Figure 5 (b). As shown, Figure 6 The semiconductor device includes an active region (Active Region), Gate PAD is a gate pad, and Source PAD is a source pad; as shown in Figure 5 (a), a plurality of repeatable source contact units are arranged in the active region (Active Region), and the polysilicon electrode is divided into multiple segments, as shown in Figure 5 (b), a contact (CT) is punched on part of the segmented polysilicon electrode to form a first contact hole CT1, so that part of the polysilicon electrode is connected with the source metal layer 10; as shown in Figure 5 (a), the layout with a plurality of semiconductor devices is divided into a first layout structure by the source metal layer 10 and the first contact hole (CT1).

[0051] In detail, the semiconductor device includes: a drain structure including oppositely arranged front and back surfaces; a drift region super-junction structure arranged on the front surface of the drain structure; an active region (Active Region) including a source region structure and a polysilicon electrode, the active region (Active Region) structure is arranged on the side of the drift region super-junction structure away from the drain structure, and the polysilicon electrode is located inside the active region (Active Region) structure.

[0052] Specifically, as shown in Figure 5(b) shows, the drain structure includes a second-conductivity-type drain region 2 and a drain metal layer 1, the second-conductivity-type drain region 2 includes oppositely arranged front and back surfaces; the drain metal layer 1 is arranged on the back surface of the second-conductivity-type drain region 2.

[0053] In more detail, as shown in Figure 5 (b) shows, the drift zone super-junction structure includes a second-conductivity-type drift zone 3, a first-conductivity-type drift zone 4, the second-conductivity-type drift zone 3 is arranged on the front surface of the second-conductivity-type drain region 2, and the second-conductivity-type drift zone 3 includes a plurality of first pillar regions; the first-conductivity-type drift zone 4 is arranged in the first pillar regions.

[0054] In more detail, as shown in Figure 5 (b) shows, the source structure includes a first-conductivity-type body region 5, a second-conductivity-type source region 6, a first-conductivity-type ohmic contact region 7, and a source metal layer 10, the first-conductivity-type body region 5 is arranged in the first pillar region, the first-conductivity-type body region 5 is located on the side of the first-conductivity-type drift zone 4 away from the second-conductivity-type drain region 2, and the side and part of the bottom of the first-conductivity-type body region 5 are in contact with the second-conductivity-type drift zone 3; the second-conductivity-type source region 6 is arranged in the first-conductivity-type body region 5; the first-conductivity-type ohmic contact region 7 is arranged in the first-conductivity-type body region 5, the first-conductivity-type ohmic contact region 7 is between two second-conductivity-type source regions 6, and the bottom of the first-conductivity-type ohmic contact region 7 is lower than the bottom of the second-conductivity-type source region 6; the source metal layer 10 is arranged on the side of the first-conductivity-type ohmic contact region 7 away from the second-conductivity-type drain region 2, and the source metal layer 10 covers the first-conductivity-type ohmic contact region 7 and part of the second-conductivity-type source region 6.

[0055] In more detail, as shown in Figure 5 (b) shows, the polycrystal electrode includes an insulating medium layer 8, a source polycrystal 91, and a gate polycrystal 92, the insulating medium layer 8 is arranged on the side of the second-conductivity-type drift zone 3 away from the second-conductivity-type drain region 2, and the insulating medium layer 8 covers part of the second-conductivity-type drift zone 3, the first-conductivity-type body region 5, and part of the second-conductivity-type source region 6; the source polycrystal 91 is arranged on the side of the insulating medium layer 8 away from the second-conductivity-type drain region 2, and the insulating medium layer 8 wraps part of the source polycrystal 91, a first contact hole (CT1) is arranged on the side of the source polycrystal 91 away from the second-conductivity-type drain region 2, so that the source metal layer 10 covers part of the source polycrystal 91; the gate polycrystal 92 is arranged on the side of the insulating medium layer 8 away from the second-conductivity-type drain region 2, and the insulating medium layer 8 wraps the gate polycrystal 92.

[0056] In more detail, the extension direction of the first-conductivity-type drift zone 4 and the extension direction of the gate polycrystal 92 are parallel or orthogonal to each other. Specifically, as shown in Figure 5As shown, the extending direction of the gate polysilicon 92 above the first-conductivity-type drift region 4 is parallel to the extending direction of the first-conductivity-type drift region 4, or the extending direction of the gate polysilicon 92 is perpendicular to the extending direction of the first-conductivity-type drift region 4 (not shown in the figure).

[0057] It is to be noted that the gate polysilicon 92 and the source polysilicon 91 can be formed by planar growth on the side of the insulating medium layer 8 facing away from the second-conductivity-type drain region 2, or can be formed by trench etching on the side of the insulating medium 8 facing away from the source polysilicon 91, and injecting polysilicon material into the etched trench.

[0058] It is to be noted that the semiconductor device material provided by the present application can be made of silicon, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, gallium oxide or germanium silicon. In the semiconductor device, the semiconductor doping type of the first-conductivity-type drift region 4, the first-conductivity-type body region 5 and the first-conductivity-type ohmic contact region 7 is P-type semiconductor, and the semiconductor doping type of the second-conductivity-type drain region 2, the second-conductivity-type drift region 3 and the second-conductivity-type source region 6 is N-type semiconductor; or the semiconductor doping type of the first-conductivity-type drift region 4, the first-conductivity-type body region 5 and the first-conductivity-type ohmic contact region 7 is N-type semiconductor, and the semiconductor doping type of the second-conductivity-type drain region 2, the second-conductivity-type drift region 3 and the second-conductivity-type source region 6 is P-type semiconductor.

[0059] It is to be further noted that the second-conductivity-type drift region 3 and the first-conductivity-type body region 5 are moderately doped, and the second-conductivity-type drain region 2, the second-conductivity-type source region 6 and the first-conductivity-type ohmic contact region 7 are heavily doped. In the provided semiconductor device, the order of magnitude of the impurity concentration of the moderately doped is ∈ (1×10 16 cm -3 , 1×10 18 cm -3 , and the order of magnitude of the impurity concentration of the heavily doped is greater than 1×10 18 cm -3 .

[0060] As shown in Figures 5 to 10 , the present application further provides a layout structure having a plurality of semiconductor devices, which includes the semiconductor device as described above, as shown in Figure 5 (a), the layout structure includes a first contact hole (CT1), a second contact hole (CT2), a source polysilicon 91 and a gate polysilicon 92, as shown in Figure 5(b) as shown, the first contact hole (CT1) is the connection area of the source metal layer 10 and the source poly 91, and the second contact hole (CT2) is the connection area of the source metal layer 10 and the second conductive type source region 6 and the first conductive type ohmic contact region 7; the first contact hole (CT1) is located between and parallel to two adjacent second contact holes (CT2), the two adjacent second contact holes (CT2) are parallel to each other and have the same length, the length of the first contact hole (CT1) is less than that of the second contact hole (CT2), the poly material between the source poly 91 and the gate poly 92 is disconnected, the starting points of the plurality of first contact holes (CT1) are arranged on the same cross section, and the lengths of the first contact holes (CT1) are the same.

[0061] In detail, as shown in Figure 5 (a) shown, the first contact hole (CT1) is the connection area of the source metal layer 10 and the source poly 91, and the second contact hole (CT2) is the connection area of the source metal layer 10 and the second conductive type source region 6 and the first conductive type ohmic contact region 7; the first contact hole (CT1) is located between and parallel to two adjacent second contact holes (CT2), the two adjacent second contact holes (CT2) are parallel to each other and have the same length, the length of the first contact hole (CT1) is less than that of the second contact hole (CT2), the poly material between the source poly 91 and the gate poly 92 is disconnected, the starting points of the plurality of first contact holes (CT1) are arranged on the same cross section, and the lengths of the first contact holes (CT1) are the same. Two adjacent second contact holes (CT2) on the same straight line are isolated by the gate poly 92, and the gate poly 92 is arranged on the side of the second contact hole (CT2) away from the first contact hole (CT1). The first contact hole (CT1) and the second contact hole (CT2) constitute a repeatable source contact unit. Among them, as shown in Figure 7 (b) shown, the first contact hole (CT1) is the connection area of the source metal layer 10 and the source poly 91, and the second contact hole (CT2) is the connection area of the source metal layer 10 and the second conductive type source region 6 and the first conductive type ohmic contact region 7; the first contact hole (CT1) is located between and parallel to two adjacent second contact holes (CT2), the two adjacent second contact holes (CT2) are parallel to each other and have the same length, the length of the first contact hole (CT1) is less than that of the second contact hole (CT2), the poly material between the source poly 91 and the gate poly 92 is disconnected, the starting points of the plurality of first contact holes (CT1) are arranged on the same cross section, and the lengths of the first contact holes (CT1) are the same. Two adjacent second contact holes (CT2) on the same straight line are isolated by the gate poly 92, and the gate poly 92 is arranged on the side of the second contact hole (CT2) away from the first contact hole (CT1). The first contact hole (CT1) and the second contact hole (CT2) constitute a repeatable source contact unit. Among them, as shown in

[0062] In detail, as shown in Figure 8 (a) shown, the first contact hole (CT1) is the connection area of the source metal layer 10 and the source poly 91, and the second contact hole (CT2) is the connection area of the source metal layer 10 and the second conductive type source region 6 and the first conductive type ohmic contact region 7; the first contact hole (CT1) is located between and parallel to two adjacent second contact holes (CT2), the two adjacent second contact holes (CT2) are parallel to each other and have the same length, the length of the first contact hole (CT1) is less than that of the second contact hole (CT2), the poly material between the source poly 91 and the gate poly 92 is disconnected, the starting points of the plurality of first contact holes (CT1) are arranged on the same cross section, and the lengths of the first contact holes (CT1) are the same. Two adjacent second contact holes (CT2) on the same straight line are isolated by the gate poly 92, and the gate poly 92 is arranged on the side of the second contact hole (CT2) away from the first contact hole (CT1). The first contact hole (CT1) and the second contact hole (CT2) constitute a repeatable source contact unit. Among them, as shown in

[0063] In detail, as shown in Figure 9 (a), the fourth layout structure with multiple semiconductor devices provided by the present application is characterized in that the first contact holes (CT1) are located between two adjacent second contact holes (CT2) and parallel to each other, the two adjacent second contact holes (CT2) are parallel to each other and have the same length, the length of the first contact hole (CT1) is smaller than that of the second contact hole (CT2), the polycrystalline material between the source polycrystal 91 and the gate polycrystal 92 is disconnected, the starting points of the multiple first contact holes (CT1) are located at the same cross section and the length of each first contact hole (CT1) is the same, the second contact holes (CT2) on the same straight line are continuously connected, and the first contact hole (CT1) is arranged on the side of the second contact hole (CT2) away from the first contact hole (CT1).

[0064] It should be noted that, as shown in Figure 9 (a), along the cross section B-B', the semiconductor device is dissected to obtain the cross-sectional view of the semiconductor device as shown in Figure 9 (b); Figure 9 The semiconductor device of the fourth layout structure provided by the present application is different from that of the first layout structure provided by the present application in that the multiple first contact holes (CT1) are arranged at the same cross section, as shown in Figure 5 (a), the semiconductor device has three first contact holes (CT1) between the source metal layer 10 and the source polycrystal 91 in the B-B' cross section. Figure 9

[0065] In detail, as shown in Figure 10 (a), the fifth layout structure with multiple semiconductor devices provided by the present application is characterized in that the first contact holes (CT1) are located between two adjacent second contact holes (CT2) and parallel to each other, the two adjacent second contact holes (CT2) are parallel to each other and have the same length, the length of the first contact hole (CT1) is smaller than that of the second contact hole (CT2), the polycrystalline material between the source polycrystal 91 and the gate polycrystal 92 is disconnected, the starting points of the multiple first contact holes (CT1) are located at the same cross section and the length of each first contact hole (CT1) is the same, the second contact holes (CT2) on the same straight line are continuously connected, and the gate polycrystal 92 is arranged on the side of the second contact hole (CT2) away from the first contact hole (CT1).

[0066] ​The application provides a semiconductor device and a layout structure with multiple semiconductor devices, the semiconductor device comprising: the semiconductor device comprises an active region, the active region comprising a polycrystalline electrode and a source metal layer, a first contact hole is arranged between the source metal layer and the polycrystalline electrode, and the source polycrystalline is connected with the source metal layer through the first contact hole. The semiconductor device provided by the application connects the polycrystalline electrode with the source metal layer through the first contact hole, which not only reduces the parasitic capacitance between the gate and the drain of the device, but also increases the RC absorption network between the drain and the source of the device, and optimizes the switching efficiency and the anti-electromagnetic interference capability of the device; the device can be applied to both planar gates and trench gates, in the trench structure, the new trench structure can increase the parasitic capacitance between the gate and the source, and reduce the risk of false opening of the device; because the withstand voltage main body of the device is a super-junction structure, the disconnection of the polycrystalline electrode is located at the top of the body region, and the withstand voltage characteristics of the device are not affected. Through the first contact hole, the layout structure can be set according to the actual situation when designing the layout structure, and the device is more stable.

[0067] The above examples only illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above examples without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought of the application should be covered by the claims of the application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes an active region, which includes a polycrystalline electrode and a source metal layer, wherein a portion of the source metal layer is connected to a portion of the polycrystalline electrode through a first contact hole.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes: A drain structure comprising a front side and a back side disposed opposite to each other; A drift region superjunction structure is disposed on the front side of the drain structure; The active region includes a source region structure and the polycrystalline electrode. The active region structure is disposed on the side of the drift region superjunction structure away from the drain structure, and the polycrystalline electrode is located inside the active region structure.

3. The semiconductor device according to claim 2, characterized in that, The drift region superjunction structure includes: A second conductivity type drift region is disposed on the front side of the drain structure, and the second conductivity type drift region includes a plurality of first pillar regions; A first conductivity type drift region is disposed within the first column region.

4. The semiconductor device according to claim 3, characterized in that, The source structure includes: A first conductivity type body region is disposed on the side of the first pillar region away from the drain structure and covers the first conductivity type drift region. A second conductivity type source region is disposed within the first conductivity type body region; A first conductivity type ohmic contact region is disposed within the first conductivity type body region and is located between two second conductivity type source regions; A source metal layer is disposed on the side of the first conductivity type ohmic contact region away from the drain structure, and covers the first conductivity type ohmic contact region and part of the second conductivity type source region.

5. The semiconductor device according to claim 4, characterized in that, The polycrystalline electrode includes: An insulating dielectric layer is disposed on the side of the second conductivity type drift region away from the drain structure, and the insulating dielectric layer covers part of the second conductivity type drift region, the first conductivity type body region and part of the second conductivity type source region; A source polycrystalline silicon is disposed on the side of the insulating dielectric layer away from the drain structure, and the insulating dielectric layer encapsulates the source polycrystalline silicon. The first contact hole is disposed on the side of the source polycrystalline silicon away from the drain structure, such that the source metal layer covers a portion of the source polycrystalline silicon. A gate polycrystalline structure is disposed on the side of the insulating dielectric layer opposite to the drain structure, and the insulating dielectric layer encapsulates the gate polycrystalline structure.

6. The semiconductor device according to claim 5, characterized in that, The extension direction of the first conductivity type drift region is parallel or orthogonal to the extension direction of the gate polycrystalline material.

7. A layout structure having multiple semiconductor devices, characterized in that, The layout structure includes any one of the semiconductor devices as described in claims 1-6. The layout structure includes a first contact hole, a second contact hole, a source polycrystalline material, and a gate polycrystalline material. The first contact hole is a connection region between the source metal layer and the source polycrystalline material. The second contact hole is a connection region between the source metal layer and a source region of a second conductivity type and a source region of a first conductivity type. The first contact hole is located between two adjacent second contact holes and is parallel to each other. Two adjacent second contact holes are parallel to each other and have the same length. The length of the first contact hole is less than that of the second contact hole. The polycrystalline material between the source polycrystalline material and the gate polycrystalline material is disconnected. The starting points of the plurality of first contact holes are set at the same cross-section and the length of each first contact hole is the same.

8. The layout structure having multiple semiconductor devices according to claim 7, characterized in that, Two adjacent second contact holes on the same straight line are isolated by the gate polysilicon, and the gate polysilicon is disposed on the side of the second contact hole away from the first contact hole.

9. The layout structure having multiple semiconductor devices according to claim 8, characterized in that, The first contact hole is provided at both ends of the opposite side of the second contact hole.

10. The layout structure having multiple semiconductor devices according to claim 7, characterized in that, The second contact holes on the same straight line are continuously connected. The first contact hole is provided on the side of the second contact hole away from the first contact hole, or the gate polysilicon is provided on the side of the second contact hole away from the first contact hole.

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