Timing window masking circuit and flip-flop for radiation hardened integrated circuits

Abstract

The application relates to a timing window shielding circuit and a flip-flop for a radiation-resistant integrated circuit in the technical field of integrated circuit reinforcement design, which solves the SET problem from the "time domain" angle, directly acts on the source of error occurrence, is applicable to various timing circuits needing protection, has high universality, and has short protection window and is opened only after the clock edge, does not change the setup time and the hold time of the original circuit, has no influence on the system working frequency and the timing performance, is realized by standard digital units, has simple circuit structure, low area and power consumption, is easy to integrate at various process nodes, has good low-power and low-cost characteristics, can shield SET interference in the timing sensitive window accurately, efficiently and with low cost, and meets the application requirements of modern high-performance radiation-resistant integrated circuits.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit ruggedization design technology, and relates to a timing window shielding circuit and trigger for radiation-resistant integrated circuits. Background Technology

[0002] In electronic systems used in high-reliability applications such as aerospace, integrated circuits (ICs) constantly face the severe challenges of the space radiation environment. High-energy particles (such as protons and heavy ions) in the space radiation environment can trigger single-event effects (SEE) when they strike semiconductor devices. Among these, single-event transient (SET) pulses are one of the main causes of soft errors in circuits. SET pulses manifest as brief spikes in the voltage or current at internal nodes of a circuit. When these spikes propagate to the clock or control signal terminals (such as reset and set) of sequential circuits (such as flip-flops and latches), they can have catastrophic consequences.

[0003] The flip-flop is most sensitive to the SET pulse near the effective transition edge (such as the rising edge) of its clock signal. During this period, the flip-flop's internal latch is in the critical phase of sampling and state updating (i.e., setup and hold time windows), and the circuit node stability is at its worst. If a SET pulse appears on the control signal line at this time, the flip-flop is very likely to misinterpret it as a valid control command (such as a valid reset signal) and capture it, leading to an unexpected and permanent erroneous flip-flop output state, i.e., a single-event upset (SEU), which may ultimately cause the entire electronic system to malfunction.

[0004] In existing circuit-level redundancy hardening designs (such as DICE structures), while they can improve the SEU resistance of the memory cells themselves, the global control signal paths such as reset and set signals are usually not designed with the same degree of redundancy, remaining vulnerable to SET (Set-Off) and unable to solve the SET problem on the control signal lines. Traditional filtering techniques use simple RC filtering or glitch detection logic for hardening, which can filter out some SET pulses, but introduce significant signal delays, affecting the circuit's maximum operating frequency. The filtering threshold is also easily affected by process, voltage, and temperature (PVT) variations, resulting in low reliability. Many traditional hardening solutions are either too costly in terms of performance (speed, area, and power consumption) or cannot accurately and efficiently protect against the most dangerous periods, highlighting the contradiction between performance and reliability and failing to meet the application requirements of modern high-performance radiation-hardened integrated circuits. Summary of the Invention

[0005] To address the problems existing in the aforementioned traditional technologies, this invention proposes a timing window shielding circuit for radiation-hardened integrated circuits, a ruggedized trigger, and a Flash cell data storage method, which can accurately, efficiently, and with low overhead shield SET interference within the timing-sensitive window, meeting the application requirements of modern high-performance radiation-hardened integrated circuits.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0007] On the one hand, a timing window shielding circuit for radiation-resistant integrated circuits is provided, including a protection pulse generation module and a signal shielding logic module. The input terminal of the protection pulse generation module is used to connect to the system clock signal, the output terminal of the protection pulse generation module is connected to one input terminal of the signal shielding logic module, the other input terminal of the signal shielding logic module is used to connect to the signal to be protected of the integrated circuit, and the output terminal of the signal shielding logic module is used to output the signal after SET shielding.

[0008] The protection pulse generation module is used to generate a protection pulse synchronized with the system clock, and the signal shielding logic module is used to perform SET pulse isolation on the signal to be protected within the protection window provided by the protection pulse.

[0009] The width of the protection pulse satisfies: T_d ≥ T_setup + T_hold + T_margin, where T_d is the width of the protection pulse, T_setup is the shortest time during which the input signal to be protected must remain stable before the effective transition edge of the clock signal arrives, T_hold is the shortest time during which the input signal to be protected must continue to remain stable after the effective transition edge of the clock signal arrives, and T_margin is an additional buffer time added on top of the sum of the shortest times T_setup and T_hold.

[0010] In one embodiment, the protection pulse generation module includes a delay unit and a logic combination unit. The delay unit includes an even number of inverters connected in series, and the input of the delay unit is used to receive the system clock signal.

[0011] The logic combination unit includes an AND gate and an inverter. The input of the inverter in the logic combination unit is connected to the output of the delay unit. The output of the inverter in the logic combination unit is connected to one input of the AND gate. The other input of the AND gate is used to input the system clock signal. The output of the AND gate is used to output a protection pulse.

[0012] In one embodiment, the delay unit includes four inverters connected in series.

[0013] In one embodiment, the protection pulse generation module generates a protection pulse with a width exactly equal to the fixed delay generated by the delay unit in each clock cycle.

[0014] In one embodiment, the protection window is open when the protection pulse is high and closed when the protection pulse is low.

[0015] In one embodiment, the signal shielding logic module includes an AND gate and an inverter. The input of the inverter in the signal shielding logic module is connected to the output of the protection pulse generation module. The output of the inverter in the signal shielding logic module is connected to one input of the AND gate, and the other input of the AND gate is used to input the signal to be protected. When the protection window is closed, the signal output by the AND gate completely follows the signal to be protected. When the protection window is open, the signal output by the AND gate is forced to an invalid level.

[0016] On the other hand, a ruggedized trigger is also provided, including the timing window shielding circuit for radiation-resistant integrated circuits mentioned above. The timing window shielding circuit is integrated into the signal path to be protected of the trigger. The timing window shielding circuit is used to isolate the SET pulse in the signal path to be protected. The signal path to be protected includes a reset signal path and a set signal path.

[0017] One of the above technical solutions has the following advantages and beneficial effects:

[0018] The aforementioned timing window shielding circuit and trigger for radiation-hardened integrated circuits innovatively address the SET problem from a "time domain" perspective, directly targeting the root cause of the error—the timing-sensitive window. This allows for precise protection strategies and effectively eliminates most single-event upsets caused by SET pulses. The circuit design is highly versatile, serving as an independent circuit architecture independent of specific circuit structures, and can be flexibly applied to various timing circuits requiring protection. Because the protection window is extremely short and only opens after the clock edge, it does not alter the setup and hold times of the original circuit, has no impact on the system's operating frequency and timing performance, and incurs near-zero performance overhead, perfectly solving the performance degradation problem caused by traditional filtering techniques. The designed circuit is entirely implemented using standard digital units, resulting in a simple circuit structure, extremely low area and power consumption, and easy integration across various process nodes, exhibiting excellent low power consumption and low cost characteristics. Furthermore, the width of the protection pulse is determined by the physical dimensions of the delay chain, minimizing environmental influences, ensuring stable and reliable operation, and accurately, efficiently, and with low overhead shielding against SET interference within the timing-sensitive window, universally meeting the application requirements of modern high-performance radiation-hardened integrated circuits. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the module structure of a timing window shielding circuit for a radiation-hardened integrated circuit in one embodiment;

[0021] Figure 2 This is a schematic diagram of the module principle of the delay unit in one embodiment;

[0022] Figure 3 This is a circuit diagram of a logic combination unit in one embodiment;

[0023] Figure 4 A simulation waveform diagram of the protection pulse generation in one embodiment;

[0024] Figure 5 This is a circuit diagram of a signal shielding logic module in one embodiment;

[0025] Figure 6 This is a schematic diagram of one overall structure of the timing window shielding circuit in one embodiment;

[0026] Figure 7 A simulated waveform is generated for the protected signal in one embodiment. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0028] It should be noted that, in this document, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments. The term "and / or" as used herein refers to any combination of one or more of the associated listed items, and all possible combinations, including such combinations.

[0029] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0030] In one embodiment, such as Figure 1 As shown, a timing window shielding circuit for radiation-hardened integrated circuits is provided, including a protection pulse generation module and a signal shielding logic module. The input terminal of the protection pulse generation module is used to receive the system clock signal, and the output terminal of the protection pulse generation module is connected to one input terminal of the signal shielding logic module. The other input terminal of the signal shielding logic module is used to receive the signal to be protected from the integrated circuit, and the output terminal of the signal shielding logic module is used to output the signal after SET shielding. The protection pulse generation module generates a protection pulse synchronized with the system clock, and the signal shielding logic module performs SET pulse isolation on the signal to be protected within the protection window provided by the protection pulse.

[0031] The width of the protection pulse satisfies: T_d ≥ T_setup + T_hold + T_margin, where T_d is the width of the protection pulse, T_setup is the shortest time during which the input signal to be protected must remain stable before the effective transition edge of the clock signal arrives, T_hold is the shortest time during which the input signal to be protected must continue to remain stable after the effective transition edge of the clock signal arrives, and T_margin is an additional buffer time added on top of the sum of the shortest times T_setup and T_hold.

[0032] It is understood that the core design concept of this embodiment is to establish a dynamic protection window for the timing circuit that is synchronized with the effective edge of the clock, and to actively shield all changes in the input signal during the dynamic protection window period, thereby fundamentally eliminating the possibility of the SET pulse being sampled.

[0033] The protection pulse generation module acts as the "clock" of the protection window, generating a protection pulse that is precisely synchronized with the system clock. The signal shielding logic module acts as the "executor" of the protection window, isolating sensitive signals within the protection window.

[0034] The timing window shielding circuit described above for radiation-hardened integrated circuits innovatively addresses the SET problem from a "time domain" perspective, directly targeting the root cause of errors—the timing-sensitive window. This allows for precise protection strategies and effectively eliminates most single-event upsets (SETs) caused by SET pulses. The circuit design is highly versatile, serving as an independent circuit architecture independent of specific circuit structures. It can be flexibly applied to various sequential circuits requiring protection, such as, but not limited to, DICE flip-flops, TMR (triple modular redundancy) systems, latches, and shift registers, demonstrating extremely high versatility. Because the protection window is extremely short and only opens after the clock edge, it does not alter the setup and hold times of the original circuit, has no impact on the system's operating frequency and timing performance, and incurs near-zero performance overhead, perfectly solving the performance degradation problem caused by traditional filtering techniques. The designed circuit is entirely implemented using standard digital units, resulting in a simple circuit structure, extremely low area and power consumption, and easy integration across various process nodes, exhibiting excellent low power consumption and low cost characteristics. Furthermore, the width of the protection pulse is determined by the physical dimensions of the delay chain, making it less affected by environmental factors, ensuring stable and reliable operation, and high robustness, making it well-suited for applications in harsh radiation environments.

[0035] In one embodiment, the protection pulse generation module includes a delay unit and a logic combination unit. The delay unit includes an even number of inverters connected in series, and its input is used to receive the system clock signal. The logic combination unit includes an AND gate and an inverter. The input of the inverter in the logic combination unit is connected to the output of the delay unit, and the output of the inverter is connected to one input of the AND gate. The other input of the AND gate is used to receive the system clock signal, and the output of the AND gate is used to output the protection pulse.

[0036] Specifically, the protection pulse generation module includes a delay unit and a logic combination unit, such as... Figure 2 As shown, the delay unit consists of multiple logic gates (preferably an even number of inverters connected in series) used to generate a fixed delay (denoted as T_d) for the clock signal CLK (i.e., the system clock signal) input to the integrated circuit, and output a delayed clock signal (denoted as CLK_d). The delay unit employs an inverter chain implementation, ensuring that the fixed delay T_d has consistent process, voltage, and temperature (PVT) characteristics with the timing parameters of the flip-flop itself (such as setup time and hold time). When environmental changes (such as space radiation) cause the sensitive window of the flip-flop to widen or narrow, the width of the protection window provided by the delay unit can adaptively change accordingly, thus providing reliable protection under various operating conditions and greatly improving the robustness of the integrated circuit. Furthermore, the design of the delay unit is essentially based on standard digital cells, resulting in a simple circuit structure that facilitates portability and integration across different process nodes.

[0037] like Figure 3As shown, the logic combination unit can be constructed using an AND gate and an inverter. The first input of the AND gate is connected to the original clock signal CLK, and the second input of the AND gate is connected to the inverted signal N_CLK_d of the aforementioned delayed clock signal CLK_d (obtained through an inverter between the delay unit and the AND gate). Figure 3 In this circuit, terminals with the same signal name are connected together, and the same applies below. The working principle is as follows:

[0038] When the valid edge (rising edge) of the original clock signal CLK arrives, the clock signal CLK immediately goes high, while the delayed clock signal CLK_d remains low due to the delay, and its inverted signal N_CLK_d goes high. At this time, both inputs of the logic combination unit are high, and the output protection pulse (denoted as GPulse) goes high. In some implementations, the protection window is open when the protection pulse is high and closed when the protection pulse is low. It can be understood that this embodiment defines: when the protection pulse GPulse is high, it indicates that the protection window is open; when the protection pulse GPulse is low, it indicates that the protection window is closed, thus efficiently and accurately indicating the opening and closing of the protection window, improving subsequent shielding efficiency (eliminating the need for further judgment on whether the protection window is open).

[0039] In some implementations, after a fixed delay T_d, the delayed clock signal CLK_d goes high, its inverted signal N_CLK_d goes low, and the output of the logic combination unit goes low, closing the protection window. Thus, the protection pulse generation module generates a protection pulse with a width precisely equal to the fixed delay generated by the delay unit in each clock cycle; that is, it can generate a protection pulse GPulse with a width precisely equal to the fixed delay T_d in each clock cycle. Figure 4 The method describes how, under SMIC 55nm process, 25° and TT process angles, the clock signal CLK is generated into a delayed clock signal CLK_d by four inverters connected in series, and then... Figure 3 The waveform diagram of the protection pulse GPulse generated by the circuit shown is shown.

[0040] In one embodiment, the signal shielding logic module includes an AND gate and an inverter. The input of the inverter in the signal shielding logic module is connected to the output of the protection pulse generation module, and the output of the inverter is connected to one input of the AND gate. The other input of the AND gate is used to input the signal to be protected. When the protection window is closed, the signal output by the AND gate completely follows the signal to be protected; when the protection window is open, the signal output by the AND gate is forced to an invalid level.

[0041] Specifically, the signal shielding logic module uses an AND gate as its main module structure. The integrated circuit signal to be protected (e.g., but not limited to data signal D and reset signal R) and the inverted signal N_Gpulse of the protection pulse GPulse (obtained through an inverter) serve as the two input signals to the signal shielding logic module. The working principle of the signal shielding logic module is as follows:

[0042] During the normal operation period (protection pulse GPulse is low): the inverted signal N_GPulse of the protection pulse GPulse is high, and the output of the signal shielding logic module completely follows the original input signal (i.e., the signal to be protected). During the protection period (protection pulse GPulse is high): the inverted signal N_GPulse of the protection pulse GPulse is low, forcing the output of the signal shielding logic module to logic '0' (or invalid level), effectively shielding the signal regardless of whether a SET pulse exists on the original input signal. Taking the protection reset signal R as an example, the circuit diagram of the signal shielding module is given as follows: Figure 5 As shown.

[0043] In some implementations, the aforementioned timing window shielding circuit can be integrated into the reset and set signal paths of a radiation-hardened DICE trigger (rising edge type) (e.g., by directly connecting the timing window shielding circuit between the signal to be protected and its back-end processing circuit, so that the signal to be protected first passes through the timing window shielding circuit before being connected to its back-end processing circuit). Taking the protection reset signal R as an example: the external reset signal R is connected to the signal shielding logic module, and its shielded reset signal RMasked is then connected to the DICE latch unit of the radiation-hardened DICE trigger; this circuit structure, while maintaining the high reliability of the DICE trigger itself, greatly solves the SET sensitivity problem of its control signal path.

[0044] In one embodiment, the delay unit comprises four inverters connected in series. It is understood that... Figure 6 This paper illustrates one example of an implementation method for protecting the reset signal R using a delay unit consisting of four inverters connected in series. Figure 7 The simulation waveform of the timing shielding circuit protecting the reset signal is also shown. Near the effective edge of the clock (taking the rising edge as an example), an error pulse (SET pulse) is injected into the trigger reset signal to generate an interfered reset signal R_SET. The protected reset signal RMasked can be obtained through the timing window shielding circuit. Those skilled in the art will understand that the specific number of inverters in series in the delay unit can be adjusted according to the process node of the integrated circuit and the required fixed delay T_d, and the protection effect can be accurately determined by simulation using conventional simulation methods.

[0045] In the above embodiments, the width of the protection pulse GPulse (i.e., the fixed delay T_d) is a core technical parameter. Its design must satisfy: T_d ≥ T_setup + T_hold + T_margin, to ensure complete coverage of the timing-sensitive window of the protected timing unit in the applied integrated circuit. Here, T_setup refers to the shortest time that the input signal to be protected (e.g., but not limited to data signal D and reset signal R) must remain stable before the effective transition edge (e.g., rising edge) of the clock signal CLK arrives; T_hold refers to the shortest time that the input signal to be protected must continue to remain stable after the effective transition edge of the clock signal CLK arrives; and T_margin is an additional buffer time added on top of the sum of the shortest times T_setup and T_hold. This design margin of adding the time buffer T_margin is to address practical issues such as process variations, environmental changes, and signal integrity in integrated circuits. Adding this design margin ensures that the protection window can completely cover the sensitive period of the protected timing circuit even in the worst-case scenario, thereby significantly improving the robustness and reliability of the circuit.

[0046] A fixed delay T_d can be precisely configured by adjusting the number of inverter stages and the transistor size in the delay unit to ensure that its width T_d (i.e., the width of the protection pulse) completely covers the timing-sensitive window of the protected sequential circuit under all process, voltage, and temperature (PVT) conditions. The specific number of inverter stages and transistor size required to achieve the fixed delay T_d can be determined using conventional circuit simulation methods.

[0047] In one embodiment, a ruggedized trigger is also provided, including the timing window shielding circuit for radiation-hardened integrated circuits described above. The timing window shielding circuit is integrated into the signal path to be protected of the trigger, and the timing window shielding circuit is used to isolate the SET pulse in the signal path to be protected; the signal path to be protected includes a reset signal path and a set signal path.

[0048] It is understood that at least one of the reset signal path and the set signal path in the ruggedized trigger of this embodiment integrates the timing window shielding circuit for radiation-resistant integrated circuits described above (other signal paths that also need protection can be integrated with timing window shielding circuits in the same way). For a detailed explanation, please refer to the description of the timing window shielding circuit embodiment for radiation-resistant integrated circuits described above. Moreover, the composition and connection relationship of the other existing circuit units of the ruggedized trigger can be understood by referring to the existing circuit configuration of each circuit unit in the existing ruggedized triggers in the art. It will not be elaborated here.

[0049] The aforementioned ruggedized trigger, by integrating the timing window shielding circuit for radiation-resistant integrated circuits into the signal path that needs protection, can effectively eliminate most single-event upsets caused by SET pulses, thereby improving the trigger's anti-single-event upset performance.

[0050] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A timing window shielding circuit for radiation-hardened integrated circuits, characterized in that, It includes a protection pulse generation module and a signal shielding logic module. The input terminal of the protection pulse generation module is used to receive the system clock signal. The output terminal of the protection pulse generation module is connected to one input terminal of the signal shielding logic module. The other input terminal of the signal shielding logic module is used to receive the signal to be protected of the integrated circuit. The output terminal of the signal shielding logic module is used to output the signal after SET shielding. The protection pulse generation module is used to generate a protection pulse synchronized with the system clock, and the signal shielding logic module is used to perform SET pulse isolation on the signal to be protected within the protection window provided by the protection pulse. The width of the protection pulse satisfies: T_d ≥ T_setup + T_hold + T_margin, where T_d is the width of the protection pulse, T_setup is the shortest time during which the input signal to be protected must remain stable before the effective transition edge of the clock signal arrives, T_hold is the shortest time during which the input signal to be protected must continue to remain stable after the effective transition edge of the clock signal arrives, and T_margin is an additional buffer time added on top of the sum of the shortest times T_setup and T_hold.

2. The timing window shielding circuit for radiation-resistant integrated circuits according to claim 1, characterized in that, The protection pulse generation module includes a delay unit and a logic combination unit. The delay unit includes an even number of inverters connected in series. The input of the delay unit is used to connect to the system clock signal. The logic combination unit includes an AND gate and an inverter. The input of the inverter in the logic combination unit is connected to the output of the delay unit. The output of the inverter in the logic combination unit is connected to one input of the AND gate. The other input of the AND gate is used to input the system clock signal. The output of the AND gate is used to output a protection pulse.

3. The timing window shielding circuit for radiation-resistant integrated circuits according to claim 2, characterized in that, The delay unit consists of four inverters connected in series.

4. The timing window shielding circuit for radiation-resistant integrated circuits according to claim 2 or 3, characterized in that, The protection pulse generation module generates a protection pulse with a width exactly equal to the fixed delay generated by the delay unit in each clock cycle.

5. The timing window shielding circuit for radiation-resistant integrated circuits according to claim 4, characterized in that, The protection window is open when the protection pulse is high; the protection window is closed when the protection pulse is low.

6. The timing window shielding circuit for radiation-hardened integrated circuits according to claim 1, characterized in that, The signal shielding logic module includes an AND gate and an inverter. The input of the inverter in the signal shielding logic module is connected to the output of the protection pulse generation module. The output of the inverter in the signal shielding logic module is connected to one input of the AND gate, and the other input of the AND gate is used to input the signal to be protected. When the protection window is closed, the signal output by the AND gate completely follows the signal to be protected. When the protection window is open, the signal output by the AND gate is forced to an invalid level.

7. A ruggedized trigger, characterized in that, The timing window shielding circuit for radiation-resistant integrated circuits as described in any one of claims 1 to 6 is integrated into the signal path to be protected of the trigger, and the timing window shielding circuit is used to isolate the SET pulse in the signal path to be protected. The signal path to be protected includes the reset signal path and the set signal path.

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