Quadrature phase calibration circuit, operation method of quadrature phase calibration circuit and chip

Abstract

The invention provides a quadrature phase calibration circuit, an operation method of the quadrature phase calibration circuit and a chip, and relates to the field of artificial intelligence chips. The quadrature phase calibration circuit comprises a delay circuit, a first voltage regulation circuit, a second voltage regulation circuit, a comparator circuit and a state machine circuit. The signal input end is connected with the first input end of the delay circuit, and the delay circuit transmits the output to the first voltage regulating circuit and the second voltage regulating circuit respectively. The calibration ends of the two voltage regulating circuits are fed back to the signal input end, and the outputs of the two voltage regulating circuits are jointly fed into the comparator circuit to form a pair of differential signals. A judgment result output by the comparator circuit is sent to the state machine circuit to be analyzed, the state machine circuit generates a corresponding control signal and feeds the control signal back to the second input end of the delay circuit, and therefore a complete closed-loop regulation and control system is formed. The invention aims to solve the problem that an existing quadrature phase calibration scheme cannot meet the calibration precision requirement.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of artificial intelligence chips, in particular to a quadrature phase calibration circuit, an operation method of the quadrature phase calibration circuit and a chip. BACKGROUND

[0002] With the rapid development of artificial intelligence, the total amount of data processing is increasing, and the requirement for data transmission rate is also increasing. In the process of high-speed transmission, high-precision phase calibration technology is needed to ensure high-quality signal transmission. Through quadrature phase calibration, the interference caused by amplitude fluctuation and noise can be effectively eliminated, ensuring the accuracy and stability of the signal in the transmission process, and thus improving the performance and accuracy of the entire system.

[0003] However, the current quadrature phase calibration technology cannot meet the application requirements in the high-speed transmission and large-scale data processing scenarios in terms of calibration accuracy. SUMMARY

[0004] The embodiments disclosed in the present application provide a quadrature phase calibration circuit, an operation method of the quadrature phase calibration circuit and a chip. The embodiments of the present application adopt the following technical solutions: In a first aspect, a quadrature phase calibration circuit is provided, comprising: a delay circuit, a first voltage regulating circuit, a second voltage regulating circuit, a comparator circuit and a state machine circuit. The first input end of the delay circuit is electrically connected with the signal input end. The first output end of the delay circuit is electrically connected with the input end of the first voltage regulating circuit. The second output end of the delay circuit is electrically connected with the input end of the second voltage regulating circuit. The calibration end of the first voltage regulating circuit is electrically connected with the signal input end. The output end of the first voltage regulating circuit is electrically connected with the first input end of the comparator circuit. The calibration end of the second voltage regulating circuit is electrically connected with the signal input end. The output end of the second voltage regulating circuit is electrically connected with the second input end of the comparator circuit. The voltage signals output by the first voltage regulating circuit and the second voltage regulating circuit constitute a differential pair signal. The output end of the comparator circuit is electrically connected with the input end of the state machine circuit. The output end of the state machine circuit is electrically connected with the second input end of the delay circuit.

[0005] The quadrature phase calibration circuit provided by the present application dynamically adjusts the input threshold of the comparator circuit by using two voltage circuits. The two voltage circuits generate different voltage signals respectively. By adjusting the voltage signals input into the comparator circuit, the input threshold of the comparator circuit can be accurately controlled. In this way, not only the amplitude fluctuation interference caused by the fixed threshold is eliminated, but also the adaptability of the system to external changes is improved, and the calibration accuracy is improved. Moreover, by making the two voltage circuits output a set of differential pair signals, the interference of the comparator circuit caused by the signals of the two input ends of the comparator circuit approaching each other can be improved, thereby further improving the calibration accuracy of the quadrature phase calibration circuit.

[0006] In a possible implementation of the first aspect, the comparator circuit is configured to output a voltage comparison result based on the input differential pair signal, the state machine circuit is configured to adjust a code word signal output to the delay circuit based on the voltage comparison result, and the delay circuit is configured to receive a first clock signal input at a signal input terminal and output a second clock signal at a first output terminal and a second output terminal, a phase difference between the second clock signal and the first clock signal being determined based on the code word signal.

[0007] In a possible implementation of the first aspect, the first voltage regulation circuit includes an XNOR phase detector and a first integrator circuit, the second voltage regulation circuit includes an XOR phase detector and a second integrator circuit, an input terminal of the XNOR phase detector is electrically connected to an input terminal of the first voltage regulation circuit, an output terminal of the XNOR phase detector is electrically connected to an input terminal of the first integrator circuit, a calibration terminal of the XNOR phase detector is electrically connected to a calibration terminal of the first voltage regulation circuit, an output terminal of the first integrator circuit is electrically connected to an output terminal of the first voltage regulation circuit, an input terminal of the XOR phase detector is electrically connected to an input terminal of the second voltage regulation circuit, an output terminal of the XOR phase detector is electrically connected to an input terminal of the second integrator circuit, a calibration terminal of the XOR phase detector is electrically connected to a calibration terminal of the second voltage regulation circuit, and an output terminal of the second integrator circuit is electrically connected to an output terminal of the second voltage regulation circuit.

[0008] In a possible implementation of the first aspect, the XNOR phase detector is configured to convert the second clock signal into a first duty cycle signal, the first integrator circuit is configured to convert the first duty cycle signal into a first voltage signal, the XOR phase detector is configured to convert the second clock signal into a second duty cycle signal, and the second integrator circuit is configured to convert the second duty cycle signal into a second voltage signal, the first voltage signal and the second voltage signal forming the differential pair signal.

[0009] In a second aspect, an operation method of a quadrature phase calibration circuit is provided, the method including: in a first calibration stage, determining an initial code word based on a bisection method; in a second calibration stage, determining a first flipped code word and a second flipped code word based on the initial code word; in a third calibration stage, flipping first and second voltage signals input to a comparator circuit, and determining a third flipped code word and a fourth flipped code word based on the first flipped code word and the second flipped code word; determining a target code word based on an average of a sum of the first flipped code word, the second flipped code word, the third flipped code word, and the fourth flipped code word; and adjusting a code word signal provided by a state machine circuit to a delay circuit based on the target code word.

[0010] The operation method of the quadrature phase calibration circuit provided by the embodiments of the present application ensures accurate positioning of a flipping point in each calibration process by flipping input signals of a comparator circuit and re-executing multiple calibration operations, and improves the measurement accuracy of the comparator circuit.

[0011] In a possible implementation of the second aspect, in the second calibration stage, the first flip code and the second flip code are determined based on the initial code word, comprising: determining a first initial code word based on the initial code word, obtaining a first modified code word based on the first initial code word, the first initial code word and the first modified code word being sequentially and equally increased, determining the first flip code based on a voltage comparison result corresponding to the first modified code word and a voltage comparison result corresponding to the first initial code word, determining a second initial code word based on the initial code word, obtaining a second modified code word based on the second initial code word, the second initial code word and the second modified code word being sequentially and equally decreased, and determining the second flip code based on a voltage comparison result corresponding to the second modified code word and a voltage comparison result corresponding to the second initial code word.

[0012] In a possible implementation of the second aspect, the first flip code is determined based on a voltage comparison result corresponding to the first modified code word and a voltage comparison result corresponding to the first initial code word, comprising: determining whether the voltage comparison result corresponding to the first modified code word and the voltage comparison result corresponding to the first initial code word are the same, in the case that the voltage comparison result corresponding to the first modified code word and the voltage comparison result corresponding to the first initial code word are different, repeatedly performing the step of determining whether the voltage comparison result corresponding to the first modified code word and the voltage comparison result corresponding to the first initial code word are the same, and in the case that the number of times of determination is greater than or equal to a determination threshold, determining the first modified code word as the first flip code.

[0013] In a possible implementation of the second aspect, the second flip code is determined based on a voltage comparison result corresponding to the second modified code word and a voltage comparison result corresponding to the second initial code word, comprising: determining whether the voltage comparison result corresponding to the second modified code word and the voltage comparison result corresponding to the second initial code word are the same, in the case that the voltage comparison result corresponding to the second modified code word and the voltage comparison result corresponding to the second initial code word are different, repeatedly performing the step of determining whether the voltage comparison result corresponding to the second modified code word and the voltage comparison result corresponding to the second initial code word are the same, and in the case that the number of times of determination is greater than or equal to a determination threshold, determining the second modified code word as the second flip code.

[0014] In a possible implementation of the second aspect, determining the third flipped code word and the fourth flipped code word based on the first flipped code word and the second flipped code word comprises: determining a third initial code word based on a sum average result of the first flipped code word and the second flipped code word, determining a third modified code word based on a voltage comparison result corresponding to the third initial code word, the third initial code word and the third modified code word being sequentially equal in decrement or sequentially equal in increment, determining the third flipped code word based on a voltage comparison result corresponding to the third initial code word and a voltage comparison result corresponding to the third modified code word, determining a fourth initial code word based on a comparison result of the third flipped code word and the third initial code word, determining a fourth modified code word based on a voltage comparison result corresponding to the fourth initial code word, the fourth initial code word and the fourth modified code word being sequentially equal in decrement or sequentially equal in increment, and determining the fourth flipped code word based on a voltage comparison result corresponding to the fourth initial code word and a voltage comparison result corresponding to the fourth modified code word.

[0015] In a third aspect, a chip is provided, comprising the quadrature phase calibration circuit of any one of the first aspect or any one of the implementation forms thereof.

[0016] It can be understood that the technical effects of the third aspect refer to the technical effects of the first aspect and any one of the implementation forms thereof, which are not repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 FIG. 1 is a structural schematic diagram of a quadrature phase calibration circuit according to an embodiment of the present application; Figure 2 FIG. 2 is a structural schematic diagram of a quadrature phase calibration circuit according to another embodiment of the present application; Figure 3 FIG. 3 is a structural schematic diagram of a quadrature phase calibration circuit according to another embodiment of the present application; Figure 4 FIG. 4 is a step flowchart of an operation method of a quadrature phase calibration circuit according to an embodiment of the present application; Figure 5 FIG. 5 is a step flowchart of an operation method of a quadrature phase calibration circuit according to another embodiment of the present application; Figure 6 FIG. 6 is a step flowchart of an operation method of a quadrature phase calibration circuit according to another embodiment of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments provided by the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0019] Unless otherwise required by context, the term "including" as used herein is to be interpreted as open, i.e. meaning "including, but not limited to." In describing the embodiments, the terms "one embodiment," "some embodiments," "an exemplary embodiment," "an example embodiment," "exemplary embodiments," or "some examples" are used. Such terms are not necessarily referring to the same embodiment or example. Furthermore, the terms "embodiment" or "example" are used to describe at least one embodiment or example. Thus, the terms "embodiment" or "example" include at least one embodiment or example.

[0020] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description, and are not to be construed as indicating or implying relative importance or implying the number of the indicated technical features. Thus, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise stated.

[0021] In describing some embodiments, the term "electrically connected" and its derivatives can be used. For example, the term "electrically connected" can be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact, in which case "electrically connected" can also be described as "electrically connected." In addition, the term "electrically connected" can also mean that two or more components have no direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0022] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0023] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B. The use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps. In addition, the use of "based on" means open and inclusive, as a process, step, calculation, or other action "based on" one or more conditions or values can be based on additional conditions or values in practice.

[0024] The use of "configured to" herein means open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

[0025] In the current era of rapid development of artificial intelligence technology, the total amount of global data generation and processing is increasing exponentially, and the data transmission rate is also constantly breaking through the original upper limit. When the signal rate enters a higher transmission level, any slight timing deviation or phase mismatch can cause serious inter-symbol interference and bit error rate rise, directly affecting the effective throughput and reliability of the system. In high-speed communication systems, information is often carried on mutually orthogonal carriers, i.e., in-phase components and quadrature components. Ideally, the two signals should maintain a 90-degree phase difference to ensure that the original data can be demodulated without distortion at the receiving end.

[0026] However, in actual hardware systems, due to the inherent tolerance of analog components, channel characteristic drift caused by temperature changes, differences in PCB wiring length, and slight asymmetry of the clock distribution network, etc., signal distortion, jitter or distortion may occur, affecting the high-quality transmission of signals.

[0027] In related technologies, the above problems can be improved by using a quadrature phase calibration technique, which is a technique for ensuring that the signal maintains ideal orthogonality during transmission and eliminates phase errors caused by hardware, environment, or other factors. It is commonly used in high-speed communication systems, especially in scenarios where signals need to carry a large amount of information, such as high-data-rate wireless communication, optical fiber communication, etc. Specifically, the quadrature phase calibration technique ensures that the two orthogonal signals (i.e., in-phase components and quadrature components) maintain an accurate 90-degree phase difference by detecting and adjusting the phase difference of the signal in real time.

[0028] As an example, refer to Figure 1 The quadrature phase calibration circuit shown in FIG. 1 includes a delay circuit, an XOR phase detector, an integration circuit, a comparator circuit, and a state machine circuit. The first input terminal of the delay circuit is connected to the signal input terminal, the output terminal of the delay circuit is electrically connected to the input terminal of the XOR phase detector, the calibration terminal of the XOR phase detector is electrically connected to the signal input terminal, the output terminal of the XOR phase detector is connected to the input terminal of the integration circuit, the output terminal of the integration circuit is electrically connected to the first input terminal of the comparator circuit, the second input terminal of the comparator circuit is connected to the bias voltage input terminal, the output terminal of the comparator circuit is electrically connected to the input terminal of the state machine circuit, and the output terminal of the state machine circuit is electrically connected to the second input terminal of the delay circuit.

[0029] In the above-mentioned quadrature phase calibration circuit, a first clock signal (reference clock signal) can be input through a signal input terminal. The first clock signal is directly input to one input terminal of the XOR phase detector as a calibration reference, and the other input terminal of the XOR phase detector is connected to the output terminal of the delay circuit. The delay circuit performs controllable delay processing on the first clock signal and outputs a second clock signal. In the ideal calibration state, by accurately controlling the delay amount, the first clock signal and the second clock signal can be accurately phase-shifted by 90°, i.e., the quadrature relationship is formed. Then, the second clock signal is sent to the other input terminal of the XOR phase detector. The XOR phase detector simultaneously receives the original first clock signal and the delayed second clock signal, and then outputs a pulse width signal representing the phase relationship between the first clock signal and the second clock signal. When the phase difference deviates from the ideal 90°, the pulse width will change accordingly. The pulse width signal output by the XOR phase detector is then sent to the integration circuit. The integration circuit converts the pulse width signal into a smooth direct current voltage signal whose direct current level is proportional to the pulse width. Then the direct current voltage signal is sent to one input terminal of the comparator circuit and compared with a preset fixed bias voltage (usually corresponding to the expected integration voltage of the ideal 90° phase difference) connected to the other input terminal of the comparator circuit. The output of the comparator circuit is a digital decision signal representing whether the current phase difference is leading or lagging the target value. The digital decision signal is sent to the state machine circuit, which makes logical judgments based on the comparison result of the comparator circuit according to a preset algorithm (such as binary search or step adjustment), and generates a corresponding code word signal. The code word signal is fed back to the second input terminal of the delay circuit, so as to dynamically and accurately adjust the delay amount of the delay circuit and change the phase adjustment value of the second clock signal.

[0030] The above-mentioned quadrature phase calibration circuit converts the phase relationship between the clock signal input to the delay circuit and the clock signal output from the delay circuit into a pulse width signal, then integrates the pulse width signal representing the phase error to convert it into a corresponding direct current voltage signal, and then compares the direct current voltage signal with a preset threshold voltage to accurately determine whether the signal phase is in the leading or lagging state. The state machine circuit adjusts the code word signal output based on the comparison result, and feeds back the code word signal to the delay circuit to control the delay amount inside the delay circuit. Through such a closed-loop feedback mechanism, the quadrature phase calibration circuit can dynamically compensate for the phase deviation and finally adjust the phase difference between the two clock signals to an accurate quadrature relationship.

[0031] However, the above-mentioned quadrature phase calibration circuit has some deficiencies. First, the above-mentioned scheme relies on a fixed bias voltage as the threshold reference for the decision of the comparator circuit. In the ideal case, the threshold Vth should be set to half of the signal amplitude. However, in the actual working condition, the amplitude of the signal may fluctuate due to power supply noise, channel loss or temperature effect. At this time, if the threshold voltage remains fixed, it will lead to the deviation of the decision point of the comparator circuit from the theoretical midpoint, thereby introducing systematic phase measurement error, making the calibrated quadrature phase deviate from the expected 90 degrees. The non-ideal characteristics of the comparator circuit itself is another defect. First, when the voltage values of the two input terminals of the comparator circuit are very close, the output state may become uncertain due to internal noise and random disturbance, and even oscillation. In the convergence stage of the calibration process, the output voltage of the integrator will approach the fixed threshold, and it is in this critical state that the unreliability of the comparison result will seriously delay or even disturb the judgment logic of the state machine. Second, the inherent input offset voltage of the comparator circuit will introduce a constant DC bias. For a single comparison, this small bias voltage is enough to falsely flip the decision result, so that the final accuracy of the entire high-precision closed-loop calibration system is limited by this lowest performance analog component, causing the degradation of the overall system performance.

[0032] To improve the above-mentioned problems, the present application provides a quadrature phase calibration circuit, by setting two voltage circuits, dynamically adjusting the dynamic threshold of the input of the comparator circuit, which can improve the interference of the amplitude fluctuation of the fixed threshold on the comparison result of the comparator circuit, thereby improving the calibration accuracy of the quadrature phase calibration circuit, and by outputting a set of differential pair signals from the two voltage circuits, which can improve the interference of the comparison result of the comparator circuit when the signals of the two input terminals of the comparator circuit are close, thereby further improving the calibration accuracy of the quadrature phase calibration circuit.

[0033] As an example, referring to Figure 2 The quadrature phase calibration circuit shown in the figure comprises a delay circuit, a first voltage regulating circuit, a second voltage regulating circuit, a comparator circuit and a state machine circuit. The first input terminal of the delay circuit is electrically connected with the signal input terminal. The first output terminal of the delay circuit is electrically connected with the input terminal of the first voltage regulating circuit. The second output terminal of the delay circuit is electrically connected with the input terminal of the second voltage regulating circuit. The calibration terminal of the first voltage regulating circuit is electrically connected with the signal input terminal. The output terminal of the first voltage regulating circuit is electrically connected with the first input terminal of the comparator circuit. The calibration terminal of the second voltage regulating circuit is electrically connected with the signal input terminal. The output terminal of the second voltage regulating circuit is electrically connected with the second input terminal of the comparator circuit. The voltage signals outputted by the first voltage regulating circuit and the second voltage regulating circuit constitute a differential pair signal. The output terminal of the comparator circuit is electrically connected with the input terminal of the state machine circuit. The output terminal of the state machine circuit is electrically connected with the second input terminal of the delay circuit.

[0034] The working principle of the quadrature phase calibration circuit provided by the embodiment of the present application is described below. The reference clock signal can be input into the delay circuit from the signal input end. The delay circuit processes the clock signal based on the control code word received by its second input end, and outputs two clock signals with a phase relationship close to quadrature but not yet accurately calibrated. The two signals are output from the first output end and the second output end respectively, and are sent to the first voltage regulating circuit and the second voltage regulating circuit respectively.

[0035] The first voltage regulating circuit and the second voltage regulating circuit are phase-to-voltage conversion units for converting phase error information into a voltage signal that can be accurately processed. Specifically, each voltage regulating circuit acts as a phase-to-voltage converter, synchronously receives the original reference clock and the clock to be calibrated processed by the delay circuit, and linearly maps the phase difference therebetween into a direct current voltage signal. The voltage signals output by the two symmetrical voltage regulating circuits constitute a pair of differential signals, which enables the subsequent comparator circuit to not rely on a fixed threshold voltage susceptible to amplitude fluctuations. This differential architecture can have the ability to suppress common mode interference and effectively alleviate the decision error introduced by the self-offset voltage of the comparator circuit.

[0036] After receiving the first voltage signal output by the first voltage regulating circuit and the second voltage signal output by the second voltage regulating circuit, the comparator circuit can output a digital signal representing the comparison result to the state machine circuit based on the relative size relationship between the first voltage signal and the second voltage signal.

[0037] For example, when the first voltage signal is greater than the second voltage, the comparator can output a digital signal of 0, and when the first voltage signal is less than or equal to the second voltage, the comparator can output a digital signal of 1. Alternatively, when the first voltage signal is greater than the second voltage, the comparator can output a digital signal of 1, and when the first voltage signal is less than or equal to the second voltage, the comparator can output a digital signal of 0.

[0038] After the state machine circuit receives the digital signal, it can output a code word signal representing the calibration phase adjustment result to the delay circuit based on the digital signal. The delay circuit adjusts the phase difference between the first clock signal and the second clock signal based on the received code word signal, thereby achieving accurate clock synchronization or phase calibration. Specifically, the delay circuit dynamically adjusts the delay time based on the indication information in the code word signal to control the phase difference between the two clock signals, so that the signal synchronization meets the phase requirements.

[0039] The orthogonal phase calibration circuit provided in the application dynamically adjusts the input threshold of the comparator circuit by adopting two voltage circuits. The two voltage circuits respectively generate different voltage signals, and by adjusting the amplitudes of these signals, the input threshold of the comparator circuit can be accurately controlled. In this way, not only is the amplitude fluctuation interference caused by the fixed threshold eliminated, but also the adaptability of the system to external changes is improved, and the judgment accuracy of the comparator circuit is improved.

[0040] The first voltage regulating circuit and the second voltage regulating circuit can have various implementation manners in circuit structure. In a feasible implementation manner, referring to Figure 3 , the first voltage regulating circuit comprises an XNOR phase detector and a first integration circuit, and the second voltage regulating circuit comprises a NOR phase detector and a second integration circuit. The input end of the XNOR phase detector is electrically connected with the input end of the first voltage regulating circuit, the output end of the XNOR phase detector is electrically connected with the input end of the first integration circuit, the calibration end of the XNOR phase detector is electrically connected with the calibration end of the first voltage regulating circuit, the output end of the first integration circuit is electrically connected with the output end of the first voltage regulating circuit, the input end of the NOR phase detector is electrically connected with the input end of the second voltage regulating circuit, the output end of the NOR phase detector is electrically connected with the input end of the second integration circuit, the calibration end of the NOR phase detector is electrically connected with the calibration end of the second voltage regulating circuit, and the output end of the second integration circuit is electrically connected with the output end of the second voltage regulating circuit.

[0041] It should be noted that the first input end of the comparator circuit can be a positive input end, and the second input end can be a negative input end, that is, the XNOR phase detector is connected with the positive input end of the comparator circuit through the first integration circuit, and the NOR phase detector is connected with the negative input end of the comparator circuit through the second integration circuit. While the first input end of the comparator circuit can be a negative input end, and the second input end can be a positive input end, that is, the XNOR phase detector is connected with the negative input end of the comparator circuit through the first integration circuit, and the NOR phase detector is connected with the positive input end of the comparator circuit through the second integration circuit. The specific connection relationship between the comparator circuit and the phase detector is not limited in the application.

[0042] In a feasible implementation manner, the XNOR phase detector is used to convert the second clock signal into a first duty cycle signal, the first integration circuit is used to convert the first duty cycle signal into a first voltage signal, the NOR phase detector is used to convert the second clock signal into a second duty cycle signal, and the second integration circuit is used to convert the second duty cycle signal into a second voltage signal.

[0043] In the embodiment, the XNOR phase discriminator is used to convert the second clock signal into the first duty cycle signal. Specifically, the XNOR phase discriminator outputs a duty cycle signal related to the phase of the input clock signal by performing logical operation on the input clock signal. The function of the integration circuit is to integrate the duty cycle signal, thereby generating a first voltage signal related to the duty cycle. The first voltage signal reflects the average value of the duty cycle signal over a period of time, thereby providing a stable voltage reference for subsequent calibration. The XOR phase discriminator is used to convert the second clock signal into the second duty cycle signal. The function of the NOR phase discriminator is similar to that of the XNOR phase discriminator, but the logical operation is different, which is used to generate a duty cycle signal related to the phase of the input signal. The second integration circuit is used to convert the second duty cycle signal into the second voltage signal. Similar to the first integration circuit, the second integration circuit generates a second voltage signal by integrating the second duty cycle signal. The second voltage signal also reflects the average change of the duty cycle signal over time, thereby providing further reference for signal processing in the calibration process. The first voltage signal and the second voltage signal constitute a differential signal pair. Therefore, when the input comparator circuit, even if the first voltage signal and the second voltage signal are similar, it will not affect the accuracy of the judgment of the comparator circuit.

[0044] The above embodiment describes the structure and working principle of the quadrature phase calibration circuit provided by the present application. In order to further improve the calibration accuracy, based on the above quadrature phase calibration circuit, the embodiment of the present application provides an operation method of the quadrature phase calibration circuit. Referring to the step flow chart of the operation method of the quadrature phase calibration circuit shown in Figure 4

[0045] S401: In the first calibration stage, the initial code word is determined based on the bisection method.

[0046] After the initial clock signal is input to the signal input end of the quadrature phase calibration circuit, the calibration process can be started. The calibration process can be divided into three calibration stages. The first calibration stage can be a coarse calibration stage, in which the signal is roughly calibrated by the bisection method. Specifically, the bisection method gradually divides the calibration interval in half to quickly narrow the possible phase error range. In this way, an initial code word (phase1_code0) can be quickly obtained, and the time of the entire calibration process is shortened. This fast coarse adjustment process ensures that the calibration system obtains sufficient phase calibration information in a short time, thereby providing a more ideal initial value for the subsequent fine adjustment stage.

[0047] ​As an example, in the determination of the initial code word, the code word most significant bit (MSB) is set to 1 and the rest of the positions are set to 0 at initialization, the reference code word can be "10000", and the bit index n = 5 is set at the same time. Then enter the calibration cycle: the delay circuit outputs the corresponding delay amount based on the current code word output, and waits for the feedback signal output by the comparator. If the feedback signal is -1 (indicating phase lag), the current code bit code[n-1]=1 is kept; if the feedback signal is 0 (indicating phase advance), the position 0 (code[n-1]=0) is set. After completing the current bit decision, the bit index n is reduced by 1, and the system performs the same decision operation on the next high bit. Such iterative cycles determine the values of each code bit from the highest bit to the lowest bit, until n = 0, all bits are calibrated, the first calibration stage is completed, and the initial code word (phase1_code0) is obtained.

[0048] S402: In the second calibration stage, based on the initial code word, the first flip code word and the second flip code word are determined.

[0049] After obtaining the initial code word through the first calibration stage, the initial code word can be used as the basis for code word adjustment in the second calibration stage. A fine calibration is then performed. Specifically, by accurately capturing the flip critical point of the comparator output result, the time of signal flip can be monitored and identified in real time. Thus, the measurement error caused by the accuracy limitation of the comparator itself or noise interference is effectively reduced, and the calibration accuracy is significantly improved. The code word corresponding to the flip critical point can be the first flip code word (phase2_code0) and the second flip code word (phase2_code1).

[0050] S403: In the third calibration stage, the first voltage signal and the second voltage signal at the input end of the comparator circuit are flipped, and based on the first flip code word and the second flip code word, the third flip code word and the fourth flip code word are determined.

[0051] After the first flipping code word (phase2_code0) and the second flipping code word (phase2_code1) are determined through the second calibration stage, then the third flipping code word and the fourth flipping code word can be determined based on the first flipping code word (phase2_code0) and the second flipping code word (phase2_code1). Specifically, in the third calibration stage, first, the first voltage signal and the second voltage signal at the input end of the flipping comparator circuit are needed. For example, if the first voltage signal is input at the first input end of the comparator circuit and the second voltage signal is input at the second voltage end in the second calibration stage, then in the third calibration stage, the second voltage signal is needed to be input at the first input end of the comparator circuit and the first voltage signal is needed to be input at the second voltage end. Then, based on the first flipping code word (phase2_code0) and the second flipping code word (phase2_code1), the flipping critical point is re-determined through circulation and feedback, and the code word corresponding to the flipping critical point can be the third flipping code word (phase3_code0) and the fourth flipping code word (phase3_code1).

[0052] S404: Determine the target code word based on the sum and average result of the first flipping code word, the second flipping code word, the third flipping code word and the fourth flipping code word, and adjust the code word signal provided by the state machine circuit to the delay circuit based on the target code word.

[0053] After completing the three calibration stages and obtaining the first flipping code word (phase2_code0), the second flipping code word (phase2_code1), the third flipping code word (phase3_code0) and the fourth flipping code word (phase3_code1), then the target code word (tar_code) can be determined based on this. Specifically, the target code word (tar_code) can satisfy the relationship shown in formula (1).

[0054] tar_code=(phase2_code0+phase2_code1+phase3_code0+phase3_code1) / 4 (1).

[0055] After the target code word is determined, the state machine circuit can adjust the code word signal output to the delay circuit based on the target code word. The delay circuit controls the delay value of the clock signal based on the received adjusted code word signal, so as to accurately adjust the phase difference between the first clock signal and the second clock signal. Specifically, the delay circuit will dynamically adjust the delay time of its internal delay element based on the phase information represented by the target code word, so that the phase difference between the two clock signals is minimized or reaches the expected value.

[0056] In a feasible implementation, in the second calibration stage, the specific implementation steps of determining the first flipping code word and the second flipping code word based on the initial code word can include S501 to S504, as shown in the step flow chart of FIG. 5. Figure 5 Figure 5

[0057] S501: determining a first initial code word based on the initial code word, obtaining a first modified code word based on the first initial code word, and sequentially increasing the first initial code word and the first modified code word by equal increments; S502: determining the first flipping code word based on the voltage comparison result corresponding to the first modified code word and the voltage comparison result corresponding to the first initial code word; S503: determining a second initial code word based on the initial code word, obtaining a second modified code word based on the second initial code word, and sequentially decreasing the second initial code word and the second modified code word by equal increments; S504: determining the second flipping code word based on the voltage comparison result corresponding to the second modified code word and the voltage comparison result corresponding to the second initial code word.

[0058] First, the determination process of the first flipping code word is described. After the initial code word (phase1_code0) is determined, an adjustment value can be added to the initial code word (phase1_code0) to obtain a first initial code word. As an example, the adjustment value can be 8, and the first initial code word can be (phase1_code0+8). Then, the code word signal output to the delay circuit is adjusted based on the first initial code word, and the comparison result fed back by the comparator is waited. Then, the first initial code word is finely adjusted based on the comparison result fed back by the comparator to obtain a first modified code word. As an example, if the voltage comparison result fed back by the comparator is 1, the first modified code word can be (phase1_code0+8+1), and if the comparison result fed back by the comparator is 0, the first modified code word can be (phase1_code0+8-1). Then, the voltage comparison result based on the first modified code word is obtained, and the first modified code word is updated based on the voltage comparison result based on the first modified code word. As an example, if the voltage comparison result fed back by the comparator is 1, the first modified code word is adjusted based on the first modified code word to obtain an updated first modified code word (phase1_code0+8+1+1) or (phase1_code0+8-1-1).

[0059] ​​Then, the first flipping code word is determined based on the voltage comparison results corresponding to the first modified code word and the second modified code word. In an example, the first flipping code word is determined based on the voltage comparison results corresponding to the first modified code word and the second modified code word, including: determining whether the voltage comparison result corresponding to the first modified code word is the same as the voltage comparison result corresponding to the second modified code word, and in the case that the voltage comparison result corresponding to the first modified code word is different from the voltage comparison result corresponding to the second modified code word, repeatedly performing the step of determining whether the voltage comparison result corresponding to the first modified code word is the same as the voltage comparison result corresponding to the second modified code word, and in the case that the number of times of determination is greater than or equal to a determination threshold, determining the second modified code word as the first flipping code word.

[0060] After obtaining the voltage comparison result of the first modified code word, it is compared with the voltage comparison result of the first starting code word. If they are the same, the process of updating the first modified code word is continued. If they are different, the repeated adoption operation needs to be performed. As an example, if the voltage comparison result corresponding to the first starting code word is 1, and if the voltage comparison result corresponding to the first modified code word is also 1, then the step of updating the first modified code word needs to be continued. However, if the voltage comparison result corresponding to the first starting code word is 1, and if the voltage comparison result corresponding to the first modified code word is 0, it indicates that a flipping point may occur at this time. If a flipping point occurs, further determination and confirmation are needed. Specifically, the voltage comparison result needs to be verified for multiple times in succession to determine the exact position of the flipping point. As an example, a threshold value of 8 is set, that is, the opposite voltage comparison result needs to occur for 8 times in succession to confirm that the current first modified code word has experienced flipping and determine it as the first flipping code word. The way of verifying for multiple times in succession helps to exclude accidental signal fluctuation or error and ensures that the determination of the flipping point is more accurate. After confirming the flipping point, the system can continue to perform the subsequent calibration operation based on the flipping code word, thereby further optimizing the phase calibration of the signal and ensuring that the final calibration result is more accurate and stable.

[0061] Then, the determination process of the second flipping code word is described. After determining the initial code word (phase1_code0), a second starting code word can be obtained by reducing an adjustment value from the initial code word (phase1_code0). As an example, the adjustment value can be 8, and the second starting code word can be (phase1_code0-8). The process of determining the second flipping code word based on the second starting code word is the same as the process of determining the first flipping code word based on the first starting code word, and thus is not described in detail.

[0062] In an embodiment, the second flipping code word is determined based on the voltage comparison result corresponding to the second modified code word and the voltage comparison result corresponding to the second initial code word. The determination includes: determining whether the voltage comparison result corresponding to the second modified code word is the same as the voltage comparison result corresponding to the second initial code word; if the voltage comparison result corresponding to the second modified code word is different from the voltage comparison result corresponding to the second initial code word, repeating the determination; and if the number of times of the determination is greater than or equal to a threshold, determining the second modified code word as the second flipping code word.

[0063] The determination of the second flipping code word based on the voltage comparison result corresponding to the second modified code word and the voltage comparison result corresponding to the second initial code word is the same as the determination of the second flipping code word based on the voltage comparison result corresponding to the first modified code word and the voltage comparison result corresponding to the first initial code word, and thus will not be described again.

[0064] In an embodiment, the third flipping code word and the fourth flipping code word are determined based on the first flipping code word and the second flipping code word. The determination includes: determining a third initial code word based on the sum of the first flipping code word and the second flipping code word; determining a third modified code word based on a voltage comparison result corresponding to the third initial code word, the third initial code word and the third modified code word being sequentially equal in decrement or sequentially equal in increment; determining a third flipping code word based on the voltage comparison result corresponding to the third initial code word and the voltage comparison result corresponding to the third modified code word; determining a fourth initial code word based on a comparison result of the third flipping code word and the third initial code word; determining a fourth modified code word based on a voltage comparison result corresponding to the fourth initial code word, the fourth initial code word and the fourth modified code word being sequentially equal in decrement or sequentially equal in increment; and determining a fourth flipping code word based on the voltage comparison result corresponding to the fourth initial code word and the voltage comparison result corresponding to the fourth modified code word. Figure 6 Figure 6 The determination of the third flipping code word and the fourth flipping code word based on the first flipping code word and the second flipping code word can include S601 to S606, as shown in the flow chart of FIG. 6.

[0065] S601: determining a third initial code word based on the sum of the first flipping code word and the second flipping code word; S602: determining a third modified code word based on a voltage comparison result corresponding to the third initial code word, the third initial code word and the third modified code word being sequentially equal in decrement or sequentially equal in increment; S603: determining a third flipping code word based on the voltage comparison result corresponding to the third initial code word and the voltage comparison result corresponding to the third modified code word; S604: determining a fourth initial code word based on a comparison result of the third flipping code word and the third initial code word; S605: determining a fourth modified code word based on a voltage comparison result corresponding to the fourth initial code word, the fourth initial code word and the fourth modified code word being sequentially equal in decrement or sequentially equal in increment; S606: determining a fourth flipping code word based on the voltage comparison result corresponding to the fourth initial code word and the voltage comparison result corresponding to the fourth modified code word.

[0066] ​Firstly, the determination process of the third flipping code word is explained. After the first flipping code word (phase2_code0) and the second flipping code word (phase2_code1) are determined, the third initial code word (phase3_avg) can be determined according to the average result of the sum of the first flipping code word (phase2_code0) and the second flipping code word (phase2_code1), which satisfies the relationship shown in formula (2).

[0067] phase3_avg = ((phase2_code0 + phase2_code1) / 2) (2).

[0068] After the third initial code word (phase3_avg) is obtained, then the code word signal output to the delay circuit is adjusted based on the third initial code word (phase3_avg), and the voltage comparison result fed back by the comparator is waited, and the adjustment value of the third initial code word (phase3_avg) is adjusted according to the voltage comparison result fed back by the comparator, to obtain the third modified code word. As an example, if the voltage comparison result fed back by the comparator is 1, the third modified code word can be (phase3_avg-1), and if the voltage comparison result fed back by the comparator is 0, the third modified code word can be (phase3_avg+1). Then, according to whether the voltage comparison result corresponding to the third modified code word is the same as the voltage comparison result corresponding to the third initial code word, it is judged whether the flipping point is found. As an example, if the voltage comparison result corresponding to the third initial code word is 1, and the voltage comparison result corresponding to the third modified code word is also 1, then the step of updating the third modified code word needs to be continued to be executed, but if the voltage comparison result corresponding to the third initial code word is 1, and the voltage comparison result corresponding to the third modified code word is 0, it means that the flipping point may occur at this time. If the flipping point occurs, further judgment and confirmation need to be performed. Specifically, the voltage comparison result needs to be verified continuously for multiple times to determine the exact position of the flipping point. As an example, the threshold is set to 8, that is, the opposite voltage comparison result needs to occur for 8 times continuously to confirm that the current third modified code word has experienced flipping, and determine it as the third flipping code word.

[0069] After the third flip code word is obtained, a fourth start code word can be determined according to a comparison result of the third flip code word (phase3_code0) and the third start code word (phase3_avg). For example, if the third flip code word (phase3_code0) is greater than the third start code word (phase3_avg), the fourth start code word can be (phase3_code0+n), and if the third flip code word (phase3_code0) is less than or equal to the third start code word (phase3_avg), the fourth start code word can be (phase3_code0-n), where n is an adjustment value that can be adjusted according to actual application requirements.

[0070] After the fourth start code word is obtained, the code word signal output to the delay circuit is adjusted based on the fourth start code word, and the voltage comparison result fed back by the comparator is waited for, and the adjustment value of the fourth start code word is adjusted according to the voltage comparison result fed back by the comparator to obtain a fourth modified code word. For example, if the voltage comparison result corresponding to the fourth start code word is 1, and the voltage comparison result corresponding to the fourth modified code word is also 1, the step of updating the fourth modified code word needs to be continuously performed, but if the voltage comparison result corresponding to the fourth start code word is 1 and the voltage comparison result corresponding to the fourth modified code word is 0, it means that a flip point may occur at this time. If a flip point occurs, further judgment and confirmation need to be performed. Specifically, the voltage comparison result needs to be verified continuously for multiple times to determine the exact position of the flip point. For example, a threshold value of 8 is set, that is, the opposite voltage comparison results need to occur continuously for 8 times to confirm that the current fourth modified code word has experienced a flip and determine it as a fourth flip code word.

[0071] The above embodiments describe the operation method of the quadrature phase calibration circuit. The operation method of the quadrature phase calibration circuit provided by the embodiments of the present application ensures accurate positioning of the flip point in each calibration process by reversing the input signal of the comparator circuit and re-executing multiple calibration operations, offsets the systematic error caused by the bias voltage through reverse calibration, and improves the measurement accuracy of the comparator circuit.

[0072] The embodiments of the present application also provide a chip including the quadrature phase calibration circuit in the above embodiments.

[0073] It should be noted that the division of the above modules is only a functional division adopted for ease of description, and in actual implementation, one module can be implemented by multiple modules, and the functions of multiple modules can be implemented by the same module. These modules can be located in the same device or in different devices.

[0074] The hardware module in the implementations can be implemented mechanically or electronically. For example, a hardware module can comprise dedicated circuitry or logic that is permanently configured to perform certain operations. Such a hardware module can be implemented, for example, using various types of chip(s) (for example, artificial intelligence chip(s)) or programmable logic devices (for example, field-programmable gate array(s) (FPGA(s)) or programmable logic array(s) (PLA(s))).

[0075] Any combination of the technical features in the above embodiments can be made, and in order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered that it is within the scope of the description. The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that, for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

[0076] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features in the formula; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A quadrature phase calibration circuit, characterized in that, include: Delay circuit, first voltage regulation circuit, second voltage regulation circuit, comparator circuit, and state machine circuit; The first input terminal of the delay circuit is electrically connected to the signal input terminal, the first output terminal of the delay circuit is electrically connected to the input terminal of the first voltage regulation circuit, and the second output terminal of the delay circuit is electrically connected to the input terminal of the second voltage regulation circuit. The calibration terminal of the first voltage regulating circuit is electrically connected to the signal input terminal, and the output terminal of the first voltage regulating circuit is electrically connected to the first input terminal of the comparator circuit. The calibration terminal of the second voltage regulating circuit is electrically connected to the signal input terminal, and the output terminal of the second voltage regulating circuit is electrically connected to the second input terminal of the comparator circuit. The voltage signals output by the first voltage regulating circuit and the second voltage regulating circuit constitute a differential pair signal. The output terminal of the comparator circuit is electrically connected to the input terminal of the state machine circuit; The output terminal of the state machine circuit is electrically connected to the second input terminal of the delay circuit.

2. The quadrature phase calibration circuit according to claim 1, characterized in that, The comparator circuit is used to output a voltage comparison result based on the input differential pair signal; The state machine circuit is used to adjust the codeword signal output to the delay circuit based on the voltage comparison result; The delay circuit is used to receive a first clock signal input from the signal input terminal and output a second clock signal through the first output terminal and the second output terminal. The phase difference between the second clock signal and the first clock signal is determined based on the codeword signal.

3. The quadrature phase calibration circuit according to claim 1 or 2, characterized in that, The first voltage regulating circuit includes a NOR phase detector and a first integrating circuit, and the second voltage regulating circuit includes an XOR phase detector and a second integrating circuit. The input terminal of the XNOR phase detector is electrically connected to the input terminal of the first voltage regulating circuit, the output terminal of the XNOR phase detector is electrically connected to the input terminal of the first integrating circuit, the calibration terminal of the XNOR phase detector is electrically connected to the calibration terminal of the first voltage regulating circuit, and the output terminal of the first integrating circuit is electrically connected to the output terminal of the first voltage regulating circuit. The input terminal of the XOR phase detector is electrically connected to the input terminal of the second voltage regulating circuit, the output terminal of the XOR phase detector is electrically connected to the input terminal of the second integrator circuit, the calibration terminal of the XOR phase detector is electrically connected to the calibration terminal of the second voltage regulating circuit, and the output terminal of the second integrator circuit is electrically connected to the output terminal of the second voltage regulating circuit.

4. The quadrature phase calibration circuit according to claim 3, characterized in that, The XOR phase detector is used to convert the second clock signal into a first duty cycle signal, and the first integrating circuit is used to convert the first duty cycle signal into a first voltage signal. The XOR phase detector is used to convert the second clock signal into a second duty cycle signal, and the second integrator is used to convert the second duty cycle signal into a second voltage signal. The first voltage signal and the second voltage signal constitute a differential pair signal.

5. An operation method for an orthogonal phase calibration circuit, characterized in that, The method, applied to the quadrature phase calibration circuit according to any one of claims 1-4, comprises: In the first calibration phase, the initial codeword is determined based on the binary search method; In the second calibration phase, based on the initial codeword, a first flip codeword and a second flip codeword are determined; In the third calibration stage, the first voltage signal and the second voltage signal at the input of the comparator circuit are flipped, and the third flip codeword and the fourth flip codeword are determined based on the first flip codeword and the second flip codeword. Based on the summation and average of the first, second, third, and fourth flipped codewords, a target codeword is determined, and the codeword signal provided by the state machine circuit to the delay circuit is adjusted based on the target codeword.

6. The operation method of the orthogonal phase calibration circuit according to claim 5, characterized in that, In the second calibration phase, based on the initial codeword, determining the first flip codeword and the second flip codeword includes: Based on the initial codeword, a first starting codeword is determined, and a first corrected codeword is obtained based on the first starting codeword. The first starting codeword and the first corrected codeword are increased by equal amounts in sequence. Based on the voltage comparison result corresponding to the first corrected codeword and the voltage comparison result corresponding to the first start codeword, the first flip codeword is determined; Based on the initial codeword, a second starting codeword is determined, and a second corrected codeword is obtained based on the second starting codeword. The second starting codeword and the second corrected codeword are decreased by an equal amount in sequence. The second flip codeword is determined based on the voltage comparison result corresponding to the second corrected codeword and the voltage comparison result corresponding to the second start codeword.

7. The operation method of the quadrature phase calibration circuit according to claim 6, characterized in that, Determining the first flip codeword based on the voltage comparison result corresponding to the first corrected codeword and the voltage comparison result corresponding to the first start codeword includes: Determine whether the voltage comparison result corresponding to the first corrected codeword is the same as the voltage comparison result corresponding to the first start codeword; If the voltage comparison result corresponding to the first correction codeword is different from the voltage comparison result corresponding to the first start codeword, the step of determining whether the voltage comparison result corresponding to the first correction codeword is the same as the voltage comparison result corresponding to the first start codeword is repeated. If the number of judgments is greater than or equal to the judgment threshold, the first corrected codeword is determined as the first flipped codeword.

8. The operation method of the quadrature phase calibration circuit according to claim 6, characterized in that, The step of determining the second flip codeword based on the voltage comparison result corresponding to the second corrected codeword and the voltage comparison result corresponding to the second start codeword includes: Determine whether the voltage comparison result corresponding to the second correction codeword is the same as the voltage comparison result corresponding to the second start codeword; If the voltage comparison result corresponding to the second correction codeword is different from the voltage comparison result corresponding to the second start codeword, the step of determining whether the voltage comparison result corresponding to the second correction codeword is the same as the voltage comparison result corresponding to the second start codeword is repeated. If the number of judgments is greater than or equal to the judgment threshold, the second corrected codeword is determined as the second flipped codeword.

9. The operation method of the quadrature phase calibration circuit according to claim 5, characterized in that, The determination of the third and fourth flip codes based on the first and second flip codes includes: Based on the sum and average of the first and second flipped codewords, a third starting codeword is determined; Based on the voltage comparison result corresponding to the third start codeword, the third correction codeword is determined, and the third start codeword and the third correction codeword are sequentially decreased or sequentially increased by equal amount. The third flip codeword is determined based on the voltage comparison result corresponding to the third start codeword and the voltage comparison result corresponding to the third correction codeword; Based on the comparison result between the third flip codeword and the third starting codeword, the fourth starting codeword is determined; Based on the voltage comparison result corresponding to the fourth start codeword, the fourth correction codeword is determined, and the fourth start codeword and the fourth correction codeword are sequentially decreased or sequentially increased by equal amount. The fourth flip codeword is determined based on the voltage comparison result corresponding to the fourth start codeword and the voltage comparison result corresponding to the fourth correction codeword.

10. A chip, characterized in that, Includes the quadrature phase calibration circuit as described in any one of claims 1 to 4.

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