Semiconductor device and manufacturing method thereof
By forming an isolation layer within the substrate and utilizing conductive structures to connect devices and peripheral circuit structures, the problems of increased cost and wasted area during chip miniaturization are solved, achieving cost reduction and performance optimization.
Patent Information
- Application Number
- CN202511300389.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-11
- Publication Date
- 2025-12-19
AI Technical Summary
While existing technologies can reduce chip size, they also increase production costs and result in significant waste of substrate area, especially the wafer area where peripheral circuits are located.
An isolation layer is formed within the substrate, with the device structure and peripheral circuit structure located on different sides of the isolation layer. Electrical connection is achieved through a conductive structure that penetrates the substrate and the isolation layer, avoiding the need for additional wafer fabrication.
While reducing chip size, production costs are lowered, substrate area is not wasted, substrate utilization is improved, and semiconductor device performance is optimized.
Smart Images
Figure CN121174512A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND
[0002] At present, a memory array and a peripheral circuit are manufactured separately on two wafers, and then the two wafers are bonded to realize the purpose of reducing chip size.
[0003] However, the additional manufacturing of the peripheral circuit on one wafer will cause the production cost to increase, which is not conducive to mass production; and the area occupied by the memory array is much larger than the area occupied by the peripheral circuit, resulting in a large amount of wasted area of the wafer on which the peripheral circuit is located.
[0004] Therefore, how to reduce chip size while reducing production cost and avoiding wafer area waste is a problem to be solved at present. SUMMARY
[0005] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof.
[0006] To achieve the above-mentioned purpose, the present application provides a semiconductor device, comprising:
[0007] a substrate having a first surface and a second surface opposite to each other, and an isolation layer formed in the substrate;
[0008] a device structure formed on the substrate away from the second surface side of the isolation layer;
[0009] a peripheral circuit structure formed on the substrate away from the first surface side of the isolation layer;
[0010] a conductive structure penetrating through the substrate and the isolation layer, the conductive structure being used to electrically connect the peripheral circuit structure to the first surface side of the substrate or to electrically connect the device structure to the second surface side of the substrate.
[0011] Optionally, the substrate is an SOI substrate, the SOI substrate comprising a lower layer substrate, an insulating buried layer and a semiconductor layer stacked together, one side of the semiconductor layer away from the insulating buried layer being the first surface, one side of the lower layer substrate away from the insulating buried layer being the second surface, and the insulating buried layer serving as the isolation layer; or the substrate is a bulk substrate, the bulk substrate having a first doped region and a second doped region connected together, the first doped region and the second doped region having opposite doping types, and the first doped region and the second doped region serving as the isolation layer.
[0012] Optionally, the conductive structure is insulated from the substrate by an insulating layer.
[0013] Optionally, the device structure comprises a memory array, the peripheral circuit structure comprises a CMOS structure and a metal interconnection structure, and the conductive structure is electrically connected to the CMOS structure through the metal interconnection structure; or, the device structure comprises a memory array and a metal interconnection structure, the conductive structure is electrically connected to the memory array through the metal interconnection structure, and the peripheral circuit structure comprises a CMOS structure.
[0014] Optionally, the memory array is of a NOR, NAND or DRAM structure.
[0015] Optionally, the semiconductor device further comprises:
[0016] a first insulating medium layer formed on the first surface side of the substrate, the first insulating medium layer covering the device structure;
[0017] a second insulating medium layer formed on the second surface side of the substrate, the second insulating medium layer covering the peripheral circuit structure, and the first insulating medium layer or the second insulating medium layer exposing the conductive structure.
[0018] Optionally, the semiconductor device further comprises:
[0019] a carrier sheet located on the side of the peripheral circuit structure or the device structure away from the substrate.
[0020] The present application also provides a method for manufacturing a semiconductor device, comprising:
[0021] providing a substrate, the substrate having opposite first and second surfaces, and an isolation layer formed in the substrate;
[0022] forming a device structure on the substrate on the side of the isolation layer away from the second surface, and forming a peripheral circuit structure on the substrate on the side of the isolation layer away from the first surface;
[0023] forming a conductive structure penetrating through the substrate and the isolation layer, the conductive structure being used to electrically connect the peripheral circuit structure to the first surface side of the substrate or to electrically connect the device structure to the second surface side of the substrate.
[0024] Optionally, the substrate is an SOI substrate, the SOI substrate comprises a lower substrate, an insulating buried layer and a semiconductor layer stacked together, one side of the semiconductor layer away from the insulating buried layer is the first surface, one side of the lower substrate away from the insulating buried layer is the second surface, and the insulating buried layer serves as the isolation layer; or, the substrate is a bulk substrate, the bulk substrate is formed with a first doped region and a second doped region connected together, the first doped region and the second doped region are opposite in doping type, and the first doped region and the second doped region serve as the isolation layer.
[0025] Optionally, the device structure comprises a memory array, the peripheral circuit structure comprises a CMOS structure and a metal interconnection structure, and the conductive structure is electrically connected with the CMOS structure through the metal interconnection structure; or, the device structure comprises a memory array and a metal interconnection structure, the conductive structure is electrically connected with the memory array through the metal interconnection structure, and the peripheral circuit structure comprises a CMOS structure.
[0026] Optionally, the memory array is of a NOR, NAND or DRAM structure.
[0027] Optionally, the method for manufacturing the semiconductor device further comprises:
[0028] forming a first insulating medium layer on one side of the first surface of the substrate, the first insulating medium layer covering the device structure; and forming a second insulating medium layer on one side of the second surface of the substrate, the second insulating medium layer covering the peripheral circuit structure, the first insulating medium layer or the second insulating medium layer exposing the conductive structure.
[0029] Optionally, before forming the conductive structure penetrating through the substrate and the isolation layer, the method for manufacturing the semiconductor device further comprises:
[0030] forming a carrier sheet on one side of the peripheral circuit structure or the device structure away from the substrate.
[0031] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:
[0032] 1. The semiconductor device of the present application, comprising: a substrate having a first surface and a second surface opposite to each other, and an isolation layer formed in the substrate; a device structure formed on the substrate away from the second surface side of the isolation layer; a peripheral circuit structure formed on the substrate away from the first surface side of the isolation layer; and a conductive structure penetrating through the substrate and the isolation layer, and used for electrically connecting the peripheral circuit structure to the first surface side of the substrate or for electrically connecting the device structure to the second surface side of the substrate. Thus, the chip size can be reduced, the production cost can be lowered, and the substrate area can be saved.
[0033] 2. The manufacturing method of the semiconductor device of the present application, comprising: providing a substrate having a first surface and a second surface opposite to each other, and an isolation layer formed in the substrate; forming a device structure on the substrate away from the second surface side of the isolation layer, and forming a peripheral circuit structure on the substrate away from the first surface side of the isolation layer; and forming a conductive structure penetrating through the substrate and the isolation layer, and used for electrically connecting the peripheral circuit structure to the first surface side of the substrate or for electrically connecting the device structure to the second surface side of the substrate. Thus, the chip size can be reduced, the production cost can be lowered, and the substrate area can be saved. BRIEF DESCRIPTION OF DRAWINGS
[0034] Figure 1 is a top view of the semiconductor device of the first embodiment of the present application;
[0035] Figure 2 is a top view of the semiconductor device of the second embodiment of the present application;
[0036] Figure 3 is a flow chart of the manufacturing method of the semiconductor device of an embodiment of the present application
[0037] Figures 4a-4e is Figure 3 a device schematic diagram in the manufacturing method of the semiconductor device shown in the figure.
[0038] wherein the accompanying Figures 1-4e The reference signs in the accompanying drawings are explained as follows:
[0039] 10-Substrate; 101-Lower substrate; 102-Buried insulating layer; 103-Semiconductor layer; 111-First doped region; 112-Second doped region; 12-First gate structure; 13-First insulating dielectric layer; 131-First dielectric layer; 132-Second dielectric layer; 141-Second gate structure; 142-Second source region; 143-Second drain region; 15-Second metal interconnect structure; 16-Second insulating dielectric layer; 171-Conductive structure; 172-Insulating layer; 18-Carrier sheet; 191-Bonding adhesive; 192-Carrier substrate. Detailed Implementation
[0040] To make the objectives, advantages, and features of the present invention clearer, the semiconductor device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0041] An embodiment of the present invention provides a semiconductor device, the semiconductor device comprising: a substrate having a first surface and a second surface opposite to each other, and an isolation layer formed therein; a device structure formed on the substrate on the side of the isolation layer away from the second surface; a peripheral circuit structure formed on the substrate on the side of the isolation layer away from the first surface; and a conductive structure penetrating the substrate and the isolation layer, the conductive structure being used to electrically connect the peripheral circuit structure to the first surface side of the substrate or to electrically connect the device structure to the second surface side of the substrate.
[0042] See below. Figures 1-2 The semiconductor device provided in this embodiment is described in detail.
[0043] The substrate 10 has a first surface and a second surface facing away from each other. An isolation layer is formed within the substrate 10, which divides the substrate 10 into two parts in a direction perpendicular to the first surface of the substrate 10. The isolation layer serves an isolation function.
[0044] In one embodiment, such as Figure 1 As shown, the substrate 10 is an SOI (Semiconductor On Insulator) substrate. The SOI substrate includes a stacked lower substrate 101, a buried insulating layer 102, and a semiconductor layer 103. The side of the semiconductor layer 103 away from the buried insulating layer 102 is the first surface, and the side of the lower substrate 101 away from the buried insulating layer 102 is the second surface. The buried insulating layer 102 serves as the isolation layer. Alternatively, in another embodiment, as... Figure 2As shown, the substrate 10 is a bulk substrate, in which a first doped region 111 and a second doped region 112 are formed in connection. The doping types of the first doped region 111 and the second doped region 112 are opposite. The first doped region 111 and the second doped region 112 serve as the isolation layer.
[0045] The first doped region 111 is closer to the first surface than the second doped region 112. The isolation effect is achieved by reverse biasing the PN junction formed between different doped regions or between different doped regions and the substrate.
[0046] Taking the first doped region 111 as P-type and the second doped region 112 as N-type as an example, by connecting the first doped region 111 to a low potential (e.g., floating, grounded, or connected to a negative voltage) and the second doped region 112 to a high potential (e.g., connected to a positive voltage), the PN junction formed between the first doped region 111 and the second doped region 112 is reverse biased, the depletion region expands, and the diffusion of holes and electrons is blocked, so as to achieve the isolation effect.
[0047] In another embodiment, an isolation effect is achieved by forming a PN junction with the first doped region 111 or the second doped region 112, thereby blocking the diffusion of holes and electrons through depletion region diffusion. When the device structure and peripheral circuit structure are in operation, a voltage is applied to the substrate (body region), thereby forming a PN junction with the first doped region 111 or the second doped region 112 with reverse bias.
[0048] The materials of the lower substrate 101, the semiconductor layer 103 and the bulk substrate can be semiconductor materials such as silicon and germanium, and the material of the insulating buried layer 102 can be insulating materials such as silicon oxide. This application does not impose any restrictions on these materials.
[0049] The device structure is formed on the substrate 10 on the side of the isolation layer away from the second surface, and the peripheral circuit structure is formed on the substrate 10 on the side of the isolation layer away from the first surface.
[0050] In one embodiment, the device structure is electrically connected to a first metal interconnect structure (not shown), enabling a voltage to be applied to the device structure through the first metal interconnect structure; the device structure includes a memory array, and the peripheral circuit structure includes a CMOS structure and a second metal interconnect structure 15, the second metal interconnect structure 15 being electrically connected to the CMOS structure.
[0051] Alternatively, in another embodiment, a first metal interconnect structure (not shown) is electrically connected to the peripheral circuit structure, enabling a voltage to be applied to the peripheral circuit structure through the first metal interconnect structure; the device structure includes a memory array and a second metal interconnect structure 15, the second metal interconnect structure 15 being electrically connected to the memory array, and the peripheral circuit structure includes a CMOS structure.
[0052] In one embodiment, the memory array is an array of memory cells. Each memory cell may include a transistor structure, which may include a first gate structure 12, a first source region (not shown), and a first drain region (not shown). The first gate structure 12 may include stacked tunneling oxide layers (not shown), floating gate layers (not shown), inter-gate dielectric layers (not shown), and control gate layers (not shown). The first source region and the first drain region may be located in the substrates 10 on both sides of the first gate structure 12, and both the first source region and the first drain region may be electrically connected. The CMOS structure may include a second gate structure 141, a second source region 142, and a second drain region 143. The second gate structure 141 may include a stacked gate dielectric layer (not shown) and a gate layer (not shown). The second source region 142 and the second drain region 143 may be located in the substrate 10 on both sides of the second gate structure 141. The second source region 142 and the second drain region 143 may be electrically connected to the second metal interconnect structure 15 or the first metal interconnect structure.
[0053] In one embodiment, the storage array can be a NOR, NAND, or DRAM structure, etc.
[0054] In other embodiments, the device structure may further include a first body region (not shown), in which the first source region and the first drain region are formed on both sides of the first gate structure 12. The doping type of the first body region is opposite to that of the first source region and the first drain region. The first gate structure 12 and the first body region may also be electrically connected to a first metal interconnect structure or a second metal interconnect structure 15. The peripheral circuit structure may further include a second body region (not shown), in which the second source region 142 and the second drain region 143 are formed on both sides of the second gate structure 141. The doping type of the second body region is opposite to that of the second source region 142 and the second drain region 143. The second gate structure 141 and the second body region may also be electrically connected to the second metal interconnect structure 15 or a first metal interconnect structure.
[0055] The conductive structure 171 extends through the substrate 10 and the isolation layer. The conductive structure 171 is used to electrically connect the peripheral circuit structure to one side of the first surface of the substrate 10, so that a voltage can be applied to the peripheral circuit structure through the conductive structure 171; or, the conductive structure 171 is used to electrically connect the device structure to one side of the second surface of the substrate 10, so that a voltage can be applied to the device structure through the conductive structure 171.
[0056] In one embodiment, the peripheral circuit structure includes the CMOS structure and the second metal interconnect structure 15. The conductive structure 171 is electrically connected to the CMOS structure through the second metal interconnect structure 15 to electrically connect the CMOS structure to one side of the first surface of the substrate 10. The second source region 142, the second drain region 143, the second gate structure 141, and the second body region are all electrically connected to the conductive structure 171 through the second metal interconnect structure 15, allowing voltages to be applied to the second source region 142, the second drain region 143, the second gate structure 141, and the second body region respectively through the conductive structure 171.
[0057] In another embodiment, the device structure includes the memory array and the second metal interconnect structure 15. The conductive structure 171 is electrically connected to the memory array through the second metal interconnect structure 15 to electrically connect the memory array to one side of the second surface of the substrate 10. The first source region, the first drain region, the first gate structure 12, and the first body region are all electrically connected to the conductive structure 171 through the second metal interconnect structure 15, allowing voltages to be applied to the first source region, the first drain region, the first gate structure 12, and the first body region respectively through the conductive structure 171.
[0058] In one embodiment, the conductive structure 171 is also electrically connected to a corresponding first metal interconnect structure on the device structure or the peripheral circuit structure.
[0059] The conductive structure 171 is insulated from the substrate 10 by an insulating layer 172, that is, the insulating layer 172 is formed between the sidewall of the conductive structure 171 and the substrate 10.
[0060] In one embodiment, the conductive structure 171 may include a through-silicon via (TSV), a third metal interconnect structure, and pads. The third metal interconnect structure is electrically connected to the second metal interconnect structure 15 through the through-silicon via, and the insulating layer 172 is formed on the sidewall of the through-silicon via.
[0061] In one embodiment, when the device structure and the peripheral circuit structure are working, the substrate 10 is connected to the corresponding potential through the conductive structure 171, so as to electrically connect the first doped region 111 and the second doped region 112 to the corresponding potential, thereby causing the PN junction formed between the first doped region 111 and the second doped region 112 to be reverse-biased and achieving the effect of isolation after the PN junction is reverse-biased, so that there is no need to set an additional metal interconnect structure to reverse-bias the PN junction.
[0062] The semiconductor device further includes:
[0063] A first insulating dielectric layer 13 is formed on one side of the first surface of the substrate 10, and the first insulating dielectric layer 13 covers the device structure;
[0064] A second insulating dielectric layer 16 is formed on one side of the second surface of the substrate 10, and the second insulating dielectric layer 16 covers the peripheral circuit structure.
[0065] When the conductive structure 171 is used to electrically connect the peripheral circuit structure to one side of the first surface of the substrate 10, the first insulating dielectric layer 13 exposes the conductive structure 171; when the conductive structure 171 is used to electrically connect the device structure to one side of the second surface of the substrate 10, the second insulating dielectric layer 16 exposes the conductive structure 171.
[0066] Both the first insulating dielectric layer 13 and the second insulating dielectric layer 16 may comprise stacked multilayer dielectric layers. Taking the conductive structure 171 used to electrically connect the peripheral circuit structure to one side of the first surface of the substrate 10 as an example, in one embodiment, such as... Figure 1 and Figure 2 As shown, the first insulating dielectric layer 13 includes a stacked first dielectric layer 131 and a second dielectric layer 132. A via conductive structure penetrates the first dielectric layer 131, the substrate 10, the isolation layer, and a portion of the thickness of the second insulating dielectric layer 16 to electrically connect with the second metal interconnect structure 15. An insulating layer 172 is formed on the sidewall of the via conductive structure to insulate the via conductive structure from the substrate 10. The third metal interconnect structure is formed in the second dielectric layer 132 on the via conductive structure, and the second dielectric layer 132 exposes the third metal interconnect structure.
[0067] In one embodiment, the semiconductor device further includes a carrier sheet 18. When the conductive structure 171 is used to electrically connect the peripheral circuit structure to one side of the first surface of the substrate 10, the carrier sheet 18 is located on the side of the peripheral circuit structure away from the substrate 10; when the conductive structure 171 is used to electrically connect the device structure to one side of the second surface of the substrate 10, the carrier sheet 18 is located on the side of the device structure away from the substrate 10.
[0068] When the carrier sheet 18 is located on the side of the peripheral circuit structure away from the substrate 10, the carrier sheet 18 is bonded to the side of the second insulating dielectric layer 16 away from the substrate 10; when the carrier sheet 18 is located on the side of the device structure away from the substrate 10, the carrier sheet 18 is bonded to the side of the first insulating dielectric layer 13 away from the substrate 10.
[0069] The carrier sheet 18 can be any carrier sheet with a load-bearing function, such as silicon wafer, glass, or ceramic. The quality requirements for the carrier sheet 18 are not high, and there is no need to fabricate a structure on the carrier sheet 18. The carrier sheet 18 only needs to serve a supporting function, so the added cost is limited.
[0070] In one embodiment, the bonding may be a melt bond.
[0071] As can be seen from the above, since the isolation layer is formed within the substrate 10, the device structure is formed on the side of the substrate 10 away from the second surface of the isolation layer, and the peripheral circuit structure is formed on the side of the substrate 10 away from the first surface of the isolation layer. The conductive structure 171 is used to electrically connect the peripheral circuit structure to the first surface of the substrate 10 or to electrically connect the device structure to the second surface of the substrate 10. This allows the device structure and the peripheral circuit structure to be fabricated on the same substrate 10, meaning the peripheral circuit structure shares the substrate 10 where the device structure is located, thereby avoiding the device structure being... The increased production cost and wasted substrate area caused by fabricating the device structure and the peripheral circuit structure on two separate substrates are eliminated. This allows for a reduction in chip size while simultaneously lowering production costs and avoiding wasted substrate area. Furthermore, since the substrate area occupied by the device structure is much larger than that occupied by the peripheral circuit structure, the substrate 10 on the side of the isolation layer away from the first surface can be used not only to house the peripheral circuit structure but also to house other functional structures (such as error correction structures). This further improves the utilization rate of the substrate 10 where the device structure is located and optimizes the performance of the semiconductor device.
[0072] One embodiment of the present invention provides a method for manufacturing a semiconductor device, see reference. Figure 3 , Figure 3 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, the method comprising:
[0073] A substrate is provided, the substrate having a first surface and a second surface opposite to each other, and an isolation layer is formed in the substrate;
[0074] A device structure is formed on the substrate on the side of the isolation layer away from the second surface, and a peripheral circuit structure is formed on the substrate on the side of the isolation layer away from the first surface;
[0075] A conductive structure is formed that extends through the substrate and the isolation layer. The conductive structure is used to electrically connect the peripheral circuit structure to the first surface side of the substrate or to electrically connect the device structure to the second surface side of the substrate.
[0076] See below. Figures 1-2 , Figures 4a-4e The method for manufacturing the semiconductor device provided in this embodiment will be described in more detail; wherein, Figures 4a-4e The image shown is for making Figure 1 The diagram shows the various steps involved in the semiconductor device.
[0077] A substrate 10 is provided, the substrate 10 having a first surface and a second surface facing away from each other, and an isolation layer is formed within the substrate 10. The isolation layer divides the substrate 10 into two parts in a direction perpendicular to the first surface of the substrate 10.
[0078] In one embodiment, such as Figure 1 and Figure 4a As shown, the substrate 10 is an SOI (Semiconductor On Insulator) substrate. The SOI substrate includes a stacked lower substrate 101, an insulating buried layer 102, and a semiconductor layer 103. The side of the semiconductor layer 103 away from the insulating buried layer 102 is the first surface, and the side of the lower substrate 101 away from the insulating buried layer 102 is the second surface. The insulating buried layer 102 serves as the isolation layer.
[0079] Alternatively, in another embodiment, such as Figure 2 As shown, the substrate 10 is a bulk substrate, in which a first doped region 111 and a second doped region 112 are formed in connection. The doping types of the first doped region 111 and the second doped region 112 are opposite. The first doped region 111 and the second doped region 112 serve as the isolation layer.
[0080] The first doped region 111 and the second doped region 112 can be formed by using an ion implantation process.
[0081] The first doped region 111 is closer to the first surface than the second doped region 112. The isolation effect is achieved by reverse biasing the PN junction formed between different doped regions or between different doped regions and the substrate.
[0082] Taking the first doped region 111 as P-type and the second doped region 112 as N-type as an example, by connecting the first doped region 111 to a low potential (e.g., floating, grounded, or connected to a negative voltage) and the second doped region 112 to a high potential (e.g., connected to a positive voltage), the PN junction formed between the first doped region 111 and the second doped region 112 is reverse biased, the depletion region expands, and the diffusion of holes and electrons is blocked, so as to achieve the isolation effect.
[0083] In another embodiment, an isolation effect is achieved by forming a PN junction with the first doped region or the second doped region, thereby blocking the diffusion of holes and electrons through depletion region diffusion. When the device structure and peripheral circuit structure are operating, a voltage is applied to the substrate (body region), thereby forming a PN junction with the first doped region or the second doped region with reverse bias.
[0084] The materials of the lower substrate 101, the semiconductor layer 103 and the bulk substrate can be semiconductor materials such as silicon and germanium, and the material of the insulating buried layer 102 can be insulating materials such as silicon oxide. This application does not impose any restrictions on these materials.
[0085] like Figures 4a-4c As shown, a device structure is formed on the substrate 10 on the side of the isolation layer away from the second surface, and a peripheral circuit structure is formed on the substrate 10 on the side of the isolation layer away from the first surface.
[0086] There is no restriction on the order in which the device structure is formed and the peripheral circuit structure is formed.
[0087] In one embodiment, the device structure includes a memory array, and the peripheral circuit structure includes a CMOS structure and a second metal interconnect structure 15, the second metal interconnect structure 15 being electrically connected to the CMOS structure.
[0088] Alternatively, in another embodiment, the device structure includes a memory array and a second metal interconnect structure 15, the second metal interconnect structure 15 being electrically connected to the memory array, and the peripheral circuit structure includes a CMOS structure.
[0089] In one embodiment, the memory array is a memory cell array. The memory cell may include a transistor structure. The transistor structure may include a first gate structure 12, a first source region (not shown), and a first drain region (not shown). The first gate structure 12 may include a stacked tunneling oxide layer (not shown), a floating gate layer (not shown), an inter-gate dielectric layer (not shown), and a control gate layer (not shown). The first source region and the first drain region may be located in the substrate 10 on both sides of the first gate structure 12.
[0090] In other embodiments, the device structure may further include a first body region (not shown), wherein the first source region and the first drain region are formed in the first body region on both sides of the first gate structure 12, and the doping type of the first body region is opposite to that of the first source region and the first drain region.
[0091] In one embodiment, the CMOS structure may include a second gate structure 141, a second source region 142, and a second drain region 143. The second gate structure 141 may include a stacked gate dielectric layer (not shown) and a gate layer (not shown). The second source region 142 and the second drain region 143 may be located in the substrate 10 on both sides of the second gate structure 141.
[0092] In other embodiments, the peripheral circuit structure may further include a second body region (not shown), wherein the second source region 142 and the second drain region 143 are formed in the second body region on both sides of the second gate structure 141, and the doping type of the second body region is opposite to that of the second source region 142 and the second drain region 143.
[0093] In one embodiment, the second metal interconnect structure 15 may be electrically connected to the first source region, the first drain region, the first gate structure 12, and the first body region; or, in another embodiment, the second metal interconnect structure 15 may be electrically connected to the second source region 142, the second drain region 143, the second gate structure 141, and the second body region.
[0094] In one embodiment, the storage array can be a NOR, NAND, or DRAM structure, etc.
[0095] In one embodiment, the peripheral circuit structure includes a CMOS structure and a second metal interconnect structure 15. The method for manufacturing the semiconductor device further includes forming a first metal interconnect structure (not shown) electrically connected to the device structure, enabling a voltage to be applied to the device structure through the first metal interconnect structure. In one embodiment, the first metal interconnect structure may be electrically connected to both the first source region and the first drain region. In other embodiments, the first metal interconnect structure may also be electrically connected to the first gate structure 12 and the first body region.
[0096] Alternatively, in another embodiment, the device structure includes a memory array and a second metal interconnect structure 15. The method of manufacturing the semiconductor device further includes forming a first metal interconnect structure (not shown) electrically connected to the peripheral circuit structure, enabling a voltage to be applied to the peripheral circuit structure through the first metal interconnect structure. In one embodiment, the first metal interconnect structure may be electrically connected to both the second source region 142 and the second drain region 143. In other embodiments, the first metal interconnect structure may also be electrically connected to the second gate structure 141 and the second body region.
[0097] like Figure 4e As shown, a conductive structure 171 is formed that penetrates the substrate 10 and the isolation layer. The conductive structure 171 is used to electrically connect the peripheral circuit structure to the first surface side of the substrate 10; or, the conductive structure 171 is used to electrically connect the device structure to the second surface side of the substrate 10.
[0098] In one embodiment, the peripheral circuit structure includes the CMOS structure and the second metal interconnect structure 15. The conductive structure 171 is electrically connected to the CMOS structure through the second metal interconnect structure 15 to electrically connect the CMOS structure to one side of the first surface of the substrate 10. The second source region 142, the second drain region 143, the second gate structure 141, and the second body region are all electrically connected to the conductive structure 171 through the second metal interconnect structure 15, allowing voltages to be applied to the second source region 142, the second drain region 143, the second gate structure 141, and the second body region respectively through the conductive structure 171.
[0099] In another embodiment, the device structure includes the memory array and the second metal interconnect structure 15. The conductive structure 171 is electrically connected to the memory array through the second metal interconnect structure 15 to electrically connect the memory array to one side of the second surface of the substrate 10. The first source region, the first drain region, the first gate structure 12, and the first body region are all electrically connected to the conductive structure 171 through the second metal interconnect structure 15, allowing voltages to be applied to the first source region, the first drain region, the first gate structure 12, and the first body region respectively through the conductive structure 171.
[0100] In one embodiment, the conductive structure 171 is also electrically connected to a corresponding first metal interconnect structure on the device structure or the peripheral circuit structure.
[0101] The conductive structure 171 is insulated from the substrate 10 by an insulating layer 172, that is, the insulating layer 172 is formed between the sidewall of the conductive structure 171 and the substrate 10.
[0102] In one embodiment, the conductive structure 171 may include a through-silicon via (TSV), a third metal interconnect structure, and pads. The third metal interconnect structure is electrically connected to the second metal interconnect structure 15 through the through-silicon via, and the insulating layer 172 is formed on the sidewall of the through-silicon via.
[0103] In one embodiment, when the device structure and the peripheral circuit structure are working, the substrate 10 is connected to the corresponding potential through the conductive structure 171, so as to electrically connect the first doped region 111 and the second doped region 112 to the corresponding potential, thereby causing the PN junction formed between the first doped region 111 and the second doped region 112 to be reverse-biased and achieving the effect of isolation after the PN junction is reverse-biased, so that there is no need to set an additional metal interconnect structure to reverse-bias the PN junction.
[0104] The method for manufacturing the semiconductor device further includes: forming a first insulating dielectric layer 13 on one side of the first surface of the substrate 10, the first insulating dielectric layer 13 covering the device structure; and forming a second insulating dielectric layer 16 on one side of the second surface of the substrate 10, the second insulating dielectric layer 16 covering the peripheral circuit structure.
[0105] When the conductive structure 171 is used to electrically connect the peripheral circuit structure to one side of the first surface of the substrate 10, the first insulating dielectric layer 13 exposes the conductive structure 171; when the conductive structure 171 is used to electrically connect the device structure to one side of the second surface of the substrate 10, the second insulating dielectric layer 16 exposes the conductive structure 171.
[0106] Both the first insulating dielectric layer 13 and the second insulating dielectric layer 16 may include stacked multilayer dielectric layers.
[0107] In one embodiment, before forming the conductive structure 171 through the substrate 10 and the isolation layer, the method of manufacturing the semiconductor device further includes forming a carrier sheet 18 on the side of the peripheral circuit structure or the device structure away from the substrate 10.
[0108] Wherein, when the conductive structure 171 is used to electrically connect the peripheral circuit structure to one side of the first surface of the substrate 10, the carrier sheet 18 is located on the side of the peripheral circuit structure away from the substrate 10, and the carrier sheet 18 is bonded to the side of the second insulating dielectric layer 16 away from the substrate 10; when the conductive structure 171 is used to electrically connect the device structure to one side of the second surface of the substrate 10, the carrier sheet 18 is located on the side of the device structure away from the substrate 10, and the carrier sheet 18 is bonded to the side of the first insulating dielectric layer 13 away from the substrate 10.
[0109] The carrier sheet 18 can be any carrier sheet with a load-bearing function, such as silicon wafer, glass, or ceramic. The quality requirements for the carrier sheet 18 are not high, and there is no need to fabricate a structure on the carrier sheet 18. The carrier sheet 18 only needs to serve a supporting function, so the added cost is limited.
[0110] In one embodiment, the bonding may be a melt bond.
[0111] Taking the formation of the device structure followed by the formation of the peripheral circuit structure as an example, in one embodiment, the steps of forming the device structure, the peripheral circuit structure, the first insulating dielectric layer 13, the second insulating dielectric layer 16, the conductive structure 171, and the carrier sheet 18 include: Figure 4a As shown, a device structure is formed on the substrate 10 on the side of the isolation layer away from the second surface, and a first dielectric layer 131 is formed on the first surface side of the substrate 10, the first dielectric layer 131 covering the device structure; as Figure 4b As shown, the substrate 192 is bonded to the side of the first dielectric layer 131 away from the substrate 10; a thinning process is performed on the second surface of the substrate 10; as... Figure 4c As shown, the peripheral circuit structure is formed on the substrate 10 on the side of the isolation layer away from the first surface, and the second insulating dielectric layer 16 is formed on the second surface side of the substrate 10, the second insulating dielectric layer 16 covering the peripheral circuit structure; as Figure 4d As shown, the carrier sheet 18 is bonded to the side of the second insulating dielectric layer 16 away from the substrate 10; the carrier substrate 192 is debonded to the side of the first dielectric layer 131 away from the substrate 10; as shown... Figure 4eAs shown, a via conductive structure is formed that penetrates the first dielectric layer 131, the substrate 10, the isolation layer, and a portion of the thickness of the second insulating dielectric layer 16. The via conductive structure is electrically connected to the second metal interconnect structure 15. The insulating layer 172 is formed on the sidewall of the via conductive structure to insulate the via conductive structure from the substrate 10. A second dielectric layer 132 is formed on the side of the first dielectric layer 131 away from the substrate 10, and a third metal interconnect structure is formed in the second dielectric layer 132 on the via conductive structure. The second dielectric layer 132 exposes the third metal interconnect structure. The first dielectric layer 131 and the second dielectric layer 132 constitute the first insulating dielectric layer 13.
[0112] In one embodiment, the supporting substrate 192 and the side of the first dielectric layer 131 away from the substrate 10 can be bonded by bonding adhesive 191.
[0113] The supporting substrate 192 can be a support wafer such as silicon wafer, glass, or ceramic.
[0114] When the supporting substrate 192 is bonded to the side of the first dielectric layer 131 away from the substrate 10 by the bonding adhesive 191, the debonding method may include: physical separation, high temperature baking, ultraviolet irradiation or laser irradiation to make the bonding adhesive 191 lose its stickiness, or dissolving the bonding adhesive 191 with a solvent.
[0115] As can be seen from the above, since the isolation layer is formed within the substrate 10, the device structure is formed on the side of the substrate 10 away from the second surface of the isolation layer, and the peripheral circuit structure is formed on the side of the substrate 10 away from the first surface of the isolation layer. The conductive structure 171 is used to electrically connect the peripheral circuit structure to the first surface of the substrate 10 or to electrically connect the device structure to the second surface of the substrate 10. This allows the device structure and the peripheral circuit structure to be fabricated on the same substrate 10, meaning the peripheral circuit structure shares the substrate 10 where the device structure is located, thereby avoiding the device structure being... The increased production cost and wasted substrate area caused by fabricating the device structure and the peripheral circuit structure on two separate substrates are eliminated. This allows for a reduction in chip size while simultaneously lowering production costs and avoiding wasted substrate area. Furthermore, since the substrate area occupied by the device structure is much larger than that occupied by the peripheral circuit structure, the substrate 10 on the side of the isolation layer away from the first surface can be used not only to house the peripheral circuit structure but also to house other functional structures (such as error correction structures). This further improves the utilization rate of the substrate 10 where the device structure is located and optimizes the performance of the semiconductor device.
[0116] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: A substrate having a first surface and a second surface facing away from each other, and an isolation layer formed therein; The device structure is formed on the substrate on the side of the isolation layer away from the second surface; The peripheral circuit structure is formed on the substrate on the side of the isolation layer away from the first surface; A conductive structure extends through the substrate and the isolation layer, the conductive structure being used to electrically connect the peripheral circuit structure to one side of the first surface of the substrate or to electrically connect the device structure to one side of the second surface of the substrate.
2. The semiconductor device as claimed in claim 1, characterized in that, The substrate is an SOI substrate, which includes a stacked lower substrate, an insulating buried layer, and a semiconductor layer. The side of the semiconductor layer away from the insulating buried layer is the first surface, and the side of the lower substrate away from the insulating buried layer is the second surface. The insulating buried layer serves as the isolation layer. Alternatively, the substrate is a bulk substrate, in which a first doped region and a second doped region are formed, with the first doped region and the second doped region having opposite doping types. The first doped region and the second doped region serve as the isolation layer.
3. The semiconductor device as described in claim 1, characterized in that, The conductive structure is insulated from the substrate by an insulating layer.
4. The semiconductor device as claimed in claim 1, characterized in that, The device structure includes a memory array, and the peripheral circuit structure includes a CMOS structure and a metal interconnect structure, wherein the conductive structure is electrically connected to the CMOS structure through the metal interconnect structure; or, the device structure includes a memory array and a metal interconnect structure, wherein the conductive structure is electrically connected to the memory array through the metal interconnect structure, and the peripheral circuit structure includes a CMOS structure.
5. The semiconductor device as claimed in claim 4, characterized in that, The storage array is of NOR, NAND, or DRAM structure.
6. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: A first insulating dielectric layer is formed on one side of the first surface of the substrate, and the first insulating dielectric layer covers the device structure; A second insulating dielectric layer is formed on one side of the second surface of the substrate, the second insulating dielectric layer covering the peripheral circuit structure, and the first insulating dielectric layer or the second insulating dielectric layer exposing the conductive structure.
7. The semiconductor device according to any one of claims 1-6, characterized in that, The semiconductor device further includes: The carrier sheet is located on the side of the peripheral circuit structure or the device structure away from the substrate.
8. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate having a first surface and a second surface opposite to each other, and an isolation layer is formed in the substrate; A device structure is formed on the substrate on the side of the isolation layer away from the second surface, and a peripheral circuit structure is formed on the substrate on the side of the isolation layer away from the first surface; A conductive structure is formed that extends through the substrate and the isolation layer. The conductive structure is used to electrically connect the peripheral circuit structure to the first surface side of the substrate or to electrically connect the device structure to the second surface side of the substrate.
9. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The substrate is an SOI substrate, which includes a stacked lower substrate, an insulating buried layer, and a semiconductor layer. The side of the semiconductor layer away from the insulating buried layer is the first surface, and the side of the lower substrate away from the insulating buried layer is the second surface. The insulating buried layer serves as the isolation layer. Alternatively, the substrate is a bulk substrate, in which a first doped region and a second doped region are formed, with the first doped region and the second doped region having opposite doping types. The first doped region and the second doped region serve as the isolation layer.
10. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The device structure includes a memory array, and the peripheral circuit structure includes a CMOS structure and a metal interconnect structure, wherein the conductive structure is electrically connected to the CMOS structure through the metal interconnect structure; or, the device structure includes a memory array and a metal interconnect structure, wherein the conductive structure is electrically connected to the memory array through the metal interconnect structure, and the peripheral circuit structure includes a CMOS structure.
11. The method for manufacturing a semiconductor device as described in claim 10, characterized in that, The storage array is of NOR, NAND, or DRAM structure.
12. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The method for manufacturing the semiconductor device further includes: A first insulating dielectric layer is formed on one side of the first surface of the substrate, the first insulating dielectric layer covering the device structure; and a second insulating dielectric layer is formed on one side of the second surface of the substrate, the second insulating dielectric layer covering the peripheral circuit structure, wherein the first insulating dielectric layer or the second insulating dielectric layer exposes the conductive structure.
13. A method for manufacturing a semiconductor device according to any one of claims 8-12, characterized in that, Before forming a conductive structure penetrating the substrate and the isolation layer, the method for manufacturing the semiconductor device further includes: A carrier sheet is formed on the side of the peripheral circuit structure or the device structure away from the substrate.