Method for manufacturing ldmos, ldmos device and mask for lithography

Abstract

The application provides a preparation method of an LDMOS, an LDMOS device and a mask for lithography. The method comprises the following steps: providing a semiconductor substrate, forming at least one LDMOS device structure on the semiconductor substrate, wherein the LDMOS device structure comprises a gate, a source region, a drain region and a drift region, and a groove isolation region is arranged in the drift region; forming a first dielectric layer on the semiconductor substrate with the LDMOS device structure; forming at least one field plate connecting hole penetrating through the first dielectric layer and extending into the groove isolation region; filling the field plate connecting hole with a conductive substance to form a first field plate embedded in the groove isolation region; and the longitudinal depth of the field plate connecting hole in the groove isolation region satisfies that the depth of the field plate connecting hole in the groove isolation region near the gate is greater than the depth of the field plate connecting hole in the groove isolation region far from the gate. Since the first field plate is embedded in the groove isolation region, the occupation of the semiconductor surface area is reduced, which is beneficial to the miniaturization and integration of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, in particular to a preparation method of LDMOS, an LDMOS device and a mask for lithography. BACKGROUND

[0002] Under the background of the rapid development of the current semiconductor industry, as a high-performance power device, Lateral Diffused Metal Oxide Semiconductor (LDMOS for short) has been widely used in many fields such as automotive electronics, industrial control, communication equipment, etc. due to its excellent electrical characteristics and high voltage resistance. When the electrode of the LDMOS device is connected with other external electronic elements, the aggregation of electric charge may cause breakdown phenomenon, thereby causing leakage.

[0003] In order to prevent high voltage breakdown, the related art usually increases a field plate above the gate and extends the width of the field plate above the gate to cover more of the trench isolation region on one side of the gate, so as to provide a reverse electric field for the electrode (such as the source or the drain) of the semiconductor through the field plate extending to the trench isolation region, thereby offsetting the high voltage charge of the electrode.

[0004] However, increasing the field plate above the gate and covering it on the trench isolation region will occupy more semiconductor surface area, thereby increasing the overall size of the semiconductor, which is not conducive to the miniaturization and integration development of the chip. SUMMARY

[0005] The embodiments of the present application provide a preparation method of LDMOS, an LDMOS device and a mask for lithography, which can not only offset the high voltage charge of the drain and effectively prevent the high voltage breakdown of the drain, but also reduce the occupation of the semiconductor surface area, so that the overall size of the semiconductor is smaller. The specific scheme is as follows:

[0006] In a first aspect, the present application provides a preparation method of LDMOS, which comprises:

[0007] providing a semiconductor substrate, forming at least one LDMOS device structure on the semiconductor substrate, the LDMOS device structure at least comprising a gate, a source region, a drain region and a drift region, and a trench isolation region is arranged in the drift region;

[0008] forming a first dielectric layer on the semiconductor substrate in which the LDMOS device structure is formed;

[0009] forming at least one field plate connecting hole penetrating through the first dielectric layer and extending into the trench isolation region;

[0010] filling a conductive substance in the field plate connecting hole to form a first field plate embedded in the trench isolation region;

[0011] The longitudinal depth of the field plate connection hole formed in the trench isolation region satisfies:

[0012] The depth of the trench isolation region near the gate side is greater than the depth of the trench isolation region far from the gate side.

[0013] Optionally, forming the field plate connection hole penetrating through the first dielectric layer and extending into the trench isolation region specifically includes:

[0014] The process of forming the connection hole above the LDMOS device is simultaneously performed with the process of forming the field plate connection hole using the same photolithography mask.

[0015] In a second aspect, the present application further provides a preparation method of an LDMOS, which includes:

[0016] providing a semiconductor substrate, forming at least one LDMOS device structure on the semiconductor substrate, the LDMOS device structure including at least a gate, a source region, a drain region and a drift region, and a trench isolation region being arranged in the drift region;

[0017] forming a first dielectric layer on the semiconductor substrate on which the LDMOS device structure is formed;

[0018] forming at least one field plate connection hole penetrating through the first dielectric layer and extending into the trench isolation region;

[0019] filling the field plate connection hole with a conductive substance to form a first field plate embedded in the trench isolation region;

[0020] forming a connection structure electrically connected to the first field plate, and applying an electric potential to the first field plate through the connection structure, the connection structure being electrically connected to the source level.

[0021] In a third aspect, the present application further provides a preparation method of an LDMOS, which includes:

[0022] providing a semiconductor substrate, forming at least one LDMOS device structure on the semiconductor substrate, the LDMOS device structure including at least a gate, a source region, a drain region and a drift region, and a trench isolation region being arranged in the drift region;

[0023] forming a first dielectric layer on the semiconductor substrate on which the LDMOS device structure is formed;

[0024] forming at least one field plate connection hole penetrating through the first dielectric layer and extending into the trench isolation region;

[0025] injecting N-type ions into the drift region at the bottom of the field plate connection hole;

[0026] filling conductive substance in the field plate connecting hole to form a first field plate embedded in the trench isolation region.

[0027] In a fourth aspect, the present application provides an LDMOS device, comprising:

[0028] a semiconductor substrate, at least one LDMOS device structure is formed on the semiconductor substrate, the LDMOS device structure at least comprises a gate, a source region, a drain region and a drift region, and a trench isolation region is arranged in the drift region;

[0029] a first dielectric layer is formed on the semiconductor substrate where the LDMOS device structure is formed, the first dielectric layer is penetrated by at least one field plate connecting hole which extends into the trench isolation region; conductive substance is filled in the field plate connecting hole to form a first field plate embedded in the trench isolation region;

[0030] wherein the longitudinal depth of the field plate connecting hole in the trench isolation region satisfies:

[0031] the depth of the trench isolation region near the gate side is greater than the depth of the trench isolation region far from the gate side.

[0032] In a fifth aspect, the present application provides a mask for lithography, comprising a field plate connecting hole pattern and an LDMOS device connecting hole pattern, the pattern size of the field plate connecting hole pattern near the gate part of the semiconductor substrate to be etched is greater than the pattern size far from the gate part; wherein the area where the pattern is located is a light transmission area or a light shielding area.

[0033] Compared with the prior art, the present application has the following advantages:

[0034] The preparation method of the LDMOS provided by the embodiment of the present application provides a semiconductor substrate, forms at least one LDMOS device structure on the semiconductor substrate, and the LDMOS device structure at least includes a gate, a source region, a drain region and a drift region, and a trench isolation region is arranged in the drift region. By arranging the drift region and the trench isolation region in the drift region, the voltage resistance of the device can be increased. Then, a first dielectric layer is formed on the semiconductor substrate on which the LDMOS device structure is formed, the first dielectric layer can protect the LDMOS device structure, and then at least one field plate connecting hole penetrating through the first dielectric layer and extending into the trench isolation region is formed, and a conductive substance is filled in the field plate connecting hole to form a first field plate embedded in the trench isolation region. In this way, the first field plate embedded in the trench isolation region can be used to provide a reverse electric field for the electrode of the LDMOS device structure, effectively offset the high-voltage charge of the electrode in the LDMOS device structure, and prevent the electrode from being subjected to high-voltage breakdown. Moreover, since the first field plate is embedded in the trench isolation region, compared with the way of increasing the field plate above the gate and extending to cover the trench isolation region, the occupation of the semiconductor surface area is greatly reduced, which is beneficial to the miniaturization and integration of the chip.

[0035] Meanwhile, since the electric field intensity is greater closer to the gate, the longitudinal depth of the field plate connecting hole formed in the present application in the trench isolation region satisfies that the depth of the first field plate on the side close to the gate in the trench isolation region is greater than the depth of the first field plate on the side far from the gate in the trench isolation region. The design of the depth difference makes the depth of the first field plate on the side close to the gate greater than the depth of the first field plate on the side far from the gate, so that the first field plate on the side close to the gate can generate more reverse charges to offset the electric field of greater intensity close to the gate, so as to more effectively and reasonably offset the high-voltage charge of the electrode, and further improve the effect of preventing high-voltage breakdown. In addition, the depth-differentiated field plate setting mode can reasonably utilize the space of the trench isolation region according to the actual situation of the electric field distribution while ensuring the protection effect, avoids unnecessary material waste and space occupation, and further optimizes the structure of the LDMOS device. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a flow chart of an example of the preparation method of the LDMOS provided by the embodiment of the present application.

[0037] Figure 2 is a structural schematic diagram of the semiconductor substrate provided in the preparation method of the LDMOS provided by the embodiment of the present application.

[0038] Figure 3 is a schematic diagram of forming a first dielectric layer on a semiconductor substrate in the preparation method of the LDMOS provided by the embodiment of the present application.

[0039] Figure 4FIG. 1 is a schematic diagram of one example of a method for manufacturing an LDMOS according to an embodiment of the present application.

[0040] Figure 5 FIG. 2 is a schematic diagram of another example of a method for manufacturing an LDMOS according to an embodiment of the present application.

[0041] Figure 6 FIG. 3 is a schematic diagram of one example of implanting N-type ions in the drift region at the bottom of the field plate connection hole according to an embodiment of the present application.

[0042] Figure 7 FIG. 4 is a schematic diagram of another example of implanting N-type ions in the drift region at the bottom of the field plate connection hole according to an embodiment of the present application.

[0043] Figure 8 FIG. 5 is a schematic diagram of one example of an LDMOS device formed according to an embodiment of the present application.

[0044] Figure 9 FIG. 6 is a schematic diagram of another example of an LDMOS device formed according to an embodiment of the present application.

[0045] Figure 10 FIG. 7 is a flow chart of another example of a method for manufacturing an LDMOS according to an embodiment of the present application.

[0046] Figure 11 FIG. 8 is a flow chart of yet another example of a method for manufacturing an LDMOS according to an embodiment of the present application.

[0047] Figure 12 FIG. 9 is a schematic diagram of one example of a mask for photolithography according to an embodiment of the present application.

[0048] Figure 13 FIG. 10 is a schematic diagram of another example of a mask for photolithography according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without the specific details set forth in this description. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure aspects of the present application.

[0050] It should be noted that the terms "first", "second", "third", etc. in the claims, specification and drawings of the present application are used to distinguish similar objects, and are not intended to describe a specific order or sequence. The data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include", "have" and their variants are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0051] It should be understood that in the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" is only a description of the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the existence of A alone, the existence of A and B together, and the existence of B alone. The character " / " generally represents an "or" relationship between the associated objects. "Including A, B and / or C" means including any one or any two or three of A, B and C.

[0052] It should be understood that in the embodiments of the present application, "B corresponding to A", "B corresponding to A", "A corresponding to B" or "B corresponding to A" means that B is associated with A, and B can be determined according to A. Determining B according to A does not mean that B is determined only according to A, but also can be determined according to A and / or other information.

[0053] The electrodes of the LDMOS device may, when connected with other external electronic elements, cause breakdown due to the accumulation of electric charges, thereby causing leakage. In order to prevent high-voltage breakdown, the related art usually increases a field plate above the gate and extends the width of the field plate above the gate to cover more of the trench isolation region on the side of the gate, thereby providing a reverse electric field for the electrodes (such as the source or the drain) of the semiconductor through the field plate extending to the trench isolation region to offset the high-voltage charges of the electrodes. However, increasing the field plate above the gate and covering it on the trench isolation region occupies more semiconductor surface area, thereby increasing the overall size of the semiconductor, which is not conducive to the miniaturization and integration development of chips. Therefore, there is an urgent need for a way that can offset the high-voltage charges of the drain, effectively prevent high-voltage breakdown of the drain, and reduce the occupation of the semiconductor surface area, so that the overall size of the semiconductor is smaller.

[0054] Based on the above reasons, the first embodiment of the present application provides a preparation method of an LDMOS, which can offset the high-voltage charges of the drain, effectively prevent high-voltage breakdown of the drain, reduce the occupation of the semiconductor surface area, and make the overall size of the semiconductor smaller.

[0055] The technical solutions of the present application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in detail in some embodiments.

[0056] The following will be described in detail with reference to the drawings Figures 1-9 The preparation method of the LDMOS provided in the embodiments of the present application is introduced.

[0057] As Figure 1 shown is a flow chart of the preparation method of the semiconductor device provided in the embodiments of the present application, including the following steps S110-S140.

[0058] Step S110: providing a semiconductor substrate, forming at least one LDMOS device structure on the semiconductor substrate, the LDMOS device structure at least including a gate 7, a source region 9, a drain region 4 and a drift region 5, and a trench isolation region 6 is arranged in the drift region 5.

[0059] The semiconductor substrate is a substrate for forming a semiconductor device. The semiconductor substrate material includes but is not limited to pure single crystal silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc. The material of the semiconductor substrate can be selected according to actual needs in the preparation process.

[0060] As Figure 2 shown is a schematic diagram of an example of the semiconductor substrate provided in the preparation method of the LDMOS provided in the embodiments of the present application, which can include an epitaxial layer 2 and a substrate layer 1, wherein the epitaxial layer 2 is formed with the above-mentioned at least one LDMOS device structure.

[0061] The substrate layer 1 can provide support and suitable lattice structure for the growth of the epitaxial layer 2. The substrate layer 1 can be a P-type substrate, i.e. a P-type doped single crystal silicon substrate, which has good electrical conductivity and mechanical properties and can meet the basic performance requirements of a semiconductor device. The substrate layer 1 can also be an N-type doped single crystal silicon substrate or a substrate of other materials, which can be selected flexibly by those skilled in the art according to device design and performance requirements.

[0062] The epitaxial layer 2 is a layer of semiconductor material formed on the substrate layer 1 by an epitaxial growth (Epitaxy or Epi for short) process. The epitaxial layer 2 can be the same material as the substrate layer 1 (homoepitaxy) or a different material (heteroepitaxy). Specifically, the epitaxial layer 2 can be silicon-based or silicon carbide. The epitaxial layer 2 can be P-type doped or N-type doped, and the specific doping type and concentration can be adjusted according to the design requirements of the LDMOS device. As Figure 2The P-type substrate layer 1 and the P-type epitaxial layer 2 are shown.

[0063] In forming the LDMOS device structure on the semiconductor substrate, the positions and shapes of the gate 7, the source region 9, the drain region 4 and the drift region 5 can be defined on the semiconductor substrate by photolithography, etching and other processes. The gate 7 is used to control the turn-on and turn-off of the LDMOS device, and is usually made of polycrystalline silicon or metal material. The source region 9 and the drain region 4 are the input and output terminals of the current, respectively, and are generally doped by ion implantation to form a high concentration of P-type or N-type.

[0064] The drift region 5 can be located between the source region 9 and the drain region 4, and is used to withstand high voltage. The drift region 5 can be adjacent to the drain region 4, or the drain region 4 can be located within the drift region 5 to improve the voltage withstand capability of the drain region 4 device. The doping concentration of the drift region 5 can be relatively low compared to the source region 9 or the drain region 4, which can increase the voltage withstand capability of the device. The drift region 5 can be doped with N-type impurities or P-type impurities, and the specific doping type and concentration can be determined according to the actual design requirements. The type of impurities doped in the drift region 5 can be the same as the type of impurities doped in the source or drain to ensure smooth transmission of charges. For example, as shown in the figure, the drain region 4 is N-type doped, and the drift region 5 is also N-type doped, i.e. the drift region 5 is an N-type drift region (N-Drift Field, abbreviated as NDF). Figure 2

[0065] The trench isolation region 6 is provided in the drift region 5, and the trench isolation region 6 can be formed by a shallow trench isolation (Shallow Trench Isolation, abbreviated as STI) method. The shallow trench isolation is to etch a shallow trench on the surface of the semiconductor substrate, and then fill the trench with insulating material such as silicon dioxide to form the trench isolation region 6. The trench isolation region 6 can be used as a drift region, but the trench silicon dioxide is relatively thick and has poor electric field modulation capability, so a large trench width is generally required to withstand the high voltage of the drain.

[0066] The trench isolation region 6 can be formed in the drift region 5 by photolithography and etching and other processes. The trench isolation region 6 can isolate different device structures or regions from each other, reducing mutual interference and leakage. The setting of the trench isolation region 6 can also reduce the electric field strength near the electrode and improve the breakdown voltage of the electrode. By setting the drift region 5 and the trench isolation region 6 therein, the voltage withstand capability of the device can be effectively increased, and the LDMOS device can be ensured to work stably in a high voltage environment.

[0067] Optionally, as shown in the figure, the source region 9 and the drain region 4 can be located in the drift region 5, and the source region 9 and the drain region 4 can be separated by a trench isolation region 6. Figure 2 ​As shown, a contact etch stop layer (CESL) can also be formed on the semiconductor substrate. CESL layer 3 is located on the surface of the semiconductor substrate and covers the LDMOS device structure formed on the semiconductor substrate. It serves to stop the etching process during subsequent etching of the contact holes, preventing over-etching damage to the semiconductor substrate or other LDMOS device structures. CESL can be made of materials such as silicon nitride (SiN) or silicon oxynitride (SiON), and is deposited on the semiconductor substrate surface using processes such as chemical vapor deposition (CVD). The thickness of CESL layer 3 can be from 200 Å to 500 Å. This thickness range ensures effective etching stop during contact hole etching, providing suitable etching resistance, without causing excessive stress on the LDMOS device structure on the semiconductor substrate, and without affecting subsequent processes due to excessive thickness. Here, 1 Å refers to 1 angstrom, and 1 angstrom is 0.1 nanometers.

[0068] Optionally, such as Figure 2 As shown, the above-described LDMOS device structure may further include a base region 8. The base region 8 can be located near the source region 9, or the source region 9 can be located within the base region 8. The base region 8 is used to adjust the potential and charge distribution of the source region 9, enabling the LDMOS device to withstand higher voltages and operate normally. The doping type and concentration of the base region 8 can be adjusted according to the design requirements of the LDMOS device. The doping types of the base region 8 and the source region 9 can be opposite to form a PN junction. For example, as... Figure 2 As shown, if the source region 9 is N-type doped, the base region 8 can be P-type doped, forming a P-type base region PBD (P-Base). The above LDMOS device structure can also include a body connection region 11, which can be P-type doped and is used to lead out the body electrode.

[0069] Step S120: A first dielectric layer 12 is formed on the semiconductor substrate on which the LDMOS device structure is formed.

[0070] The first dielectric layer 12 is an interlayer dielectric (ILD) layer, which can be deposited on the surface of a semiconductor substrate using methods such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The material of the first dielectric layer 12 can be silicon dioxide, silicon nitride, or other materials with good insulating properties. The first dielectric layer 12 serves to protect and insulate the LDMOS device structure, preventing damage from the external environment and preventing leakage between different device structures.

[0071] After the first dielectric layer 12 is formed, it can also be subjected to a planarization process to better ensure the smooth progress of subsequent processes. The planarization process can use chemical mechanical polishing (CMP) to polish the surface of the first dielectric layer 12 to make it flat, so that its surface roughness meets the process requirements. Other planarization methods such as reflow or electrochemical mechanical planarization can also be used, and the application does not specifically limit it.

[0072] Step S130: Form at least one field plate connection hole 14 that penetrates the first dielectric layer 12 and extends into the trench isolation region 6.

[0073] In this step, the field plate connection hole 14 extending into the trench isolation region 6 can be formed by a photolithography and etching process. Specifically, a photoresist 13 (PR) can be coated on the surface of the first dielectric layer 12, the pattern of the field plate connection hole 14 is transferred to the photoresist 13 by a photolithography process to form a photoresist mask, and then an etching process is used to etch the first dielectric layer 12 using the photoresist mask as a template until the trench isolation region 6 is etched, thereby forming the field plate connection hole 14 that penetrates the first dielectric layer 12 and extends into the trench isolation region 6.

[0074] The photoresist can be a positive photoresist or a negative photoresist. The solubility of the positive photoresist increases after exposure, and the exposed part is dissolved during development. The solubility of the negative photoresist decreases after exposure, and the unexposed part is dissolved during development. According to the actual process requirements and the characteristics of the photolithography equipment, the appropriate type of photoresist can be selected.

[0075] The etching process can be dry etching or wet etching. Dry etching has high etching precision and directionality, and can accurately control the size and shape of the field plate connection hole 14, which is suitable for occasions with high size precision requirements. Wet etching has a relatively high etching rate and a relatively simple process, but the directionality and precision of etching are relatively poor. In this application, the appropriate etching process can be selected according to actual needs.

[0076] The number and distribution of the field plate connection hole 14 can be adjusted according to the specific design requirements of the LDMOS device. The field plate connection hole 14 can be set to one or multiple (i.e. two or more). By setting multiple field plate connection holes 14, the reverse electric field can be more effectively provided for the electrode (such as the source or drain) of the semiconductor to offset the high-voltage charge of the electrode and improve the voltage withstand capability of the device. At the same time, the size of the field plate connection hole 14 can be set according to actual conditions to ensure that it can meet the needs of electric field offset and will not occupy too much area on the surface of the semiconductor.

[0077] The depth of the field plate connection hole 14 extending into the trench isolation region 6 can be determined according to the voltage withstand requirement of the LDMOS device and actual design needs. If the depth of the field plate connection hole 14 extending into the trench isolation region 6 is too shallow, it can not effectively provide sufficient reverse electric field for the electrode of the semiconductor, so as to hardly offset the high-voltage charge of the electrode, resulting in that the voltage withstand capability of the device is not obviously improved and there is still a risk of high-voltage breakdown. If the depth of the field plate connection hole 14 extending into the trench isolation region 6 is too deep, although a stronger reverse electric field can be provided, the process difficulty and cost can be increased, and meanwhile the structural stability of the trench isolation region 6 can be affected, for example, the insulation performance of the trench isolation region 6 can be damaged, and leakage problems can be caused. In the embodiment of the present application, the specific depth of the field plate connection hole 14 extending into the trench isolation region 6 can be flexibly set according to needs.

[0078] After the formation of the field plate connection hole 14, it can also be cleaned and surface treated to remove residues and impurities generated in the etching process, so as to ensure that the inner wall of the field plate connection hole 14 is clean and smooth, and to provide a good foundation for the subsequent field plate forming process. The cleaning and surface treatment process can use chemical cleaning, plasma cleaning and the like, and the specific process parameters and methods can be selected according to actual conditions.

[0079] In one embodiment, step S130 can form the field plate connection hole 14 by the following steps: using the same photomask, forming the connection hole 15 above the LDMOS device at the same time as forming the field plate connection hole 14.

[0080] The connection hole 15 above the LDMOS device can include a source connection hole, a drain connection hole, a gate 7 connection hole, and can also include other types of connection holes, which are not specifically limited in the present application. The source connection hole is used to electrically connect the source region 9 with the external circuit to realize the input of current; the drain connection hole is used to connect the drain region 4 with the external circuit to realize the output of current; and the gate 7 connection hole is used to connect the gate 7 with the external control circuit to realize the conduction and cutoff of the LDMOS device by controlling the voltage of the gate 7.

[0081] In the embodiment, as shown in Figure 12 , 13 , the photomask 100 includes a field plate connection hole pattern 102 for defining the position and shape of the field plate connection hole 14, and an LDMOS device connection hole pattern for defining the position and shape of the connection hole 15 above the LDMOS device. The LDMOS device connection hole pattern can include a source connection hole pattern 101, a drain connection hole pattern 103, and can also include various connection hole patterns such as a gate connection hole pattern.

[0082] Specifically, as shown in Figure 4 , Figure 5As shown, the field plate connection hole pattern on the mask and the LDMOS device connection hole pattern can be simultaneously transferred to the photoresist 13 by a photolithography process, and then the first dielectric layer 12 is etched using the photoresist 13 as a mask, thereby simultaneously forming the field plate connection hole 14 and the connection hole 15 above the LDMOS device.

[0083] The present embodiment uses the same mask to simultaneously form the connection hole 15 above the LDMOS device and the field plate connection hole 14, which can simultaneously form multiple connection holes and avoid the process of using an additional mask to form the field plate connection hole 14, greatly reducing the steps and time of photolithography and etching processes, improving production efficiency, and reducing the number of masks used and production costs. Moreover, since the field plate connection hole 14 and the connection hole 15 above the LDMOS device are formed simultaneously, the relative position accuracy between them can be better guaranteed, improving the overall performance and stability of the device.

[0084] In another embodiment, the field plate connection hole 14 can also be formed by the following steps in step S130: using a different mask, forming the field plate connection hole 14 before or after the process of forming the connection hole 15 above the LDMOS device.

[0085] Specifically, when different masks are used, a field plate connection hole 14 mask and an LDMOS device connection hole mask can be provided, wherein the field plate connection hole 14 mask contains a field plate connection hole pattern for defining the position and shape of the field plate connection hole 14, and the LDMOS device connection hole mask contains an LDMOS device connection hole pattern for defining the position and shape of the connection hole 15 above the LDMOS device. In the present embodiment, the field plate connection hole 14 can be formed first based on the field plate connection hole 14 mask and by photolithography and etching processes, and then the connection hole 15 above the LDMOS device can be formed based on the LDMOS device connection hole mask and by photolithography and etching processes; or, the connection hole 15 above the LDMOS device can be formed first based on the LDMOS device connection hole mask, and then the field plate connection hole 14 can be formed based on the field plate connection hole 14 mask, and the order of forming the field plate connection hole 14 and the connection hole 15 above the LDMOS device is not limited.

[0086] For example, in the case of forming the connection hole 15 above the LDMOS device first and then forming the field plate connection hole 14, the following steps can be taken. First, photoresist is coated on the surface of the first dielectric layer 12, and the LDMOS device connection hole pattern on the LDMOS device connection hole mask is transferred to the photoresist by photolithography to form a photoresist mask. Then, the first dielectric layer 12 is etched using the photoresist mask as a template until the corresponding region is etched, thereby forming the connection hole 15 above the LDMOS device. Then, photoresist is coated again on the surface of the first dielectric layer 12, and the field plate connection hole pattern is transferred to the photoresist using the field plate connection hole 14 mask by photolithography to form a new photoresist mask. Then, the first dielectric layer 12 is etched using the new photoresist mask as a template until the trench isolation region 6 is etched, thereby forming the field plate connection hole 14.

[0087] The present embodiment can more accurately control the formation process of each connection hole using different masks for photolithography, thereby ensuring the quality and performance of the connection hole. In some cases, if the first-formed connection hole has a problem, it will not affect the formation of the subsequent other connection hole, thereby reducing the risk of the entire device being scrapped due to a manufacturing error of one connection hole, and providing higher flexibility in the process.

[0088] In the present embodiment, when the field plate connection hole 14 includes multiple field plate connection holes, the same field plate connection hole mask can be used to form multiple field plate connection holes at the same time, or different field plate connection hole masks can be provided, each of which is used for photolithography to form an etching pattern of each field plate connection hole 14, and then each field plate connection hole 14 is formed by etching. The specific method can be flexibly selected by those skilled in the art.

[0089] In one embodiment, after forming the field plate connection hole 14, a barrier layer can be formed on the inner wall of the field plate connection hole 14. The barrier layer is used to prevent the conductive material used to fill the field plate connection hole 14 from diffusing into the surrounding first dielectric layer 12 or semiconductor substrate, thereby affecting the performance and stability of the device. The material of the barrier layer can be titanium (Ti), titanium nitride (TiN), or other materials with good barrier properties. Physical vapor deposition (PVD) or atomic layer deposition (ALD) can be used to deposit the barrier layer on the inner wall of the field plate connection hole 14.

[0090] Step S140: filling the field plate connection hole 14 with a conductive material to form a first field plate 17 embedded in the trench isolation region 6.

[0091] The conductive material can be metal, such as aluminum, copper, tungsten, etc. The metal has good conductivity, which can ensure the field plate to effectively transmit electric charge and provide a reverse electric field for the electrode of the semiconductor. The process of filling the conductive material can use physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, etc.

[0092] Physical vapor deposition refers to depositing metal atoms in the field plate connection hole 14 by evaporation or sputtering in a vacuum environment. This method can accurately control the thickness and quality of the deposition. Chemical vapor deposition is a method of generating solid conductive material by chemical reaction of gaseous reactants at high temperature or in a plasma environment and depositing it in the field plate connection hole 14. This method has the advantage of good step coverage and is suitable for filling high aspect ratio field plate connection holes 14. Electroplating is a method of using the field plate connection hole 14 as a cathode and placing it in an electrolyte containing metal ions. By applying an electric field, metal ions are reduced and deposited on the cathode surface. This method can quickly fill the field plate connection hole 14 and obtain a conductive material with high purity.

[0093] In one embodiment, when filling the conductive material in the field plate connection hole 14, step S140 can use the same filling process to fill the conductive material in the upper connection hole of the LDMOS device at the same time. This can reduce the process steps, improve production efficiency, and avoid the time and cost consumption caused by the separate filling process for the field plate connection hole 14. In addition, using the same filling process to fill the field plate connection hole 14 and the upper connection hole of the LDMOS device at the same time can better ensure the consistency of the conductive material in the field plate connection hole 14 and the upper connection hole of the LDMOS device, including uniformity, composition, etc., thereby improving the performance stability of the entire device.

[0094] In another embodiment, step S140 can also use different filling processes to fill the field plate connection hole 14 and the upper connection hole 15 of the LDMOS device respectively when filling the conductive material in the field plate connection hole 14. For example, the field plate connection hole 14 can be filled first, and then the upper connection hole 15 of the LDMOS device is filled, or the upper connection hole 15 of the LDMOS device is filled first, and then the field plate connection hole 14 is filled. Separate filling can better meet the special requirements of different connection holes for the conductive material filling process. For example, if the aspect ratio of the field plate connection hole 14 is large, it can be more suitable to fill it by using a process such as chemical vapor deposition which has good step coverage; and for the upper connection hole 15 of the LDMOS device, if the filling speed and purity are required to be high, it can be more suitable to fill it by using an electroplating process. Separate use of different filling processes can optimize the specific conditions of each connection hole, so as to ensure that the filling quality and performance of each connection hole reach an optimal state.

[0095] After filling the conductive material, a planarization process can also be performed to remove excess conductive material, so that the surface of the first field plate 17 is flush with the surface of the first dielectric layer 12, so as to ensure the flatness of the field plate surface and provide a good foundation for subsequent process steps.

[0096] After the first field plate 17 is embedded in the trench isolation region 6, the electric field distribution of the LDMOS device can be effectively improved. When the device is in a high-voltage working state, the first field plate 17 can form a reverse electric field near the trench isolation region 6, which can offset part of the electric field near the electrode adjacent to the first field plate 17, thereby reducing the electric field strength and improving the withstand voltage capability of the device. At the same time, the first field plate 17 can also play a shielding role to reduce the mutual interference between different device structures, and improve the stability and reliability of the device.

[0097] The preparation method of the LDMOS provided by the embodiment of the present application provides a semiconductor substrate, forms at least one LDMOS device structure on the semiconductor substrate, the LDMOS device structure at least includes a gate 7, a source region 9, a drain region 4 and a drift region 5, and a trench isolation region 6 is arranged in the drift region 5. By arranging the drift region 5 and the trench isolation region 6 in the drift region 5, the withstand voltage capability of the device can be increased. Then, a first dielectric layer 12 is formed on the semiconductor substrate on which the LDMOS device structure is formed, the first dielectric layer 12 can protect the LDMOS device structure. Then, at least one field plate connecting hole 14 penetrating through the first dielectric layer 12 and extending into the trench isolation region 6 is formed, and a conductive substance is filled in the field plate connecting hole 14 to form a first field plate 17 embedded in the trench isolation region 6. In this way, the first field plate 17 embedded in the trench isolation region 6 can be used to provide a reverse electric field for the electrode of the LDMOS device structure, effectively offsetting the high-voltage charge of the electrode in the LDMOS device structure, and preventing the electrode from being subjected to high-voltage breakdown. Moreover, since the first field plate 17 is embedded in the trench isolation region 6, compared with the way of increasing the field plate above the gate 7 and extending to cover the trench isolation region 6, the occupation of the semiconductor surface area is greatly reduced, which is beneficial to the miniaturization and integration of the chip.

[0098] In an embodiment, as shown in Figure 4 、 Figure 6 The field plate connecting hole 14 can include two or more, and is arranged in a direction away from the gate 7. Specifically, each field plate connecting hole 14 can be arranged in a direction away from the gate 7 in sequence, so that a plurality of first field plates 17 arranged in a direction away from the gate 7 can be formed. The plurality of first field plates 17 arranged in a direction away from the gate 7 can form a more uniform and stronger reverse electric field distribution, thereby more effectively offsetting the high-voltage charge of the electrode. In this case, the field plate connecting hole 14 can include two, three or more, and the specific number can be determined according to the specific design and withstand voltage requirement of the LDMOS device. When more field plate connecting holes 14 form more first field plates 17, the regulation of the electric field can be more precise, and the stability of the device in a high-voltage environment can be further improved. When the number of field plate connecting holes 14 and the first field plates 17 is small, the process is simpler, and the cost is also lower. The specific number can be flexibly set by those skilled in the art according to actual needs.

[0099] The spacing between each field plate connecting hole 14 arranged in a direction away from the gate 7 should not be too large, so as to avoid the formation of a continuous and effective reverse electric field, affecting the offset effect of the high-voltage charge of the electrode and reducing the withstand voltage capability of the device. However, the spacing should not be too small, so as to avoid the mutual interference of the electric fields between adjacent first field plates 17.

[0100] When the first field plate 17 includes multiple ones arranged in sequence in a direction away from the gate 7, the width of each first field plate 17 can be set relatively narrow, so that sufficient reverse electric field can be provided, and the change of the electric field distribution on the semiconductor surface can be better adapted to, and the flexibility of the electric field adjustment can be improved. Moreover, the multiple narrow first field plates 17 are formed by using different field plate connection hole patterns of different sizes on a mask to form openings on the substrate, and based on the etching load effect of different openings in etching, trenches of different depths are formed to more accurately modulate the electric field distribution. In addition, all the connection hole patterns of the first field plates are placed on one mask, which can reduce the risk of uneven electric field distribution caused by process errors. The addition of the first field plate can reduce the width of the trench 6 and reduce the occupation of the semiconductor surface area, so that the chip layout is more compact and reasonable.

[0101] When the field plate connection hole 14 includes one, one first field plate 17 can be formed. In this case, as shown in Figure 5 、 Figure 7 , the first field plate 17 can be set relatively wide in a direction away from the gate 7, so as to provide a large enough reverse electric field coverage range to more effectively offset the high-voltage charge of the electrode. The relatively wide single first field plate 17 has relatively low requirements for the precision of the photolithography and etching processes in manufacturing, which can reduce the process difficulty and cost to some extent, and can also simplify the manufacturing process.

[0102] In actual applications, those skilled in the art can comprehensively consider various factors such as the specific performance requirements of the LDMOS device, the electric field distribution characteristics, and the process cost to select multiple first field plates 17 or a single first field plate 17.

[0103] In an embodiment, as shown in Figures 4-7 , the longitudinal depth of the field plate connection hole 14 formed in the trench isolation region 6 can satisfy that the depth in the trench isolation region 6 on the side close to the gate 7 is greater than the depth in the trench isolation region 6 on the side away from the gate 7. In this way, the embedding depth of the first field plate 17 formed on the side close to the gate 7 in the trench isolation region 6 can be greater, and the strong electric field in the region close to the gate 7 can be more effectively adjusted. Since the electric field intensity near the gate 7 is often high when the LDMOS device is working, the problem of electric field concentration is prone to occur. By setting the first field plate 17 on the side close to the gate 7 to be deeper, the strong electric field in this region can be better offset, the peak value of the electric field intensity can be reduced, and the withstand voltage capability and reliability of the device can be improved. By setting the first field plate 17 on the side away from the gate 7 to be shallower, the influence on the electric field distribution in the region away from the gate 7 can be reduced, and the rationality of the electric field distribution of the entire device can be ensured. At the same time, the setting of the depth difference can also help to optimize the electric field adjustment effect of the first field plate 17, so that the electric field distribution is more uniform.

[0104] In one embodiment, when the field plate connection hole 14 includes one, the depth of the field plate connection hole 14 near the gate 7 side can be set to be greater than the depth away from the gate 7 side.

[0105] As shown in FIG. 1, the field plate connection hole 14 includes one, and the bottom of the field plate connection hole 14 is tapered along the direction away from the gate 7, so that the bottom of the field plate connection hole 14 is an inclined surface, and the first field plate 17 formed by the field plate connection hole 14 has a larger depth in the trench isolation region 6 near the gate 7 side and a smaller depth away from the gate 7 side. Figure 5 、 Figure 7 、 Figure 9 As shown in FIG. 1, the field plate connection hole 14 includes one, and the bottom of the field plate connection hole 14 is tapered along the direction away from the gate 7, so that the bottom of the field plate connection hole 14 is an inclined surface, and the first field plate 17 formed by the field plate connection hole 14 has a larger depth in the trench isolation region 6 near the gate 7 side and a smaller depth away from the gate 7 side.

[0106] Alternatively, when the field plate connection hole 14 includes one, the bottom of the field plate connection hole 14 can also be stepped, that is, the bottom of the field plate connection hole 14 is composed of multiple planes with different depths, and the plane near the gate 7 side has a greater depth than the plane away from the gate 7 side. This way can also make the first field plate 17 formed by the field plate connection hole 14 have a larger depth in the trench isolation region 6 near the gate 7 side and a smaller depth away from the gate 7 side. The stepped bottom of the field plate connection hole 14 can flexibly adjust the depth and width of each plane according to different electric field distribution requirements, improving the accuracy of electric field adjustment. Moreover, the stepped field plate connection hole 14 is easier to control the size and position of each depth plane during the manufacturing process, reducing the manufacturing error.

[0107] Alternatively, when the field plate connection hole 14 includes one, the bottom of the field plate connection hole 14 can also be wavy, and the wave trough near the gate 7 side is deeper than the wave trough away from the gate 7 side. The first field plate 17 formed by the wavy field plate connection hole 14 can also provide a stronger reverse electric field in the region near the gate 7, while maintaining a relatively weak reverse electric field in the region away from the gate 7, to adapt to the electric field distribution requirements of different regions. The wavy design can make the electric field distribution more continuous and natural, avoiding sudden changes in the electric field.

[0108] When the field plate connection hole 14 includes one, the bottom of the field plate connection hole 14 can also have other irregular shapes, as long as it can meet the condition that the depth in the trench isolation region 6 near the gate 7 side is greater than the depth in the trench isolation region 6 away from the gate 7 side. Different irregular shapes can be selected according to the specific electric field distribution simulation results and actual process conditions to achieve the electric field adjustment effect.

[0109] In another embodiment, when the field plate connection hole 14 includes two or more and is arranged away from the gate 7, the depth of the field plate connection hole 14 close to the gate 7 in at least two of the two or more field plate connection holes 14 is greater than the depth of the field plate connection hole 14 away from the gate 7 into the trench isolation region 6.

[0110] Specifically, the depth of the field plate connection hole 14 close to the gate 7 in each field plate connection hole 14 can be greater than the depth of the field plate connection hole 14 away from the gate 7 into the trench isolation region 6, that is, the depth of each field plate connection hole 14 into the trench isolation region 6 gradually decreases in the direction away from the gate 7, so that the multiple first field plates 17 formed gradually decrease in depth in the direction away from the gate 7, which can more specifically adjust the electric field intensity in different regions. The electric field intensity in the region close to the gate 7 is high, and the first field plate 17 with a greater depth can more effectively offset the strong electric field in this region and reduce the problem of electric field concentration; while the electric field intensity in the region away from the gate 7 is relatively low, the first field plate 17 with a shallower depth can not only play a certain role in adjusting the electric field, but also not excessively affect the electric field distribution in this region, ensuring the rationality and uniformity of the electric field distribution of the entire device.

[0111] Alternatively, the depth of the field plate connection hole 14 close to the gate 7 in at least two of the two or more field plate connection holes 14 can be greater than the depth of the field plate connection hole 14 away from the gate 7 into the trench isolation region 6, and the depth of the other field plate connection hole 14 can be flexibly set according to actual needs, for example, when the number of field plate connection holes 14 is three, in the first and second field plate connection holes 14, the depth of the field plate connection hole 14 close to the gate 7 in the first is greater than the depth of the field plate connection hole 14 away from the gate 7 in the second into the trench isolation region 6, and the depth of the third field plate connection hole 14 farthest from the gate 7 into the trench isolation region 6 can be less than or equal to the depth of the second field plate connection hole 14. Such a setting can flexibly adjust the depth of different field plate connection holes 14 according to the actual electric field distribution needs to achieve more precise electric field adjustment.

[0112] Alternatively, the depth of the field plate connection holes 14 close to the gate 7 in the trench isolation region 6 can be greater than the depth of the field plate connection holes 14 far away from the gate 7. For example, when there are four field plate connection holes 14, the depth of the first two field plate connection holes 14 close to the gate 7 is greater than the depth of the last two field plate connection holes 14 far away from the gate 7. This arrangement can be used to flexibly adjust the electric field in the case of complex electric field distribution. The first field plate 17 close to the gate 7 has a greater depth, which can concentrate on adjusting the strong electric field near the gate 7, while the field plate connection holes 14 far away from the gate 7 have a smaller depth, which can be adjusted according to the specific situation of the electric field in this area, so that the electric field distribution of the entire device is more in line with the design requirements, and the voltage resistance and stability of the device are further improved.

[0113] Alternatively, the depth of the field plate connection holes 14 close to the gate 7 in the trench isolation region 6 can be greater than the depth of the field plate connection holes 14 far away from the gate 7. For example, when there are four field plate connection holes 14, the depth of the first two field plate connection holes 14 close to the gate 7 is greater than the depth of the last two field plate connection holes 14 far away from the gate 7. This arrangement can be used to flexibly adjust the electric field in the case of complex electric field distribution. The first field plate 17 close to the gate 7 has a greater depth, which can concentrate on adjusting the strong electric field near the gate 7, while the field plate connection holes 14 far away from the gate 7 have a smaller depth, which can be adjusted according to the specific situation of the electric field in this area, so that the electric field distribution of the entire device is more in line with the design requirements, and the voltage resistance and stability of the device are further improved.

[0114] For the plurality of field plate connection holes 14 arranged away from the gate 7, the bottom shape of the field plate connection holes 14 can also have multiple options. For example, the bottom of the field plate connection holes 14 can be inclined, and the inclination direction gradually decreases in depth along the direction away from the gate 7, so that the first field plate 17 formed close to the gate 7 has a greater depth in the trench isolation region 6, and the depth away from the gate 7 is smaller, achieving a smoother electric field transition and avoiding electric field discontinuity; alternatively, the bottom of the field plate connection holes 14 can be a flat surface, and the depth of the flat surface of different field plate connection holes 14 can decrease along the direction away from the gate 7. This flat surface arrangement is relatively simple in manufacturing process and can better control the depth of each field plate connection hole 14; alternatively, the bottom of the field plate connection holes 14 can also be stepped, wavy or other irregular shapes, which are not specifically limited in the present application.

[0115] For the plurality of field plate connection holes 14 arranged in the direction away from the gate 7, the bottom shape of each field plate connection hole 14 can be the same or different, for example, the bottom shape of each field plate connection hole 14 is a flat surface or an inclined surface, which can simplify the manufacturing process and facilitate uniform control of process parameters; or, the bottom of part of the field plate connection holes 14 is a flat surface, part is an inclined surface, or part is a combination of different shapes such as a stepped shape, and such diversified combinations can more flexibly adjust the electric field according to the electric field distribution characteristics of different regions.

[0116] Due to the concentration of the electric field near the gate 7, a higher electric field strength is easily generated, and in the embodiment, the field plate connection hole 14 close to the gate 7 is arranged deeper, and the first field plate 17 formed by embedding in the trench isolation region 6 is also deeper, which can more effectively provide a stronger reverse electric field in this region to offset the high-voltage charge of the electrode and avoid problems such as electric field breakdown. The electric field strength in the region away from the gate 7 is relatively low, and the field plate connection hole 14 is arranged shallow, which can play a certain role in adjusting the electric field and will not greatly interfere with the original electric field distribution in this region, ensuring the rationality and stability of the electric field distribution of the entire device.

[0117] In an embodiment, the depth of the field plate connection hole 14 formed near the gate 7 side in the trench isolation region 6 is greater than the depth of the field plate connection hole 14 formed away from the gate 7 side in the trench isolation region 6, which can be realized by the following process steps S131-S132.

[0118] Step S131: Define the etching pattern by the lithography process to realize that the width of the field plate connection hole pattern close to the gate 7 side is greater than the width of the field plate connection hole pattern away from the gate 7 side.

[0119] The above etching pattern can be understood as a pattern formed on the photoresist for subsequent etching process. The lithography process refers to transferring the designed pattern to the photoresist by a mask for lithography.

[0120] Specifically, a mask for lithography can be provided, the mask for lithography includes a field plate connection hole pattern, the width of the field plate connection hole pattern close to the gate 7 side on the mask for lithography is greater than the width of the field plate connection hole pattern away from the gate 7 side, the pattern on the mask for lithography matches the target size and shape of the field plate connection hole 14, and then the mask for lithography is used for photoetching exposure on the semiconductor substrate coated with photoresist, so that the pattern corresponding to the pattern on the mask for lithography is formed on the photoresist. In this way, the field plate connection hole pattern with the width close to the gate 7 side being greater than the width away from the gate 7 side is formed on the photoresist to define the etching pattern.

[0121] Optionally, the etching pattern can be a pattern with the width gradually decreasing from the gate 7 to the direction away from the gate 7, for example, as shown in FIG. 6A. Figure 5 、 Figure 7As shown, the field plate connection hole pattern can be a trapezoid gradually decreasing in width from the side close to the gate electrode 7 to the side away from the gate electrode 7, or a triangle, a sector, etc. The etching pattern can also be a combined pattern in which the side close to the gate electrode 7 is wider and the side away from the gate electrode 7 is narrower, for example, a combination of a rectangle and a triangle, in which the rectangle is close to the gate electrode 7 and the triangle is away from the gate electrode 7, and the width of the rectangle is greater than that of the triangle. Such a combined pattern can also meet the requirement that the width of the side close to the gate electrode 7 is greater than that of the side away from the gate electrode 7.

[0122] Step S132: Different etching depths at different positions are realized by using different etching rates of etching patterns of different sizes in the etching process.

[0123] In the etching process, the etching rate of the etching pattern of a larger size is relatively fast, because in the plasma etching process, active particles in the plasma are more likely to reach the region of the etching pattern of a larger size, so that the etching rate of the region is accelerated. Therefore, as shown, a field plate connection hole pattern is formed on the photoresist, in which the width of the side close to the gate electrode 7 is greater than that of the side away from the gate electrode 7. In the etching process, the side close to the gate electrode 7 is etched deeper because of the fast etching rate of the etching pattern of a larger size; and the etching depth of the side away from the gate electrode 7 is relatively shallow because of the slow etching rate of the etching pattern of a smaller size, so that the depth of the field plate connection hole 14 close to the gate electrode 7 in the trench isolation region 6 is greater than that of the field plate connection hole 14 away from the gate electrode 7 in the trench isolation region 6. Figures 4-7

[0124] The present embodiment utilizes the different etching rates of etching patterns of different sizes to efficiently and conveniently realize the different depths of the side close to the gate electrode 7 and the side away from the gate electrode 7 of the field plate connection hole 14 by using the existing photoetching and etching equipment, without the need for additional complex equipment or process improvement. The different depth requirements can be realized by one etching, thereby reducing the production cost.

[0125] In a specific embodiment, the depth of the field plate connection hole 14 close to the gate electrode 7 into the trench isolation region 6 is greater than that of the field plate connection hole 14 away from the gate electrode 7 into the trench isolation region 6 in at least two of the two or more field plate connection holes 14 described above, which can be realized by the following steps S133-S134.

[0126] Step S133: The etching pattern is defined by the opening size of the field plate connection hole pattern on the side close to the gate electrode 7 being greater than that of the field plate connection hole 14 on the side away from the gate electrode 7 through the photoetching process.

[0127] ​Specifically, a mask for lithography can be provided, and the mask for lithography includes various field plate connection hole patterns, each of which is used to etch a corresponding field plate connection hole 14. In the various field plate connection hole patterns on the mask for lithography, the opening size of the field plate connection hole pattern on the side close to the gate electrode 7 is greater than the opening size of the field plate connection hole pattern on the side away from the gate electrode 7. Then, the mask for lithography is used to perform lithography exposure on a semiconductor substrate coated with photoresist, so that a pattern corresponding to the pattern on the mask for lithography is formed on the photoresist. In this way, an etching pattern in which the opening size of the field plate connection hole pattern on the side close to the gate electrode 7 is greater than the opening size of the field plate connection hole pattern on the side away from the gate electrode 7 is formed on the photoresist. The opening size can include at least one size parameter that can affect the etching effect, such as the width, length, and area of the field plate connection hole pattern, or other size parameters. For example, as shown in FIGS. 29 and 30, the opening width of the field plate connection hole pattern on the side close to the gate electrode 7 is greater than the opening width of the field plate connection hole pattern on the side away from the gate electrode 7. Figure 4 、 Figure 6

[0128] Step S134: Different etching depths of the field plate connection holes 14 at different positions are realized by using different etching rates of the etching patterns with different opening sizes in the etching process.

[0129] In the etching process, the etching rate of the etching pattern with a larger opening size is relatively faster. Therefore, after the etching pattern in which the opening size of the field plate connection hole pattern on the side close to the gate electrode 7 is greater than the opening size of the field plate connection hole pattern on the side away from the gate electrode 7 is formed on the photoresist, in the etching process, the side close to the gate electrode 7 is etched deeper due to the larger opening size and the faster etching rate, while the side away from the gate electrode 7 is etched relatively shallowly due to the smaller opening size and the slower etching rate. In this way, the depth of the field plate connection hole 14 on the side close to the gate electrode 7 extending into the trench isolation region 6 is greater than the depth of the field plate connection hole 14 on the side away from the gate electrode 7 extending into the trench isolation region 6.

[0130] This method of controlling the depth of the field plate connection hole 14 by using different etching rates of the etching patterns with different opening sizes is compatible with existing lithography and etching processes, and does not require large-scale modification of existing equipment and processes, thereby reducing production costs and process difficulty. Moreover, by accurately controlling the pattern design of the mask for lithography, the accuracy and consistency of the etching depth can be ensured.

[0131] ​In other embodiments, the depth of the field plate connection hole 14 in the trench isolation region 6 near the side of the gate 7 can be greater than the depth of the field plate connection hole 14 in the trench isolation region 6 far from the side of the gate 7. Other ways can also be used to achieve this. For example, a relatively shallow basic etching depth hole can be formed by multiple times of photolithography and etching, and then a second photolithography is performed on the region near the side of the gate 7 using a specially designed photomask that covers only the region near the side of the gate 7. Then, a second etching is performed to deepen the etching depth near the side of the gate 7. In this way, the depth difference of the field plate connection hole 14 near the side of the gate 7 and far from the side of the gate 7 can be achieved. The depth difference of the field plate connection hole 14 can also be achieved by other ways, which are not specifically limited in the present application.

[0132] In an embodiment, the gate 7 of the LDMOS device can extend over the trench isolation region 6 of the drift region 5 to form a second field plate covering part of the trench isolation region 6.

[0133] Specifically, the conductive part of the gate 7 can be extended over the trench isolation region 6 of the drift region 5, so that the gate 7 can cover part of the trench isolation region 6 to form a second field plate.

[0134] When the gate 7 extends to form a second field plate, the drift region 5 will be subjected to a certain voltage during device operation. Since the second field plate covers part of the trench isolation region 6, it can generate an additional electric field adjustment effect in this region. In a high-voltage working state, the drift region 5 is subjected to a high voltage, and uneven electric field distribution can easily lead to excessively high local electric field strength, thereby causing breakdown of the device and other problems. Under the action of the voltage of the gate 7, the second field plate will induce charges of opposite polarity to the charges of the drift region 5 on the surface of the trench isolation region 6 it covers. These induced charges will interact with the charges of the drift region 5, thereby weakening the electric field strength in this region and avoiding the phenomenon of electric field concentration. The present embodiment can further improve the voltage withstand capability and stability of the device by adding a second field plate.

[0135] Specifically, part of the gate 7 can extend over the trench isolation region 6 of the drift region 5, and the width of the gate 7 covering the trench isolation region 6 can be set according to actual needs. The greater the coverage width, the stronger the reverse adjustment effect on the electric field, but the greater the coverage width, the greater the area occupied by the LDMOS device, which is not conducive to the miniaturization design of the device. Therefore, in actual applications, the appropriate width of the gate 7 covering the trench isolation region 6 can be determined by considering factors such as electric field adjustment effect and device area.

[0136] In the high-voltage working state of the gate 7, the second field plate can disperse the electric field from the edge of the gate 7 to a larger area, avoid excessive concentration of the electric field at the edge of the gate 7, reduce the electric field intensity at the edge of the gate 7, and reduce the risk of breakdown of the gate 7.

[0137] In another embodiment, the gate 7 of the LDMOS device can also not cover the trench isolation region 6 of the drift region 5, that is, the gate 7 is arranged staggered with the trench isolation region 6 of the drift region 5, so that there is no overlapping part between the gate 7 and the trench isolation region 6. In this way, the size of the gate 7 can be reduced, the structure of the LDMOS device is more compact, the capacitive coupling between the gate 7 and the drift region 5 can be reduced, the switching loss of the device can be reduced, and the switching speed of the device can be improved. At the same time, this arrangement can also simplify the manufacturing process and improve production efficiency.

[0138] In practical applications, whether the gate 7 covers part of the trench isolation region 6 or is arranged staggered with the trench isolation region 6 can be flexibly set by those skilled in the art according to actual conditions.

[0139] In an embodiment, the above method can further include the following steps: forming a connection structure 18 electrically connected to the first field plate 17, and applying an electric potential to the first field plate 17 through the connection structure 18.

[0140] When the formed first field plate 17 includes two or more, as shown in Figure 8 The same connection structure 18 can be electrically connected to each first field plate 17 to make each first field plate 17 apply the same electric potential, which is relatively simple to operate and can ensure the consistency of the electric field adjustment of each first field plate 17. Alternatively, different connection structures can be electrically connected to each first field plate 17 to make each first field plate 17 apply different electric potentials, which can more accurately adjust the electric field according to the specific electric field of each region.

[0141] The connection structure 18 electrically connected to the first field plate 17 can be a metal wire, a metal via, a metal pad, or other metal structures. These connection structures 18 can effectively achieve electrical connection with the first field plate 17 and stable application of the electric potential. The material of the connection structure 18 can be copper, aluminum, or other metals.

[0142] The connection structure 18 electrically connected to the first field plate 17 can be formed by any one of physical vapor deposition, chemical vapor deposition, and electroplating.

[0143] The physical vapor deposition method can use the metal material (such as copper, aluminum, etc.) to be deposited as a target material, which is placed in a vacuum chamber. Then, the target material atoms are sputtered out by high-energy particles (such as argon ions) bombarding the surface of the target material, and are deposited on the surface of the semiconductor substrate to form a metal connection structure. The chemical vapor deposition method can use a gaseous metal compound containing metal elements to undergo a chemical reaction under high temperature, plasma, or the like, to deposit a solid metal connection structure on the surface of the semiconductor substrate. The electroplating method can immerse the substrate in an electroplating solution containing metal ions, and apply a proper current to reduce and deposit the metal ions to gradually grow the required connection structure. In actual applications, a method can be selected according to actual needs to realize the connection structure 18 electrically connected to the first field plate 17.

[0144] Optionally, the connection structure 18 electrically connected to the first field plate 17 can be realized in the following manner: the connection structure 18 electrically connected to the first field plate 17 is formed at the same time as the connection structure 19 above the LDMOS device.

[0145] The connection structure 19 above the LDMOS device can include a connection structure electrically connected to the source, a connection structure electrically connected to the drain, etc. In the embodiments of the present application, the connection structures of various electrodes above the device and the connection structure 18 of the first field plate 17 can be constructed at the same time through the metal interconnection layer, so as to improve the manufacturing efficiency and reduce the additional process steps and costs. For example, when the physical vapor deposition method is used to manufacture the metal interconnection layer, the connection structure 18 electrically connected to the first field plate 17 can be deposited at the same time as the connection structure 19 electrically connected to the source and the connection structure 19 electrically connected to the drain.

[0146] Optionally, the connection structure 18 electrically connected to the first field plate 17 can be realized in the following manner: the connection structure 19 above the LDMOS device and the connection structure 18 electrically connected to the first field plate 17 are formed through different processes, respectively. For example, the connection structure 19 above the LDMOS device can be formed through the physical vapor deposition method first, and then the connection structure 18 electrically connected to the first field plate 17 is formed through the electroplating method. In this way, the most suitable process method can be selected according to the characteristics and needs of different connection structures, so as to ensure the performance and quality of the connection structure.

[0147] Optionally, the connection structure electrically connecting the first field plate 17 can be electrically connected with the source level. Specifically, the connection structure of the first field plate 17 can be connected with the source level through a metal via, a metal wire or the like, so that the first field plate 17 has the same electric potential as the source level. Since the source level has a relatively stable electric potential in the LDMOS device, electrically connecting the first field plate 17 with the source level enables the first field plate 17 to have a more stable electric potential basis when adjusting the electric field, thereby more effectively adjusting the electric field and enhancing the voltage withstand capability and stability of the device. In addition, electrically connecting the first field plate 17 with the source level can reduce the gate charge due to the small voltage variation range of the first field plate and the drain, thereby improving the switching speed of the device. At the same time, this connection mode can also simplify the circuit design, reduce additional potential application structures, and reduce production cost and process complexity.

[0148] Alternatively, the connection structure electrically connecting the first field plate 17 can also be electrically connected with other independent potential sources, such as being connected with a special voltage source. In this way, the electric potential size and polarity applied to the first field plate 17 can be flexibly adjusted according to actual electric field adjustment requirements.

[0149] The connection structure electrically connecting the first field plate 17 can also be electrically connected with the gate 7. When electrically connected with the gate 7, the first field plate 17 will be affected by the voltage of the gate 7. During the operation of the device, the change of the voltage of the gate 7 will be transmitted to the first field plate 17, so that the first field plate 17 can dynamically adjust the electric field according to the working state of the gate 7.

[0150] In an embodiment, as shown in Figure 6 、 Figure 7 After forming the field plate connection hole 14, before filling the conductive substance, the method can further include: implanting N-type ions 16 into the drift region 5 at the bottom of the field plate connection hole 14.

[0151] Specifically, the N-type ions 16 can be implanted into the drift region 5 at the bottom of the field plate connection hole 14 by an ion implantation device. The implanted N-type ions 16 can be phosphorus ions, arsenic ions or the like. These N-type ions 16 can effectively change the electrical properties of the drift region 5, such as increasing the electron concentration of the drift region 5, thereby reducing the resistance of the drift region 5. When the device is working, the lower resistance can reduce the current loss in the drift region 5 and improve the conduction efficiency of the device. At the same time, the implanted N-type ions 16 can also enhance the carrier concentration of the drift region 5, so that the drift region 5 can better conduct current when bearing voltage, further improving the performance of the device. At the same time, the N-type ion implantation can also reduce the parasitic capacitance of the gate and the drain, thereby improving the switching speed of the device.

[0152] As shown in Figure 6 、 Figure 7As shown, N-type ions 16 can be implanted into the drift region 5 near the bottom of the trench isolation region 6. Since the area near the bottom of the trench isolation region 6 is the main path for current conduction, the current is concentrated there. Implanting N-type ions 16 into this location can significantly improve current conduction. Furthermore, additional N-type ion implantation can better shield the interface charge at the bottom of the trench and the silicon interface, reducing charge loss during device switching and improving switching speed. N-type ions 16 can also be implanted into other locations in the drift region 5 corresponding to the bottom of the field plate connection hole 14; this application does not specifically limit the location.

[0153] In this embodiment, the source region 9 and drain region 4 on the semiconductor substrate are also N-type doped regions, which have the same conductivity type as the N-type ions 16 implanted into the drift region 5. This consistency helps to make the current conduct more smoothly between the source region 9, drift region 5 and drain region 4 when the device is working, and further optimizes the electrical performance of the device.

[0154] In one specific embodiment, the injected particles are more widely distributed and have a higher concentration in the bottom drift region 5 corresponding to the deeper portion of the field plate connection hole 14 or the field plate connection hole 14 with a larger depth.

[0155] Among them, wider distribution means that the injected N-type ions 16 have a larger diffusion range in the drift region 5 and can cover a larger area, which can be a wider distribution in the depth direction or a wider distribution in the width direction; higher concentration means that more N-type ions 16 are injected per unit volume.

[0156] Specifically, such as Figures 6-9 As shown, when the depth of the field plate connection hole 14 near the gate 7 is greater than the depth of the portion farther from the gate 7, the bottom drift region 5 corresponding to the deeper portion of the field plate connection hole 14 has a wider distribution and higher concentration of injected particles, while the bottom drift region 5 corresponding to the shallower portion of the field plate connection hole 14 has a smaller distribution range and lower concentration of injected particles than the deeper portion. When there are multiple field plate connection holes 14, the bottom drift region 5 corresponding to the deeper field plate connection hole 14 has a wider distribution and higher concentration of injected particles, while the bottom drift region 5 corresponding to the shallower field plate connection hole 14 has a smaller distribution range and lower concentration of injected particles than the bottom drift region 5 corresponding to the deeper field plate connection hole 14. This difference in the distribution and concentration of injected particles can further optimize the electrical performance of the drift region 5. For the bottom drift region 5 corresponding to the deeper field plate connection hole 14, due to the wider distribution and higher concentration of injected particles, the electron concentration in this region can be increased to a greater extent, the resistance can be reduced, the current conduction in this region can be smoother, the current loss in the drift region 5 can be reduced, and the conduction efficiency of the device can be improved.

[0157] The second embodiment of this application provides a method for fabricating LDMOS, such as...Figure 10 As shown in the figure, the method comprises steps S210-S250.

[0158] Step S210: providing a semiconductor substrate, forming at least one LDMOS device structure on the semiconductor substrate, the LDMOS device structure at least comprising a gate 7, a source region 9, a drain region 4, and a drift region 5, a trench isolation region 6 being arranged in the drift region 5;

[0159] Step S220: forming a first dielectric layer 12 on the semiconductor substrate on which the LDMOS device structure is formed;

[0160] Step S230: forming at least one field plate connecting hole 14 penetrating through the first dielectric layer 12 and extending into the trench isolation region 6;

[0161] Step S240: filling a conductive substance in the field plate connecting hole 14 to form a first field plate 17 embedded in the trench isolation region 6;

[0162] Step S250: forming a connecting structure 18 electrically connecting the first field plate 17, and applying an electric potential to the first field plate 17 through the connecting structure 18, the connecting structure 18 being electrically connected to a source level.

[0163] The specific content of the embodiment and the corresponding beneficial effects can be referred to the related description in the first embodiment, and the embodiment will not be described in detail.

[0164] The third embodiment of the present application provides a preparation method of an LDMOS, as shown in the figure. Figure 11 As shown in the figure, the method comprises steps S310-S350.

[0165] Step S310: providing a semiconductor substrate, forming at least one LDMOS device structure on the semiconductor substrate, the LDMOS device structure at least comprising a gate 7, a source region 9, a drain region 4, and a drift region 5, a trench isolation region 6 being arranged in the drift region 5;

[0166] Step S320: forming a first dielectric layer 12 on the semiconductor substrate on which the LDMOS device structure is formed;

[0167] Step S330: forming at least one field plate connecting hole 14 penetrating through the first dielectric layer 12 and extending into the trench isolation region 6;

[0168] Step S340: implanting N-type ions 16 into the drift region 5 at the bottom of the field plate connecting hole 14;

[0169] Step S350: filling a conductive substance in the field plate connecting hole 14 to form a first field plate 17 embedded in the trench isolation region 6.

[0170] The specific content of the embodiment and the corresponding beneficial effects can be referred to the related description in the first embodiment, and the embodiment will not be described in detail.

[0171] The fourth embodiment of the present application further provides an LDMOS device, which comprises a semiconductor substrate, at least one LDMOS device structure is formed on the semiconductor substrate, the LDMOS device structure at least comprises a gate 7, a source region 9, a drain region 4 and a drift region 5, a trench isolation region 6 is arranged in the drift region 5; a first dielectric layer 12 is formed on the semiconductor substrate where the LDMOS device structure is formed, the first dielectric layer 12 is penetrated by at least one field plate connecting hole 14 which extends into the trench isolation region 6; the field plate connecting hole 14 is filled with a conductive substance to form a first field plate 17 embedded in the trench isolation region 6.

[0172] The longitudinal depth of the field plate connecting hole 14 in the trench isolation region 6 satisfies that the depth of the field plate connecting hole 14 in the trench isolation region 6 near the gate 7 is greater than the depth of the field plate connecting hole 14 in the trench isolation region 6 far from the gate 7.

[0173] Optionally, the gate 7 of the LDMOS device extends above the trench isolation region 6 of the drift region 5 to form a second field plate covering part of the trench isolation region 6.

[0174] Optionally, the field plate connecting hole 14 comprises two or more, and is arranged in the direction away from the gate 7.

[0175] Optionally, among the two or more field plate connecting holes 14, the depth of the field plate connecting hole 14 near the gate 7 extending into the trench isolation region 6 is greater than the depth of the field plate connecting hole 14 far from the gate 7 extending into the trench isolation region 6.

[0176] Optionally, the first field plate 17 is electrically connected with a connecting structure 18, and the connecting structure 18 is used to apply an electric potential to the first field plate 17.

[0177] Optionally, the connecting structure 18 is electrically connected with the source electrode.

[0178] Optionally, the drift region 5 at the bottom of the field plate connecting hole 14 is implanted with N-type ions 16.

[0179] Optionally, the drift region 5 at the bottom of the field plate connecting hole 14 with a deeper depth or the field plate connecting hole 14 with a greater depth is implanted with ions with a wider distribution and a greater concentration.

[0180] The related content of the LDMOS device provided by the embodiment and the corresponding beneficial effects can be referred to the first embodiment, and will not be described in detail here.

[0181] The fifth embodiment of the present application also provides a mask plate 100 for photolithography, which comprises a field plate connection hole pattern 102, an LDMOS field plate connection hole pattern, the LDMOS field plate connection hole pattern can comprise a source connection hole pattern 101 and a drain connection hole pattern 103, the pattern size of the field plate connection hole pattern 102 close to the gate part of the semiconductor substrate to be etched is greater than the pattern size far from the gate part, wherein the area where the pattern is located is a light transmission area or a light shielding area.

[0182] Through the mask plate 100 for photolithography, the etching patterns of the connection holes and the etching patterns of the field plate connection holes on the LDMOS device can be formed on the semiconductor substrate at the same time.

[0183] Optionally, as shown in the figure, the field plate connection hole pattern 102 comprises two or more, each field plate connection hole pattern 102 is arranged along the direction away from the gate of the semiconductor substrate to be etched, and at least two of each field plate connection hole pattern 102 satisfy that the pattern area close to the gate of the semiconductor substrate to be etched is greater than the pattern area far from the gate, so that at least two of the etching patterns of the field plate connection holes formed on the semiconductor substrate satisfy that the opening size of the etching pattern close to the gate is greater than the opening size of the etching pattern far from the gate, thereby enabling the depth of the field plate connection hole close to the gate to be greater than the depth of the field plate connection hole far from the gate. Figure 13 Optionally, as shown in the figure, the field plate connection hole pattern 102 comprises two or more, each field plate connection hole pattern 102 is arranged along the direction away from the gate of the semiconductor substrate to be etched, and at least two of each field plate connection hole pattern 102 satisfy that the pattern area close to the gate of the semiconductor substrate to be etched is greater than the pattern area far from the gate, so that at least two of the etching patterns of the field plate connection holes formed on the semiconductor substrate satisfy that the opening size of the etching pattern close to the gate is greater than the opening size of the etching pattern far from the gate, thereby enabling the depth of the field plate connection hole close to the gate to be greater than the depth of the field plate connection hole far from the gate.

[0184] Figure 12 Optionally, as shown in the figure, the pattern width of the field plate connection hole pattern 102 close to the gate part of the semiconductor substrate to be etched can be greater than the pattern width far from the gate part, so that in the etching pattern of the field plate connection hole formed on the semiconductor substrate, the width close to the gate part is greater than the width far from the gate part.

[0185] The area where the field plate connection hole pattern 102 and the LDMOS field plate connection hole pattern are located can be a light transmission area or a light shielding area, when the area where the pattern is located is a light transmission area, a positive photoresist can be used for photolithography, light transmits through the light transmission area to irradiate the photoresist, so that the irradiated part of the photoresist dissolves in the developing process, thereby forming the required etching pattern on the semiconductor substrate. When the area where the pattern is located is a light shielding area, a negative photoresist can be used, light cannot transmit through the light shielding area, the photoresist not irradiated dissolves in the developing process, thereby obtaining the corresponding etching pattern.

[0186] The specific pattern size and shape of the field plate connection hole pattern 102 in the embodiment correspond to the shape and size of the etching pattern in the first embodiment, and can be referred to the related description of the mask plate 100 for photolithography and the related description of the etching pattern in the first embodiment, which will not be described in detail here.

[0187] ​Although the present application is disclosed with reference to the preferred embodiments above, it is not intended to limit the present application, and any person skilled in the art who learns the present application can make possible changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims of the present application.

Claims

1. A method of fabricating an LDMOS, characterized by, The method comprises: providing a semiconductor substrate, forming at least one LDMOS device structure on the semiconductor substrate, the LDMOS device structure comprising at least a gate, a source region, a drain region and a drift region, a trench isolation region being arranged in the drift region; forming a first dielectric layer on the semiconductor substrate on which the LDMOS device structure is formed; forming at least one field plate connection hole penetrating through the first dielectric layer and extending into the trench isolation region; implanting N-type ions into the drift region at the bottom of the field plate connection hole; filling the field plate connection hole with a conductive substance to form a first field plate embedded in the trench isolation region; wherein the longitudinal depth of the formed field plate connection hole in the trench isolation region satisfies: the depth of the field plate connection hole in the trench isolation region near the gate is greater than the depth of the field plate connection hole in the trench isolation region far from the gate, and the N-type ions implanted into the drift region at the bottom of the part of the field plate connection hole with greater depth or the field plate connection hole with greater depth are more widely distributed and have greater concentration.

2. The method of claim 1, wherein, forming the field plate connection hole penetrating through the first dielectric layer and extending into the trench isolation region specifically comprises: forming the field plate connection hole simultaneously with the process of forming the connection hole above the LDMOS device structure using the same photomask.

3. The method of claim 1, wherein, forming the field plate connection hole penetrating through the first dielectric layer and extending into the trench isolation region specifically comprises: forming the field plate connection hole before or after the process of forming the connection hole above the LDMOS device structure using different photomasks.

4. The method according to claim 2 or 3, characterized in that, filling the field plate connection hole with a conductive substance comprises: filling the field plate connection hole simultaneously with filling the conductive substance in the connection hole above the LDMOS device structure using the same filling process.

5. The method according to any one of claims 1 to 3, characterized in that, the gate of the LDMOS device structure extends above the trench isolation region of the drift region to form a second field plate covering part of the trench isolation region.

6. The method of claim 1, wherein: the width of the field plate connection hole pattern near the gate is greater than the width of the field plate connection hole pattern far from the gate by a photolithography process to define the etching pattern; different etching depths at different positions are achieved by different etching rates of etching patterns of different sizes in the etching process.

7. The method of any one of claims 1-3, wherein, The field plate connection hole comprises two or more, and is arranged along the direction away from the gate.

8. The method of claim 7, wherein: the depth of the field plate connection hole near the gate extending into the trench isolation region is greater than the depth of the field plate connection hole far from the gate extending into the trench isolation region in at least two of the two or more field plate connection holes.

9. The method of claim 8, wherein, The depth of the field plate connection hole near the gate extending into the trench isolation region is greater than the depth of the field plate connection hole far from the gate extending into the trench isolation region in at least two of the two or more field plate connection holes, which is achieved by: the opening size of the field plate connection hole pattern near the gate is greater than the opening size of the field plate connection hole pattern far from the gate by a photolithography process to define the etching pattern; different etching depths of the field plate connection hole at different positions are achieved by different etching rates of etching patterns of different opening sizes in the etching process.

10. The method of claim 1 or 9, further comprising forming a connection structure electrically connecting the first field plate, through which an electric potential is applied to the first field plate.

11. The method of claim 10, wherein, The connection structure is electrically connected with the source electrode.

12. An LDMOS device, characterized by, Comprise: a semiconductor substrate, on which at least one LDMOS device structure is formed, the LDMOS device structure at least comprising a gate, a source region, a drain region and a drift region, and a trench isolation region is arranged in the drift region; a first dielectric layer is formed on the semiconductor substrate on which the LDMOS device structure is formed, the first dielectric layer is provided with at least one field plate connection hole penetrating into the trench isolation region, the drift region at the bottom of the field plate connection hole is implanted with N-type ions; the field plate connection hole is filled with a conductive substance to form a first field plate embedded in the trench isolation region; wherein the longitudinal depth of the field plate connection hole in the trench isolation region satisfies: The depth of the field plate connection hole in the trench isolation region near the gate side is greater than that far from the gate side, and the N-type ions implanted in the bottom drift region corresponding to the part of the field plate connection hole with deeper depth or the field plate connection hole with greater depth are more widely distributed and have greater concentration.

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