Transistor, chip, semiconductor device and electronic equipment

Abstract

The embodiment of the invention discloses a transistor, a chip, a semiconductor device and electronic equipment, the transistor comprises a source electrode, a drain electrode, a grid electrode, a gate oxide dielectric layer, a channel and an insertion layer, and the gate oxide dielectric layer is arranged between the grid electrode and the channel; the insertion layer is arranged in at least one of the following positions: a position between the source electrode and the channel, a position between the drain electrode and the channel or a position between the gate electrode and the gate oxide dielectric layer; the metal activity of the insertion layer is weaker than the metal activity of the source electrode, the drain electrode or the grid electrode in direct contact with the insertion layer. According to the embodiment of the invention, the stability of the transistor can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a transistor, a chip, a semiconductor device and an electronic device. BACKGROUND

[0002] With the development of Internet technology and cloud computing technology, the information age is rapidly changing to the big data era, making the demand for storage systems continue to rise. The growing amount of information makes storage chips play a very important role in the entire integrated circuit industry market. However, with the development of Moore's law, the gap between processors and memories is getting bigger and bigger. The growth rate of microprocessors far exceeds that of memories, resulting in a "memory wall" as the storage density and read-write speed of the memory cannot keep up with the operation speed of the processor, ultimately affecting the overall performance of the system. The stability of the transistor in the existing memory will affect the read-write speed of the memory, so how to improve the stability of the transistor is a problem to be solved. SUMMARY

[0003] The embodiments of the present application provide a transistor, a chip, a semiconductor device and an electronic device, which can improve the stability of the transistor.

[0004] In a first aspect, the embodiments of the present application provide a transistor, which includes a source, a drain, a gate, a gate oxide layer, a channel and an insertion layer; the insertion layer includes one or more of a first insertion layer, a second insertion layer and a third insertion layer; the first insertion layer is arranged between the source and the channel, the second insertion layer is arranged between the drain and the channel, and the third insertion layer is arranged between the gate and the gate oxide layer; the metal activity of the first insertion layer is weaker than that of the source, the metal activity of the second insertion layer is weaker than that of the drain, and the metal activity of the third insertion layer is weaker than that of the gate.

[0005] If the contact electrode uses active metal, and the channel or the gate oxide dielectric layer can have a redox reaction with the contact electrode during the transistor preparation process, such as during stress or annealing or oxide deposition, an interface metal oxide is formed, which affects the contact resistance, affects the ion movement, and reduces the stability of the transistor. At the same time, after the redox reaction of the channel, the oxygen element is missing, forming oxygen vacancies, and the carrier concentration rises, which also affects the stability of the transistor. Therefore, in the embodiments of the present application, an insertion layer (such as a first insertion layer or a second insertion layer) can be arranged between the channel and the contact electrode (such as the source or the drain), or an insertion layer (such as a third insertion layer) can be arranged between the gate oxide dielectric layer and the gate electrode. The metal activity of the insertion layer should be weaker than the metal activity of the source, the drain or the gate electrode in direct contact with the insertion layer, so that the insertion layer can inhibit the contact of the oxygen element in the channel or the gate oxide dielectric layer with the metal electrode, avoid the redox reaction between the channel or the gate oxide dielectric layer and the contact electrode, and thus improve the stability of the transistor.

[0006] In some embodiments, the material of the insertion layer is one or more of gallium oxide GaO, zinc oxide ZnO, indium oxide InOx, titanium dioxide TiO2, tungsten oxide WO3, molybdenum oxide MoO, aluminum oxide AlO, nickel Ni, palladium Pd, platinum Pt, silver Ag, and gold Au.

[0007] In the embodiments of the present application, the material of the insertion layer can be selected according to the metal activity of the source, the drain or the gate electrode in direct contact with the insertion layer, that is, the material of the first insertion layer can be selected according to the metal activity of the source, the material of the second insertion layer can be selected according to the metal activity of the drain, and the material of the third insertion layer can be selected according to the metal activity of the gate. In order to make the insertion layer inhibit the redox reaction between the channel, the gate oxide dielectric layer and the metal electrode, the metal activity of the insertion layer should be weaker than the metal activity of the source, the drain or the gate electrode in direct contact with the insertion layer, so as to improve the stability of the transistor. Therefore, the material of the insertion layer in the embodiments of the present application can be one or more of gallium oxide GaO, zinc oxide ZnO, indium oxide InOx, titanium dioxide TiO2, tungsten oxide WO3, molybdenum oxide MoO, aluminum oxide AlO, nickel Ni, palladium Pd, platinum Pt, silver Ag, and gold Au, which can be selected according to the metal activity of the source, the drain or the gate electrode in direct contact with the insertion layer.

[0008] In some embodiments, the thickness of the insertion layer is less than the thickness of the gate oxide dielectric layer.

[0009] In the embodiments of the present application, the thickness of the insertion layer is generally less than the thickness of the gate oxide dielectric layer, so as to avoid the influence of the excessive thickness of the insertion layer on the conductivity of the transistor.

[0010] In some embodiments, the thickness of the insertion layer is greater than or equal to 1 nanometer and less than or equal to 2 nanometers.

[0011] In the embodiments of the present application, in order to make the insertion layer inhibit the contact between the oxygen element in the channel or gate oxide medium layer and the metal electrode, the thickness of the insertion layer should be greater than or equal to 1 nanometer. Meanwhile, in order to prevent the insertion layer from being too thick, resulting in the transistor being too large in size and also affecting the conductivity of the transistor, the thickness of the insertion layer arranged between the source and the channel, between the drain and the channel, or between the gate and the gate oxide medium layer in the transistor is not more than 2 nanometers.

[0012] In some embodiments, the thicknesses of the first insertion layer, the second insertion layer and the third insertion layer are the same, or the thicknesses of at least one of the first insertion layer, the second insertion layer and the third insertion layer are different; the materials of the first insertion layer, the second insertion layer and the third insertion layer are the same, or the materials of at least one of the first insertion layer, the second insertion layer and the third insertion layer are different.

[0013] In the embodiments of the present application, the insertion layer between the source and the channel, the insertion layer between the drain and the channel, or the insertion layer between the gate and the gate oxide medium layer can be arranged with the same thickness or different thicknesses. Meanwhile, since the materials of the source, the drain and the gate can be the same or different, the material of the insertion layer in contact with the source, the drain or the gate can be selected according to the metal activity of the source, the drain or the gate, so as to ensure that the metal activity of the insertion layer is weaker than the metal activity of the electrode in direct contact with the insertion layer, and to inhibit the redox reaction between the channel or the gate oxide medium layer and the metal electrode, so as to improve the stability of the transistor.

[0014] In some embodiments, the gate, the gate oxide medium layer, the channel, the source and the drain are sequentially arranged along the vertical direction of the substrate of the transistor; the length of the gate along the substrate direction is equal to the length of the gate oxide medium layer, and the length of the channel is less than the length of the gate oxide medium layer; the source and the drain are spaced apart from each other and arranged in parallel; the source and the drain include first and second portions with different heights along the vertical direction of the substrate; one side of the bottom of the first portion is in contact with the gate oxide medium layer, and the insertion layer is arranged between the other side of the first portion close to the channel and the channel; the insertion layer is arranged between one side of the bottom of the second portion and the channel.

[0015] In the embodiment of the present application, the transistor of the back gate structure includes three ports of source, gate and drain and a channel, the material of the channel is oxide, and the materials of the source and the drain are active metals. In order to avoid the oxidation-reduction reaction of the oxygen element in the channel with the source and the drain respectively during the preparation process of the transistor of the back gate structure, an insertion layer is arranged on the surface of the channel which is in contact with the source and the drain respectively. Assuming that the insertion layer arranged between the channel and the source is a first insertion layer, and the insertion layer arranged between the channel and the drain is a second insertion layer, the metal activity of the first insertion layer should be weaker than the metal activity of the source metal, and the metal activity of the second insertion layer should be weaker than the metal activity of the drain metal. Further, the first insertion layer can inhibit the oxidation-reduction reaction of the channel with the source, and the second insertion layer can inhibit the oxidation-reduction reaction of the channel with the drain, thereby improving the stability of the transistor.

[0016] In some embodiments, an insertion layer is arranged between one side of the bottom of the first part and the gate oxide medium layer respectively.

[0017] In the embodiment of the present application, in order to avoid the oxidation-reduction reaction between the channel and the source and the drain during the preparation process of the transistor of the back gate structure, an insertion layer needs to be deposited on the channel and the exposed gate oxide medium layer before the source and the drain are deposited. In order to facilitate preparation, the surface of the source and the drain which is in contact with the gate oxide medium layer can also be provided with an insertion layer, so that the insertion layer deposited on the gate oxide medium layer does not need to be etched, and the source and the drain can be directly deposited after the deposition of the insertion layer, thereby simplifying the preparation process of the transistor.

[0018] In some embodiments, the transistor includes a third part and a fourth part, wherein the third part includes a source, an insulating layer and a drain which are arranged in the vertical direction of the substrate of the transistor in sequence; a first opening is arranged on the surface of the drain, and the first opening penetrates the drain and the insulating layer to expose the source at the bottom; the fourth part includes a channel, a gate oxide medium layer, an insertion layer and a gate; the gate includes a protruding part and a horizontal part, the insertion layer, the gate oxide medium layer and the channel are sequentially stacked on the surface of the protruding part and the horizontal part of the gate in the vertical direction of the substrate; the protruding part of the fourth part inserts the first opening of the third part, so that the channel of the fourth part is in contact with the source, the drain and the insulating layer of the third part respectively.

[0019] In the embodiments of the present application, the transistor of the vertical gate-all-around structure includes three ports of source, gate and drain and a channel, the material of the gate oxide dielectric layer is oxide, and the material of the gate is active metal. In order to avoid the oxidation-reduction reaction between the oxygen element in the gate oxide dielectric layer and the gate in the preparation process of the transistor of the vertical gate-all-around structure, a third insertion layer is arranged at the surface where the gate oxide dielectric layer and the gate are in contact with each other. The metal activity of the third insertion layer should be weaker than the metal activity of the gate metal. Further, the third insertion layer can inhibit the oxidation-reduction reaction between the gate oxide dielectric layer and the gate, thereby improving the stability of the transistor.

[0020] In some embodiments, an insertion layer is arranged between the drain and the channel in the third part, and / or an insertion layer is arranged between the source and the channel in the third part.

[0021] In the embodiments of the present application, the material of the channel is oxide, and the materials of the source and the drain are active metal. In order to avoid the oxidation-reduction reaction between the drain and the channel in the preparation process of the transistor of the vertical gate-all-around structure, an insertion layer can be arranged between the drain and the channel. The metal activity of the insertion layer should be weaker than the metal activity of the drain metal, thereby improving the stability of the transistor. In order to avoid the oxidation-reduction reaction between the source and the channel, an insertion layer can also be arranged between the source and the channel. The metal activity of the insertion layer should be weaker than the metal activity of the source metal, thereby further improving the stability of the transistor.

[0022] In a second aspect, the embodiments of the present application provide a transistor preparation method, which includes: preparing a source, a drain, a gate, a channel and a gate oxide dielectric layer; preparing an insertion layer; the insertion layer includes one or more of a first insertion layer, a second insertion layer and a third insertion layer; the first insertion layer is arranged between the source and the channel, the second insertion layer is arranged between the drain and the channel, and the third insertion layer is arranged between the gate and the gate oxide dielectric layer; the metal activity of the first insertion layer is weaker than that of the source, the metal activity of the second insertion layer is weaker than that of the drain, and the metal activity of the third insertion layer is weaker than that of the gate.

[0023] In some embodiments, the preparation of the source, the drain, the gate, the channel, the gate oxide dielectric layer and the insertion layer includes: sequentially depositing the gate, the gate oxide dielectric layer and the channel on the surface of the substrate of the transistor; etching both ends of the channel to expose part of the gate oxide dielectric layer; depositing the first insertion layer and the second insertion layer on the surface of the channel layer and the exposed gate oxide dielectric layer; depositing the source on the first insertion layer, and depositing the drain on the second insertion layer.

[0024] In some embodiments, the method for preparing the source electrode, the drain electrode, the gate electrode, the channel, the gate oxide layer and the insertion layer comprises: sequentially depositing the source electrode, the insulating layer and the drain electrode on the surface of the substrate of the transistor; etching the drain electrode and the insulating layer to form a first opening; wherein the first opening penetrates through the drain electrode and the insulating layer to expose the source electrode at the bottom; and sequentially depositing the channel, the gate oxide layer, the third insertion layer and the gate electrode on the inside of the first opening and the surface of the drain electrode.

[0025] In a third aspect, the embodiments of the present application provide a chip, which comprises the transistor according to any one of the first aspect.

[0026] In a fourth aspect, the embodiments of the present application provide a semiconductor device, which comprises the chip according to any one of the third aspect.

[0027] In a fifth aspect, the embodiments of the present application provide an electronic device, which comprises a circuit board and the semiconductor device according to any one of the fourth aspect, and the circuit board is electrically connected with the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A circuit schematic diagram of a 2T0C structure Gain-cell memory and a 3D schematic diagram of a vertical transistor structure are provided in the embodiments of the present application.

[0029] Figure 2 A cross-sectional view of a transistor is provided in the embodiments of the present application.

[0030] Figure 3 A schematic diagram of the thickness of an insertion layer is provided in the embodiments of the present application.

[0031] Figure 4 A structural schematic diagram of a back gate structure transistor is provided in the embodiments of the present application.

[0032] Figure 5 A structural schematic diagram of another back gate structure transistor is provided in the embodiments of the present application.

[0033] Figure 6 A structural schematic diagram of a vertical ring gate structure transistor is provided in the embodiments of the present application.

[0034] Figure 7 A structural schematic diagram of another vertical ring gate structure transistor is provided in the embodiments of the present application.

[0035] Figure 8 A structural schematic diagram of another vertical ring gate structure transistor is provided in the embodiments of the present application.

[0036] Figure 9A step flow chart of a back gate structure transistor manufacturing method is provided for the embodiment of the present application.

[0037] Figure 10 A back gate structure transistor manufacturing flow chart is provided for the embodiment of the present application.

[0038] Figure 11 A step flow chart of a vertical ring gate structure transistor manufacturing method is provided for the embodiment of the present application.

[0039] Figure 12 A vertical ring gate structure transistor manufacturing flow chart is provided for the embodiment of the present application.

[0040] Figure 13 Another vertical ring gate structure transistor manufacturing flow chart is provided for the embodiment of the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application will be described below with reference to the drawings.

[0042] The terms “first”, “second”, “third”, and “fourth” and the like in the description and claims of the present application and the accompanying drawings are used to distinguish different objects, and are not used to describe a particular order. In addition, the terms “include” and “have” and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include other steps or units not listed or can optionally include other steps or units inherent to the process, method, product or device.

[0043] It should be understood that in the present application, “at least one” refers to one or more, and “multiple” refers to two or more. “And / or” is used to describe the association between the associated objects, which means that there can be three relationships, for example, “A and / or B” can represent three cases: only A, only B, and A and B at the same time, where A and B can be singular or plural. The character “ / ” generally represents an “or” relationship between the associated objects. “At least one of the following” or similar expressions means any combination of these items, including single or multiple combinations of any combination. For example, at least one of a, b or c can represent: a, b, c, “a and b”, “a and c”, “b and c”, or “a and b and c”, where a, b, and c can be single or multiple.

[0044] Reference to“an embodiment” herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase“in one embodiment” in various places in the specification are not necessarily referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is appreciated that embodiments described herein can be combined with other embodiments unless explicitly stated otherwise.

[0045] First, in order to facilitate the understanding of the embodiments of the present application, the technical problems to be solved by the embodiments of the present application and the application scenarios are specifically analyzed as follows.

[0046] Gain-cell memory is a storage cell used for embedded dynamic random access memory (eDRAM) to store data in memory. eDRAM is a memory technology designed to provide high-density and small-area storage solutions. The design of Gain-cell memory aims to solve the data retention time limitation of eDRAM and provide higher area efficiency and bit density.

[0047] Among them, the read speed of the Gain-cell memory with 2T0C structure can be as low as nanosecond level, and its area occupation is only one third of that of static random access memory (SRAM). It is composed of two transistors (2T) and zero capacitance (0C). However, due to the leakage phenomenon of the transistor inside the storage cell, it is necessary to refresh every certain period of time to maintain the integrity of the data in actual application, which brings great dynamic power consumption. Therefore, people use ultra-low leakage thin film transistor (TFT) as the transistor in the 2T0C structure, which greatly reduces the dynamic power consumption and improves the storage market. At the same time, by using the advantages of low process temperature of TFT, compatible with traditional microelectronic process, etc., the storage cell can be applied to the back end of line (BEOL), realizing hetero-integration and stacked integration, and improving the storage density.

[0048] Please refer to Figure 1 , Figure 1A circuit schematic diagram of a 2T0C structure Gain-cell memory and a 3D schematic diagram of a vertical transistor structure are provided for embodiments of the present application. In order to improve the retention time of the 2T0C structure memory, TFT is used to replace the transistor in the memory, and the channel selection of the transistor has extremely low leakage of amorphous metal oxide, such as indium gallium zinc oxide (IGZO), or other wide band gap materials, etc. The working principle of the 2T0C structure Gain-cell memory is shown in (a) of Figure 1 , which consists of two transistors, namely a write transistor (WTR) and a read transistor (RTR). One end of the WTR is connected to a write word line (WWL), one end is connected to a write bit line (WBL), and the other end is connected to one end of the RTR. One end of the RTR is connected to a read word line (RWL), and one end of the RTR is connected to a read bit line (RBL). First, in the "write" operation, the WTR is controlled to be turned on by the WWL, and the potential of the WBL is transmitted to the gate of the RTR, so that the gate potential of the RTR is synchronized with the WBL to realize the writing of "0" and "1". Second, the WWL controls the WTR to be turned off, and the gate potential of the RTR is determined by the amount of electricity stored in the node. Since the leakage of TFT is much lower than that of silicon transistor, the current on the gate of RTR is greatly reduced through the leakage of WTR, which greatly improves the storage time of the memory. In the "read" operation, only the current of the RTR needs to be read, and then the storage state can be judged according to the high and low of the current.

[0049] It should be noted that the 2T0C structure memory based on planar devices needs to be multi-layered, and the preparation process is complex, the area utilization rate is low, and it is difficult to realize high integration density of the storage array. In order to solve this problem, the 2T0C storage unit with vertical transistor structure emerges as the times require, as shown in (b) of Figure 1 , the occupied area of each storage unit is close to 4F 2With the development of Moore's Law, in order to further improve the storage density, a 3D 1T1C memory array can be prepared by a back-end transistor stacking method, which requires that the channel material of the transistor can be prepared in a low-temperature environment, and the oxide semiconductor material is the best choice. If the contact electrode uses an active metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), etc., and the channel or gate oxide dielectric layer may have a redox reaction with the contact electrode during the transistor preparation process, such as during stress or annealing or oxide deposition, an interface metal oxide is formed, which affects the contact resistance, ion movement, and transistor stability. At the same time, after the redox reaction of the metal oxide, oxygen vacancies are formed, the carrier concentration rises, and the transistor reliability and threshold voltage are affected.

[0050] Therefore, by implementing the transistor provided by the embodiments of the present application, the transistor can be applied to various memories composed of transistors. By providing an insertion layer between the channel and the electrode, or providing an insertion layer between the gate oxide dielectric layer and the electrode, the redox reaction between the channel material, the gate oxide dielectric layer material and the contact electrode is avoided, the stability of the transistor is improved, and the read / write speed of the memory is improved. The specific implementation can be referred to in the following embodiments, and the embodiments of the present application will not be described here.

[0051] Secondly, based on the above-mentioned technical problems, in order to facilitate understanding of the embodiments of the present application, the transistor based on the embodiments of the present application will be described first.

[0052] The embodiments of the present application provide a transistor, which is a field effect transistor, comprising a source, a drain, a gate, a gate oxide dielectric layer, a channel and an insertion layer. The insertion layer is arranged at least one of the following positions: between the source and the channel, between the drain and the channel, or between the gate and the gate oxide dielectric layer. It can be understood that the insertion layer includes one or more of a first insertion layer, a second insertion layer and a third insertion layer; wherein the first insertion layer is arranged between the source and the channel, the second insertion layer is arranged between the drain and the channel, and the third insertion layer is arranged between the gate and the gate oxide dielectric layer; the metal activity of the first insertion layer is weaker than that of the source, the metal activity of the second insertion layer is weaker than that of the drain, and the metal activity of the third insertion layer is weaker than that of the gate.

[0053] For example, please refer to Figure 2 , Figure 2 is a cross-sectional view of a transistor provided by the embodiments of the present application. As Figure 2As shown, transistor 10 includes a source 101, a drain 102, a gate 103, a channel 104, a gate oxide dielectric layer 105, and an insertion layer 106. In this example, the insertion layer 106 is disposed between the source 101 and the channel 104, between the drain 102 and the channel 104, and between the gate 103 and the gate oxide dielectric layer 105. It should be noted that in the cross-sectional views of the transistor in this application embodiment and the following related embodiments, the substrate is located below the transistor, can be electrically connected to the transistor, and serves to support the transistor.

[0054] like Figure 2 As shown, in the structure of the transistor 10 provided in this application, the X-axis direction is parallel to the substrate direction (i.e., the left-right direction), and the Y-axis direction is perpendicular to the substrate direction (i.e., the up-down direction). Along the X-axis direction is the width direction of the source 101, drain 102, gate 103, channel 104, gate oxide layer 105, and insertion layer 106; along the Y-axis direction is the thickness direction of the source 101, drain 102, gate 103, channel 104, gate oxide layer 105, and insertion layer 106. Furthermore, the cross-sectional views of the transistors and other related devices in this application and the following related embodiments are also applicable. Figure 2 The coordinate system shown (X-axis and Y-axis).

[0055] Next, with Figure 2 Taking the transistor 10 shown as an example, this application describes the transistor involved in the embodiments.

[0056] Transistor 10 includes a source 101, a drain 102, and a gate 103. The source 101, gate 103, and drain 102 can be arranged horizontally at intervals along the X-axis, or they can be arranged in other ways. Figure 2 This example only illustrates one configuration. Source 101, drain 102, and gate 103 are three important pins in a field-effect transistor (FET). Source 101 is the pin through which charge carriers (i.e., charge carriers) enter channel 104; drain 102 is the pin through which charge carriers leave channel 104; and gate 103 controls the conductivity between source 101 and drain 102. The voltage at gate 103 controls the flow of charge carriers in channel 104, thereby controlling the current between source 101 and drain 102.

[0057] Optionally, the source 101, drain 102 and gate 103 can be made of metallic or conductive materials, such as titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide (In-Ti-O (ITO)), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag) or any combination thereof.

[0058] The transistor 10 also includes a channel 104, which is a pathway formed after a voltage is applied to the gate 103, allowing charge carriers to flow between the source 101 and the drain 102, thereby controlling the conductivity of the transistor 10. When the gate 103 applies an appropriate voltage, the channel 104 is formed, allowing current to flow through the transistor 10.

[0059] In some embodiments, the material of the channel 104 can be a metal oxide, such as an amorphous metal oxide.

[0060] The transistor 10 also includes a gate oxide layer 105, which can be in contact with the gate 103, serving as an insulating barrier to prevent current flow between the gate 103 and the channel 104, ensuring the proper functioning of the transistor.

[0061] Optionally, the material of the gate oxide layer 105 can be an insulating material, such as silicon dioxide SiO2, aluminum oxide Al2O3, hafnium oxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, yttrium trioxide Y2O3, silicon nitride Si3N4, or any combination of these materials, or a stack structure of these materials.

[0062] The transistor 10 also includes an insertion layer 106, which can be disposed between at least one of the source 101 and the channel 104, the drain 102 and the channel 104, or the gate 103 and the gate oxide layer 105, such as the second insertion layer 1061 disposed between the drain 102 and the channel 104, the third insertion layer 1062 disposed between the gate 103 and the gate oxide layer 105, and the first insertion layer 1063 disposed between the source 101 and the channel 104. The metal reactivity of the insertion layer 106 should be weaker than that of the source 101, the drain 102, or the gate 103, which are in direct contact with the insertion layer 106, thereby preventing the oxygen elements in the channel 104 or the gate oxide layer 105 from coming into contact with the metal electrodes (source 101, drain 102, or gate 103), avoiding redox reactions between the channel 104 or the gate oxide layer 105 and the contact electrodes, and thereby improving the stability of the transistor.

[0063] In some embodiments, the material of the insertion layer 106 can be a metal or a metal oxide, such as one or more of gallium oxide GaO, zinc oxide ZnO, indium oxide InOx, titanium dioxide TiO2, tungsten oxide WO3, molybdenum oxide MoO, aluminum oxide AlO, nickel Ni, palladium Pd, platinum Pt, silver Ag, or gold Au.

[0064] Specifically, the material of the insertion layer 106 can be selected according to the metal activity of the source electrode 101, the drain electrode 102 or the gate electrode 103 directly contacting the insertion layer 106, that is, the material of the first insertion layer 1063 can be selected according to the metal activity of the source electrode 101, the material of the second insertion layer 1061 can be selected according to the metal activity of the drain electrode 102, and the material of the third insertion layer 1062 can be selected according to the metal activity of the gate electrode 103. In order to inhibit the redox reaction between the channel 104, the gate oxide layer 105 and the metal electrode by the insertion layer 106, the metal activity of the insertion layer 106 should be weaker than the metal activity of the source electrode 101, the drain electrode 102 or the gate electrode 103 directly contacting the insertion layer 106, so as to improve the stability of the transistor. For example, the metal activity of the second insertion layer 1061 should be weaker than the metal activity of the drain electrode 102, the metal activity of the third insertion layer 1062 should be weaker than the metal activity of the gate electrode 103, and the metal activity of the first insertion layer 1063 should be weaker than the metal activity of the source electrode 101. It can be understood that the weaker the metal activity of the insertion layer 106, the less likely the insertion layer 106 reacts with oxygen elements. Therefore, the material of the insertion layer 106 in the embodiments of the present application can be selected from one or more of gallium oxide GaO, zinc oxide ZnO, indium oxide InOx, titanium dioxide TiO2, tungsten oxide WO3, molybdenum oxide MoO, aluminum oxide AlO, nickel Ni, palladium Pd, platinum Pt, silver Ag and gold Au according to the metal activity of the source electrode 101, the drain electrode 102 or the gate electrode 103 directly contacting the insertion layer 106.

[0065] In some embodiments, the metal activity of the metal elements is arranged in descending order as follows: cesium (Cs), rubidium (Rb), potassium (K), radium (Ra), barium (Ba), strontium (Sr), calcium (Ca), sodium (Na), lithium (Li), actinium (Ac), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), yttrium (Y), magnesium (Mg), dysprosium (Dy), americium (Am), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), scandium (Sc), plutonium (Pu), thorium (Th), neptunium (Np), beryllium (Be), uranium (U), hafnium (Hf), aluminum (Al), titanium (Ti), zirconium (Zr), vanadium (V), manganese (Mn), niobium (Nb), zinc (Zn), chromium (Cr), gallium (Ga), iron (Fe), cadmium (Cd), indium (In), thallium (Tl), cobalt (Co), nickel (Ni), molybdenum (Mo), tin (Sn), lead (Pb), copper (Cu), technetium (Tc), polonium (Po), mercury (Hg), silver (Ag), rhodium (Rh), palladium (Pd), platinum (Pt), gold (Au).

[0066] For example, assuming the material of the source electrode 101 is molybdenum Mo, according to the above-mentioned metal activity order, it can be determined that the material of the first insertion layer 1063 can be composed of one or more metal elements after molybdenum Mo, for example, the material of the first insertion layer can be silver Ag.

[0067] For example, assuming the material of the drain electrode 102 is titanium nitride TiN, according to the above-mentioned metal activity order, it can be determined that the material of the second insertion layer 1061 can be composed of one or more metal elements after titanium Ti, for example, the material of the second insertion layer can be gallium oxide GaO.

[0068] For example, assuming the material of the gate electrode 103 is aluminum Al, according to the above-mentioned metal activity order, it can be determined that the material of the third insertion layer 1062 can be composed of one or more metal elements after aluminum Al, for example, the material of the third insertion layer can be nickel Ni.

[0069] In some embodiments, the material of any one or more of the source electrode 101, the drain electrode 102 and the gate electrode 103 can be composed of one metal element or multiple metal elements. If composed of multiple metal elements, the material of the corresponding insertion layer is determined based on the metal element with the lowest metal activity among the multiple metal elements. For example, assuming the material of the source electrode 101 is composed of aluminum Al and molybdenum Mo, the metal activity of molybdenum Mo is lower than that of aluminum Al, according to the above-mentioned metal activity order, it can be determined that the material of the first insertion layer 1063 can be composed of one or more metal elements after molybdenum Mo, for example, the material of the first insertion layer 1063 can be silver Ag.

[0070] In some embodiments, the thickness of the insertion layer 106 is less than the thickness of the gate oxide layer 105.

[0071] Specifically, the thickness of the gate oxide layer 105 is generally set to 10 nanometers. The thickness of the insertion layer 106 is generally less than the thickness of the gate oxide layer 105, so as to avoid affecting the conductivity of the transistor 10 due to the excessive thickness of the insertion layer 106.

[0072] In some embodiments, the thickness of the insertion layer 106 is greater than or equal to 1 nanometer and less than or equal to 2 nanometers.

[0073] Specifically, please refer to Figure 3 , Figure 3 A schematic diagram of the thickness of the insertion layer provided by the embodiments of the present application is shown in (a) of FIG. 1. Figure 3 In (a) of FIG. 1, it is assumed that the second insertion layer 1061 is arranged between the drain electrode 102 and the channel 104, and the thickness h1 of the second insertion layer 1061 along the Y-axis direction perpendicular to the substrate direction of the transistor 10 (i.e., the up-down direction) is greater than or equal to 1 nanometer and less than or equal to 2 nanometers. Figure 3(b) of the above assumes that a third insertion layer 1062 is provided between the gate 103 and the gate oxide layer 105, and the thickness h2 of the third insertion layer 1062 in the Y-axis direction perpendicular to the substrate direction (i.e., the up-down direction) of the transistor 10 is greater than or equal to 1 nm and less than or equal to 2 nm. Figure 3 (c) of the above assumes that a first insertion layer 1063 is provided between the source 101 and the channel 104, and the thickness h3 of the first insertion layer 1063 in the Y-axis direction perpendicular to the substrate direction (i.e., the up-down direction) of the transistor 10 is greater than or equal to 1 nm and less than or equal to 2 nm. In order to prevent the insertion layer 106 from coming into contact with oxygen elements in the channel 104 or the gate oxide layer 105 and the metal electrode (the source 101, the drain 102, or the gate 103), the thickness of the insertion layer 106 should be greater than or equal to 1 nm. Meanwhile, in order to prevent the insertion layer 106 from being too thick, which would make the transistor 10 too large in volume and also affect the conductivity of the transistor 10, the thickness of the insertion layer provided between the source 101 and the channel 104, between the drain 102 and the channel 104, or between the gate 103 and the gate oxide layer in the transistor 10 is not more than 2 nm.

[0074] In some embodiments, the thicknesses of the insertion layers 106 at different positions are the same or different; the materials of the insertion layers 106 at different positions are the same or different, i.e., the thicknesses of the first insertion layer, the second insertion layer, and the third insertion layer are the same, or the thicknesses of at least one of the first insertion layer 1063, the second insertion layer 1061, and the third insertion layer 1062 are different; the materials of the first insertion layer 1063, the second insertion layer 1061, and the third insertion layer 1062 are the same, or the materials of at least one of the first insertion layer 1063, the second insertion layer 1061, and the third insertion layer 1062 are different.

[0075] Specifically, refer to Figure 3 , Figure 3 (a) of the above assumes that a second insertion layer 1061 is provided between the drain 102 and the channel 104, and the metal reactivity of the second insertion layer 1061 should be weaker than that of the drain 102; Figure 3 (b) of the above assumes that a third insertion layer 1062 is provided between the gate 103 and the gate oxide layer 105, and the metal reactivity of the third insertion layer 1062 should be weaker than that of the gate 103; Figure 3The (c) in the above formula assumes that a first insertion layer 1063 is arranged between the source 101 and the gate oxide layer 105, and the metal lability of the first insertion layer 1063 should be weaker than that of the source 101. The first insertion layer 1063 between the source 101 and the channel 104, the second insertion layer 1061 between the drain 102 and the channel 104, or the third insertion layer 1062 between the gate 103 and the gate oxide layer 105 can be arranged with the same thickness or different thickness, i.e., h1, h2 and h3 can be equal or not equal, as long as they are between 1-2 nanometers. At the same time, since the materials of the source 101, the drain 102 and the gate 103 can be the same or different, the material of the insertion layer 106 in contact with the source 101, the drain 102 or the gate 103 can be selected according to the metal lability of the source 101, the drain 102 or the gate 103, so as to ensure that the metal lability of the insertion layer 106 is weaker than that of the source 101, the drain 102 or the gate 103 in direct contact with the insertion layer 106, and to inhibit the redox reaction between the channel 104 or the gate oxide layer 105 and the metal electrode, so as to improve the stability of the transistor.

[0076] Next, taking the transistor 10 shown in the above formula as an example, a transistor with a back gate structure provided by an embodiment of the present application is introduced. Figure 4

[0077] Please refer to Figure 4 , Figure 4 FIG. 1 is a structural schematic diagram of a transistor with a back gate structure provided by an embodiment of the present application. The gate 103, the gate oxide layer 105, the channel 104, the source 101 and the drain 102 are sequentially arranged in the vertical direction (i.e., the Y-axis direction) of the substrate of the transistor 10. It should be noted that the thickness of the gate 103, the gate oxide layer 105, the channel 104, the source 101 and the drain 102 in the Y-axis direction is not limited in the present application.

[0078] The length of the gate 103 in the direction of the substrate (i.e., the X-axis direction) is equal to the length of the gate oxide layer 105, i.e., the gate 103 and the gate oxide layer 105 are arranged with the same length in the stacking direction, so as to avoid the contact between the gate 103 and the channel 104, the source 101 or the drain 102, which causes the transistor 10 to fail to work normally.

[0079] The length of the channel 104 is less than the length of the gate oxide layer 105. Optionally, the channel 104 is located in the middle of the gate oxide layer 105, and the left and right sides of the channel 104 respectively expose part of the gate oxide layer 105.

[0080] ​The source electrode 101 and the drain electrode 102 are spaced apart from each other and arranged in parallel. The source electrode 101 and the drain electrode 102 include a first part and a second part that are different in height in the vertical direction of the substrate (i.e., along the Y axis). One side of the bottom of the first part is in contact with the gate oxide layer 105, and one side of the first part close to the channel 104 is provided with an insertion layer 106, i.e., the insertion layer 10612 in Figure 4 , the insertion layer 10622. One side of the bottom of the second part is provided with an insertion layer 106, i.e., the insertion layer 10611 in Figure 4 , the insertion layer 10621.

[0081] In the above embodiment, the transistor 10 of the back gate structure includes a source electrode 101, a gate electrode 103, and a drain electrode 102, and a channel 104. The material of the channel 104 is a metal oxide, and the material of the source electrode 101 and the drain electrode 102 is an active metal. In order to avoid the redox reaction of the oxygen element in the channel 104 with the source electrode 101 and the drain electrode 102 during the preparation process of the transistor 10 of the back gate structure, an insertion layer 106 is arranged on the surface where the channel 104 is in contact with the source electrode 101 and the drain electrode 102. Assuming that the insertion layer 106 arranged between the channel 104 and the source electrode 101 is a third insertion layer 1062, and the insertion layer 106 arranged between the channel 104 and the drain electrode 102 is a second insertion layer 1061. The metal activity of the third insertion layer 1062 should be weaker than the metal activity of the source electrode 101, and the metal activity of the second insertion layer 1061 should be weaker than the metal activity of the drain electrode 102. Further, the third insertion layer 1062 can inhibit the redox reaction between the channel 104 and the source electrode 101, and the second insertion layer 1061 can inhibit the redox reaction between the channel 104 and the drain electrode 102, thereby improving the stability of the transistor 10.

[0082] In some embodiments, please refer to Figure 5 , Figure 5 , another structure schematic diagram of a transistor of a back gate structure provided by the embodiments of the present application, Figure 5 , the insertion layer 10613 in Figure 5 , the insertion layer 10623.

[0083] Specifically, during the fabrication of the back-gate structure transistor 10, the gate 103, gate oxide layer 105, channel 104, source 101, and drain 102 are deposited sequentially. After the channel 104 is deposited, it needs to be etched so that the length of the channel 104 is less than the length of the gate oxide layer 105. Therefore, the subsequently deposited source 101 and drain 102 will contact the channel 104 and the gate oxide layer 105. To avoid redox reactions between the channel 104 and the source 101 and drain 102, an insertion layer 106 needs to be deposited on the channel 104 and the exposed gate oxide layer 105 before depositing the source 101 and drain 102. For ease of fabrication, the side of the source 101 and drain 102 that contacts the gate oxide layer 105 can also have the insertion layer 106, i.e. Figure 5 The insertion layers 10613 and 10623 in the transistor do not require etching of the insertion layer 106 deposited on the gate oxide dielectric layer 105. The source 101 and drain 102 can be deposited directly after the insertion layer 106 is deposited, which simplifies the fabrication process of the transistor 10.

[0084] Optionally, the positions of source 101 and drain 102 can be interchanged.

[0085] Optionally, in the back-gate structure transistor 10, an insertion layer may also be provided between the gate 103 and the gate oxide dielectric layer 105 to suppress the redox reaction between the gate oxide dielectric layer 105 and the gate 103, thereby improving the stability of the transistor 10.

[0086] Next, with Figure 6 Taking the transistor 10 shown as an example, this application introduces a transistor with a vertical ring gate structure.

[0087] like Figure 6 As shown, Figure 6 This is a schematic diagram of a vertical ring gate structure transistor provided in an embodiment of this application. The transistor 10 includes a third part and a fourth part.

[0088] The third part includes a source 101, an insulating layer 107, and a drain 102, which are sequentially stacked along the vertical direction (i.e., the Y-axis direction) of the substrate of transistor 10. The insulating layer 107 is used to suppress the source 101 and the drain 102. Optionally, the source 101 and the drain 102 can be interchanged. A first opening is provided on the surface of the drain 102, and the first opening penetrates the drain 102 and the insulating layer 107 until the source 101 is exposed at the bottom.

[0089] Optionally, the first opening may penetrate through the drain 102 and the insulating layer 107 and part of the source 101 until part of the source 101 is exposed at the bottom.

[0090] The fourth part includes a channel 104, a gate oxide dielectric layer 105, an insertion layer 106, and a gate 103. The gate 103 includes a raised portion and a horizontal portion. The insertion layer 106, the gate oxide dielectric layer 105, and the channel 104 are sequentially stacked on the surfaces of the raised portion and the horizontal portion of the gate 103 in a direction perpendicular to the substrate (i.e., along the Y-axis direction).

[0091] The protrusion of the fourth part is inserted into the first opening of the third part, so that the channel 104 of the fourth part contacts the source 101, drain 102 and insulating layer 107 of the third part respectively.

[0092] Optional, please see Figure 7 , Figure 7 This is a schematic diagram of another vertical ring gate structure transistor provided in an embodiment of this application. The third part may include two insulating layers, namely... Figure 7 The insulating layers 1071 and 1072 are provided. Insulating layer 1071 is disposed between the source electrode 101 and the drain electrode 102, and insulating layer 1072 is disposed above the drain electrode 102. Insulating layer 1072 can be used to prevent the drain electrode 102 from directly contacting the channel 104 of the fourth part.

[0093] In the above embodiment, the vertical ring gate transistor 10 includes three ports: a source 101, a gate 103, and a drain 102, and a channel 104. The gate oxide dielectric layer 105 is made of metal oxide, and the gate 103 is made of an active metal. To prevent the oxygen element in the gate oxide dielectric layer 105 from reacting with the gate 103 during the fabrication of the vertical ring gate transistor 10, an insertion layer 106 is provided on the surface where the gate oxide dielectric layer 105 and the gate 103 are in contact. The metal reactivity of the insertion layer 106 should be weaker than that of the metal in the gate 103. Therefore, the insertion layer 106 can suppress the redox reaction between the gate oxide dielectric layer 105 and the gate 103, thereby improving the stability of the transistor 10.

[0094] In some embodiments, see Figure 8 , Figure 8 This is a schematic diagram of another vertical ring gate structure transistor provided in an embodiment of this application. Figure 8 A third insertion layer 1062 is provided between the drain 102 and the channel 104 in the third part, and / or a second insertion layer 1061 is provided between the source 101 and the channel 104 in the third part.

[0095] Specifically, the material of the channel 104 is metal oxide, and the materials of the source 101 and the drain 102 are active metals. In order to avoid the redox reaction between the drain 102 and the channel 104 in the preparation process of the vertical gate-all-around transistor 10, a third interlayer 1062 can be arranged between the drain 102 and the channel 104. The metal activity of the third interlayer 1062 should be weaker than the metal activity of the drain 102, so as to improve the stability of the transistor. At the same time, in order to avoid the redox reaction between the source 101 and the channel 104, a first interlayer 1063 can also be arranged between the source 101 and the channel 104. The metal activity of the first interlayer 1063 should be weaker than the metal activity of the source 101, so as to further improve the stability of the transistor 10.

[0096] In summary, in the embodiments of the present application, the oxide is used as the material of the channel 104 or the material of the gate oxide dielectric layer 105. If the active metal is used as the contact electrode (the source 101, the drain 102 or the gate 103), the redox reaction may occur between the channel 104 or the gate oxide dielectric layer 105 and the contact electrode in the preparation process of the transistor, such as in the stress or annealing or oxide deposition process, so as to form the interface metal oxide, thereby affecting the contact resistance, affecting the ion movement and reducing the stability of the transistor. At the same time, after the redox reaction of the channel 104, the oxygen element is lost to form the oxygen vacancy, and the carrier concentration rises, which also affects the stability of the transistor 10. Therefore, in the embodiments of the present application, the interlayer can be arranged between the channel 104 and the electrode, or the interlayer can be arranged between the gate oxide dielectric layer 105 and the gate 103. The interlayer can inhibit the contact between the oxygen element in the channel or the gate oxide dielectric layer and the metal electrode, avoid the redox reaction between the channel or the gate oxide dielectric layer and the contact electrode, and improve the stability of the transistor.

[0097] The embodiments of the present application provide a transistor preparation method, which comprises: preparing a source, a drain, a gate, a channel, a gate oxide dielectric layer; preparing an interlayer; the interlayer comprises one or more of a first interlayer, a second interlayer and a third interlayer.

[0098] The first interlayer is arranged between the source and the channel, the second interlayer is arranged between the drain and the channel, and the third interlayer is arranged between the gate and the gate oxide dielectric layer. The metal activity of the first interlayer is weaker than that of the source, the metal activity of the second interlayer is weaker than that of the drain, and the metal activity of the third interlayer is weaker than that of the gate.

[0099] The embodiments of the present application are based on the above Figure 5 The embodiments of the present application provide a back gate structure transistor and a manufacturing method thereof.

[0100] Please refer toFigure 9 , Figure 9 A flowchart illustrating the steps of a back-gate structure transistor fabrication method provided in this application embodiment, the method comprising:

[0101] Step S1: Deposit a gate layer on the substrate surface.

[0102] Optional, such as Figure 10 As shown in (1), the material of the gate 103 can be a metallic material or a conductive material, such as titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, indium tin oxide In-Ti-O (ITO), aluminum Al, copper Cu, ruthenium Ru, silver Ag, or any combination thereof.

[0103] Optionally, the substrate material may include one of the following: bulk silicon, SOI, germanium, germanium silicon, gallium nitride, and indium gallium arsenide.

[0104] Optionally, the length of the gate 103 can be L1 along the direction parallel to the substrate.

[0105] Step S2: Deposit a gate oxide dielectric layer on the surface of the gate layer.

[0106] Optional, such as Figure 10 As shown in (2), the gate oxide dielectric layer 105 can be made of insulating materials, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2), yttrium oxide (Y2O3), silicon nitride (Si3N4), or any combination of these materials, stacked structures, and stacked structures of combined materials.

[0107] Optionally, the length of the gate oxide dielectric layer 105 is also L1 along the direction parallel to the substrate.

[0108] Step S3: Deposit a channel layer on the surface of the gate oxide dielectric layer.

[0109] Optional, such as Figure 10 As shown in (3), the material of the channel 104 can be a metal oxide, such as an amorphous metal oxide.

[0110] Step S4: Etch both ends of the channel layer to expose part of the gate oxide dielectric layer at both ends of the channel layer.

[0111] Optional, such as Figure 10 As shown in (4) in the figure, the length of the channel 104 along the direction parallel to the substrate is also L2, and L2 is less than L1.

[0112] Step S5: Deposit a first insertion layer and a second insertion layer on the surface of the channel layer and the exposed gate oxide dielectric layer.

[0113] Optional, such asFigure 10 As shown in (5), the material of the insertion layer 106 (including the first insertion layer 1063 and the second insertion layer 1061) is one or more of the following: calcium oxide GaO, zinc oxide ZnO, stainless steel InOx, titanium dioxide TiO2, tungsten oxide WO3, molybdenum oxide MoO, aluminum oxide AlO, nickel Ni, palladium Pd, platinum Pt, silver Ag, and gold Au.

[0114] Step S6: Deposit a source electrode on the first insertion layer and deposit a drain electrode on the second insertion layer.

[0115] Optional, such as Figure 10 As shown in (6), the source electrode 101 and the drain electrode 102 can be made of metallic materials or conductive materials, such as titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, indium tin oxide In-Ti-O (ITO), aluminum Al, copper Cu, ruthenium Ru, silver Ag, etc., or any combination thereof.

[0116] It should be noted that the back-gate structure transistor involved in the fabrication method of the back-gate structure transistor in the embodiments of this application can also refer to the above-described method. Figures 4-5 The example shown.

[0117] Please see Figure 11 , Figure 11 A flowchart illustrating the steps of a method for fabricating a vertical ring gate structure transistor, as provided in this application embodiment, includes:

[0118] Step S1: Deposit a source electrode on the substrate surface.

[0119] Specifically, such as Figure 12 As shown in (1), a source electrode 101 can be deposited on the substrate surface.

[0120] Step S2: An insulating layer is deposited on the source surface.

[0121] Specifically, such as Figure 12 As shown in (2), an insulating layer 107 is deposited on the source electrode 101, such that the source electrode 101 and the insulating layer 107 are stacked.

[0122] Step S3: Deposit a drain electrode on the surface of the insulating layer.

[0123] Specifically, such as Figure 12 As shown in (3), a drain 102 is deposited on the insulating layer 107, such that the source 101, the insulating layer 107 and the drain 102 are stacked.

[0124] Step S4: Etch and drill holes in the drain and insulating layer to form the first opening, thus obtaining the third part.

[0125] Specifically, such asFigure 12 etching and hole digging of the drain 102 and the insulating layer 107 to form a first opening, the first opening penetrating the drain 102 and the insulating layer 107 to expose the source 101.

[0126] Step S5, depositing a channel on the third part surface.

[0127] Specifically, depositing a channel on the inside of the first opening and the drain surface, as shown in (5) of FIG. 1C. Figure 12

[0128] Step S6, depositing a gate oxide dielectric layer on the channel surface.

[0129] Specifically, as shown in (6) of FIG. 1D, depositing a gate oxide dielectric layer 105 on the channel 104 surface. Figure 12

[0130] Step S7, depositing a third insertion layer on the gate oxide dielectric layer surface.

[0131] Specifically, as shown in (7) of FIG. 1E, in order to avoid redox reaction between the gate 103 and the gate oxide dielectric layer 105, depositing a third insertion layer on the gate oxide dielectric layer 105 surface. Figure 12 Step S8, depositing a gate on the third insertion layer surface.

[0132] Specifically, as shown in (8) of FIG. 1F, depositing a gate 103 on the insertion layer 106 (i.e. the third insertion layer) surface.

[0133] Figure 13 In some embodiments, after step S3, an insulating layer 107 can also be deposited on the drain 102.

[0134] In some embodiments, as shown in (9) of FIG. 1G,

[0135] Another vertical ring gate structure transistor manufacturing process flow diagram provided by the embodiments of the present application. After step S8, the drain 102 can also be etched to form a structure as shown in (9) of FIG. 1G, and then an insertion layer 106 is deposited between the drain 102 and the channel 104. After back etching to form a structure as shown in (10) of FIG. 1H, back filling the drain 102 with metal material can form the final structure as shown in (11) of FIG. 1I. Figure 13 Figure 13 Another vertical ring gate structure transistor manufacturing process flow diagram provided by the embodiments of the present application. After step S8, the drain 102 can also be etched to form a structure as shown in (9) of FIG. 1G, and then an insertion layer 106 is deposited between the drain 102 and the channel 104. After back etching to form a structure as shown in (10) of FIG. 1H, back filling the drain 102 with metal material can form the final structure as shown in (11) of FIG. 1I. Figure 13 Figure 13 Figures 6-8

[0136] It should be noted that the vertical ring gate structure transistor involved in the manufacturing method of the vertical ring gate structure transistor in the embodiments of the present application can also correspond to the above-mentioned Figures 2-8 ​​​​​​​The illustrated embodiment.

[0137] In addition, the embodiment of the present application further provides a semiconductor device, which comprises a substrate and the above-mentioned Figures 2-8 The transistor mentioned in the illustrated embodiment.

[0138] The embodiment of the present application further provides a chip, wherein the chip comprises a circuit and the above-mentioned Figures 2-8 The transistor mentioned in the illustrated embodiment or the semiconductor device mentioned in the above-mentioned embodiment, wherein the chip can be composed of a single chip or composed of a plurality of chips.

[0139] The embodiment of the present application further provides an electronic device, which can comprise a circuit board and the above-mentioned Figures 2-8 The transistor mentioned in the illustrated embodiment.

[0140] It should be understood that the semiconductor device, the chip and the electronic device provided by the present application can be consistent with the above-mentioned transistor technical solutions provided by the present application, and the specific content and beneficial effects can be referred to the above-mentioned ​ The gate structure device mentioned in the illustrated embodiment, which will not be described here.

[0141] In the above-mentioned embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0142] It should be noted that, for the above-mentioned method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited to the action sequence described, because according to the present application, some steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0143] In several embodiments provided by the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic. The division of the above-mentioned units is only a logical function division. There can be another division manner for actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical or other forms.

[0144] The units described as separate components above can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0145] In addition, the functional units in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0146] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, essentially or the part that contributes to the prior art, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc., and specifically can be a processor in the computer device) to perform all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium can include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM), and various program codes that can be stored in the medium.

[0147] The above-described embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A transistor, comprising: The transistor comprises a source, a drain, a gate, a gate oxide layer, a channel and an intercalation layer; the intercalation layer comprises one or more of a first intercalation layer, a second intercalation layer and a third intercalation layer; The first intercalation layer is arranged between the source and the channel, the second intercalation layer is arranged between the drain and the channel, and the third intercalation layer is arranged between the gate and the gate oxide layer. The metal activity of the first intercalation layer is weaker than that of the source, the metal activity of the second intercalation layer is weaker than that of the drain, and the metal activity of the third intercalation layer is weaker than that of the gate.

2. The transistor of claim 1, wherein The thickness of the intercalation layer is less than the thickness of the gate oxide layer.

3. The transistor of claim 2, wherein The thickness of the intercalation layer is greater than or equal to 1 nanometer and less than or equal to 2 nanometers.

4. The transistor according to any one of claims 1 to 3, wherein The material of the intercalation layer is one or more of gallium oxide GaO, zinc oxide ZnO, indium oxide InOx, titanium dioxide TiO2, tungsten oxide WO3, molybdenum oxide MoO, aluminum oxide AlO, nickel Ni, palladium Pd, platinum Pt, silver Ag and gold Au.

5. The transistor according to any one of claims 1 to 3, wherein The thickness of the first intercalation layer, the second intercalation layer and the third intercalation layer is the same, or the thickness of at least one of the first intercalation layer, the second intercalation layer and the third intercalation layer is different; the material of the first intercalation layer, the second intercalation layer and the third intercalation layer is the same, or the material of at least one of the first intercalation layer, the second intercalation layer and the third intercalation layer is different.

6. The transistor according to any one of claims 1 to 5, wherein The gate, the gate oxide layer, the channel, the source and the drain are sequentially arranged along the vertical direction of the substrate of the transistor; the length of the gate along the substrate direction is equal to the length of the gate oxide layer, and the length of the channel is less than the length of the gate oxide layer. The source and the drain are spaced apart and arranged in parallel; the source and the drain comprise a first part and a second part with different heights along the vertical direction of the substrate; One side of the bottom of the first part is in contact with the gate oxide layer, and the intercalation layer is arranged between the other side of the first part close to the channel and the channel. The intercalation layer is arranged between one side of the bottom of the second part and the channel.

7. The transistor of claim 6, wherein The intercalation layer is arranged between one side of the bottom of the first part and the gate oxide layer.

8. The transistor according to any one of claims 1 to 5, wherein The transistor comprises a third part and a fourth part, wherein the third part comprises the source, an insulating layer and the drain sequentially arranged along the vertical direction of the substrate of the transistor; a first opening is arranged on the surface of the drain, and the first opening penetrates through the drain and the insulating layer to expose the source at the bottom; The fourth part comprises the channel, the gate oxide layer, the intercalation layer and the gate; the gate comprises a raised part and a horizontal part, and the intercalation layer, the gate oxide layer and the channel are sequentially stacked on the surface of the raised part and the horizontal part of the gate along the vertical direction of the substrate. The protrusion of the fourth part is inserted into the first opening of the third part, so that the channel of the fourth part is in contact with the source, the drain and the insulating layer of the third part respectively.

9. The transistor of claim 8, wherein The insertion layer is arranged between the drain and the channel in the third part, and / or the insertion layer is arranged between the source and the channel in the third part.

10. A method of fabricating a transistor, comprising: The method comprises: forming a source, a drain, a gate, a channel, a gate oxide dielectric layer; forming an insertion layer; the insertion layer comprises one or more of a first insertion layer, a second insertion layer, and a third insertion layer; The first insertion layer is arranged between the source and the channel, the second insertion layer is arranged between the drain and the channel, and the third insertion layer is arranged between the gate and the gate oxide dielectric layer. The metal activity of the first insertion layer is weaker than that of the source, the metal activity of the second insertion layer is weaker than that of the drain, and the metal activity of the third insertion layer is weaker than that of the gate.

11. The method of claim 10, wherein, The preparation of the source, the drain, the gate, the channel, the gate oxide dielectric layer and the insertion layer comprises: forming the gate, the gate oxide dielectric layer and the channel on the substrate surface of the transistor in sequence; etching both ends of the channel so that part of the gate oxide dielectric layer is exposed at both ends of the channel; forming the first insertion layer and the second insertion layer on the channel layer and the exposed gate oxide dielectric layer surface; forming the source on the first insertion layer and the drain on the second insertion layer.

12. The method of claim 10, wherein, The preparation of the source, the drain, the gate, the channel, the gate oxide dielectric layer and the insertion layer comprises: forming the source, the insulating layer and the drain on the substrate surface of the transistor in sequence; etching the drain and the insulating layer to form a first opening; wherein the first opening penetrates the drain and the insulating layer to expose the source at the bottom; forming the channel, the gate oxide dielectric layer, the third insertion layer and the gate in the first opening and on the drain surface in sequence.

13. A chip, characterized by The transistor comprises any one of the above claims 1-9.

14. A semiconductor device, characterized by comprising: The chip comprises a controller and the semiconductor device of claim 13.

15. An electronic device, comprising: The circuit board is electrically connected with the semiconductor device.

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