Semiconductor device, integrated circuit, electronic equipment and preparation method of semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, an integrated circuit, electronic equipment and a preparation method of the semiconductor device, and relates to the technical field of electronic equipment. The semiconductor device includes a substrate, a first electrode, a second electrode, a channel layer, and a gate. Wherein a first groove is formed in the substrate; the first electrode and the second electrode are arranged on the substrate and are respectively arranged on two sides of the first groove along the first direction; the first direction is parallel to the substrate. At least part of the channel layer is arranged on the inner wall of the first groove and the opposite side faces of the first electrode and the second electrode. And at least part of the grid electrode is filled in the first groove. According to the semiconductor device, the channel layer and the grid electrode are sequentially arranged in the first groove, and the first electrode and the second electrode are respectively arranged at the two sides of the notch of the first groove, so that the length of the channel can be prolonged, the influence of a short channel effect on the semiconductor device is reduced, and the electrical performance of the semiconductor device is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic devices, and in particular to a semiconductor device, an integrated circuit, an electronic device, and a preparation method of the semiconductor device. BACKGROUND

[0002] With the continuous development of advanced process technology nodes along Moore's law, the size of semiconductor devices and the area of standard cells (STD CELL) are continuously miniaturized, thereby achieving the benefits of cost reduction, power consumption reduction, performance improvement, and miniaturized design.

[0003] However, with the continuous miniaturization and increasing integration of semiconductor devices, various defects have appeared in the semiconductor devices, for example, the contact area between the source (or drain) and the channel layer in the semiconductor device gradually decreases, resulting in a decrease in the on-current of the semiconductor device and a decrease in the response speed. At the same time, with the continuous miniaturization of semiconductor devices, the distance between the source and the drain in the semiconductor device gradually decreases, exacerbating the short channel effect of the semiconductor device, for example, causing leakage problems between the source and the drain. SUMMARY

[0004] Embodiments of the present application provide a semiconductor device, an integrated circuit, an electronic device, and a preparation method of the semiconductor device, which aims to increase the contact area between the source (or drain) and the channel layer in the semiconductor device, reduce the contact resistance, thereby increasing the on-current of the semiconductor device, improving the response speed of the semiconductor device, in addition, it can also reduce the influence of the short channel effect on the semiconductor device, and optimize the electrical performance of the semiconductor device.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a semiconductor device is provided, which includes a substrate, a first electrode, a second electrode, a channel layer, and a gate.

[0007] The substrate is provided with a first recess. The first electrode and the second electrode are arranged on the substrate and are arranged on opposite sides of the first recess along a first direction; the first direction is parallel to the substrate. At least part of the channel layer is arranged on the inner wall of the first recess and the opposite sides of the first electrode and the second electrode. At least part of the gate is filled in the first recess.

[0008] In the semiconductor device provided by the embodiments of the present application, the first recess is formed in the substrate, the channel layer and the gate are sequentially arranged on the inner wall of the first recess, and the source and the drain are arranged at the opening of the first recess. The path of the channel formed in the channel layer can extend along the inner wall of the first recess. Compared with the case where the path of the channel extends along the straight line distance between the source and the drain, the length of the path of the channel extending along the inner wall of the first recess is longer, so that the probability of the leakage problem between the source and the drain can be effectively reduced, the influence of the short channel effect on the semiconductor device is reduced, and the electrical performance of the semiconductor device is improved.

[0009] In addition, by arranging part of the channel layer on the opposite sides of the first electrode and the second electrode, while realizing the electrical contact (for example, ohmic contact) between the channel layer and the source and the drain, the channel layer vertically attached to the sides of the first electrode and the second electrode can greatly increase the contact area between the channel layer and the source (and the channel layer and the drain), thereby reducing the contact resistance, improving the on-current of the semiconductor device, and improving the response speed of the semiconductor device.

[0010] In a possible implementation of the first aspect, the gate includes a first sub-portion and a second sub-portion arranged integrally, the first sub-portion is filled in the first recess, and the second sub-portion is filled between the first electrode and the second electrode.

[0011] That is, not only the surface of the part of the channel layer located in the first recess is covered with the gate, but also the surface of the part of the channel layer located on the opposite sides of the first electrode and the second electrode can be covered with the gate, so that the gate and the channel layer have sufficient facing area, the control ability of the gate to the channel in the channel layer is enhanced, the probability of the leakage problem between the source and the drain is further reduced, and the electrical performance of the semiconductor device is optimized.

[0012] In a possible implementation of the first aspect, the surface of the gate away from the bottom of the first recess is closer to the bottom of the first recess than the surface of the first electrode and the second electrode facing the substrate.

[0013] That is, the gate can be filled only in the first recess, so that the gate and the first electrode and the second electrode have no facing area, thereby avoiding the problem that the parasitic capacitance is generated between the gate and the first electrode or between the gate and the second electrode, and the performance of the semiconductor device is damaged.

[0014] In a possible implementation of the first aspect, the semiconductor device further includes an insulating portion. The insulating portion is arranged on the side of the gate away from the bottom of the first recess, and at least part of the insulating portion is filled between the first electrode and the second electrode.

[0015] The insulating portion can protect the surface of the gate away from the bottom of the first recess from damage and avoid unintended electrical connection between the first electrode, the second electrode and the gate.

[0016] In a possible implementation of the first aspect, the substrate further includes a second recess, the second recess is arranged at the bottom of the first recess; the channel layer further is arranged on the inner wall of the second recess; and the gate further is filled in the second recess.

[0017] That is, the channel layer not only covers the inner wall of the first recess, but also covers the inner wall of the second recess, the inner wall of the second recess is used to increase the contact area between the gate and the channel layer, thereby improving the control ability of the gate to the channel and further optimizing the electrical performance of the semiconductor device.

[0018] In a possible implementation of the first aspect, the two side walls of the first recess opposite in the first direction are recessed in directions away from each other. Thus, the area of the inner wall of the first recess is increased, so that the area of the channel layer attached to the inner wall of the first recess is also increased, further increasing the path length of the channel formed in the channel layer and optimizing the electrical performance of the semiconductor device.

[0019] In a possible implementation of the first aspect, the semiconductor device includes a plurality of transistors, each transistor including a substrate, a first electrode, a second electrode, a channel layer and a gate; the plurality of transistors are arranged in the first direction and the second direction; the second direction is parallel to the substrate and intersects the first direction.

[0020] At least two transistors arranged adjacent in the first direction share the second electrode.

[0021] The transistors in multiple directions can increase the capacity of the semiconductor device, and the two transistors arranged adjacent in the first direction share the second electrode, which can reduce the design space occupied by the transistors and is conducive to improving the integration of the semiconductor device.

[0022] In a possible implementation of the first aspect, the semiconductor device further includes a first partition portion. The first partition portion is arranged between two transistors arranged adjacent in the second direction. The gates of at least two transistors arranged adjacent in the second direction penetrate the first partition portion and are electrically connected to each other, and the channel layers, the first electrodes and the second electrodes of the at least two transistors arranged adjacent in the second direction are electrically insulated by the first partition portion, so as to realize the isolation between the two transistors arranged adjacent in the second direction and avoid unintended electrical connection between the two transistors.

[0023] In a possible implementation manner of the first aspect, the first partition portion includes a third groove, the third groove is arranged between two first grooves arranged adjacent in the second direction, and the third groove is in communication with the first grooves; a groove bottom of the third groove is closer to the side surface of the substrate away from the first electrode than a groove bottom of the first groove. A part of the gate is also filled in the third groove, and the gates in at least two transistors arranged adjacent in the second direction pass through the first partition portion through the third groove; a part of the channel layer is also arranged on two side walls of the third groove opposite in the second direction.

[0024] By arranging the third groove and arranging the channel layer on the side walls of the third groove, the width (perpendicular to the path length of the channel) of the channel layer is increased by the side walls of the third groove on the first partition portion, the on-off ratio of the semiconductor device is improved, and the contact area of the gate and the channel layer is also increased, so that the control ability of the gate to the channel is improved, and the electrical performance of the semiconductor device is further optimized.

[0025] In a possible implementation manner of the first aspect, the first electrode and the second electrode each include a conductive layer and a conductive portion. The upper surface of the substrate, the first partition portion, and the channel layer surround a first cavity, the conductive portion is filled in the first cavity, and the conductive layer is arranged between the inner wall of the first cavity and the conductive portion.

[0026] By surrounding the conductive layer around the multiple surfaces of the conductive portion, the contact area between the part for contacting the channel layer and the part for realizing the external connection of the source electrode or the drain electrode in the first electrode or the second electrode is increased, so that the two have a better electrical connection effect, and the electrical performance of the semiconductor device can also be optimized.

[0027] In a second aspect, a preparation method of a semiconductor device is provided, and the preparation method includes the following steps.

[0028] A sacrificial layer is covered on a substrate. A first groove is formed; the first groove extends in a second direction, and a side wall of the first groove extends from a surface of the sacrificial layer away from the substrate into the substrate; the first groove divides the sacrificial layer into a first sacrificial portion and a second sacrificial portion, and a part of the first groove in the substrate is a first groove; the first sacrificial portion and the second sacrificial portion are arranged on two sides of the first groove in a first direction; the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction. A channel layer and a gate are sequentially formed in the first groove; at least a part of the channel layer is arranged on an inner wall of the first groove and opposite side surfaces of the first sacrificial portion and the second sacrificial portion; and at least a part of the gate is filled in the first groove. The first sacrificial portion is replaced by a first electrode, and the second sacrificial portion is replaced by a second electrode.

[0029] The technical effects brought by the preparation method in the second aspect can be referred to the technical effects brought by the design manner of the semiconductor device in the first aspect, which will not be repeated here.

[0030] In a possible implementation of the second aspect, after the sacrificial layer is covered on the substrate, and before the first slot is formed, the method further includes: opening a second slot, and filling the first partition in the second slot; the first partition extends along the first direction, and the first partition breaks at least part of the sacrificial layer and at least part of the substrate. The first slot also breaks at least part of the first partition, and the part of the first slot in the first partition is a third groove.

[0031] After the channel layer and the gate are sequentially formed in the first slot, the method further includes: removing the first partition and part of the channel layer exposed after the first partition is removed. The first partition is filled again.

[0032] Through the embodiment, a semiconductor device with multiple transistors can be prepared, and in particular, multiple transistors arranged in the second direction and sharing a gate can be prepared.

[0033] In a possible implementation of the second aspect, after the first slot is formed, and before the channel layer and the gate are sequentially formed in the first slot, the method further includes: continuing to etch the part of the first slot belonging to the first partition, so that the bottom of the third groove is closer to the side surface of the substrate away from the first sacrificial part than the bottom of the first groove.

[0034] Through the embodiment, in the semiconductor device prepared, the channel layer not only adheres to the inner wall of the first groove, but also adheres to the side wall of the third groove, so as to increase the width (the length perpendicular to the path of the channel) of the channel layer, improve the on-off ratio of the semiconductor device, and also increase the contact area between the gate and the channel layer, so as to improve the control ability of the gate to the channel, and further optimize the electrical performance of the semiconductor device.

[0035] In a possible implementation of the second aspect, before the sacrificial layer is covered on the substrate, the method further includes: forming a second partition in the substrate; the second partition extends along the first direction, and breaks at least part of the substrate. After the sacrificial layer is formed, the sacrificial layer covers the second partition. The first slot also breaks at least part of the second partition, and the part of the first slot in the second partition is a second groove.

[0036] After the first slot is formed, and before the channel layer and the gate are sequentially formed in the first slot, the method further includes: continuing to etch the part of the first slot belonging to the second partition, so that the bottom of the second groove is closer to the side surface of the substrate away from the first sacrificial part than the bottom of the first groove.

[0037] Through the embodiment, the channel layer can be attached to the inner wall of the first recess and the sidewall of the second recess in the prepared semiconductor device, so that the width (perpendicular to the length of the channel path) of the channel layer can be increased, the on-off ratio of the semiconductor device can be improved, the contact area between the gate and the channel layer can be increased, the control ability of the gate to the channel can be improved, and the electrical performance of the semiconductor device can be further optimized.

[0038] In a possible implementation of the second aspect, the first electrode and the second electrode each include a conductive layer and a conductive part. Replacing the first sacrificial part with the first electrode and replacing the second sacrificial part with the second electrode includes:

[0039] The first sacrificial part and the second sacrificial part are removed to form a plurality of first cavities; the upper surface of the substrate, the first partition part, and the channel layer enclose the first cavities. The conductive layer is formed on the inner wall of the first cavities. The conductive part is formed; the conductive part is filled in the first cavities, and the conductive layer is arranged between the inner wall of the first cavities and the conductive part.

[0040] Through the embodiment, the conductive layer can surround the plurality of surfaces of the conductive part, so that the contact area between the part (that is, the conductive layer) for contacting the channel layer and the part (that is, the conductive part) for realizing the external connection of the source or the drain in the first electrode or the second electrode can be increased, the electrical connection effect of the two can be better, and the electrical performance of the semiconductor device can be optimized.

[0041] In a third aspect, an integrated circuit is provided, which includes an electronic device and the semiconductor device provided in any one of the embodiments of the first aspect. The electronic device is electrically connected to the semiconductor device.

[0042] In a fourth aspect, an electronic device is provided, which includes a circuit board and the integrated circuit provided in the embodiments of the third aspect. The integrated circuit is arranged on the circuit board and is electrically connected to the circuit board.

[0043] The technical effects brought by the integrated circuit in the third aspect and the electronic device in the fourth aspect can refer to the technical effects brought by the design of the semiconductor device in the first aspect, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 A structural schematic diagram of an electronic device provided in the embodiments of the present application is shown;

[0045] Figure 2 A structural schematic diagram of a semiconductor device provided in the embodiments of the present application is shown;

[0046] Figure 3 A sectional view along the section line A-A' in Figure 2 ;

[0047] Figure 4 A relationship curve between a contact area of a channel layer and a source and an on-current is provided for an embodiment of the present application.

[0048] Figure 5 Another structural schematic diagram of a semiconductor device is provided for an embodiment of the present application.

[0049] Figure 6 Another structural schematic diagram of a semiconductor device is provided for an embodiment of the present application.

[0050] Figure 7 A sectional view along the section line B-B' in FIG. 1B is provided for an embodiment of the present application. Figure 6

[0051] Figure 8 Another structural schematic diagram of a semiconductor device is provided for an embodiment of the present application.

[0052] Figure 9 A sectional view along the section line C-C' in FIG. 1C is provided for an embodiment of the present application. Figure 8

[0053] Another sectional view along the section line C-C' in FIG. 1C is provided for an embodiment of the present application. Figure 10 Figure 8 A front view of a semiconductor device is provided for an embodiment of the present application.

[0054] Figure 11 A flow chart of a preparation process of a semiconductor device is provided for an embodiment of the present application.

[0055] Figures 12-15 Structural diagrams corresponding to respective preparation steps of a semiconductor device are provided.

[0056] DETAILED DESCRIPTION Figures 16-31 The technical solutions in some embodiments of the present application will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments provided by the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0057] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0058] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. ​​

[0059] Unless otherwise required by context, the term "including" as used herein is to be construed as open-ended, i.e., to the effect that "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "an exemplary embodiment," "exemplary embodiments," or "some examples" are intended to mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the present application. These terms are not necessarily intended to refer to the same embodiment or example. In addition, a particular feature, structure, material, or characteristic can be included in any one or more embodiments or examples.

[0060] Hereinafter, the terms "first", "second", and the like are used only for descriptive purposes, and cannot be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0061] Connection / connection: can refer to a mechanical connection relationship or a physical connection relationship, that is, A and B are connected or A and B are connected, which means that there is a fastening component (such as a screw, a bolt, a rivet, etc.) between A and B, or A and B are in contact with each other and A and B are difficult to separate, wherein A and B can be fixedly connected, or detachably connected, or integrated; it can be directly connected, or indirectly connected through an intermediate medium.

[0062] Coupling: can be understood as direct coupling and / or indirect coupling, and "coupling connection" can be understood as direct coupling connection and / or indirect coupling connection. Direct coupling can also be referred to as "electrical connection", which means that the components are directly or indirectly in physical contact and electrically conductive, for example, in the form of connection between different components in the circuit structure through the entity circuit of the copper foil or wire of the printed circuit board (PCB) that can transmit electrical signals; "indirect coupling" can be understood as electrical conduction through space / non-contact. In one embodiment, indirect coupling can also be referred to as capacitive coupling, for example, through the coupling between the gap between the two conductive parts to form an equivalent capacitor to realize signal transmission.

[0063] "A, B, and C at least one of them" has the same meaning as "A, B, or C at least one of them", which includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0064] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0065] As used herein, "parallel," "perpendicular," "equal" include the recited condition and conditions that approximate the recited condition, the range of approximation being within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement at issue and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable deviation range for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable deviation range for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable deviation range for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0066] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0067] In addition, the scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, as new scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0068] The electronic device provided by the embodiments of the present application can be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), a drone, a radar, an aerospace device, a vehicle-mounted device, a vehicle, or a different type of user equipment or terminal device; or the electronic device can also be a network device such as a base station. The embodiments of the present application do not specially limit the specific form of the electronic device.

[0069] Figure 1A structural schematic diagram of an electronic device is exemplarily provided in the embodiments of the present application. As shown in Figure 1 The electronic device 1000 includes an integrated circuit 100 and a circuit board 200, and the integrated circuit 100 can be arranged on the circuit board 200.

[0070] Exemplarily, the circuit board 200 can be a printed circuit board (PCB).

[0071] It can be understood that, Figure 1 The structure of the electronic device 1000 shown in the above is not a specific limitation on the electronic device 1000. The electronic device 1000 can include more or less components than those shown in Figure 1 , or can combine some of the components shown in Figure 1 , or can be arranged differently from the components shown in Figure 1 .

[0072] The embodiments of the present application further provide an integrated circuit 100.

[0073] Exemplarily, as shown in Figure 1 , the integrated circuit 100 can include a logic circuit 101, an analog circuit 102, a storage circuit 103, and an input / output circuit 104, etc.

[0074] It should be understood that the integrated circuit 100 includes but is not limited to the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104. For example, in addition to the aforementioned four circuits, the integrated circuit 100 can also include other types or functions of circuits, or discrete devices.

[0075] In addition, the integrated circuit 100 can include one or more of the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104.

[0076] On this basis, the number of the logic circuit 101, the analog circuit 102, the storage circuit 103, and the input / output circuit 104 included in the integrated circuit 100 can be set as needed. The integrated circuit 100 can include one or more logic circuits 101. The integrated circuit 100 can also include one or more analog circuits 102. The integrated circuit 100 can also include one or more storage circuits 103. The integrated circuit 100 can also include one or more input / output circuits 104.

[0077] As shown in Figure 1 , the integrated circuit 100 can include a semiconductor device 10 and some electronic devices 20. The electronic devices 20 are electrically connected to the semiconductor device 10.

[0078] Exemplarily, referring to Figure 1 The semiconductor device 10 and the electronic device 20 can be integrated in a logic circuit 101, and the semiconductor device 10 and the electronic device 20 in the logic circuit 101 cooperate with each other to realize the functions such as AND, OR and NOT in the logic circuit 101.

[0079] Exemplarily, the electronic device 20 can be a resistor, a capacitor or the like.

[0080] Exemplarily, the semiconductor device 10 and the electronic device 20 can also be arranged in other circuits, for example, can be arranged in a storage circuit 103, and the present application does not make specific limitation thereto.

[0081] The present application also provides a semiconductor device 10.

[0082] Exemplarily, the semiconductor device 10 can be a transistor, for example, can be an oxide thin-film transistor (TFT) or a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0083] Or exemplarily, the semiconductor device 10 can also be a memory, for example, can be a dynamic random access memory (DRAM), for example, can be a part belonging to a transistor in a 1T1C architecture DRAM.

[0084] Figure 2 A structure diagram of the semiconductor device 10 provided by the present application, Figure 3 is a sectional view along the section line A-A' in Figure 2 .

[0085] In some embodiments, as shown in Figure 2 , the semiconductor device 10 includes a substrate 11, a first electrode 21, a second electrode 22, a channel layer 3 and a gate 4.

[0086] The substrate 11 serves as a bearing plate for bearing the above-mentioned first electrode 21, second electrode 22, channel layer 3 and gate 4 and the like, so as to facilitate the preparation of the aforementioned structures in the semiconductor device 10.

[0087] Exemplarily, the material of the substrate 11 can include at least one of monocrystalline silicon (Si), monocrystalline germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), a group III-V compound semiconductor material, a group II-VI compound semiconductor material, or other semiconductor materials known in the art, or can also be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0088] Referring to Figure 2 and Figure 3 , the substrate 11 is provided with a first recess U1.

[0089] For example, referring to Figure 2 and Figure 3 , the first recess U1 can be etched downward from the upper surface of the substrate 11 (in the orientation of Figure 3 ), and the bottom U1' of the first recess U1 is formed inside the substrate 11, so that the opening of the first recess U1 is upward in the orientation of Figure 3 .

[0090] It can be understood that Figure 3 the cross-sectional view can only show the bottom U1' of the first recess U1, and the sidewall of the first recess U1 extends upward from the bottom U1' in Figure 3 .

[0091] Exemplarily, the bottom U1' of the first recess U1 can be a plane, or can also be a curved surface (see Figure 2 ), and the embodiments of the present application do not limit this.

[0092] Exemplarily, the first recess U1 can be a rectangular recess, an elliptical recess, a circular recess, or a recess of other irregular shapes, and the embodiments of the present application do not limit this.

[0093] Referring to Figure 2 , the first electrode 21 and the second electrode 22 are arranged on the substrate 11, and the first electrode 21 and the second electrode 22 are arranged on the two sides of the first recess U1 along the first direction X. For example, referring to Figure 2 , the first electrode 21 and the second electrode 22 are arranged at the opening of the first recess U1 and are arranged on the two sides of the opening.

[0094] Wherein, the first direction X is parallel to the substrate 11, for example, referring to Figure 2 and Figure 3 , the first direction X is parallel to the bottom surface of the substrate 11.

[0095] Exemplarily, referring to Figure 2 , the opposite two sides of the first electrode 21 and the second electrode 22 can be tangent to (for example, substantially located in the same plane) the sidewall of the first recess U1. For example, referring to Figure 2For example, the first electrode 21 is arranged on the left side of the first recess U1, and the side of the first electrode 21 facing the second electrode 22 is tangent to the side wall on the left side of the first recess U1. Similarly, the second electrode 22 is arranged on the right side of the first recess U1, and the side of the second electrode 22 facing the first electrode 21 is tangent to the side wall on the right side of the first recess U1, so as to facilitate the synchronous preparation of the first recess U1 and the two electrodes (the first electrode 21 and the second electrode 22).

[0096] Alternatively, for example, the opposite two sides of the first electrode 21 and the second electrode 22 can also have a certain spacing from the slot of the first recess U1. For example, the side of the first electrode 21 facing the second electrode 22 can be farther away from the second electrode 22 (i.e., arranged more to the left) relative to the left side wall of the first recess U1, and the side of the second electrode 22 facing the first electrode 21 can be farther away from the first electrode 21 (i.e., arranged more to the right) relative to the right side wall of the first recess U1.

[0097] The first electrode 21 and the second electrode 22 are used as the source and the drain in the semiconductor device 10 and have electrical conductivity.

[0098] For example, the materials of the first electrode 21 and the second electrode 22 can be metal materials, which can include tungsten (W), titanium (Ti), copper (Cu), molybdenum (Mo), gold (Au), silver (Ag), aluminum (Al), ruthenium (Ru), or other metal or alloy materials having electrical conductivity.

[0099] Alternatively, for example, the materials of the first electrode 21 and the second electrode 22 can also be semiconductor materials, which can include silicon (Si), titanium nitride (TiN), indium tin oxide (ITO), or other semiconductor materials. In this case, the first electrode 21 and the second electrode 22 can be highly doped to improve their electrical conductivity.

[0100] Referring to Figure 2 At least part of the channel layer 3 is arranged on the inner wall of the first recess U1 (including the bottom U1' of the first recess U1 and the side wall of the first recess U1), and the opposite sides of the first electrode 21 and the second electrode 22.

[0101] It can be understood that the "opposite sides of the first electrode 21 and the second electrode 22" herein refer to the sides of the first electrode 21 and the second electrode 22 facing each other, i.e., the side of the first electrode 21 close to the second electrode 22 and the side of the second electrode 22 close to the first electrode 21.

[0102] The material of the channel layer 3 is a semiconductor material, i.e., a channel (carrier) can be formed in the channel layer 3, so that the channel layer 3 has conductivity, realizing the conduction between the source and the drain in the semiconductor device 10, thereby realizing the opening of the semiconductor device 10. In the case where no channel is formed in the channel layer 3, the channel layer 3 has electrical insulation, so as to realize the electrical insulation between the source and the drain in the semiconductor device 10, thereby realizing the closing of the semiconductor device 10.

[0103] For example, the material of the channel layer 3 can include at least one of single crystal silicon (Si), polycrystalline silicon (poly-Si), amorphous silicon (amorphous-Si), indium gallium zinc oxide (In-Ga-Zn-O, referred to as IGZO), single crystal germanium (Ge), zinc oxide (ZnO), indium tin oxide (ITO), titanium dioxide (TiO2), molybdenum disulfide (MoS2), gallium arsenide (GaAs), indium phosphide (InP), a III-V compound semiconductor material, a II-VI compound semiconductor material, or other semiconductor materials known in the art.

[0104] Referring to Figure 2 The two ends of the channel layer 3 are in contact with the first electrode 21 and the second electrode 22, respectively. In the case where a channel is formed in the channel layer 3, the channel layer 3 has conductivity, so as to realize the conduction between the first electrode 21 and the second electrode 22, i.e., realize the conduction between the source and the drain in the semiconductor device 10, thereby realizing the opening of the semiconductor device 10.

[0105] For example, the channel layer 3 can be doped, for example, high-concentration doped, so that the channel layer 3 can form an ohmic contact with the source and the drain (i.e., the first electrode 21 and the second electrode 22) in the semiconductor device 10, improving the transmission performance of the electrical signal between the source (e.g., the first electrode 21), the channel layer 3, and the drain (e.g., the second electrode 22) in the semiconductor device 10.

[0106] Referring to Figure 2 The middle part of the channel layer 3 is attached to the inner wall of the first recess U1. In the process of opening the semiconductor device 10, the channel needs to pass through the part of the channel layer 3 located on the inner wall of the first recess U1, so as to realize the conduction between the first electrode 21 and the second electrode 22, i.e., the transmission path of the channel formed in the semiconductor device 10 is not a straight line distance between the source and the drain (i.e., between the first electrode 21 and the second electrode 22), but is arranged in a curve along the shape of the channel layer 3, for example, the transmission path of the channel includes the part of the channel layer 3 in contact with the first electrode 21, the part of the channel layer 3 in contact with the inner wall of the first recess U1, and the part of the channel layer 3 in contact with the second electrode 22.

[0107] Compared with the straight channel between the source and the drain, the curved channel of the semiconductor device 10 provided in the embodiments of the present application has a longer transmission path, so that the leakage current between the source and the drain can be avoided, and the electrical performance of the semiconductor device 10 is improved.

[0108] Exemplarily, the control of the length of the channel path formed in the channel layer 3 can be realized by controlling the depth of the first groove U1. For example, the deeper the depth of the first groove U1 is, the larger the inner wall area of the first groove U1 is, and the longer the length of the channel layer 3 is, and the longer the transmission path of the channel formed in the channel layer 3 is.

[0109] Referring to Figure 2 , at least part of the gate 4 is filled in the first groove U1.

[0110] The gate 4 serves as the control electrode of the transistor T, and is used to control the formation of the channel in the channel layer 3, so as to control the conduction between the first electrode 21 and the second electrode 22 which are electrically connected to the two ends of the channel layer 3, or control the non-formation of the channel in the channel layer 3, so as to control the disconnection between the first electrode 21 and the second electrode 22 which are electrically connected to the two ends of the channel layer 3, that is, to control the opening and closing of the semiconductor device 10.

[0111] Exemplarily, the gate 4 has electrical conductivity, and the material of the gate 4 can be a metal material or other conductive material. For example, the material of the gate 4 can include at least one of titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide (ITO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), etc.

[0112] Referring to Figure 2 , by filling the gate 4 in the first groove U1 and arranging the channel layer 3 on the inner wall of the first groove U1, the gate 4 covers the part of the channel layer 3 on the inner wall of the first groove U1, that is, the gate 4 and the channel layer 3 have a facing area, so that the gate 4 can control the channel in the channel layer 3, and the opening and closing of the semiconductor device 10 can be realized.

[0113] Exemplarily, referring to Figure 2 and Figure 3 , the semiconductor device 10 further includes a gate oxide layer 5 which is arranged between the gate 4 and the channel layer 3.

[0114] For example, the channel layer 3 is attached to the inner wall of the first groove U1, the gate oxide layer 5 is attached to the side of the channel layer 3 away from the inner wall of the first groove U1, and the gate 4 is arranged on the gate oxide layer 5 and fills the first groove U1, so that the gate 4 is not in direct electrical contact with the channel layer 3, and the gate 4 can control the channel in the channel layer 3, and the opening and closing of the semiconductor device 10 can be realized.

[0115] Exemplarily, the gate oxide layer 5 has an electrical insulation property, for example, the material of the gate oxide layer 5 can include one or more of silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium disulfide (HfO2), zirconium dioxide (ZrO2), titanium dioxide (TiO2), yttrium oxide (Y2O3), and silicon nitride (Si3N4), and the like insulating materials.

[0116] In the semiconductor device 10 provided by the embodiments of the present application, by opening the first recess U1 in the substrate 11, and sequentially arranging the channel layer 3 and the gate 4 (and the gate oxide layer 5 between the channel layer 3 and the gate 4) on the inner wall of the first recess U1, the source and the drain (i.e., the first electrode 21 and the second electrode 22) are arranged at the slot opening of the first recess U1, so that the path of the channel formed in the channel layer 3 can extend along the inner wall of the first recess U1, for example, the channel path can extend from one side of the slot opening of the first recess U1, through the inner wall of the first recess U1, to the other side of the slot opening of the first recess U1, compared with the case that the channel path extends along the straight line distance between the source and the drain, the length of the channel path extending along the inner wall of the first recess U1 is longer, thereby effectively reducing the probability of leakage between the source and the drain, reducing the influence of the short channel effect on the semiconductor device 10, and improving the electrical performance of the semiconductor device 10.

[0117] In addition, by arranging part of the channel layer 3 on the opposite sides of the first electrode 21 and the second electrode 22, while realizing the electrical contact (e.g., ohmic contact) between the channel layer 3 and the source and the drain, the channel layer 3 vertically attached on the side of the first electrode 21 and the second electrode 22 can greatly increase the contact area between the channel layer 3 and the source (and the channel layer 3 and the drain), thereby reducing the contact resistance, improving the on-current of the semiconductor device 10, and improving the response speed of the semiconductor device 10.

[0118] Figure 4 And Table 1 below shows the corresponding relationship between the size of the contact area between the source (or the drain) and the channel layer 3 in the semiconductor device 10 and the on-current of the semiconductor device 10:

[0119] Table 1

[0120]

[0121] Figure 4 In Table 1, the contact area between the channel layer 3 and the source (or the drain) refers to the product of the width and length of the contact area, for example, it can be the area of the side of the first electrode 21 facing the second electrode 22.

[0122] In addition, referring to Figure 4And Table 1, the semiconductor device 10 of the opening current is analyzed and detected in the case of voltage 2V.

[0123] Referring to Figure 4 And Table 1, the semiconductor device 10 of the opening current is analyzed and detected in the case of voltage 2V.

[0124] The semiconductor device 10 provided by the embodiment of the present application has a regular structure, which facilitates the superposition of structures in multiple directions, and the specific superposition manner can be referred to the following embodiments.

[0125] In some embodiments, as Figure 2 shown, the semiconductor device 10 can include a plurality of transistors T, each transistor T including the aforementioned substrate 11, the first electrode 21, the second electrode 22, the channel layer 3 and the gate 4.

[0126] Referring to Figure 2 , the plurality of transistors T can be arranged along the first direction X, or the plurality of transistors T can also be arranged along the second direction Y, or referring to Figure 2 , the plurality of transistors T can be arranged along the first direction X and the second direction Y.

[0127] That is, the semiconductor device 10 can include a plurality of transistors T that can be superimposed in multiple directions, so that the semiconductor device 10 can have different capacities to be suitable for different application scenarios, for example, in the case of using the semiconductor device 10 for information storage, the semiconductor device 10 with multiple transistors T superimposed in different directions can have a larger storage capacity.

[0128] Wherein, the first direction X and the second direction Y are parallel to the substrate 11, the first direction X can be the arrangement direction of the first electrode 21 and the second electrode 22, and the second direction Y intersects the first direction X, for example, the second direction Y is perpendicular to the first direction X.

[0129] In some embodiments, referring to Figure 2 , at least two transistors T arranged adjacent along the first direction X can share the second electrode 22, thereby improving the integration of the semiconductor device 10.

[0130] Exemplarily, referring toFigure 2 The two transistors T can also be symmetrically arranged with the second electrode 22 as the symmetric axis, so as to realize regular stacking of multiple transistors T in the first direction X.

[0131] In some embodiments, referring to Figure 2 and Figure 3 The semiconductor device 10 further comprises a first partitioning portion 71.

[0132] Referring to Figure 2 The first partitioning portion 71 is arranged between two transistors T arranged adjacently in the second direction Y, so as to realize insulation between the two transistors T arranged adjacently in the second direction Y, and avoid unintended electrical connection between the two transistors T.

[0133] For example, referring to Figure 2 The gates 4 in at least two transistors T arranged adjacently in the second direction Y can be electrically connected to each other after penetrating the first partitioning portion 71, for example, referring to Figure 3 The two corresponding gates 4 of the two transistors T can be integrally arranged, that is, the multiple transistors T arranged in the second direction Y can share the gate 4, so as to facilitate formation of a word line (abbreviated as WL) and realize synchronous transmission of control signals of the multiple transistors T.

[0134] For example, referring to Figure 2 and Figure 3 The channel layers 3 in at least two transistors T arranged adjacently in the second direction Y are electrically insulated by the first partitioning portion 71, and for the same reason, referring to Figure 2 The first electrodes 21 in two transistors T arranged adjacently in the second direction Y are electrically insulated by the first partitioning portion 71, and for the same reason, the second electrodes 22 in the two transistors T arranged adjacently in the second direction Y are electrically insulated by the first partitioning portion 71.

[0135] That is, referring to Figure 3 The two corresponding channel layers 3 of the two transistors T arranged adjacently in the second direction Y are disconnected, and for the same reason, the two corresponding first electrodes 21 of the two transistors T arranged adjacently in the second direction Y are disconnected, and the two corresponding second electrodes 22 are disconnected.

[0136] For example, referring to Figure 2 The first partitioning portion 71 can be embedded in the substrate 11, and the bottom surface of the first partitioning portion 71 can be located in the substrate 11, for example, referring to Figure 2 and Figure 3 The bottom surface of the first partitioning portion 71 can be flush with the groove bottom U1’ of the first groove U1, so that the two corresponding channel layers 3 of the two transistors T arranged adjacently in the second direction Y, the two first electrodes 21, and the two second electrodes 22 can be disconnected from each other.

[0137] Or exemplarily, refer to the subsequent Figure 6 The bottom of the first partition portion 71 can also be flush with the bottom surface of the substrate 11, that is, the first partition portion 71 can divide the substrate 11 into two parts, so as to ensure that two channel layers 3 corresponding to two transistors T arranged adjacent to each other along the second direction Y, two first electrodes 21, and two second electrodes 22 can be fully disconnected.

[0138] The foregoing embodiments can realize the improvement of the electrical performance of the semiconductor device 10 through the superposition of the number of transistors T, and in addition, the electrical performance of the semiconductor device 10 can also be improved through the deformation of the structure of the gate 4 and the like, and the specific structure deformation manner can be referred to the following embodiments.

[0139] Figure 5 And Figure 6 Another structure schematic diagram of the semiconductor device 10 provided by the embodiments of the present application.

[0140] In some embodiments, refer to Figure 5 The gate 4 includes a first sub-portion 41 and a second sub-portion 42 arranged integrally, the first sub-portion 41 is filled in the first recess U1, and the second sub-portion 42 is filled between the first electrode 21 and the second electrode 22.

[0141] That is, part of the gate 4 is not only filled in the first recess U1, but also part of the gate 4 is arranged between the first electrode 21 and the second electrode 22, that is, refer to Figure 5 Not only the surface of the part of the channel layer 3 located in the first recess U1 is covered with the gate 4 (it can be understood that there is a gate oxide layer 5 between the channel layer 3 and the gate 4), but also the surface of the part of the channel layer 3 located on the side opposite to the first electrode 21 and the second electrode 22 can be covered with the gate 4, so as to ensure that the gate 4 has sufficient facing area with the channel layer 3, thereby enhancing the control ability of the gate 4 to the channel in the channel layer 3, further reducing the probability of the leakage problem between the source and the drain, and optimizing the electrical performance of the semiconductor device 10.

[0142] In other embodiments, refer to Figure 2 And Figure 6 The gate 4 can be filled only in the first recess U1, that is, the surface of the gate 4 away from the groove bottom U1’ of the first recess U1 is closer to the groove bottom U1’ of the first recess U1 relative to the surface of the first electrode 21 and the second electrode 22 facing the substrate 11, that is, the distance d1 (refer to Figure 6) greater than or equal to 0 nm, so as to avoid the problem of the gate electrode 4 and the first electrode 21 and the second electrode 22 having a facing area, thereby avoiding the problem of the gate electrode 4 and the first electrode 21 or the gate electrode 4 and the second electrode 22 generating a parasitic capacitance, resulting in the performance of the semiconductor device 10 being impaired.

[0143] For example, referring to Figure 6 , in the case that the surface of the gate electrode 4 away from the groove bottom U1' of the first groove U1 is closer to the groove bottom U1' of the first groove U1 relative to the surface of the first electrode 21 and the second electrode 22 facing the substrate 11, the surface of the gate electrode 4 away from the groove bottom U1' of the first groove U1 has a spacing d1 between the surface of the first electrode 21 and the second electrode 22 facing the substrate 11, thereby ensuring that the gate electrode 4 and the first electrode 21 and the second electrode 22 are staggered relative to each other, avoiding the generation of a parasitic capacitance.

[0144] For example, the spacing d1 can be greater than or equal to 2 nm, for example, 2 nm, 4.5 nm, 8.743 nm, or 11 nm, etc.

[0145] In some embodiments, referring to Figure 2 and Figure 6 , the semiconductor device 10 further comprises an insulating portion 6, the gate electrode 4 is filled in the first groove U1, the insulating portion 6 is arranged on the side of the gate electrode 4 away from the groove bottom U1' of the first groove U1, and at least part of the insulating portion 6 is filled between the first electrode 21 and the second electrode 22.

[0146] For example, referring to Figure 6 , in the case that the surface of the gate electrode 4 away from the groove bottom U1' of the first groove U1 has a spacing d1 between the surface of the first electrode 21 and the second electrode 22 facing the substrate 11, in addition to the part filled between the first electrode 21 and the second electrode 22, part of the insulating portion 6 is also filled in the first groove U1.

[0147] The insulating portion 6 has electrical insulation, and its material can refer to the material of the aforementioned gate oxide layer 5 or other materials capable of achieving electrical insulation.

[0148] By arranging the insulating portion 6, the top of the gate electrode 4 can be kept insulated, avoiding the gate electrode 4 from being electrically connected in an unintended manner, and the insulating portion 6 arranged between the first electrode 21 and the second electrode 22 can avoid the first electrode 21 and the second electrode 22 being directly electrically connected.

[0149] Figure 7 is a sectional view along the section line B-B' in Figure 6 .

[0150] In some embodiments, referring to Figure 7In the case where the semiconductor device 10 includes the first partition portion 71, a third recess U3 can be formed in the first partition portion 71, and the gate electrode 4 of at least two transistors T adjacently arranged in the second direction Y can pass through the first partition portion 71 through the third recess U3.

[0151] Referring to Figure 2 and Figure 7 , the third recess U3 is provided between the two first recesses U1 corresponding to the two transistors T adjacently arranged in the second direction Y, and communicates with the first recesses U1.

[0152] It can be understood that, Figure 7 only the bottom U1' of the first recess U1 and the bottom U3' of the third recess U3 are shown in the sectional view of FIG. 10, and the wall of the first recess U1 extends from the bottom U1' of the first recess U1 toward Figure 7 above in the sectional view of FIG. 10, and the third recess U3 is the same.

[0153] Exemplarily, referring to Figure 2 , the bottom U3' of the third recess U3 can be flush with the bottom U1' of the first recess U1, and the third recess U3 can also satisfy the requirement that the gate electrode 4 passes through the first partition portion 71.

[0154] Alternatively, exemplarily, referring to Figure 7 , the bottom U3' of the third recess U3 can also be closer to the side surface of the substrate 11 away from the first electrode 21 relative to the bottom U1' of the first recess U1, that is, the depth of the third recess U3 can be deeper than the depth of the first recess U1, so that the inner wall of the first recess U1 and the inner wall of the third recess U3 form a stepped shape, and the inner wall area of the cavity formed by the first recess U1 and the third recess U3 is increased.

[0155] Referring to Figure 6 and Figure 7 , the bottom surface of the first partition portion 71 is lower than the bottom U1' of the first recess U1, so as to reserve space for the third recess U3 with a deeper depth formed in the first partition portion 71, for example, referring to Figure 6 , the bottom surface of the first partition portion 71 can be flush with the bottom surface of the substrate 11, or in other embodiments, the bottom surface of the first partition portion 71 can be located at any position lower than the bottom U1' of the first recess U1.

[0156] Referring to Figure 7 , part of the channel layer 3 is also provided on the two opposite side walls of the third recess U3 in the second direction Y, that is, the channel layer 3 is also provided on the inner wall of the third recess U3, except for the bottom U3', so as to disconnect the two channel layers 3 corresponding to the two transistors T adjacently arranged in the second direction Y from each other, referring to Figure 7The part of the two channel layers 3 in the third groove U3 is disconnected by the first partition 71.

[0157] Referring to Figure 7 , the part of the gate 4 is also filled in the third groove U3, so that the gate 4 in at least two transistors T arranged adjacent in the second direction Y penetrates the first partition 71 through the third groove U3, and in addition, the part of the gate 4 filled in the third groove U3 is also used to control the channel layer 3 attached to the sidewall of the third groove U3 to form a channel.

[0158] In this embodiment, by setting the third groove U3 and setting the channel layer 3 on the sidewall of the third groove U3, the width (the path length perpendicular to the channel) of the channel layer 3 is increased by the sidewall of the third groove U3 on the first partition 71, which improves the on-off ratio of the semiconductor device 10, and at the same time, the contact area between the gate 4 and the channel layer 3 is also increased, thereby improving the control ability of the gate 4 on the channel, and further optimizing the electrical performance of the semiconductor device 10.

[0159] Figure 8 Another structural schematic diagram of the semiconductor device 10 provided in the embodiments of the present application is shown in Figure 9 , which is a sectional view along the section line C-C’ in Figure 8 , which is a sectional view along the section line C-C’ in Figure 10 , which is another sectional view along the section line C-C’ in Figure 8 .

[0160] In some embodiments, referring to Figure 9 , the substrate 11 further includes a second groove U2, which is arranged at the groove bottom U1’ of the first groove U1.

[0161] For example, the second groove U2 can be etched from the groove bottom U1’ of the first groove U1 downward (in the direction of the arrow in Figure 9 and Figure 10 , for example), so that the inner walls of the first groove U1 and the second groove U2 are in a stepped shape, and the inner wall area of the cavity formed by the first groove U1 and the second groove U2 is increased.

[0162] Exemplarily, referring to Figure 8 , in order to facilitate the formation of the second groove U2, the semiconductor device 10 can further include a second partition 72 embedded in the substrate 11, which is located below the first electrode 21 and the second electrode 22, and avoids the second partition 72 from disconnecting the first electrode 21 or the second electrode 22, and the aforementioned second groove U2 can be opened in the second partition 72.

[0163] Exemplarily, referring to Figure 9 and Figure 10The length (dimension in the second direction Y) of the second recess U2 is smaller than the length of the first recess U1, so as to facilitate the formation of a step between the side walls of the first recess U1 and the second recess U2.

[0164] Referring to Figure 9 and Figure 10 , the part of the channel layer 3 is also arranged on the inner wall of the second recess U2, and the part of the gate 4 is also filled in the second recess U2.

[0165] That is, the channel layer 3 not only covers the inner wall of the first recess U1, but also covers the inner wall of the second recess U2, and the contact area between the gate 4 and the channel layer 3 is increased by the inner wall of the second recess U2 on the second partition 72, so as to improve the control ability of the gate 4 to the channel and further optimize the electrical performance of the semiconductor device 10.

[0166] In some embodiments, referring to Figure 10 , the second recess U2 and the third recess U3 can exist in the semiconductor device 10 at the same time, so as to realize the superposition of the performance optimization of the semiconductor device 10. The characteristics of the second recess U2 and the characteristics of the third recess U3 in this embodiment can refer to the foregoing embodiments, which will not be described here.

[0167] Figure 11 It is a front view of the foregoing Figure 2 , Figure 6 or Figure 8 .

[0168] In some embodiments, referring to Figure 11 , the two opposite side walls of the first recess U1 in the first direction X are recessed towards the direction away from each other.

[0169] That is, the side wall of the first recess U1 can be arc-shaped, so as to increase the area of the inner wall of the first recess U1, so that the area of the channel layer 3 attached to the inner wall of the first recess U1 is also increased, further increasing the path length of the channel formed in the channel layer 3, and optimizing the electrical performance of the semiconductor device 10.

[0170] In some embodiments, referring to Figure 6 , the first electrode 21 and the second electrode 22 each include a conductive layer 2A and a conductive part 2B. That is, the first electrode 21 can include a conductive layer 2A and a conductive part 2B, and the second electrode 22 can also include a conductive layer 2A and a conductive part 2B.

[0171] Wherein, the upper surface of the substrate 11, the first partition 71 and the channel layer 3 can enclose a first cavity Q1, the conductive part 2B is filled in the first cavity Q1, and the conductive layer 2A is arranged between the inner wall of the first cavity Q1 and the conductive part 2B.

[0172] That is, the conductive layer 2A is used to adhere to the surface of the first cavity Q1, and the conductive part 2B is arranged on the side of the conductive layer 2A away from the surface of the first cavity Q1.

[0173] Illustratively, the conductive layer 2A has high conductivity to facilitate ohmic contact with the channel layer 3 and improve the electrical performance of the semiconductor device 10.

[0174] The conductive part 2B is used to externally connect the entire source or drain, so as to facilitate the smooth access of the source signal or drain signal to the semiconductor device 10.

[0175] In this embodiment, the first cavity Q1 surrounded by the upper surface of the substrate 11, the first partition part 71 and the channel layer 3 is used to first adhere the conductive layer 2A for contact with the channel layer 3 to the surface of the first cavity Q1, and then fill the conductive part 2B for external electrical connection in the first cavity Q1, so that the conductive layer 2A can surround the multiple surfaces of the conductive part 2B, thereby increasing the contact area between the part (i.e. the conductive layer 2A) of the first electrode 21 or the second electrode 22 for contact with the channel layer 3 and the part (i.e. the conductive part 2B) for external connection of the source or drain, so that the two have better electrical connection effect, and the electrical performance of the semiconductor device 10 can also be optimized.

[0176] The present application also provides a preparation method of the semiconductor device 10.

[0177] Figure 12 、 Figure 13 、 Figure 14 and Figure 15 Some preparation flowcharts of the semiconductor device 10 provided by the present application, Figures 16-31 are provided for each preparation step of the semiconductor device 10.

[0178] As Figure 12 shown, the preparation method comprises the following steps S1-S4.

[0179] S1: refer to Figure 16 , a sacrificial layer B is covered on the substrate 11.

[0180] The sacrificial layer B is used to replace the conductive structure (the first electrode 21 and the second electrode 22) in the subsequent process, and the space for the subsequent conductive structure is reserved by the sacrificial layer B, which can avoid setting the conductive structure in advance, thereby avoiding damaging the conductive structure in the preparation process of other structures, and also avoiding the diffusion of the conductive material of the conductive structure in the preparation process of other structures, which affects the electrical performance of other structures.

[0181] S2: refer to Figure 18 , a first slot K1 is formed.

[0182] Referring to Figure 18 The first groove K1 extends along the second direction Y, and a sidewall of the first groove K1 extends from a surface of the sacrificial layer B away from the substrate 11 into the substrate 11, i.e., the first groove K1 breaks the sacrificial layer B and continues to etch the substrate 11.

[0183] Referring to Figure 18 The first groove K1 is used to break the sacrificial layer B into a first sacrificial part B1 and a second sacrificial part B2, and is used to remove at least part of the substrate 11. It can be understood that the part of the first groove K1 in the substrate 11 is a first recess U1.

[0184] Referring to Figure 18 The first sacrificial part B1 and the second sacrificial part B2 are separately arranged on two sides of the first recess U1 along the first direction X, and are used to be replaced by the first electrode 21 and the second electrode 22 subsequently.

[0185] The first direction X and the second direction Y are parallel to the substrate 11, and the first direction X intersects the second direction Y.

[0186] S3: Referring to Figure 19 The channel layer 3 and the gate 4 are sequentially formed in the first groove K1.

[0187] Exemplarily, it can be understood that in this step S3, referring to Figure 19 The gate oxide layer 5 is also formed, which is arranged between the gate 4 and the channel layer 3, i.e., the channel layer 3, the gate oxide layer 5 and the gate 4 are sequentially formed in the first groove K1.

[0188] Referring to Figure 19 At least part of the gate 4 is filled in the first recess U1.

[0189] Exemplarily, referring to Figure 19 In this step S3, the gate 4 formed can be filled only in the first recess U1 (the part of the first groove K1 in the substrate 11), and the insulating part 6 is formed above the gate 4, so that the gate 4 and the insulating part 6 jointly fill the first groove K1.

[0190] Or exemplarily, the gate 4 can also completely fill the first groove K1, which can be specifically referred to the corresponding Figure 5 description of the foregoing embodiments.

[0191] Referring to Figure 19 The channel layer 3 is attached to the inner wall of the first groove K1, i.e., at least part of the channel layer 3 is arranged on the inner wall of the first recess U1, and on the opposite side surfaces of the first sacrificial part B1 and the second sacrificial part B2.

[0192] It can be understood that the "opposite sides of the first and second sacrifice portions B1 and B2" herein refer to the side of the first sacrifice portion B1 facing the second sacrifice portion B2, and the side of the second sacrifice portion B2 facing the first sacrifice portion B1.

[0193] S4: Referring to Figures 22-25 , the first sacrifice portion B1 is replaced by the first electrode 21, and the second sacrifice portion B2 is replaced by the second electrode 22.

[0194] Exemplarily, referring to Figure 23 , the first electrode 21 can be an overall conductive structure, and the second electrode 22 is the same.

[0195] Or exemplarily, referring to Figure 25 , the first electrode 21 and the second electrode 22 can each include a conductive portion 2B and a conductive layer 2A partially surrounding the conductive portion 2B.

[0196] Through the above steps S1-S4, at least one semiconductor device 10 described in the foregoing embodiments, which has a longer channel path and a larger contact area between the source (or drain) and the channel layer 3, can be prepared. The technical effects corresponding to the preparation steps can be referred to the effect description of the semiconductor device 10 in the foregoing embodiments, which will not be described here.

[0197] In some embodiments, the foregoing step S4 can include the following steps S41 and S44:

[0198] S41: Referring to Figure 22 , the first sacrifice portion B1 and the second sacrifice portion B2 are removed to form a plurality of first cavities Q1.

[0199] Referring to Figure 22 , the first cavity Q1 is surrounded by the upper surface of the substrate 11, the first partition portion 71, and the channel layer 3.

[0200] S44: Referring to Figure 23 , the first cavity Q1 is filled with a conductive structure to form the first electrode 21 and the second electrode 22.

[0201] Or in some embodiments, as Figure 13 shown, the foregoing step S4 can include the following steps S41-S43:

[0202] S41: Referring to Figure 22 , the first sacrifice portion B1 and the second sacrifice portion B2 are removed to form a plurality of first cavities Q1.

[0203] S42: Referring to Figure 24 , a conductive layer 2A is formed on the inner wall of the first cavity Q1.

[0204] S43: refer to Figure 25 , the conductive part 2B is filled in the first cavity Q1, and the conductive layer 2A is arranged between the inner wall of the first cavity Q1 and the conductive part 2B.

[0205] Refer to Figure 25 , the conductive part 2B is filled in the first cavity Q1, and the conductive layer 2A is arranged between the inner wall of the first cavity Q1 and the conductive part 2B.

[0206] Through the embodiment, the conductive layer 2A can surround the multiple surfaces of the conductive part 2B, thereby increasing the contact area between the part (i.e. the conductive layer 2A) of the first electrode 21 or the second electrode 22 used for contacting the channel layer 3 and the part (i.e. the conductive part 2B) used for realizing the external connection of the source or the drain, so that the two parts have better electrical connection effect, and the electrical performance of the semiconductor device 10 can also be optimized.

[0207] In some embodiments, as shown in Figure 14 , after step S1 and before step S2, the preparation method further comprises:

[0208] S5: refer to Figure 17 , the second slot K2 is opened, and the first partition part 71 is filled in the second slot K2.

[0209] Refer to Figure 17 , the first partition part 71 extends along the first direction X, and the first partition part 71 can disconnect the sacrificial layer B.

[0210] For example, refer to Figure 17 , the first partition part 71 is used to disconnect the sacrificial layer B into two parts, and the two parts are used to form the first electrode 21 and the second electrode 22 in different transistors T (see Figure 23 ).

[0211] The first partition part 71 is also used to realize the insulation between the transistors T arranged adjacent to each other along the second direction Y in the subsequent steps.

[0212] Refer to Figure 17 , the first partition part 71 also disconnects at least part of the substrate 11.

[0213] For example, the first partition part 71 can completely disconnect the substrate 11 (see Figure 17 ), or can disconnect the substrate 11 to the target position of the substrate 11, for example, the bottom surface of the first partition part 71 can be to the position of the groove bottom of the first groove U1 formed subsequently, and the embodiment of the present application only exemplarily illustrates the structure of the first partition part 71 completely disconnecting the substrate 11, and is not limited to the formation of the structure.

[0214] For example, the material of the first partition part 71 has electrical insulation.

[0215] Exemplarily, the material of the first partition 71 is different from the material of the substrate 11, so that the first partition 71 and the substrate 11 can be etched respectively subsequently.

[0216] Exemplarily, referring to Figure 14 , the steps S2 and S3 can be continued after the step S5, referring to Figure 18 , in the case of setting the first partition 71, in the step S2, the first slot K1 also disconnects at least part of the first partition 71, and the part of the first slot K1 in the first partition 71 is the third groove U3.

[0217] As Figure 14 shown, after the step S3, the preparation method further comprises the following steps S6 and S7:

[0218] S6: referring to Figure 20 , removing the first partition 71 and the part of the channel layer 3 exposed after removing the first partition 71, so as to disconnect the two channel layers 3 corresponding to the two transistors T arranged adjacent along the second direction Y.

[0219] Exemplarily, the first partition 71 can be removed first, so as to expose the part of the channel layer 3 between the two transistors T arranged adjacent along the second direction Y, and then the part of the channel layer 3 is removed, so as to realize the disconnection of the channel layers 3 of the two transistors T.

[0220] S7: referring to Figure 21 , filling the first partition 71 again, so as to realize the electrical insulation between the two transistors T arranged adjacent along the second direction Y.

[0221] It can be understood that, referring to Figure 21 , in the step S7, the gate 4 and the gate oxide layer 5 are not disconnected, and the gate 4 and the gate oxide layer 5 pass through the first partition 71, so that the two transistors T arranged adjacent along the second direction Y can share the gate 4.

[0222] Through the embodiment, the semiconductor device 10 with multiple transistors T can be prepared, and especially the multiple transistors T arranged in the second direction Y and sharing the gate 4 can be prepared.

[0223] In some embodiments, as Figure 14 shown, in the case of setting the first partition 71, after the step S2 and before the step S3, the preparation method can further comprise:

[0224] S8: referring to Figure 26 and Figure 27 , continuing to etch the part of the first slot K1 belonging to the first partition 71, so that the groove bottom U3' (referring to Figure 27) the bottom U1' of the first groove U1 (see Figure 27 ), closer to the side surface (i.e. bottom surface) of the substrate 11 away from the first sacrificial part B1.

[0225] wherein, Figure 27 is Figure 26 a sectional view of the section line D-D' in Figure 27 , the first sacrificial part B1, the part of the substrate 11 for forming the sidewall of the first groove U1, and the first partition part 71, etc. structures in this cross section are schematically shown in the form of a dashed line box, it can be understood that the structure shown by the dashed line box is hollowed out at the position, the whole hollowed out is used to form the first slot K1.

[0226] Figure 28 To increase step S8, on the basis of Figure 27 , after filling the channel layer 3 and the gate 4 structure (i.e. step S4) corresponding to a kind of sectional view.

[0227] Referring to Figure 28 , through this embodiment, the semiconductor device 10 prepared by can make, the channel layer 3 not only adheres to the inner wall of the first groove U1, but also adheres to the sidewall of the third groove U3, so as to increase the width (perpendicular to the path length of the channel) of the channel layer 3, improve the on-off ratio of the semiconductor device 10, also increase the contact area of the gate 4 and the channel layer 3, so as to improve the control ability of the gate 4 to the channel, further optimize the electrical performance of the semiconductor device 10.

[0228] In some embodiments, as Figure 15 shown, before step S1, the preparation method can further include:

[0229] S9: referring to Figure 29 , forming a second partition part 72 in the substrate 11.

[0230] That is, before covering the sacrificial layer B, the second partition part 72 is embedded in the substrate 11, so that after step S1 (see Figure 29 ), the sacrificial layer B can cover the second partition part 72, avoid the second partition part 72 like the first partition part 71 to break off the sacrificial layer B.

[0231] Referring to Figure 29 , the second partition part 72 extends along the first direction X, and breaks at least part of the substrate 11, the figure is taken as an example to schematically show that the second partition part 72 completely breaks the substrate 11.

[0232] Exemplarily, the material of the second partition part 72 can be consistent with the material of the first partition part 71.

[0233] Exemplarily, referring toFigure 15 Steps S2 and S3 can be performed after step S1. In the case of setting the second partition 72, in step S2, the first slot K1 also disconnects at least a portion of the second partition 72. The portion of the first slot K1 located in the second partition 72 is the second groove U2. Here, the structure of the second partition 72 is similar to the structure of the first partition 71. Please refer to the foregoing description and schematic diagram of the first partition 71. It will not be repeated here.

[0234] Based on this, such as Figure 15 As shown, after step S2 and before step S3, the preparation method may further include:

[0235] S10: See Figure 30 Continue etching the portion of the first groove K1 that belongs to the second partition 72, so that the bottom U2' of the second groove U2 is closer to the side surface (i.e. the bottom surface) of the substrate 11 away from the first sacrificial portion B1, relative to the bottom U1' of the first groove U1.

[0236] Understandable, Figure 30 and Figure 27 For cross-sectional views at the same location, regarding Figure 30 The characteristics can be referenced to the Figure 26 and Figure 27 The description will not be repeated here.

[0237] Figure 31 After adding steps S9 and S10, in Figure 30 A cross-sectional view corresponding to the filling of the channel layer 3 and gate 4 and other structures (i.e., step S4) on the basis of the foundation.

[0238] See Figure 31 Through this embodiment, the channel layer 3 in the prepared semiconductor device 10 can be attached not only to the inner wall of the first groove U1, but also to the side wall of the second groove U2. This can increase the width of the channel layer 3 (the length perpendicular to the channel path), improve the switching ratio of the semiconductor device 10, increase the contact area between the gate 4 and the channel layer 3, improve the gate 4's control over the channel, and further optimize the electrical performance of the semiconductor device 10.

[0239] For example, Figure 14 and Figure 15 Some of the fabrication steps shown can be performed simultaneously. For example, step S8 can be performed simultaneously with step S10, that is, the second groove U2 and the third groove U3 are etched simultaneously, so that the second groove U2 with a greater depth (relative to the depth of the first groove U1) and the third groove U3 with a greater depth can be formed, thereby achieving the cumulative optimization of the electrical performance of the semiconductor device 10.

[0240] Of course, it is understood that the steps shown can also be performed individually Figure 15 to form a semiconductor device 10 as shown in Figure 9 .

[0241] Exemplarily, the preparation method can further include other steps, for example, after step S2, the part of the substrate 11 belonging to the side wall of the first recess U1 is etched again, so that the side wall of the first recess U1 is recessed towards the direction away from each other, forming a semiconductor device 10 as shown in Figure 11 , further optimizing the electrical performance of the semiconductor device 10.

[0242] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: The substrate has a first groove; The first electrode and the second electrode are disposed on the substrate and are respectively disposed on both sides of the first groove along the first direction; The first direction is parallel to the substrate; The channel layer is at least partially disposed on the inner wall of the first groove and on the opposite sides of the first electrode and the second electrode; The gate is at least partially filled in the first groove.

2. The semiconductor device according to claim 1, characterized in that, The gate includes an integrally formed first sub-part and a second sub-part, the first sub-part being filled in the first groove, and the second sub-part being filled between the first electrode and the second electrode.

3. The semiconductor device according to claim 1, characterized in that, The surface of the gate that is away from the bottom of the first groove is closer to the bottom of the first groove than the surfaces of the first electrode and the second electrode that face the substrate.

4. The semiconductor device according to claim 3, characterized in that, Also includes: An insulating portion is disposed on the side of the gate away from the bottom of the first groove, and at least a portion of the insulating portion fills the space between the first electrode and the second electrode.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The substrate further includes a second groove, which is disposed at the bottom of the first groove; A portion of the channel layer is also disposed on the inner wall of the second groove; a portion of the gate is also filled in the second groove.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The two opposite sidewalls of the first groove in the first direction are recessed in a direction that moves away from each other.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The device includes multiple transistors, each transistor comprising the substrate, a first electrode, a second electrode, the channel layer, and the gate; the multiple transistors are arranged in an array along a first direction and a second direction; the second direction is parallel to the substrate and intersects the first direction; In this configuration, at least two transistors arranged adjacent to each other along the first direction share the second electrode.

8. The semiconductor device according to claim 7, characterized in that, Also includes: A first partition is provided between two transistors that are adjacent to each other along the second direction; In this configuration, the gates of at least two transistors arranged adjacent to each other along the second direction pass through the first partition and are electrically connected to each other. The channel layers, the first electrodes, and the second electrodes of the at least two transistors arranged adjacent to each other along the second direction are electrically insulated from each other by the first partition.

9. The semiconductor device according to claim 8, characterized in that, The first partition portion includes a third groove, which is disposed between two adjacent first grooves arranged along the second direction and communicates with the first groove; the bottom of the third groove is closer to the side surface of the substrate away from the first electrode than the bottom of the first groove. The gate portion is also filled in the third groove, and the gates of at least two transistors arranged adjacent to each other along the second direction pass through the third groove and penetrate the first partition portion; the channel layer portion is also disposed on two opposite sidewalls of the third groove in the second direction.

10. The semiconductor device according to claim 8 or 9, characterized in that, Both the first electrode and the second electrode include a conductive layer and a conductive portion; The upper surface of the substrate, the first partition portion, and the channel layer form a first chamber, the conductive portion is filled in the first chamber, and the conductive layer is disposed between the inner wall of the first chamber and the conductive portion.

11. A method for fabricating a semiconductor device, characterized in that, include: A sacrificial layer is deposited on the substrate; Form the first groove; The first slot extends along a second direction, and the sidewall of the first slot extends from the surface of the sacrificial layer away from the substrate into the substrate; the first slot divides the sacrificial layer into a first sacrificial portion and a second sacrificial portion, and the portion of the first slot located in the substrate is a first groove; the first sacrificial portion and the second sacrificial portion are respectively disposed on both sides of the first groove along a first direction; the first direction and the second direction are parallel to the substrate, and the first direction intersects the second direction; A channel layer and a gate are sequentially formed in the first groove; at least a portion of the channel layer is disposed on the inner wall of the first groove and on the opposite sides of the first sacrificial portion and the second sacrificial portion; at least a portion of the gate is filled in the first groove; The first sacrificial part is replaced with the first electrode, and the second sacrificial part is replaced with the second electrode.

12. The preparation method according to claim 11, characterized in that, After the sacrificial layer is deposited on the substrate, and before the first trench is formed, the process further includes: A second slot is formed, and a first partition portion is filled in the second slot; the first partition portion extends along the first direction, and the first partition portion disconnects the sacrificial layer and disconnects at least a portion of the substrate; Wherein, the first slot also disconnects at least a portion of the first partition portion, and the portion of the first slot located in the first partition portion is a third groove; After the channel layer and the gate are sequentially formed in the first slot, the method further includes: Remove the first partition portion and the portion of the channel layer exposed after removing the first partition portion; The first partition is then filled again.

13. The preparation method according to claim 12, characterized in that, After the first slot is formed, and before the channel layer and the gate are sequentially formed in the first slot, the method further includes: Continue etching the portion of the first groove that belongs to the first partition, so that the bottom of the third groove is closer to the side surface of the substrate away from the first sacrificial portion, relative to the bottom of the first groove.

14. The preparation method according to any one of claims 11 to 13, characterized in that, Before covering the sacrificial layer on the substrate, the following steps are also included: A second partition portion is formed in the substrate; the second partition portion extends along the first direction and disconnects at least a portion of the substrate; Wherein, after the sacrificial layer is formed, the sacrificial layer covers the second partition portion; the first slot also disconnects at least a portion of the second partition portion, and the portion of the first slot located in the second partition portion is a second groove; After the first slot is formed, and before the channel layer and the gate are sequentially formed in the first slot, the method further includes: Continue etching the portion of the first groove that belongs to the second partition, so that the bottom of the second groove is closer to the side surface of the substrate away from the first sacrificial portion, relative to the bottom of the first groove.

15. The preparation method according to any one of claims 12 to 14, characterized in that, Both the first electrode and the second electrode include a conductive layer and a conductive portion; The step of replacing the first sacrificial portion with the first electrode and replacing the second sacrificial portion with the second electrode includes: The first sacrificial portion and the second sacrificial portion are removed to form a plurality of first chambers; the upper surface of the substrate, the first partition portion, and the channel layer surround the first chambers; The conductive layer is formed on the inner wall of the first chamber; The conductive portion is formed; the conductive portion is filled in the first cavity, and the conductive layer is disposed between the inner wall of the first cavity and the conductive portion.

16. An integrated circuit, characterized in that, include: The semiconductor device as described in any one of claims 1 to 10; Electronic devices, electrically connected to the semiconductor devices.

17. An electronic device, characterized in that, include: The integrated circuit as described in claim 16; A circuit board, on which the integrated circuit is disposed.

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