Gallium nitride high-electron-mobility transistor integrated with Schottky diode and preparation method of gallium nitride high-electron-mobility transistor

Abstract

The invention belongs to the field of semiconductor devices, provides a gallium nitride high-electron-mobility transistor integrated with a Schottky diode and a preparation method of the gallium nitride high-electron-mobility transistor, and aims to solve the problem that a conventional gallium nitride high-electron-mobility transistor (GaN HEMT) lacks a body diode. According to the invention, monolithic integration of the SBD and the GaN HEMT is realized through structural design, a low-impedance path is provided for reverse current, and the integration mode not only retains the original high performance characteristic of a GaN device, but also additionally endows the GaN device with reverse conduction and reverse recovery capabilities; moreover, through the structural design, the SBD can be synchronously completed on the basis of the existing GaN HEMT process, a special process or new equipment is not needed, and the cost is effectively controlled while the performance improvement is ensured; compared with an external interconnection diode scheme, parasitic inductance caused by lead bonding is eliminated, the voltage overshoot and ringing phenomena in the switching process are remarkably reduced, high-frequency switching application is facilitated, and switching loss can be greatly reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor devices, specifically relating to a device design that integrates a Schottky diode (SBD) in a gallium nitride high electron mobility transistor (GaNHEMT) structure, to solve the problem of reverse conduction loss caused by the lack of a body diode in traditional GaN devices. Background Technology

[0002] In the field of power electronics, gallium nitride high electron mobility transistors (GaN HEMTs) have attracted much attention due to their excellent material properties. Compared with traditional silicon-based power devices, GaN HEMTs have higher electron mobility, larger breakdown electric field, and lower on-resistance, making them highly promising for high-voltage and high-frequency applications. However, GaN HEMTs have a significant structural defect: the lack of an inherent body diode. This characteristic is naturally present in silicon-based MOSFETs, where the body PN junction diode provides a conduction path under reverse bias conditions. Due to the physical properties of the material itself and the limitations of the device structure, GaN HEMTs cannot form a similar structure. This structural deficiency brings many challenges to practical applications.

[0003] In power conversion circuits, when a device is in reverse operation, current cannot flow through the device itself. An externally connected Schottky barrier diode (SBD) is necessary to achieve reverse conduction. While this external diode solution achieves the basic function, it introduces new problems: First, the additional discrete components not only increase the system's size and weight but also introduce significant parasitic inductance. These parasitic parameters can cause voltage overshoot and ringing during high-frequency switching, severely affecting system stability and efficiency. Second, discrete diodes themselves have forward voltage drops and reverse recovery charges, both of which cause additional power losses and reduce the overall system efficiency.

[0004] To address these challenges, researchers have explored various alternatives. One common approach is to utilize the two-dimensional electron gas (2DEG) channels inherent in GaNHEMTs to achieve reverse conduction. However, this method typically results in a high on-state voltage drop, leading to significant conduction losses. Another approach is to simulate diode functionality through specialized gate drive strategies; however, this often requires complex control circuitry, increasing system complexity and compromising reliability. Furthermore, some studies have attempted to integrate reverse conduction functionality during GaN HEMT fabrication, but these methods typically require complex process adjustments or sacrifice forward performance.

[0005] As power electronic systems increasingly demand higher power density and efficiency, the limitations of existing solutions are becoming more apparent, especially in high-frequency applications where the parasitic effects and losses caused by discrete diodes become more severe. Therefore, developing a solution that can efficiently integrate reverse conduction functionality within GaN HEMTs is crucial for promoting the application of wide-bandgap semiconductor devices. This solution can not only simplify system design and reduce manufacturing costs but also significantly improve power conversion efficiency, meeting the future demands of power electronic systems for high-performance devices. Summary of the Invention

[0006] The purpose of this invention is to provide a gallium nitride high electron mobility transistor (GaN HEMT) with an integrated Schottky diode and its fabrication method, thereby solving the problem of the lack of a body diode in traditional GaN HEMTs. This invention achieves simultaneous fabrication and integration of the GaN HEMT and the GaN Schottky diode through an integrated design, enabling the reverse recovery current of the GaN HEMT to flow out through the SBD in the reverse conduction state, thus achieving low-loss reverse conduction functionality.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A gallium nitride high electron mobility transistor with integrated Schottky diode, comprising: a substrate layer 1-1, a buffer layer 1-2, a GaN channel layer 1-3, an AlGaN barrier layer 1-4, a P-GaN layer 1-5, a HEMT gate 1-6, a HEMT source 1-7, a HEMT drain 1-8, an SBD anode 1-9, and an implantation isolation region 1-10; characterized in that:

[0009] The substrate, buffer layer, GaN channel layer, and AlGaN barrier layer are arranged in order from bottom to top; the HEMT source and HEMT drain are arranged on the GaN channel layer and both form ohmic contact with the GaN channel layer. The HEMT source and HEMT drain are arranged vertically and located on the left and right sides of the AlGaN barrier layer. The HEMT drain also serves as the SBD cathode.

[0010] A P-GaN layer is disposed on an AlGaN barrier layer and patterned to form a HEMT region and an SBD region arranged side by side along a vertical direction. The HEMT region includes a first P-GaN thick layer and a first P-GaN thin layer. The first P-GaN thick layer is disposed along a vertical direction and a HEMT gate is disposed thereon. The first P-GaN thin layer is disposed along a horizontal direction and together with the first P-GaN thick layer, it forms a T-shaped extension from the HEMT source to the HEMT drain. The SBD region includes a second P-GaN thin layer and a third P-GaN thin layer. The second P-GaN thin layer is disposed along a vertical direction and an SBD anode is disposed thereon. The third P-GaN thin layer is disposed along a horizontal direction and together with the second P-GaN thin layer, it forms a T-shaped extension from the SBD anode to the diode cathode.

[0011] The left side of the SBD anode is connected to the HEMT source, and the right side forms a Schottky contact with the second P-GaN thin layer; the HEMT gate and the SBD anode are isolated by an implanted isolation region.

[0012] A gallium nitride high electron mobility transistor with integrated Schottky diode, comprising: a substrate layer 1-1, a buffer layer 1-2, a GaN channel layer 1-3, an AlGaN barrier layer 1-4, a P-GaN layer 1-5, a HEMT gate 1-6, a HEMT source 1-7, a HEMT drain 1-8, an SBD anode 1-9, an implantation isolation region 1-10, and an SBD control gate 1-11; characterized in that:

[0013] The substrate, buffer layer, GaN channel layer, and AlGaN barrier layer are arranged in order from bottom to top; the HEMT source and HEMT drain are arranged on the GaN channel layer and both form ohmic contact with the GaN channel layer. The HEMT source and HEMT drain are arranged vertically and located on the left and right sides of the AlGaN barrier layer. The HEMT drain also serves as the SBD cathode.

[0014] A P-GaN layer is disposed on an AlGaN barrier layer and patterned to form a HEMT region and an SBD region arranged side by side along a vertical direction. The HEMT region includes a first P-GaN thick layer and a first P-GaN thin layer. The first P-GaN thick layer is disposed vertically and has a HEMT gate disposed thereon. The first P-GaN thin layer is disposed laterally and together with the first P-GaN thick layer forms a T-shaped extension from the HEMT source to the HEMT drain. The SBD region includes a second P-GaN thin layer, a second P-GaN thick layer, and a third P-GaN thin layer. The second P-GaN thin layer is disposed vertically and has an SBD anode disposed thereon. The second P-GaN thick layer is disposed vertically and has an SBD control gate disposed thereon. The third P-GaN thin layer is disposed laterally and together with the second P-GaN thick layer forms a T-shaped extension from the SBD anode to the diode cathode.

[0015] The left side of the SBD anode is connected to the HEMT source, and the right side forms a Schottky contact with the second P-GaN thin layer; the HEMT gate and the SBD anode, as well as the HEMT gate and the SBD control gate, are isolated by implanted isolation regions;

[0016] The gate of the HEMT is connected to the anode of the external diode D, the source of the HEMT is connected to the input terminal of the external capacitor C, and the output terminal of the external capacitor C and the cathode of the external diode D are both connected to the SBD control gate.

[0017] A gallium nitride high electron mobility transistor with integrated Schottky diode, comprising: a substrate layer 1-1, a buffer layer 1-2, a GaN channel layer 1-3, an AlGaN barrier layer 1-4, a P-GaN layer 1-5, a HEMT gate 1-6, a HEMT source 1-7, a HEMT drain 1-8, and an SBD anode 1-9; characterized in that:

[0018] The substrate, buffer layer, GaN channel layer, and AlGaN barrier layer are arranged in order from bottom to top; the HEMT source, HEMT drain and SBD anode are arranged in order from left to right on the GaN channel layer and all form ohmic contact with the GaN channel layer. The HEMT drain also serves as the SBD cathode.

[0019] A P-GaN layer is disposed on an AlGaN barrier layer and patterned to form a HEMT region and an SBD region arranged laterally. The HEMT region is located between the HEMT source and the HEMT drain and includes a first P-GaN thick layer and a first P-GaN thin layer. The first P-GaN thick layer is arranged vertically and has the HEMT gate disposed thereon. The first P-GaN thin layer is arranged laterally and together with the first P-GaN thick layer forms a T-shaped extension from the HEMT source to the HEMT drain. The SBD region is located between the HEMT drain and the SBD anode and includes a second P-GaN thin layer and a third P-GaN thin layer. The second P-GaN thin layer is arranged vertically and the third P-GaN thin layer is arranged laterally and together with the second P-GaN thin layer forms a T-shaped extension from the SBD anode to the diode cathode. The SBD anode and the second P-GaN thin layer form a Schottky contact, and the HEMT source and the SBD anode are connected at the layout termination.

[0020] Furthermore, in the above three devices, the thickness of each P-GaN thick layer is the same, specifically 60nm to 100nm; the thickness of each P-GaN thin layer is the same, specifically 30nm to 50nm.

[0021] Furthermore, in the above three types of devices, the substrate is a SiC, Si, sapphire, or diamond substrate.

[0022] Furthermore, in the above three types of devices, the device surface is covered with a passivation layer, which is a Si3N4 material layer.

[0023] A method for fabricating a gallium nitride high electron mobility transistor with an integrated Schottky diode includes the following steps:

[0024] S1: The substrate is cleaned and annealed, and then the buffer layer, GaN channel layer, AlGaN barrier layer and P-GaN layer are grown sequentially by epitaxial process, and impurities are activated by annealing.

[0025] S2: The P-GaN layer is patterned using photolithography, and then the P-GaN layer is etched to form the patterned HEMT region and SBD region by dry etching. The etching process is divided into two stages: the first stage is to etch to form a P-GaN thick layer of the same thickness, and the second stage is to thin the corresponding P-GaN thin layer region.

[0026] S3: Ion implantation technology is used to implant isolation between the HEMT gate and the SBD anode, followed by annealing.

[0027] S4: The AlGaN barrier layer is etched to form the HEMT source, HEMT drain, and SBD anode window, and a multilayer metal is formed through a deposition process. The patterned electrode is then stripped to form a patterned electrode. After deposition, alloying annealing is performed to make the metal and semiconductor form an ohmic contact.

[0028] S5: Deposit metal in the HEMT gate and SBD control gate regions to form corresponding electrode layers.

[0029] Based on the above technical solution, the beneficial effect of the present invention is that it provides a gallium nitride high electron mobility transistor with integrated Schottky diode, which has the following advantages:

[0030] 1. This invention fundamentally solves the inherent problem of GaN power devices lacking a body diode. Through structural design, it achieves monolithic integration of SBD and GaN HEMT, providing a low-impedance path for reverse current and perfectly replacing the traditional external diode solution. This integration method not only retains the original high-performance characteristics of GaN devices, but also additionally endows them with reverse conduction capability.

[0031] 2. This invention enables SBD to be completed simultaneously on the basis of existing GaN HEMT processes through structural design, without the need for special processes or new equipment, effectively controlling costs while ensuring performance improvement;

[0032] 3. The GaN HEMT device involved in this invention extends the P-GaN layer from the gate to the drain in a T-shape, which can uniformly distribute the electric field between the gate and drain, reduce the peak electric field, and improve the device breakdown voltage. At the same time, the extended P-GaN layer can also inject holes into the channel when the device is turned on to suppress the current collapse effect.

[0033] 4. The SBD device involved in this invention extends the P-GaN layer in a T-shape from the anode to the cathode. During reverse breakdown, it can attract some electric field lines, reduce the peak electric field between the anode and the cathode, and improve the breakdown voltage of the device. At the same time, the thick P-GaN layer can also suppress leakage current and reduce device loss.

[0034] 5. Compared with external interconnect diode solutions, the present invention integrates SBD in GaN HEMT to eliminate parasitic inductance caused by wire bonding, significantly reducing voltage overshoot and ringing during switching. The characteristics of Schottky contact make reverse recovery charge almost zero, which is particularly beneficial for high-frequency switching applications and can greatly reduce switching losses. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the gallium nitride high electron mobility transistor with vertically monolithically integrated Schottky diode in Example 1;

[0036] Figure 2 This is a schematic diagram of the gallium nitride high electron mobility transistor with vertically monolithically integrated Schottky diode in Example 2;

[0037] Figure 3 This is a schematic diagram of the gallium nitride high electron mobility transistor with a laterally monolithically integrated Schottky diode in Example 3;

[0038] The diagram is labeled as follows: 1-1, Substrate layer; 1-2, Buffer layer; 1-3, GaN channel layer; 1-4, AlGaN barrier layer; 1-5, P-GaN layer; 1-6, Gate; 1-7, Source; 1-8, Drain / Cathode; 1-9, Diode anode; 1-10, Implantation isolation region; 1-11, Control gate. Detailed Implementation

[0039] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0040] Example 1

[0041] This embodiment provides a gallium nitride high electron mobility transistor (GaN HEMT) with a vertically integrated monolithic Schottky diode (SBD), the structure of which is as follows: Figure 1 As shown, according to Figure 1The view defines the left-right direction as horizontal and the front-back direction as vertical; the gallium nitride high electron mobility transistor specifically includes: substrate layer 1-1, buffer layer 1-2, GaN channel layer (unintentionally doped GaN layer) 1-3, AlGaN barrier layer 1-4, P-GaN layer 1-5, HEMT gate 1-6, HEMT source 1-7, HEMT drain 1-8, SBD anode 1-9, and implanted isolation region 1-10; wherein:

[0042] The substrate 1-1 is a SiC, Si, sapphire, or diamond substrate. The substrate 1-1, buffer layer 1-2, GaN channel layer 1-3, and AlGaN barrier layer 1-4 are arranged in order from bottom to top. The HEMT source 1-7 and HEMT drain 1-8 are disposed on the GaN channel layer 1-3 and both form ohmic contacts with the GaN channel layer 1-3. The HEMT source 1-7 and HEMT drain 1-8 are both arranged vertically and located on the left and right sides of the AlGaN barrier layer 1-4. The HEMT drain 1-8 also serves as the SBD cathode.

[0043] P-GaN layers 1-5 are disposed on AlGaN barrier layers 1-4 and are patterned to form HEMT and SBD regions arranged side by side along the vertical direction. The HEMT region includes a first P-GaN thick layer (thickness 60nm~100nm) and a first P-GaN thin layer (thickness 30nm~50nm). The first P-GaN thick layer is disposed along the vertical direction and a HEMT gate 1-6 is disposed thereon. The first P-GaN thin layer is disposed along the horizontal direction and together with the first P-GaN thick layer forms a T-shaped extension from the HEMT source 1-7 to the HEMT drain 1-8. The SBD region includes a second P-GaN thin layer and a third P-GaN thin layer. The second P-GaN thin layer is disposed along the vertical direction and an SBD anode 1-9 is disposed thereon. The third P-GaN thin layer is disposed along the horizontal direction and together with the second P-GaN thin layer forms a T-shaped extension from the SBD anode to the diode cathode.

[0044] The left side of the SBD anode 1-9 is connected to the HEMT source 1-7, and the right side forms a Schottky contact with the second P-GaN thin layer. The HEMT gate 1-6 and the SBD anode 1-9 are isolated by the injection isolation region 1-10, while other extended regions in the P-GaN layer 1-5 are not injected and isolated, which can maximize the retention of the device's forward conduction current capability.

[0045] Furthermore, the entire surface of the device is covered with a passivation layer, which is a Si3N4 material layer.

[0046] The working principle of this embodiment is as follows:

[0047] In this embodiment, the GaN HEMT device conducts electricity through a two-dimensional electron gas (2DEG) formed by polarization, creating an electron channel from the source 1-7 to the drain 1-8. This structure achieves a positive threshold voltage by depleting the 2DEG concentration below the gate 1-6 through the P-GaN layer 1-5 below the gate 1-6, thus reducing reverse conduction losses. When the potential difference between the gate 1-6 and the source 1-7 is less than the device's threshold voltage, the 2DEG below the gate 1-6 is depleted, the current path is turned off, and the device is in a blocking state. When the GaN HEMT transitions from the conducting state to the reverse conducting state, the drain voltage of the HEMT is lower than the source voltage. Since the anode of the SBD is at the same potential as the source of the HEMT, the SBD is in a forward conducting state at this time, and the reverse recovery current flows out from the electrode through the SBD, providing a reverse current path for the GaN HEMT. Meanwhile, a T-shaped extension based on P-GaN layer 1-5 is provided between the gate and drain, which can uniformly distribute the electric field between the gate and drain when the device is turned off, reduce the peak electric field, and provide the device breakdown voltage; and P-GaN layer 1-5 will also inject holes into the channel when the device is turned on, suppressing the current collapse effect.

[0048] Example 2

[0049] This embodiment provides a gallium nitride high electron mobility transistor (GaN HEMT) with a vertically integrated monolithic Schottky diode (SBD). Based on Embodiment 1, a control gate is introduced to form a controllable electron channel within the SBD structure. Through the clamping effect of an external capacitor voltage, the conduction state of the SBD is intelligently adjusted in both forward and reverse operating modes, thereby optimizing the forward conduction and reverse recovery characteristics of the GaN HEMT and reducing switching losses and reverse conduction voltage. The gallium nitride high electron mobility transistor is as follows: Figure 2 As shown, it specifically includes: substrate layer 1-1, buffer layer 1-2, GaN channel layer (unintentionally doped GaN layer) 1-3, AlGaN barrier layer 1-4, P-GaN layer 1-5, HEMT gate 1-6, HEMT source 1-7, HEMT drain 1-8, SBD anode 1-9, implanted isolation region 1-10, and SBD control gate 1-11; wherein:

[0050] The substrate 1-1 is a SiC, Si, sapphire, or diamond substrate. The substrate 1-1, buffer layer 1-2, GaN channel layer 1-3, and AlGaN barrier layer 1-4 are arranged in order from bottom to top. The HEMT source 1-7 and HEMT drain 1-8 are disposed on the GaN channel layer 1-3 and both form ohmic contacts with the GaN channel layer 1-3. The HEMT source 1-7 and HEMT drain 1-8 are both arranged vertically and located on the left and right sides of the AlGaN barrier layer 1-4. The HEMT drain 1-8 also serves as the SBD cathode.

[0051] P-GaN layers 1-5 are disposed on AlGaN barrier layers 1-4 and patterned to form HEMT and SBD regions arranged side-by-side along the vertical direction. The HEMT region includes a first thick P-GaN layer (thickness 60nm~100nm) and a first thin P-GaN layer (thickness 30nm~50nm). The first thick P-GaN layer is disposed vertically and has HEMT gate 1-6 disposed thereon. The first thin P-GaN layer is disposed laterally and together with the first thick P-GaN layer constitutes a structure consisting of H... The EMT source 1-7 extends in a T-shape to the HEMT drain 1-8; the SBD region includes: a second P-GaN thin layer, a second P-GaN thick layer and a third P-GaN thin layer, the second P-GaN thin layer is arranged in the longitudinal direction and the SBD anode 1-9 is arranged thereon, the second P-GaN thick layer is arranged in the longitudinal direction and the SBD control gate 1-11 is arranged thereon, the third P-GaN thin layer is arranged in the transverse direction and together with the second P-GaN thick layer forms a T-shaped extension from the SBD anode to the diode cathode;

[0052] The left side of the SBD anode 1-9 is connected to the HEMT source 1-7, and the right side forms a Schottky contact with the second P-GaN thin layer. The HEMT gate 1-6 and the SBD anode 1-9, as well as the HEMT gate 1-6 and the SBD control gate 1-11, are isolated by the injection isolation region 1-10. Other extended regions in the P-GaN layer 1-5 are not injected and isolated, which can maximize the retention of the device's forward conduction current capability.

[0053] HEMT gate 1-6 is connected to the anode of external diode D, HEMT source 1-7 is connected to the input terminal of external capacitor C, and the output terminal of external capacitor C and the cathode of external diode D are both connected to SBD control gate 1-11.

[0054] Furthermore, the entire surface of the device is covered with a passivation layer, which is a Si3N4 material layer.

[0055] The working principle of this embodiment is as follows:

[0056] In this embodiment, the GaN HEMT device conducts electricity through a two-dimensional electron gas (2DEG) formed by polarization, creating an electron channel from source 1-7 to drain 1-8. This structure achieves a positive threshold voltage by depleting the 2DEG concentration below gate 1-6 through the P-GaN layer 1-5 below gate 1-6, thus reducing reverse conduction losses. When the potential difference between gate 1-6 and source 1-7 is less than the device's threshold voltage, the 2DEG below gate 1-6 is depleted, the current path is turned off, and the device is in a blocking state. During forward conduction of the GaN HEMT, the external capacitor C is charged through the external diode D. When the external capacitor C is fully charged, the potential of control gate 1-11 is clamped at V. G-0.7V opens the channel between the control gate 1-11 and the cathode in the SBD, further increasing the forward conduction current of the GaN HEMT. When the GaN HEMT is in reverse conduction, the control gate 1-11 remains clamped at V. G At -0.7V, since the anode of the SBD is at the same potential as the source of the HEMT, and the cathode is at the same potential as the drain of the HEMT, the SBD is turned on. The reverse recovery current flows out from the electrode through the SBD, providing a reverse current path for the GaN HEMT. Therefore, the control gate 1-11 dynamically controls the conduction state of the Schottky diode by voltage-modulating the two-dimensional electron gas (2DEG) channel formed in the SBD. This enhances the current capability during forward conduction and provides a low-loss path during reverse recovery, improving the overall efficiency and reliability of the device.

[0057] Example 3

[0058] This embodiment provides a gallium nitride high electron mobility transistor (GaN HEMT) with a laterally monolithically integrated Schottky diode (SBD), the structure of which is as follows: Figure 3 As shown, according to Figure 3 The view defines the left-right direction as horizontal and the front-back direction as vertical; the gallium nitride high electron mobility transistor specifically includes: substrate layer 1-1, buffer layer 1-2, GaN channel layer (unintentionally doped GaN layer) 1-3, AlGaN barrier layer 1-4, P-GaN layer 1-5, HEMT gate 1-6, HEMT source 1-7, HEMT drain 1-8, and SBD anode 1-9; wherein:

[0059] The substrate 1-1 is a SiC, Si, sapphire or diamond substrate. The substrate 1-1, buffer layer 1-2, GaN channel layer 1-3 and AlGaN barrier layer 1-4 are arranged in order from bottom to top. The HEMT source 1-7, HEMT drain 1-8 and SBD anode 1-9 are arranged in order from left to right on the GaN channel layer 1-3 and all form ohmic contact with the GaN channel layer 1-3. The HEMT drain 1-8 also serves as the SBD cathode.

[0060] P-GaN layers 1-5 are disposed on AlGaN barrier layers 1-4 and patterned to form a HEMT region and an SBD region arranged laterally. The HEMT region is located between the HEMT source 1-7 and the HEMT drain 1-8, and includes: a first P-GaN thick layer (thickness 60nm~100nm) and a first P-GaN thin layer (thickness 30nm~50nm). The first P-GaN thick layer is arranged vertically and the HEMT gate 1-6 is disposed on it. The first P-GaN thin layer is arranged laterally and together with the first P-GaN thick layer constitutes a HEMT region. The source 1-7 extends in a T-shape towards the drain 1-8 of the HEMT; the SBD region is located between the drain 1-8 of the HEMT and the anode 1-9 of the SBD, and includes: a second P-GaN thin layer and a third P-GaN thin layer. The second P-GaN thin layer is arranged vertically, and the third P-GaN thin layer is arranged horizontally and together with the second P-GaN thin layer forms a T-shaped extension from the anode of the SBD to the cathode of the diode; the anode 1-9 of the SBD and the second P-GaN thin layer form a Schottky contact, and the source 1-7 of the HEMT and the anode 1-9 of the SBD are connected at the end of the layout (at the same potential).

[0061] Furthermore, the entire surface of the device is covered with a passivation layer, which is a Si3N4 material layer.

[0062] The working principle of this embodiment is as follows:

[0063] In this embodiment, the GaN HEMT device conducts electricity through a two-dimensional electron gas (2DEG) formed by polarization, creating an electron channel from the source 1-7 to the drain 1-8. This structure achieves a positive threshold voltage by depleting the 2DEG concentration below the gate 1-6 through the P-GaN layer 1-5 below the gate 1-6, thus reducing reverse conduction losses. When the potential difference between the gate 1-6 and the source 1-7 is less than the device's threshold voltage, the 2DEG below the gate 1-7 is depleted, the current path is turned off, and the device is in a blocking state. When the GaN HEMT transitions from the conducting state to the reverse conducting state, the drain voltage of the HEMT is lower than the source voltage. Since the anode of the SBD is at the same potential as the source of the HEMT, the SBD is in a forward conducting state at this time, and the reverse recovery current flows out from the electrode through the SBD, providing a reverse current path for the GaN HEMT.

[0064] Similarly, a T-shaped extension based on the P-GaN layer 1-5 is provided between the gate and drain, which can uniformly extend the electric field between the gate and drain when the device is turned off, reduce the peak electric field, and improve the device breakdown voltage. Furthermore, the P-GaN layer 1-5 injects holes into the channel when the device is turned on, suppressing the current collapse effect. Further, a T-shaped P-GaN layer extends above the barrier layer from the SBD anode 1-9 towards the cathode 1-8, which can deplete the 2DEG in the SBD channel when the HEMT is turned on, preventing current from flowing out of the SBD anode during HEMT forward conduction.

[0065] Example 4

[0066] This embodiment provides a method for fabricating a gallium nitride high electron mobility transistor with integrated Schottky diodes as described in Embodiments 1 to 3 above, including the following steps:

[0067] S1: The substrate is cleaned and annealed, and then the buffer layer, GaN channel layer, AlGaN barrier layer and P-GaN layer are grown sequentially by epitaxial process, and impurities are activated by annealing.

[0068] S2: The P-GaN layer is patterned using photolithography, and then the P-GaN layer is etched to form the patterned HEMT region and SBD region by dry etching. The etching process is divided into two stages: the first stage is to etch to form a P-GaN thick layer of the same thickness, and the second stage is to thin the corresponding P-GaN thin layer region.

[0069] S3: Ion implantation technology is used to implant isolation between the HEMT gate and the SBD anode, followed by annealing.

[0070] S4: The AlGaN barrier layer is etched to form the HEMT source, HEMT drain, and SBD anode window, and a multilayer metal is formed through a deposition process. The patterned electrode is then stripped to form a patterned electrode. After deposition, alloying annealing is performed to make the metal and semiconductor form an ohmic contact.

[0071] S5: Deposit metal in the HEMT gate and SBD control gate regions to form corresponding electrode layers;

[0072] S6: A dielectric layer is grown on the device surface at low temperature using deposition technology, followed by etching technology to open the electrode contact window.

[0073] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A gallium nitride high electron mobility transistor with an integrated Schottky diode, comprising: The structure comprises a substrate layer (1-1), a buffer layer (1-2), a GaN channel layer (1-3), an AlGaN barrier layer (1-4), a P-GaN layer (1-5), a HEMT gate (1-6), a HEMT source (1-7), a HEMT drain (1-8), an SBD anode (1-9), and an implanted isolation region (1-10); characterized in that: The substrate, buffer layer, GaN channel layer, and AlGaN barrier layer are arranged in order from bottom to top; the HEMT source and HEMT drain are arranged on the GaN channel layer and both form ohmic contact with the GaN channel layer. The HEMT source and HEMT drain are arranged vertically and located on the left and right sides of the AlGaN barrier layer. The HEMT drain also serves as the SBD cathode. A P-GaN layer is disposed on an AlGaN barrier layer and patterned to form a HEMT region and an SBD region arranged side by side along a vertical direction. The HEMT region includes a first P-GaN thick layer and a first P-GaN thin layer. The first P-GaN thick layer is disposed along a vertical direction and a HEMT gate is disposed thereon. The first P-GaN thin layer is disposed along a horizontal direction and together with the first P-GaN thick layer, it forms a T-shaped extension from the HEMT source to the HEMT drain. The SBD region includes a second P-GaN thin layer and a third P-GaN thin layer. The second P-GaN thin layer is disposed along a vertical direction and an SBD anode is disposed thereon. The third P-GaN thin layer is disposed along a horizontal direction and together with the second P-GaN thin layer, it forms a T-shaped extension from the SBD anode to the diode cathode. The left side of the SBD anode is connected to the HEMT source, and the right side forms a Schottky contact with the second P-GaN thin layer; the HEMT gate and the SBD anode are isolated by an implanted isolation region.

2. A gallium nitride high electron mobility transistor with an integrated Schottky diode, comprising: Substrate layer (1-1), buffer layer (1-2), GaN channel layer (1-3), AlGaN barrier layer (1-4), P-GaN layer (1-5), HEMT gate (1-6), HEMT source (1-7), HEMT drain (1-8), SBD anode (1-9), implanted isolation region (1-10), and SBD control gate (1-11); characterized in that: The substrate, buffer layer, GaN channel layer, and AlGaN barrier layer are arranged in order from bottom to top; the HEMT source and HEMT drain are arranged on the GaN channel layer and both form ohmic contact with the GaN channel layer. The HEMT source and HEMT drain are arranged vertically and located on the left and right sides of the AlGaN barrier layer. The HEMT drain also serves as the SBD cathode. A P-GaN layer is disposed on an AlGaN barrier layer and patterned to form a HEMT region and an SBD region arranged side by side along a vertical direction. The HEMT region includes a first P-GaN thick layer and a first P-GaN thin layer. The first P-GaN thick layer is disposed vertically and has a HEMT gate disposed thereon. The first P-GaN thin layer is disposed laterally and together with the first P-GaN thick layer forms a T-shaped extension from the HEMT source to the HEMT drain. The SBD region includes a second P-GaN thin layer, a second P-GaN thick layer, and a third P-GaN thin layer. The second P-GaN thin layer is disposed vertically and has an SBD anode disposed thereon. The second P-GaN thick layer is disposed vertically and has an SBD control gate disposed thereon. The third P-GaN thin layer is disposed laterally and together with the second P-GaN thick layer forms a T-shaped extension from the SBD anode to the diode cathode. The left side of the SBD anode is connected to the HEMT source, and the right side forms a Schottky contact with the second P-GaN thin layer; the HEMT gate and the SBD anode, as well as the HEMT gate and the SBD control gate, are isolated by implanted isolation regions; The gate of the HEMT is connected to the anode of the external diode D, the source of the HEMT is connected to the input terminal of the external capacitor C, and the output terminal of the external capacitor C and the cathode of the external diode D are both connected to the SBD control gate.

3. A gallium nitride high electron mobility transistor with an integrated Schottky diode, comprising: The structure comprises a substrate layer (1-1), a buffer layer (1-2), a GaN channel layer (1-3), an AlGaN barrier layer (1-4), a P-GaN layer (1-5), a HEMT gate (1-6), a HEMT source (1-7), a HEMT drain (1-8), and an SBD anode (1-9); characterized in that: The substrate, buffer layer, GaN channel layer, and AlGaN barrier layer are arranged in order from bottom to top; the HEMT source, HEMT drain and SBD anode are arranged in order from left to right on the GaN channel layer and all form ohmic contact with the GaN channel layer. The HEMT drain also serves as the SBD cathode. A P-GaN layer is disposed on an AlGaN barrier layer and patterned to form a HEMT region and an SBD region arranged laterally. The HEMT region is located between the HEMT source and the HEMT drain and includes a first P-GaN thick layer and a first P-GaN thin layer. The first P-GaN thick layer is arranged vertically and has the HEMT gate disposed thereon. The first P-GaN thin layer is arranged laterally and together with the first P-GaN thick layer forms a T-shaped extension from the HEMT source to the HEMT drain. The SBD region is located between the HEMT drain and the SBD anode and includes a second P-GaN thin layer and a third P-GaN thin layer. The second P-GaN thin layer is arranged vertically and the third P-GaN thin layer is arranged laterally and together with the second P-GaN thin layer forms a T-shaped extension from the SBD anode to the diode cathode. The SBD anode and the second P-GaN thin layer form a Schottky contact, and the HEMT source and the SBD anode are connected at the layout termination.

4. The gallium nitride high electron mobility transistor with integrated Schottky diode according to any one of claims 1 to 3, characterized in that, Each P-GaN thick layer has the same thickness, specifically 60nm to 100nm; each P-GaN thin layer has the same thickness, specifically 30nm to 50nm.

5. The gallium nitride high electron mobility transistor with integrated Schottky diode according to any one of claims 1 to 3, characterized in that, The substrate is SiC, Si, sapphire, or diamond.

6. The gallium nitride high electron mobility transistor with integrated Schottky diode according to any one of claims 1 to 3, characterized in that, The device surface is covered with a passivation layer, which is a Si3N4 material layer.

7. A method for fabricating a gallium nitride high electron mobility transistor with an integrated Schottky diode according to any one of claims 1 to 3, characterized in that, Includes the following steps: S1: The substrate is cleaned and annealed, and then the buffer layer, GaN channel layer, AlGaN barrier layer and P-GaN layer are grown sequentially by epitaxial process, and impurities are activated by annealing. S2: The P-GaN layer is patterned using photolithography, and then the P-GaN layer is etched to form the patterned HEMT region and SBD region by dry etching. The etching process is divided into two stages: the first stage is to etch to form a P-GaN thick layer of the same thickness, and the second stage is to thin the corresponding P-GaN thin layer region. S3: Ion implantation technology is used to implant isolation between the HEMT gate and the SBD anode, followed by annealing. S4: The AlGaN barrier layer is etched to form the metal deposition windows of HEMT source, HEMT drain and SBD anode, and multilayer metal is formed by deposition process, and patterned electrodes are formed by peeling. After deposition, alloying annealing is performed to form an ohmic contact between the metal and the semiconductor; S5: Deposit metal in the HEMT gate and SBD control gate regions to form corresponding electrode layers.

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