Preparation method of ultraviolet flip LED chip with patterned substrate and flip LED chip

Abstract

The invention relates to a preparation method of an ultraviolet flip LED chip with a patterned substrate and the flip LED chip, and belongs to the technical field of LED preparation. The method comprises the steps that a photoetching mask pattern is formed on the front face of a substrate, the photoetching mask pattern is transferred to the front face of the substrate, and the photoetching mask pattern comprises an RAM alignment mark pattern and a stress release pattern; preparing a patterned substrate structure on the back surface of the substrate, wherein the patterned substrate structure is an array formed by a concave runway and a patterned substrate; sequentially preparing epitaxial layers on the front surface of the substrate; performing mesa etching and ISO deep etching on the epitaxial layer; preparing an n-type ohmic contact electrode and a p-type ohmic contact electrode on the etched wafer; preparing a SiO2 passivation layer and a bonding pad electrode on the front surface of the wafer; and cutting the wafer along the cutting channel to obtain the ultraviolet flip LED chip. According to the invention, the epitaxial warping and cracking risks can be reduced, and the light extraction efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of LED preparation, in particular to a preparation method of an ultraviolet flip-chip LED chip of a patterned substrate and a flip-chip LED chip, and more particularly to a preparation method of a deep-ultraviolet flip-chip LED chip of a patterned substrate and a flip-chip LED chip. BACKGROUND

[0002] Light-emitting diodes (LEDs) are widely used in various lighting fields. With the progress of LED industry technology, the LED light-emitting waveband has been expanded from the visible light waveband to the ultraviolet and ultraviolet wavebands. AlGaN material can cover the UVC waveband from 260 nm to 280 nm and the UVB waveband from 280 nm to 320 nm, and is an excellent material for preparing ultraviolet LEDs. At present, the external quantum efficiency of the ultraviolet LED of the ultraviolet AlGaN material below 280 nm is about 10%, and the service life reaches 5000 h. However, compared with the external quantum efficiency of 60% of the blue light LED of InGaN material, there is still a big gap, and the market has not shown explosive growth. The light-emitting efficiency of the ultraviolet LED chip faces major challenges, which are mainly restricted by the material epitaxial quality, light extraction efficiency and the like. Among them, the high stress problem caused by the lattice mismatch and thermal mismatch between the substrate and the epitaxial layer easily causes cracks, warping and defects in the epitaxial layer, and seriously affects the performance and yield of the device; the light extraction efficiency of the ultraviolet flip-chip LED chip is restricted by the total reflection effect at the interface between the substrate and the air, and most of the light is limited in the substrate and cannot be effectively emitted.

[0003] Ultraviolet epitaxial growth belongs to heteroepitaxial growth, and there is a lattice mismatch and a thermal mismatch between the substrate material and the epitaxial layer material, which causes the epitaxial layer to release the stress in the growth process through warping. The warping not only affects the epitaxial uniformity, but also causes problems such as photolithography focusing failure, vacuum adsorption gas leakage, high-temperature process breakage and the like in the subsequent chip process, and the yield is significantly reduced. The existing process relieves the stress problem of the epitaxial layer by thinning the thickness of the epitaxial layer, thermal annealing and the like, but brings problems such as complex epitaxial process growth, high cost and poor crystal quality.

[0004] In order to improve the light-emitting efficiency of the ultraviolet flip-chip LED chip, surface roughening, metal mirror, DBR mirror and back surface patterned substrate technology have been proposed. The existing patterned substrate is mostly a full array structure, which can improve the light extraction efficiency, but the dense pattern will scatter the laser energy, hinder the formation of the modification layer in the stealth cutting, and cause the chips to be unable to be effectively separated. Some technologies adopt a scheme of cutting first and then patterning, but increase the process complexity and easily damage the epitaxial layer; some patterned substrate designs do not consider the compatibility of light scattering and cutting path, and it is difficult to balance the performance and mass production demand. SUMMARY

[0005] To solve the above technical problems, the application provides a preparation method of an ultraviolet flip LED chip of a patterned substrate and the flip LED chip. The application provides a preparation method of an ultraviolet flip LED chip of a patterned substrate, which comprises the following steps: S1, forming a photoetching mask pattern on the front surface of a substrate and transferring the photoetching mask pattern to the front surface of the substrate, wherein the photoetching mask pattern comprises a RAM alignment mark pattern and a stress release pattern; S2, preparing a patterned substrate structure on the back surface of the substrate, wherein the patterned substrate structure is an array composed of a concave racetrack and a patterned substrate; S3, sequentially preparing an AlN template layer, an n-type AlGaN layer, a multi-quantum well structure layer and a p-type AlGaN layer on the front surface of the substrate to form an epitaxial layer; S4, performing mesa etching and ISO deep etching on the epitaxial layer; S5, preparing an n-type ohmic contact electrode on the front surface of the n-type AlGaN layer after the etching in S4 and preparing a p-type ohmic contact electrode on the front surface of the p-type AlGaN layer after the etching; S6, preparing a SiO2 passivation layer on the front surface of the wafer obtained in S5 and forming a pad electrode on the front surface of the SiO2 passivation layer; S7, cutting the wafer obtained in S6 along the cutting path formed by the ISO deep etching to obtain an ultraviolet flip LED chip.

[0006] Preferably, the S1 comprises the following steps: S11, forming the RAM alignment mark pattern on the front surface of the substrate and symmetrically distributing the RAM alignment mark pattern on both sides of the center of the planar substrate, and setting the shape of the RAM alignment mark pattern as a cross shape or a herringbone shape; S12, forming the stress release pattern on the front surface of the substrate and setting the stress release pattern as a cross shape, setting the center point of the cross shape at the center of the front surface of the substrate, and setting the stress release pattern to penetrate through the entire front surface of the substrate.

[0007] Preferably, in the S1, the RAM alignment mark pattern is set as a concave shape, and the height of the RAM alignment mark is greater than or equal to 6 microns; the stress release pattern is set as a concave shape, and the height of the stress release pattern is greater than or equal to 6 microns.

[0008] Preferably, the S2 comprises the following steps: S21, preparing the concave racetrack on the back surface of the substrate by using a photoetching technology and a dry etching technology, and setting the height of the concave racetrack as 0.3-0.5 microns and the width of the concave racetrack as 30-60 microns; S22, preparing a patterned substrate by using a backside lithography technology and a dry etching technology, and setting the patterned substrate as one or a combination of at least two of an inverted trapezoidal matrix, an inverted conical matrix and a cylindrical matrix, and setting the patterned substrate as a concave type with a width of 2-5 μm and a height of 5-15 μm.

[0009] Preferably, in the step S22, when the patterned substrate is prepared by using the dry etching technology, ICP etching is used, Cl2:BCl3:Ar is used as the gas, the flow rate is 35:25:15 sccm, the power is 2000-2200 W, the RF bias power is 300-350 W, the chamber pressure is 4-5 mTorr, and the substrate temperature is 180-200℃.

[0010] Preferably, in the step S5, when the n-type ohmic contact electrode is prepared on the front side of the n-type AlGaN layer, the step S5 comprises the following steps: first, evaporating an n-type thin film electrode on the front side of the n-type AlGaN layer; and then, performing high-temperature annealing on the n-type thin film electrode in an N2 atmosphere to form the n-type ohmic contact electrode, wherein the annealing temperature is 800-950℃ and the annealing time is 30-360 s.

[0011] Preferably, in the step S5, when the p-type ohmic contact electrode is prepared on the front side of the p-type AlGaN layer, the step S5 comprises the following steps: first, evaporating a p-type thin film electrode on the front side of the p-type AlGaN layer, wherein the p-type thin film electrode is made of a metal with a high work function and the thickness of the p-type thin film electrode is 80-100 nm; and then, performing low-temperature annealing on the p-type thin film electrode in an N2, air or O2 atmosphere to form the p-type ohmic contact electrode, wherein the annealing temperature is 450-650℃ and the annealing time is 180-780 s.

[0012] Preferably, in the step S6, when the SiO2 passivation layer is prepared, the step S6 comprises the following steps: forming the SiO2 passivation layer by using a deposition, lithography and wet etching conventional process, and setting the thickness of the SiO2 passivation layer to be 300-1500 nm.

[0013] Preferably, the step S7 comprises the following steps: using a laser internal focusing technology to perform scribing, focusing an ultrashort pulse laser on the concave track on the back side of the substrate, generating a modified layer in the focal point area through nonlinear absorption, and then performing a cleaving technology to make the wafer break along the scribe line neatly, so as to separate the chips and obtain the ultraviolet flip-chip LED chip.

[0014] The application also provides an ultraviolet flip-chip LED chip prepared by using the method for preparing the ultraviolet flip-chip LED chip of the patterned substrate.

[0015] All the optional technical solutions described above can be combined arbitrarily, and the application does not describe the structures after the combination in detail.

[0016] By using the above-mentioned solutions, the application has the following advantages: By pre-setting a stress release pattern on the front surface of the substrate, the epitaxial growth mode can be converted from continuous surface growth to zoned growth, effectively dispersing stress, greatly reducing the risk of epitaxial warping and cracking, reducing the risk of chip process fragmentation, and providing a stress buffer window for subsequent high-temperature processes of the chip. By preparing a concave racetrack on the back surface of the substrate and an array of patterned substrates, the concave racetrack can provide a low-scattering path for laser stealth cutting to ensure chip separation; the patterned substrate can destroy the total reflection condition and improve the light extraction efficiency, realizing the dual optimization of performance and mass production. Through the cooperative design of the front and back patterns of the substrate and the pre-setting to the substrate preparation stage, the complexity of epitaxial growth and chip processing is greatly reduced, avoiding problems such as fragmentation and cutting failure in subsequent processes, and significantly improving production efficiency and device reliability.

[0017] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, and to implement the content of the description, the following will be described in detail with the preferred embodiments of the present application and with the aid of the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a preparation method flow chart of the patterned substrate ultraviolet flip LED chip provided by the embodiment of the present application.

[0019] Figure 2 is a planar top view of the photoetching mask pattern on the front surface of the substrate in the embodiment of the present application.

[0020] Figure 3 is a concave racetrack section view in the embodiment of the present application.

[0021] Figure 4 is a schematic diagram of the arrangement of the concave racetrack and the patterned substrate in the embodiment of the present application.

[0022] Figure 5 is a schematic diagram of the structure of the patterned substrate ultraviolet flip LED chip prepared in the embodiment of the present application. DETAILED DESCRIPTION

[0023] The specific embodiments of the present application will be further described in detail below in combination with the drawings and examples. The following examples are used to illustrate the present application, but are not used to limit the scope of the present application.

[0024] As shown in Figure 1 , the embodiment of the present application provides a preparation method of a patterned substrate ultraviolet flip LED chip, which comprises the following steps S1 to S7: S1, forming a photoetching mask pattern on the front surface of the substrate 101, and transferring the photoetching mask pattern to the front surface of the substrate 101, the photoetching mask pattern comprising a RAM alignment mark pattern and a stress release pattern.

[0025] The substrate 101 is sapphire, gallium oxide, aluminum nitride, gallium nitride, zinc oxide, magnesium oxide, diamond, gallium arsenide, indium phosphide, or glass, which is transparent to LED wavelength; the size of the substrate 101 can be 2 inches, 4 inches, 8 inches, 12 inches, etc. The surface of the substrate 101 for subsequent epitaxial growth is the front surface of the substrate 101, and the surface away from epitaxial growth is the back surface of the substrate 101. The thickness of the substrate 101 is 300-400 μm, and if it exceeds 400 μm, it needs to be thinned, rough polished, and fine polished to 300-400 μm. Preferably, for an LED chip smaller than 20 mil*20 mil in size, the thickness of the substrate 101 is 300 μm; for an LED chip larger than or equal to 20 mil*20 mil in size, the thickness of the substrate 101 is 400 μm.

[0026] Specifically, a photolithography mask pattern is formed on the front surface of the substrate 101 using a photolithography technology, and the photolithography mask pattern is transferred to the front surface of the substrate 101 using a dry etching technology. In one specific embodiment, the S1 includes S11 and S12: S11, forming a RAM alignment mark pattern on the front surface of the substrate 101, and symmetrically distributing the RAM alignment mark pattern on both sides of the center of the planar substrate, and setting the shape of the RAM alignment mark pattern as × or a horizontal bar shape.

[0027] Of course, the RAM alignment mark pattern can also be set as other shapes, and the RAM alignment mark pattern is determined according to the specific mark requirements of the exposure machine.

[0028] S12, forming a stress release pattern on the front surface of the substrate 101, and setting the stress release pattern as a cross shape, setting the center point of the cross shape at the center of the front surface of the substrate 101, and setting the stress release pattern to penetrate through the entire front surface of the substrate 101.

[0029] The vertical edge of the stress release pattern is perpendicular to the flat edge of the substrate 101, and the width of the vertical edge is 30-60 μm, preferably 50 μm; the horizontal edge of the stress release pattern is parallel to the flat edge of the substrate 101, and the width of the horizontal edge is 30-60 μm, preferably 50 μm.

[0030] As shown in FIG. 1, it is a planar top view of the photolithography mask pattern on the front surface of the substrate 101. Figure 2

[0031] In specific implementation, the RAM alignment mark pattern is set as a concave type, and the height of the RAM alignment mark is ≥6 μm, preferably 6 μm.

[0032] ​In one aspect, the RAM alignment mark pattern is used for the alignment and overlay preparation of the next step of the patterned substrate structure on the back surface of the substrate 101. In another aspect, the height of the epitaxial layer of the UV flip LED chip is generally 4.5-5.5 μm, and the RAM alignment mark must be higher than the growth thickness of the epitaxial layer. The substrate 101 further ensures that there are clear alignment mark points of 0.5 μm or more on each layer after epitaxial growth, and further ensures the accuracy of the etching and overlay of each layer of the chip pattern in the subsequent chip preparation, improves the photolithography process window, and improves product quality.

[0033] The conventional RAM alignment mark pattern is prepared in the first step of the chip process after epitaxial growth, such as the first step of the MESA step preparation in the conventional UV process. The substrate 101 has been pretreated before epitaxial growth in the present application.

[0034] In specific implementation, the stress release pattern is concave and has the same height as the RAM alignment mark, and the height of the stress release pattern is ≥6 μm, preferably 6 μm.

[0035] The stress release pattern is a process performed in advance on the substrate 101. By setting a cross-shaped stress release pattern, the substrate 101 is changed from conventional continuous growth on a flat surface to equal four-sided growth during epitaxial growth, reducing stress accumulation and growth warping during epitaxial growth, improving cracks and surface abnormalities caused by stress in the epitaxial layer, and improving the process window of epitaxial growth and further improving the yield of the epitaxial layer.

[0036] In another aspect, the stress release pattern greatly reduces the warping of the epitaxial layer, avoids frequent alarm of vacuum adsorption leakage in the chip process due to large epitaxial layer warping, and even cannot normally flow problems, avoids the problem of broken pieces, offset, and doublets in the chip process due to large epitaxial layer warping, and avoids the problem of broken pieces caused by rapid thermal stress release in high-temperature annealing and high-temperature passivation layer deposition in the chip process.

[0037] Further, the height of the concave stress release pattern is ≥6 μm, and the height of the epitaxial growth is generally 4.5-5.5 μm. Therefore, the stress release pattern is not filled by the epitaxial growth layer, and the stress release pattern is still concave with a height of 0.5 μm or more. The stress release pattern after epitaxial growth also provides a stress release window for high-temperature related processes in chip production, further improves the process window of chip production, and greatly improves the yield of the chip.

[0038] S2, a patterned substrate structure is prepared on the back surface of the substrate 101, and the patterned substrate structure is an array composed of a concave racetrack and a patterned substrate.

[0039] The back surface of the substrate 101 requires a roughness of 1 μm or less to reduce etching defects in subsequent processes. If the back surface of the substrate 101 has a roughness greater than 1 μm, polishing is required. A conventional planer machine can be used to polish the substrate 101 to a roughness of 1 μm.

[0040] In one embodiment, S2 comprises S21 and S22. S21. A concave racetrack is prepared on the back surface of the substrate 101 using photolithography and dry etching techniques. The height of the concave racetrack is set to 0.3-0.5 μm and the width is set to 30-60 μm.

[0041] The width of the concave racetrack is 30-60 μm. The specific distance is determined according to the equipment accuracy and process window of the dicing machine. The distance between the centers of adjacent concave racetracks varies according to the design size of the chip. For example, if the design size of the chip is 10 mil*20 mil, the distance between the centers of the long sides of adjacent concave racetracks is 20 mil and the distance between the centers of the short sides of adjacent concave racetracks is 10 mil. If the design size of the chip is 45 mil*45 mil, the distance between the centers of adjacent concave racetracks is 45 mil. Therefore, the concave racetrack is equivalent to the definition of the chip size. Preferably, the height of the concave racetrack is 0.4 μm, the width is 50 μm, the design size of the chip is 45 mil*45 mil, and the distance between the centers of adjacent concave racetracks is 45 mil.

[0042] The height of the concave racetrack is only 0.3-0.5 μm and the width is 30-60 μm, which belongs to shallow trench etching with a low aspect ratio. The process is simple to implement, but the difficulty lies in preparing the concave racetrack on the back surface of the substrate 101. Since the RAM alignment mark has been prepared in advance for the photolithography mask on the front surface of the substrate 101, and the substrate 101 is a transparent substrate, a common positive photoresist is used as a mask with a thickness of 3 μm. Photolithography and dry etching techniques can be used to prepare the concave racetrack. The cross-sectional view of the concave racetrack is shown in FIG. 2. Figure 3

[0043] S22. A patterned substrate is prepared on the back surface of the substrate 101 using photolithography and dry etching techniques. The patterned substrate is set to one or a combination of at least two of an inverted trapezoidal matrix, an inverted conical matrix, and a cylindrical matrix. The patterned substrate is concave with a width of 2-5 μm and a height of 5-15 μm.

[0044] Preferably, the patterned substrate is inverted conical with a width of 3 μm and a height of 8 μm.

[0045] ​Specifically, still taking the RAM alignment mark pattern of the front surface photolithography mask pattern of the substrate 101 as the alignment mark, the substrate 101 is a transparent substrate, the patterned substrate has a height of 5-15 μm and a width of 2-5 μm, which belongs to high aspect ratio, and the process implementation process can adopt hard mask + dry etching, the hard mask is SiO2, the deposition thickness of SiO2 is ≥1.5 μm, preferably, the deposition thickness of SiO2 is 1.5 μm; or photoresist + dry etching can also be used, but the thickness of the photoresist must be ≥8 μm, preferably, the thickness of the photoresist is 8 μm. Dry etching uses ICP etching, the gas uses Cl2:BCl3:Ar, the flow rate is 35:25:15 sccm, the power is 2000-2200 W, the RF bias power is 300-350 W, the chamber pressure is 4-5 mTorr, and the substrate temperature is 180-200°C. Preferably, the patterned substrate has a height of 8 μm and a width of 3 μm, the ICP power is 2100 W, the RF bias power is 320 W, the chamber pressure is 4.5 mTorr, and the temperature is 190°C.

[0046] The concave runways are adjacent to the patterned substrate, as shown in Figure 4 The concave runways and the patterned substrate are tiled in a matrix form to cover the entire wafer.

[0047] By forming the array of the concave runways and the patterned substrate on the back surface of the substrate 101, the problem that the laser cannot reach the inside of the substrate 101 to perform cutting due to the scattering of the laser reaching the surface of the substrate 101 by the dense array pattern, so that the chips cannot be separated, is effectively avoided. The present application allows the use of conventional stealth dicing technology: using laser focusing technology to dice, focusing the ultraviolet laser on the concave runways on the back surface of the planar substrate by using ultrashort pulse laser (for example, infrared laser), generating a modified layer (such as a crack or a cavity) in the focal point area through nonlinear absorption, and then expanding the internal modification layer by using a mechanical method, so that the material is neatly broken along the modification line (dicing path), thereby realizing the separation of the chips and successfully completing the preparation of the ultraviolet flip LED chip of the patterned substrate.

[0048] The array of the concave runways and the patterned substrate has a shape as shown in Figure 4

[0049] S3, sequentially preparing an AlN template layer 102, an n-type AlGaN layer 103, a multi-quantum well structure layer 104, and a p-type AlGaN layer 105 on the front surface of the substrate 101 to form an epitaxial layer. ​

[0050] Specifically, the epitaxial layer is formed on the front surface of the substrate 101 by a conventional epitaxial growth process.

[0051] Optionally, an AlN / AlGaN superlattice stress buffer layer 110 can be formed between the AlN template layer 102 and the n-type AlGaN layer 103. By providing the AlN / AlGaN superlattice stress buffer layer 110, the lattice mismatch and stress buffer between the AlN template layer 102 and the n-type AlGaN layer 103 can be adjusted, thereby improving the epitaxial growth quality.

[0052] S4, mesa etching and ISO deep etching are performed on the epitaxial layer.

[0053] Specifically, this step is a chip preparation process. Mesa etching can be performed by photolithography and dry etching process to form a MESA mesa. The depth of mesa etching is 400-800 nm, and is preferably 500 nm, and the etching is performed to the upper surface of the n-type AlGaN layer 103.

[0054] Specifically, ISO deep etching can be performed by photolithography and dry etching process, i.e. etching is performed using a scribe lane mask. The etching depth of ISO deep etching is 3000-3600 nm, and the etching width is the front scribe lane, and the front scribe lane distance, pitch and back reserved scribe lane are completely consistent. Similarly, the size is preferably designed to be 45 mil*45 mil, the front scribe lane distance is preferably 50 μm, and the center distance between adjacent scribe lanes is 45 mil.

[0055] S5, n-type ohmic contact electrode 106 is prepared on the front surface of the n-type AlGaN layer 103 after etching in S4, and p-type ohmic contact electrode 107 is prepared on the front surface of the p-type AlGaN layer 105 after etching.

[0056] Specifically, n-type ohmic contact electrode 106 can be prepared on the front surface of the n-type AlGaN layer 103 by photolithography, evaporation, and high-temperature N2 atmosphere annealing; and p-type ohmic contact electrode 107 can be prepared on the front surface of the p-type AlGaN layer 105 by photolithography, evaporation, and low-temperature O2 atmosphere annealing.

[0057] In one specific embodiment, when the n-type ohmic contact electrode 106 is prepared on the front surface of the n-type AlGaN layer 103 in S5, it includes: first, evaporating an n-type thin film electrode on the front surface of the n-type AlGaN layer 103; and then, annealing the n-type thin film electrode in an N2 atmosphere to form the n-type ohmic contact electrode 106, the annealing temperature being 800-950°C, and the annealing time being 30-360 s. The n-type thin film electrode is one or more of Ti, Al, Ni, Cr, Cu, Au, and Pt.

[0058] In one embodiment, the S5 includes the following steps when preparing the p-type ohmic contact electrode 107 on the front surface of the p-type AlGaN layer 105: first, depositing a p-type thin film electrode on the front surface of the p-type AlGaN layer 105, setting the p-type thin film electrode as a metal with high work function, and setting the thickness of the p-type thin film electrode to be between 80-100 nm; then, annealing the p-type thin film electrode in N2, air, or O2 atmosphere to form the p-type ohmic contact electrode 107, with the annealing temperature being 450-650°C and the annealing time being 180-780 s. The p-type thin film electrode is a metal with high work function, such as NiAu, NiRh, NiAuTi, NiRhTi, NiAuNiRhTi, etc.

[0059] S6, preparing a SiO2 passivation layer 108 on the front surface of the wafer obtained in S5, and forming a pad electrode 109 on the front surface of the SiO2 passivation layer 108.

[0060] Specifically, the SiO2 passivation layer 108 can be formed by a conventional process of deposition, photolithography, and wet etching; and the pad electrode 109 can be formed on the SiO2 passivation layer 108 by a conventional process of photolithography and evaporation.

[0061] In one embodiment, the S6 includes the following steps when preparing the SiO2 passivation layer 108: forming the SiO2 passivation layer 108 by a conventional process of deposition, photolithography, and wet etching, and setting the thickness of the SiO2 passivation layer 108 to be between 300-1500 nm. Preferably, the thickness of the SiO2 passivation layer 108 is 1000 nm.

[0062] Preferably, the thickness of the pad electrode 109 is 4 μm.

[0063] S7, cutting the wafer obtained in S6 along the cutting path formed by the ISO deep etching to obtain the ultraviolet flip-chip LED chip.

[0064] In the embodiment, the patterned substrate structure on the back surface of the substrate 101 allows the use of conventional stealth dicing technology. Specifically, the laser internal focusing technology is used for dicing, the ultraviolet flip-chip LED chip is prepared by focusing an ultrashort pulse laser (for example, an infrared laser) on the back surface of the substrate 101 in a concave track, generating a modified layer (such as a crack or a cavity) in the focal point area through nonlinear absorption, and then using a conventional cracking technology to expand the internal modified layer by mechanical expansion, so that the material is broken along the modified line, thereby realizing the separation of the chip and successfully completing the preparation of the ultraviolet flip-chip LED chip with the patterned substrate.

[0065] The preparation method of the flip-chip LED chip of the patterned substrate provided by the embodiment of the present application has the following beneficial effects: (1) The stress release pattern processes the substrate in advance, which changes the continuous growth of the epitaxial layer into the four-side growth, reduces the stress accumulation and growth warping in the epitaxial growth process, and controls the epitaxial warping within 50 μm, improves the abnormality of cracks and surface defects of the epitaxial layer caused by stress, improves the process window of epitaxial growth, and further improves the yield of the epitaxial layer.

[0066] (2) The stress release pattern greatly reduces the epitaxial warping, avoids the problems such as frequent air leakage alarm of the vacuum adsorption of the photolithography process, even cannot normally flow the chip, and the problems such as breaking the epitaxial layer caused by the epitaxial warping in the chip process, improves the process window of the chip process, and greatly improves the yield of the chip.

[0067] (3) The array of the concave track on the back surface of the substrate 101 and the patterned substrate effectively solves the problem that the laser cannot reach the inside of the substrate 1010 to cut and crack the chip when the laser reaches the surface of the substrate 1010 and is scattered by the dense array pattern, and further improves the light extraction efficiency of the flip-chip LED chip by more than 50%.

[0068] (4) The preparation method provided by the embodiment of the present application is a high-efficiency, good-compatibility, strong-designability and high-stability technology.

[0069] (5) The method provided by the embodiment of the present application further promotes the industrialization process of the flip-chip LED chip of the patterned substrate.

[0070] The embodiment of the present application further provides a flip-chip LED chip prepared by the preparation method of the flip-chip LED chip of the patterned substrate provided by the above embodiment. The flip-chip LED chip prepared by the embodiment of the present application is a flip-chip LED chip.

[0071] The flip LED chip provided by the embodiment of the present application can change the epitaxial growth mode from continuous surface growth to partition growth by pre-setting a stress release pattern on the front surface of the substrate, effectively disperses stress, greatly reduces the risk of epitaxial warping and cracking, reduces the risk of chip process fragmentation, and provides a stress buffer window for subsequent high-temperature processes of the chip. The array composed of the concave racetrack prepared on the back surface of the substrate and the patterned substrate can provide a low scattering path for laser stealth cutting through the concave racetrack, ensuring chip separation; the patterned substrate can destroy the total reflection condition and improve the light extraction efficiency, realizing double optimization of performance and mass production. Through the cooperative design of the patterns on the front and back surfaces of the substrate and the pre-setting to the substrate preparation stage, the complexity of epitaxial growth and chip process is greatly reduced, and problems such as fragmentation and cutting failure in subsequent processes are avoided, and the production efficiency and device reliability are significantly improved.

[0072] It should be noted that the ultraviolet flip LED chip described in the embodiment of the present application, in particular, relates to a deep ultraviolet flip LED chip.

[0073] The above only describes the preferred embodiments of the present application and is not used to limit the present application. It should be noted that for ordinary skilled persons in the art, several improvements and modifications can be made without departing from the technical principles of the present application, and these improvements and modifications should be considered as the protection scope of the present application.

Claims

1. A method for fabricating an ultraviolet flip-chip on a patterned substrate, characterized in that, include: S1, a photolithographic mask pattern is formed on the front side of the substrate (101), and the photolithographic mask pattern is transferred to the front side of the substrate (101). The photolithographic mask pattern includes a RAM alignment mark pattern and a stress relief pattern. S2, a patterned substrate structure is prepared on the back side of the substrate (101), wherein the patterned substrate structure is an array composed of a concave racetrack and a patterned substrate; S3, an epitaxial layer is formed by sequentially preparing an AlN template layer (102), an n-type AlGaN layer (103), a multi-quantum hydrazine structure layer (104), and a p-type AlGaN layer (105) on the front side of the substrate (101); S4, perform mesa etching and ISO deep etching on the epitaxial layer; S5, an n-type ohmic contact electrode (106) is prepared on the front side of the n-type AlGaN layer (103) after S4 etching, and a p-type ohmic contact electrode (107) is prepared on the front side of the p-type AlGaN layer (105) after etching. S6, a SiO2 passivation layer (108) is prepared on the front side of the wafer obtained in S5, and a pad electrode (109) is formed on the front side of the SiO2 passivation layer (108). S7, along the cutting path formed by ISO deep etching, cuts the wafer obtained in S6 to obtain ultraviolet flip LED chips.

2. The method for fabricating an ultraviolet flip-chip on a patterned substrate according to claim 1, characterized in that, S1 includes: S11, a RAM alignment mark pattern is formed on the front side of the substrate (101), and the RAM alignment mark pattern is symmetrically distributed on both sides of the center of the planar substrate. The shape of the RAM alignment mark pattern is set to an X shape or a star shape. S12, a stress relief pattern is formed on the front side of the substrate (101), and the stress relief pattern is set to a cross shape, with the center point of the cross shape set at the center of the front side of the substrate (101), and the stress relief pattern is set to run through the entire front side of the substrate (101).

3. The method for fabricating an ultraviolet flip-chip on a patterned substrate according to claim 1 or 2, characterized in that, In step S1, the RAM alignment mark pattern is set to be concave, and the height of the RAM alignment mark is set to be ≥6μm; the stress relief pattern is set to be concave, and the height of the stress relief pattern is set to be ≥6μm.

4. The method for fabricating an ultraviolet flip-chip LED on a patterned substrate according to claim 1, characterized in that, S2 includes: S21, a concave raceway is prepared on the back side of the substrate (101) using photolithography and dry etching techniques, and the height of the concave raceway is set to be 0.3-0.5μm and the width to be 30-60μm; S22, a patterned substrate is prepared on the back side of the substrate (101) using photolithography and dry etching techniques, and the patterned substrate is set to be one or a combination of at least two of the following: an inverted trapezoidal matrix, an inverted conical matrix, and a cylindrical matrix. The patterned substrate is set to be concave, with a width of 2-5 μm and a height of 5-15 μm.

5. The method for fabricating an ultraviolet flip-chip LED on a patterned substrate according to claim 4, characterized in that, When the patterned substrate is prepared using dry etching technology, the S22 uses ICP etching with Cl2:BCl3:Ar gas at a flow rate of 35:25:15 sccm, a power of 2000~2200 W, an RF bias power of 300~350 W, a chamber pressure of 4~5 mTorr, and a substrate temperature of 180~200℃.

6. The method for fabricating an ultraviolet flip-chip LED on a patterned substrate according to claim 1, characterized in that, When S5 prepares an n-type ohmic contact electrode (106) on the front side of the n-type AlGaN layer (103), it includes: firstly, depositing an n-type thin film electrode on the front side of the n-type AlGaN layer (103); then, annealing the n-type thin film electrode at high temperature in an N2 atmosphere to form an n-type ohmic contact electrode (106), with the annealing temperature being 800-950℃ and the annealing time being 30-360s.

7. The method for fabricating an ultraviolet flip-chip on a patterned substrate according to claim 1, characterized in that, When S5 prepares a p-type ohmic contact electrode (107) on the front side of the p-type AlGaN layer (105), it includes: firstly, depositing a p-type thin film electrode on the front side of the p-type AlGaN layer (105), setting the p-type thin film electrode to be a metal with a high work function, and setting the thickness of the p-type thin film electrode to be between 80-100 nm; then, performing low-temperature annealing of the p-type thin film electrode in an atmosphere of N2, air, or O2 to form the p-type ohmic contact electrode (107), with an annealing temperature of 450-650℃ and an annealing time of 180-780 s.

8. The method for fabricating an ultraviolet flip-chip on a patterned substrate according to claim 1, characterized in that, The process of preparing the SiO2 passivation layer (108) in S6 includes: forming the SiO2 passivation layer (108) through conventional processes such as deposition, photolithography, and wet etching, and setting the thickness of the SiO2 passivation layer (108) to be between 300-1500 nm.

9. The method for fabricating an ultraviolet flip-chip on a patterned substrate according to claim 1, characterized in that, The S7 includes: using laser internal focusing technology to dicing, using an ultra-short pulse laser to focus on a concave raceway on the back side of the substrate (101), generating a modified layer in the focal region through nonlinear absorption, and then using dicing technology to neatly break the wafer along the dicing track, thereby achieving chip separation and obtaining an ultraviolet flip-chip LED.

10. A flip-chip LED, characterized in that, The ultraviolet flip-chip LED is prepared using the fabrication method of the patterned substrate described in any one of claims 1 to 9.

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