Display device, method of manufacturing display device, and deposition mask

Abstract

A display device, a method of manufacturing the same, and a deposition mask are provided. The display device includes: a pixel including one or more sub-pixels, each having an emission area to emit light, and having a non-emission area around the emission area of the sub-pixel; a pixel defining layer overlapping the non-emission region, defining a trench in a boundary region between adjacent ones of the sub-pixels, and penetrating the pixel defining layer; an emission structure on the trench and a portion of the pixel defining layer; a cathode on the emission structure; and an auxiliary electrode on a portion of the cathode.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0078975, filed on June 18, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0090706, filed on July 9, 2024, in the Korean Intellectual Property Office, the entire disclosures of each of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the disclosure relate to a display device, a method of manufacturing the display device, and a deposition mask. BACKGROUND

[0003] As information technology has developed, the importance of a display device, which is a medium of connection between a user and information, has increased. SUMMARY

[0004] Aspects of embodiments of the disclosure relate to a display device having increased cathode connectivity, a method of manufacturing the display device, and a deposition mask.

[0005] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description, or can be learned by practice of the disclosed embodiments.

[0006] According to one or more embodiments of the disclosure, a display device includes: a pixel including one or more sub-pixels, the sub-pixels each having an emission region to emit light, and the pixel having a non-emission region around the emission regions of the sub-pixels; a pixel defining layer superposed with the non-emission region and defining a trench in a boundary region between adjacent ones of the sub-pixels, the trench penetrating the pixel defining layer; an emission structure on the trench and portions of the pixel defining layer; a cathode on the emission structure; and an auxiliary electrode partially on portions of the cathode.

[0007] In one or more embodiments, the auxiliary electrode can be on portions of the cathode superposed with the boundary region.

[0008] In one or more embodiments, the cathode can be superposed with a non-boundary region adjacent to the boundary region, and the auxiliary electrode can not be superposed with the non-boundary region.

[0009] In one or more embodiments, the auxiliary electrode can include a conductive material.

[0010] In one or more embodiments, the auxiliary electrode can include indium zinc oxide, aluminum, or silver.

[0011] In one or more embodiments, the display device can further include an encapsulation layer covering the cathode and the auxiliary electrode.

[0012] In one or more embodiments of the disclosure, the emission structure can include a first emission part including a first hole transport part, a first emission layer, and a first electron transport part, a second emission part including a second hole transport part, a second emission layer, and a second electron transport part, and a charge generation layer between the first emission part and the second emission part.

[0013] According to one or more embodiments of the disclosure, a display device includes a pixel including one or more sub-pixels each having an emission area to emit light, and the pixel having a non-emission area around the emission area of the sub-pixels, a pixel defining layer superposed with the non-emission area and defining a trench in a boundary area between adjacent sub-pixels of the sub-pixels, the trench penetrating the pixel defining layer, an emission structure on the trench and a portion of the pixel defining layer, and a cathode on the emission structure, wherein a thickness of a portion of the cathode superposed with the boundary area can be greater than a thickness of a portion of the cathode superposed with a non-boundary area adjacent to the boundary area.

[0014] According to one or more embodiments of the disclosure, a display device includes a pixel including one or more sub-pixels each having an emission area to emit light, and the pixel having a non-emission area around the emission area of the sub-pixels, a pixel defining layer superposed with the non-emission area and defining a trench in a boundary area between adjacent sub-pixels of the sub-pixels, the trench penetrating the pixel defining layer, an emission structure on the trench and a portion of the pixel defining layer, and a cathode on the emission structure, wherein a portion of the cathode superposed with the trench has a gentle slope.

[0015] According to one or more embodiments of the disclosure, a deposition mask includes a frame, masking parts spaced apart and / or separated (e.g., spaced apart or separated) from each other in the frame, and a support part to fix the masking parts in the frame, wherein the deposition mask defines an opening between the frame, the masking parts, and the support part.

[0016] In one or more embodiments, the structure of the masking parts can vary according to the structure of the sub-pixels to be deposited.

[0017] In one or more embodiments, the masking parts can correspond to the non-boundary areas of the sub-pixels.

[0018] In one or more embodiments, the opening can correspond to the boundary area of the sub-pixels.

[0019] In one or more embodiments, the opening can allow the deposition material to pass through so that the deposition material is deposited on the cathode superposed with the boundary area.

[0020] According to one or more embodiments of the disclosure, a method of manufacturing a display device includes the steps of forming an anode on a planarization layer; forming a pixel definition layer on the anode and a portion of the planarization layer, the pixel definition layer defining a sub-pixel at a portion of the anode on which the pixel definition layer is not positioned; forming a trench penetrating the pixel definition layer in a boundary region between adjacent sub-pixels of the sub-pixel; forming an emission structure on the trench and a portion of the pixel definition layer; forming a cathode on the emission structure; and irradiating a laser to a portion of the cathode superimposed with the trench.

[0021] In one or more embodiments, in the step of irradiating the laser, the portion of the cathode superimposed with the trench can be melted to form a gentle slope.

[0022] In one or more embodiments, a thickness of the portion of the cathode superimposed with the trench can be less than a thickness of a remaining portion not superimposed with the trench.

[0023] In one or more embodiments, the method can further include forming an encapsulation layer on the cathode. BRIEF DESCRIPTION OF DRAWINGS

[0024] The above and other aspects and features of the disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings.

[0025] Figure 1 is a block diagram of a display device according to one or more embodiments of the disclosure.

[0026] Figure 2 is a circuit diagram of a sub-pixel according to one or more embodiments of the disclosure.

[0027] Figure 3 is a top view of a display panel according to one or more embodiments of the disclosure.

[0028] Figure 4 is an exploded perspective view of a portion of a display panel according to one or more embodiments of the disclosure.

[0029] Figure 5 is a top view of a pixel according to one or more embodiments of the disclosure.

[0030] Figure 6 is a cross-sectional view taken along line I-I' in Figure 5

[0031] Figure 7 is a top view of a deposition mask according to one or more embodiments of the disclosure.

[0032] Figure 8 ​This is a perspective view illustrating an example of applying a deposition mask according to one or more embodiments of the present disclosure.

[0033] Figure 9 This is a cross-sectional view of a transmission structure according to one or more embodiments of the present disclosure.

[0034] Figure 10 This is a cross-sectional view of a transmission structure according to one or more embodiments of the present disclosure.

[0035] Figure 11 This is a top view of pixels according to one or more embodiments of the present disclosure.

[0036] Figure 12 This is a top view of pixels according to one or more embodiments of the present disclosure.

[0037] Figure 13 It is according to one or more embodiments of this disclosure along Figure 5 The sectional view taken by line I-I' in the middle.

[0038] Figures 14 to 19 This is a cross-sectional view illustrating the manufacturing process of a display device according to one or more embodiments of the present disclosure.

[0039] Figure 20 This is a block diagram of a display system according to one or more embodiments of the present disclosure.

[0040] Figure 21 This illustrates an application according to one or more embodiments of the present disclosure. Figure 20 A perspective view of a head-mounted display device for a display system.

[0041] Figure 22 This illustrates a user-wearable device according to one or more embodiments of the present disclosure. Figure 21 A diagram of a head-mounted display device. Detailed Implementation

[0042] This disclosure may be modified in many alternative forms, and therefore specific embodiments will be shown and described in more detail in the accompanying drawings. However, it should be understood that this is not intended to limit this disclosure to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of this disclosure.

[0043] Hereinafter, example embodiments according to the present disclosure will be described in greater detail with reference to the accompanying drawings. However, the present disclosure can be embodied in various different forms, and should not be construed as being limited to only the embodiments set forth herein. Rather, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. As such, processes, elements and techniques that are completely understood by those skilled in the art can not be described in detail because they are deemed as unnecessary to the understanding of the aspects and features of the present disclosure.

[0044] It will be understood that when an element such as a region, layer, film, zone or part is referred to as being "on", "connected to" or "joined to" another element, it can be directly on, connected or joined to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", "directly joined to", or "adjacent" another element, there are no intervening elements present. In addition, it will also be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements or one or more intervening elements can also be present.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. It will be further understood that the use of the terms "include", "have", "comprise" and variations thereof herein is meant to encompass the items listed thereafter and / or equivalents thereof as well as additional items.

[0046] Unless otherwise explicitly provided by the disclosure, when expressions such as "at least one of (a), (b), and (c)", "one or more of (a), (b), and (c)", and other similar expressions referring to a list of items are used, the items in the list can be included alone or in a combination of one or more of the items if written as a consecutive list, and vice versa. For example, the expressions "at least one of a, b, and c", "one selected from the group consisting of a, b, and c", "at least one of a, b, and c selected", "at least one of a, b, and c", "at least one of a, b, and c", "at least one of a to c", indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] It will be understood that, although the terms“first,”“second,”“third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus,“a first element,”“a first component,”“a first region,”“a first layer,” or“a first portion” described below could be termed a second element, a second component, a second region, a second layer, or a second portion without departing from the spirit and scope of the present disclosure.

[0048] For ease of explanation, spatial relative terms such as“on,”“above,”“under,”“below,”“upper,”“lower,” and the like can be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as“below” or“under” other elements or features would then be oriented“above” the other elements or features. Thus, the example terms“below” and“under” can encompass both orientations. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein interpreted accordingly.

[0049] As used herein, the singular forms“a,”“an,” and“the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, as used herein, the term“using” and variations thereof can be considered synonymous with the term“utilizing” and variations thereof.

[0050] Various embodiments are described in terms of exemplary idealized implementations. As such, it is contemplated that variations can occur when the shape is created, for example, due to tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the particular shapes shown, but rather, should be construed broadly to include any shape that a device can take, for example, as a result of manufacturing. As such, the shapes depicted in the figures can not reflect actual shapes of regions of a device, and the present embodiments are not limited thereby. Additionally, in the figures, the relative sizes of the elements, layers, and regions can be exaggerated for clarity.

[0051] Unless otherwise stated, like reference numerals in the figures and the written description denote like elements throughout the figures and written description. As such, the repetition of the description of the elements, components, regions, layers, and / or sections can not be provided.

[0052] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0053] Figure 1 is a block diagram of a display apparatus according to one or more embodiments of the disclosure.

[0054] Referring to Figure 1 , the display apparatus 100 can include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0055] The display panel 110 can include sub-pixels SP. The sub-pixels SP can be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The sub-pixels SP can be connected to the data driver 130 through first to n-th data lines DL1 to DLn.

[0056] Each of the sub-pixels SP can include at least one light emitting element configured to emit light. Accordingly, each of the sub-pixels SP can emit light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more of the sub-pixels SP can form one pixel PXL. For example, as shown in Figure 1 , three sub-pixels SP can form one pixel PXL.

[0057] The gate driver 120 can be connected to the sub-pixels SP arranged in a row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 can output gate signals to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. The gate control signal GCS can include a start signal indicating the start of each frame and / or a horizontal synchronization signal for outputting the gate signals in synchronization with the timing at which the data signals are applied, etc.

[0058] First to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction can also be provided. In this case, the gate driver 120 can include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm, and the emission control driver can operate under the control of the controller 150.

[0059] The gate driver 120 can be arranged at one side (e.g., one side surface) of the display panel 110. However, the disclosure is not necessarily limited thereto. For example, the gate driver 120 can be divided into two or more drivers that are physically and / or logically separated, and such drivers can be arranged at one side of the display panel 110 and the other side of the display panel 110 opposite to the one side. In this way, the gate driver 120 can be arranged around the display panel 110 in one or more suitable forms according to one or more embodiments.

[0060] The data driver 130 can be connected to the sub-pixels SP arranged in a column direction through first to nth data lines DL1 to DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. The data control signal DCS can include a source start pulse, a source shift clock, and / or a source output enable signal, etc.

[0061] The data driver 130 can apply a data signal having a gray voltage corresponding to the image data DATA to the first to nth data lines DL1 to DLn by using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA can be applied to the first to nth data lines DL1 to DLn. Accordingly, the corresponding sub-pixel SP can emit light corresponding to the data signal. Accordingly, an image can be displayed on the display panel 110.

[0062] The gate driver 120 and the data driver 130 can include complementary metal-oxide semiconductor (CMOS) circuit elements.

[0063] The voltage generator 140 can operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 can be configured to generate a plurality of voltages, and to supply the generated voltages to components of the display apparatus 100. For example, the voltage generator 140 can be configured to generate a plurality of voltages by receiving an input voltage from outside of the display apparatus 100, adjusting the received voltage, and regulating the adjusted voltage.

[0064] The voltage generator 140 can generate a first power voltage VDD and a second power voltage VSS, and the generated first power voltage VDD and second power voltage VSS can be supplied to the sub-pixel SP. The first power voltage VDD can have a relatively high voltage level, and the second power voltage VSS can have a voltage level lower than the first power voltage VDD. However, the present disclosure is not necessarily limited thereto. For example, the first power voltage VDD or the second power voltage VSS can be supplied by an external equipment of the display apparatus 100.

[0065] In addition, the voltage generator 140 can generate one or more appropriate voltages. For example, the voltage generator 140 can generate an initialization voltage applied to the sub-pixel SP. For example, a preset reference voltage can be applied to the first to nth data lines DL1 to DLn during a sensing operation for sensing an electrical characteristic of a transistor and / or a light emitting element of the sub-pixel SP, in a case where the voltage generator 140 can generate such a reference voltage.

[0066] The controller 150 can control the overall operation of the display apparatus 100. The controller 150 can receive input image data IMG and a control signal CTRL for controlling the display of the display panel 110 from the outside. The controller 150 can supply a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0067] The controller 150 can output image data DATA by converting the input image data IMG into a form suitable for the display apparatus 100 or the display panel 110. The controller 150 can output image data DATA by aligning the input image data IMG in a form suitable for a row of sub-pixels SP.

[0068] Two or more of the data driver 130, the voltage generator 140, and the controller 150 can be mounted on one integrated circuit. As Figure 1 As shown in FIG. 1, the data driver 130, the voltage generator 140, and the controller 150 can be included in a driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 can be functionally separate components within the single driver integrated circuit DIC. However, the present disclosure is not necessarily limited thereto. For example, at least one of the data driver 130, the voltage generator 140, and the controller 150 can be provided as a component separate from the driver integrated circuit DIC.

[0069] The display apparatus 100 can include at least one temperature sensor 160. The temperature sensor 160 can be configured to sense the temperature of its surrounding environment and generate temperature data TEP indicative of the sensed temperature. The temperature sensor 160 can be disposed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0070] The controller 150 can control one or more suitable operations of the display apparatus 100 in response to the temperature data TEP. The controller 150 can adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 can adjust the data signal and the first and second power voltages VDD and VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0071] Figure 2 is a circuit diagram of a sub-pixel according to one or more embodiments of the present disclosure.

[0072] In Figure 2 In Figure 1 In FIG. 1, a sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP in FIG. 1 is shown.

[0073] Referring to Figure 2 , the sub-pixel SPij can include a sub-pixel circuit SPC and a light emitting element LD.

[0074] The light emitting element LD can be connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN. Here, the first power supply voltage node VDDN is a node through which a first power supply voltage VDD in the display panel 100 is delivered, and the second power supply voltage node VSSN is a node through which a second power supply voltage VSS in the display panel 100 is delivered. Figure 1 Figure 1 The anode AE of the light emitting element LD can be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC, and the cathode CE of the light emitting element LD can be connected to the second power supply voltage node VSSN. For example, the anode AE of the light emitting element LD can be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0075] The sub-pixel circuit SPC can be connected to an i-th gate line GLi among first to m-th gate lines GL1 to GLm in the display panel 100,

[0076] an i-th emission control line ELi among first to m-th emission control lines EL1 to ELm in the display panel 100, and Figure 1 a j-th data line DLj among first to n-th data lines DL1 to DLn in the display panel 100. The sub-pixel circuit SPC can be configured to control the light emitting element LD according to signals received through these signal lines. Figure 1 Figure 1 The sub-pixel circuit SPC can operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi can include one or more sub-gate lines. As shown in

[0077] The i-th gate line GLi can include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. In this way, if the i-th gate line GLi includes two or more sub-gate lines (for example, when the i-th gate line GLi includes two or more sub-gate lines), the sub-pixel circuit SPC can operate in response to gate signals received through the respective sub-gate lines. Figure 2

[0078] ​​​The sub-pixel circuit SPC can operate in response to an emission control signal received through an i-th emission control line ELi. The i-th emission control line ELi can include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC can operate in response to an emission control signal received through a corresponding sub-emission control line.

[0079] The sub-pixel circuit SPC can receive a data signal through a j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of a gate signal received through a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can control a current flowing from a first power voltage node VDDN to a second power voltage node VSSN through the light emitting element LD according to the stored voltage in response to an emission control signal received through the i-th emission control line ELi. Thereby, the light emitting element LD can emit light having a luminance corresponding to the data signal.

[0080] Figure 3 is a top view of a display panel according to one or more embodiments of the disclosure.

[0081] Referring to Figure 3 , a display panel DP (corresponding to the display panel 110 in Figure 1 ) according to one or more embodiments can include a display area DA and a non-display area NDA. The display panel DP can display an image through the display area DA. The non-display area NDA can be arranged around the display area DA.

[0082] The display panel DP can include a substrate SUB, a sub-pixel SP, and a pad PD (also referred to as a "solder pad" or a "solder pad").

[0083] When the display panel DP is used as a display screen of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, or the like, the display panel DP can be positioned very close to the user's eyes. In this case, a sub-pixel SP having a relatively high integration can be used. In order to increase the integration of the sub-pixel SP, a silicon substrate can be provided as the substrate SUB. The sub-pixel SP and / or the display panel DP can be formed on the substrate SUB which is a silicon substrate. A display device 100 including the display panel DP formed on the substrate SUB which is a silicon substrate (see, for example, FIG. 1 of Figure 1 ) can be referred to as an OLED on silicon (OLEDoS) display device.

[0084] The subpixels SP can be arranged in the display area DA on the substrate SUB. The subpixels SP can be arranged in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the present disclosure is not necessarily limited thereto. For example, the subpixels SP can be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the subpixels SP can be arranged in a PENTILE ® shape (e.g., an RGBG matrix or an RGBG structure). PENTILE ® is a registered trademark of Samsung Display Co., Ltd. The first direction DR1 can be a row direction, and the second direction DR2 can be a column direction.

[0085] Two or more subpixels SP among the plurality of subpixels SP can constitute a pixel PXL. In other words, the pixel PXL can include one or more subpixels SP, such as two or more subpixels SP.

[0086] The components for controlling the subpixels SP can be arranged in the non-display area NDA on the substrate SUB. For example, the wirings (such as the first gate lines GL1 to the m-th gate lines GLm and the first data lines DL1 to the n-th data lines DLn in Figure 1 ) connected to the subpixels SP can be arranged in the non-display area NDA.

[0087] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 in the display panel DP can be integrated in the non-display area NDA. Figure 1 The gate driver 120 in the display panel DP can be mounted on the display panel DP and can be arranged in the non-display area NDA. However, the present disclosure is not necessarily limited thereto. For example, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. The temperature sensor 160 can be arranged in the non-display area NDA to sense a temperature of the display panel DP.

[0088] The pad PD can be arranged in the non-display area NDA on the substrate SUB. The pad PD can be electrically connected to the subpixels SP through the wirings. For example, the pad PD can be connected to the subpixels SP through the first data lines DL1 to the n-th data lines DLn.

[0089] The pad PD can join the display panel DP to other components of the display device 100 (see, for example, FIG. 1). Figure 1 The display panel DP can be electrically connected to the other components of the display device 100 (see, for example, FIG. 1) through the pad PD. Figure 1The driver integrated circuit DIC in the display panel DP can supply a voltage and a signal used for operation of components included in the display panel DP. For example, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit DIC through the pad PD. For example, the first power voltage VDD and the second power voltage VSS can be received from the driver integrated circuit DIC through the pad PD. For example, if the gate driver 120 is mounted on the display panel DP (e.g., when the gate driver 120 is mounted on the display panel DP), the gate control signal GCS can be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0090] The circuit board can be electrically connected to the pad PD through a conductive adhesive member such as an anisotropic conductive film. Here, the circuit board can be a flexible circuit board (FPCB) having a flexible material or a flexible film. The driver integrated circuit DIC can be mounted on the circuit board to be electrically connected to the pad PD.

[0091] The display area DA can have one or more suitable shapes. The display area DA can have a shape of a closed loop including straight sides and / or curved sides. For example, the display area DA can have a shape such as a polygonal shape, a circular shape, a semi-circular shape, and / or an elliptical shape, etc.

[0092] The display panel DP can have a flat display surface. However, the present disclosure is not necessarily limited thereto. For example, the display panel DP can have a display surface that is at least partially rounded. The display panel DP can be bendable, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB can include a material having a flexible property.

[0093] Figure 4 is an exploded perspective view of a portion of a display panel according to one or more embodiments of the present disclosure.

[0094] In Figure 4 In order to clarify and concisely illustrate, a portion of the display panel DP corresponding to two pixels PXL1 and PXL2 among the pixels PXL in the display panel DP is schematically shown. Figure 3 In

[0095] Referring to Figure 4 Each of the first pixel PXL1 and the second pixel PXL2 can include the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. However, the present disclosure is not necessarily limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 can include four sub-pixels SP or two sub-pixels SP.

[0096] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have a rectangular shape and have the same size when viewed in a third direction DR3 intersecting the first direction DR1 and the second direction DR2. However, the present disclosure is not necessarily limited thereto. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be modified to have one or more suitable shapes.

[0097] The display panel DP can include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, a sealing layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0098] The substrate SUB can include a silicon wafer substrate formed using a semiconductor process. The substrate SUB can include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material can include silicon (Si), germanium (Ge), and / or silicon germanium (SiGe). The substrate SUB can be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. However, the present disclosure is not necessarily limited thereto. For example, the substrate SUB can include a glass substrate or a polyimide (PI) substrate.

[0099] The pixel circuit layer PCL can be arranged on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL can include insulating layers and conductive patterns arranged between the insulating layers. The conductive patterns of the pixel circuit layer PCL can be used as at least some of circuit elements and wirings, etc. The conductive patterns can include copper, but the present disclosure is not necessarily limited thereto.

[0100] The circuit elements can include sub-pixel circuits SPC of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (see, for example, Figure 2 ). The sub-pixel circuits SPC can include transistors and one or more capacitors. Each transistor can include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode superposed on the semiconductor portion. When the substrate SUB is provided as a silicon substrate, the semiconductor portion can be included in the substrate SUB, and the gate electrode can be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. When the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode can be included in the pixel circuit layer PCL. Each capacitor can include electrodes spaced apart and / or separated (e.g., spaced apart or separated) from each other. For example, each capacitor can include electrodes spaced apart and / or separated (e.g., spaced apart or separated) from each other in a plane defined by the first direction DR1 and the second direction DR2. For example, each capacitor can include electrodes spaced apart and / or separated (e.g., spaced apart or separated) from each other in the third direction DR3 with an insulating layer interposed therebetween.

[0101] The wirings of the pixel circuit layer PCL can include signal lines such as a gate line, an emission control line, and a data line connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The wirings can further include a wiring connected to the first power voltage node VDDN in the power supply layer PSL. Figure 2 Figure 2 The wirings can further include a wiring connected to the second power voltage node VSSN in the power supply layer PSL.

[0102] The light emitting element layer LDL can include an anode AE, a pixel definition layer PDL, an emission structure EMS, and a cathode CE.

[0103] The anode AE can be disposed on the pixel circuit layer PCL. The anode AE can contact the circuit elements of the pixel circuit layer PCL. The anode AE can include an opaque conductive material capable of reflecting light, but the present disclosure is not necessarily limited thereto.

[0104] The pixel definition layer PDL can be disposed on the anode AE. The pixel definition layer PDL can include an opening OP exposing a portion of each of the anodes AE. The opening OP of the pixel definition layer PDL can be understood as an emission area corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively.

[0105] The pixel definition layer PDL can include an inorganic material. In one or more embodiments, the pixel definition layer PDL can include a plurality of stacked inorganic layers. For example, the pixel definition layer PDL can include silicon oxide (SiO x wherein 0 < x ≤ 2, for example, SiO2) and silicon nitride (SiN x wherein 0 < x ≤ 2, for example, Si3N4). However, the present disclosure is not necessarily limited thereto. For example, the pixel definition layer PDL can include an organic material.

[0106] The emission structure EMS can be disposed on the anode AE exposed by the opening OP of the pixel definition layer PDL. The emission structure EMS can include an emission layer formed to emit light, an electron transport layer formed to transport electrons, and a hole transport layer formed to transport holes.

[0107] ​The emission structure EMS can be disposed as a whole on the pixel definition layer PDL while filling the openings OP of the pixel definition layer PDL. For example, the emission structure EMS can extend across the first to third sub-pixels SP1 to SP3. In this case, at least some of the layers in the emission structure EMS can be broken or bent at the boundaries between the first to third sub-pixels SP1 to SP3. However, the present disclosure is not necessarily limited thereto. For example, portions of the emission structure EMS corresponding to the first to third sub-pixels SP1 to SP3 can be separated from each other, and these portions can be disposed in the openings OP of the pixel definition layer PDL, respectively.

[0108] The cathode CE can be disposed on the emission structure EMS. The cathode CE can extend across the first to third sub-pixels SP1 to SP3. In this way, the cathode CE can be provided as a common electrode for the first to third sub-pixels SP1 to SP3.

[0109] The cathode CE can be a thin metal layer having a thickness sufficient to transmit light emitted from the emission structure EMS. The cathode CE can be made of a metal material or a transparent conductive material so as to have a relatively thin thickness. For example, the cathode CE can include at least one of various suitable transparent conductive materials such as indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and / or gallium tin oxide. However, the present disclosure is not necessarily limited thereto. For example, the cathode CE can include at least one of silver (Ag), magnesium (Mg), and a mixture thereof (e.g., any suitable mixture).

[0110] One of the anode AE, the portion of the emission structure EMS superposed therewith, and the portion of the cathode CE superposed therewith can be understood to constitute one light emitting element LD (see, for example, FIG. 1B). Figure 2 For example, each of the light emitting elements LD of the first to third sub-pixels SP1 to SP3 can include one anode AE, the portion of the emission structure EMS superposed therewith, and the portion of the cathode CE superposed therewith. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode AE and electrons injected from the cathode CE are transported into the emission layer of the emission structure EMS to form excitons, and if the excitons transition from an excited state to a ground state (e.g., when the excitons transition from the excited state to the ground state), light can be emitted. The brightness of the light can be determined by the amount of current flowing through the emission layer. Depending on the composition of the emission layer, the wavelength range of the emitted light can be determined.

[0111] A packaging layer TFE can be disposed on the cathode CE. The packaging layer TFE can cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The packaging layer TFE can be formed to prevent or reduce the possibility of oxygen and / or moisture, etc. permeating into the light emitting element layer LDL. The packaging layer TFE can include a structure in which one or more inorganic films and one or more organic films are alternately laminated. For example, the inorganic film can include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y For example, x can range from 0 to 2, and y can range from 0 to 4). For example, the organic film can include an organic insulating material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the present disclosure is not necessarily limited thereto.

[0112] To improve the packaging efficiency of the packaging layer TFE, the packaging layer TFE can further include a thin film including aluminum oxide (AlO x ). The thin film including aluminum oxide can be disposed on an upper surface of the packaging layer TFE opposite to (e.g., facing) the optical functional layer OFL and / or on a lower surface of the packaging layer TFE opposite to (e.g., facing) the light emitting element layer LDL.

[0113] The thin film including aluminum oxide can be formed by using an atomic layer deposition (ALD) method. However, the present disclosure is not necessarily limited thereto. The packaging layer TFE can further include a thin film made of at least one of various materials suitable for improving the packaging efficiency.

[0114] The optical functional layer OFL can be disposed on the packaging layer TFE. The optical functional layer OFL can include a color filter layer CFL and a lens array LA.

[0115] The color filter layer CFL can be disposed between the packaging layer TFE and the lens array LA. The color filter layer CFL can be formed to filter light emitted from the emission structure EMS to selectively output light of a wavelength range or a color corresponding to each sub-pixel SP. The color filter layer CFL includes color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively, and each of the color filters CF can transmit light in a wavelength range corresponding to the associated sub-pixel SP. For example, the color filter CF corresponding to the first sub-pixel SP1 can transmit red light, the color filter CF corresponding to the second sub-pixel SP2 can transmit green light, and the color filter CF corresponding to the third sub-pixel SP3 can transmit blue light. At least some of the color filters CF can not be provided according to light emitted from the emission structure EMS of each sub-pixel SP.

[0116] The lens array LA can be disposed on the color filter layer CFL. The lens array LA can include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS can improve light output efficiency by outputting light emitted from the emission structure EMS to an intended path. The lens array LA can have a relatively high refractive index. For example, the lens array LA can have a higher refractive index than the cover layer OC. The lenses LS can include an organic material. For example, the lenses LS can include an acrylic material, although the present disclosure is not necessarily limited thereto.

[0117] At least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA can be shifted in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2 with respect to the openings OP of the pixel definition layer PDL. For example, in a central region of the display area DA, centers of the color filters CF and the lenses LS can be aligned with or superposed on centers of the respective openings OP of the pixel definition layer PDL when viewed in the third direction DR3. For example, in the central region of the display area DA, the openings OP of the pixel definition layer PDL can be completely superposed on the respective color filters CF of the color filter layer CFL and the respective lenses LS of the lens array LA. In a region of the display area DA adjacent to the non-display area NDA, the centers of the color filters CF and the lenses LS can be offset from the centers of the respective openings OP of the pixel definition layer PDL in a planar direction when viewed in the third direction DR3. For example, in the region of the display area DA adjacent to the non-display area NDA, the openings OP of the pixel definition layer PDL can be partially superposed (e.g., partially superposed) on the respective color filters CF of the color filter layer CFL and the respective lenses LS of the lens array LA. Accordingly, in the center of the display area DA, light emitted from the emission structure EMS can be effectively output in a normal (e.g., vertical) direction of the display surface. At the periphery of the display area DA, light emitted from the emission structure EMS can be effectively output in a direction tilted at a certain angle with respect to the normal (e.g., vertical) direction of the display surface.

[0118] The cover layer OC can be disposed on the lens array LA. The cover layer OC can cover the optical function layer OFL, the encapsulation layer TFE, the emission structure EMS, and / or the pixel circuit layer PCL. The cover layer OC can include one or more materials suitable for protecting the layers thereunder from foreign substances such as dust or moisture. For example, the cover layer OC can include at least one of an inorganic insulating film and an organic insulating film. For example, the cover layer OC can include an epoxy resin, although the present disclosure is not necessarily limited thereto. The cover layer OC can have a lower refractive index than the lens array LA.

[0119] A cover window CW can be disposed on the cap layer OC. The cover window CW can be formed to protect the layer thereunder. The cover window CW can have a higher refractive index than the cap layer OC. The cover window CW can include glass, but the present disclosure is not necessarily limited thereto. For example, the cover window CW can be an encapsulation glass formed to protect the components disposed thereunder. In one or more embodiments, the cover window CW can not be provided.

[0120] Figure 5 is a plan view of a pixel according to one or more embodiments of the present disclosure. In Figure 5 , for clarity and conciseness of explanation, the first pixel PXL1 among the first pixel PXL1 and the second pixel PXL2 in Figure 4 is schematically illustrated. The remaining pixels PXL can be formed similarly to the first pixel PXL1.

[0121] Referring to Figure 5 , the first pixel PXL1 can include first to third sub-pixels SP1 to SP3 disposed in the first direction DR1.

[0122] The first sub-pixel SP1 can include a first emission area EMA1 and a non-emission area NEA around the first emission area EMA1. The second sub-pixel SP2 can include a second emission area EMA2 and a non-emission area NEA around the second emission area EMA2. The third sub-pixel SP3 can include a third emission area EMA3 and a non-emission area NEA around the third emission area EMA3.

[0123] The first emission area EMA1 can be an area in which light is emitted from a portion of the emission structure EMS (see, for example, Figure 4 ) corresponding to the first sub-pixel SP1. The second emission area EMA2 can be an area in which light is emitted from a portion of the emission structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 can be an area in which light is emitted from a portion of the emission structure EMS corresponding to the third sub-pixel SP3. As described with reference to Figure 4 , the emission areas (or sub-pixels SP) can be understood as openings OP of the pixel definition layer PDL respectively corresponding to the first to third sub-pixels SP1 to SP3.

[0124] Figure 6 is a cross-sectional view taken along the line I-I' in Figure 5 .

[0125] Referring to Figure 6 , the substrate SUB can include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB can include silicon (Si), germanium (Ge), and / or silicon germanium (SiGe).

[0126] A pixel circuit layer PCL can be arranged on the substrate SUB. The substrate SUB and the pixel circuit layer PCL can include circuit elements of each of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL can include a transistor T SP1 of the first sub-pixel SP1, a transistor T SP2 of the second sub-pixel SP2, and a transistor T SP3 of the third sub-pixel SP3. The transistor T SP1 of the first sub-pixel SP1 can be one of transistors included in a sub-pixel circuit SPC (see, for example, FIG. 1) of the first sub-pixel SP1, the transistor T SP2 of the second sub-pixel SP2 can be one of transistors included in a sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T SP3 of the third sub-pixel SP3 can be one of transistors included in a sub-pixel circuit SPC of the third sub-pixel SP3. In Figure 2 FIG. 1, for the sake of clarity and simplicity of illustration, one of the transistors of each sub-pixel SP is shown, and the remaining circuit elements are not provided. Figure 6

[0127] The transistor T SP1 of the first sub-pixel SP1 can include a source region SRA, a drain region DRA, and a gate electrode GE.

[0128] The source region SRA and the drain region DRA can be arranged in the substrate SUB. A well WL formed by an ion implantation process is placed within the substrate SUB, and the source region SRA and the drain region DRA can be arranged to be spaced apart and / or separated (e.g., distanced or isolated) from each other within the well WL. An area between the source region SRA and the drain region DRA within the well WL can be defined as a channel region.

[0129] The gate electrode GE can be arranged in the pixel circuit layer PCL so as to overlap the channel region between the source region SRA and the drain region DRA. The gate electrode GE can be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE can include a conductive material.

[0130] The plurality of layers included in the pixel circuit layer PCL can include insulating layers and conductive patterns arranged between the insulating layers, where the conductive patterns can include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 can be electrically connected to the drain region DRA via a drain connection DRC that penetrates one or more of the insulating layers. The second conductive pattern CP2 can be electrically connected to the source region SRA via a source connection SRC that penetrates one or more of the insulating layers.

[0131] Due to the gate electrode GE and the first and second conductive patterns CP1 and CP2 being connected to other circuit elements and / or wiring, the transistor T SP1 of the first sub-pixel SP1 can be provided as one of the transistors of the first sub-pixel SP1.​

[0132] Each of the transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 can be formed similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0133] In this way, the substrate SUB and the pixel circuit layer PCL can include the circuit elements of each of the first to third sub-pixels SP1 to SP3.

[0134] The via layer VIAL can be arranged on the pixel circuit layer PCL. The via layer VIAL can have a flat surface as a whole while covering the pixel circuit layer PCL. The via layer VIAL can be formed to flatten the steps on the pixel circuit layer PCL. The via layer VIAL can include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon carbonitride (SiCN), but the present disclosure is not necessarily limited thereto.

[0135] The light emitting element layer LDL can be arranged on the via layer VIAL. The light emitting element layer LDL can include the first to third reflective electrodes RE1 to RE3, a planarization layer PLNL, the first to third anodes AE1 to AE3, a pixel definition layer PDL, an emission structure EMS, and a cathode CE.

[0136] On the via layer VIAL, the first to third reflective electrodes RE1 to RE3 can be arranged in the first to third sub-pixels SP1 to SP3, respectively. Each of the first to third reflective electrodes RE1 to RE3 can contact the circuit elements arranged in the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0137] The first to third reflective electrodes RE1 to RE3 can function as a full mirror that reflects light emitted from the emission structure EMS toward a display surface (or a cover window CW, see, for example, Figure 4 ). The first to third reflective electrodes RE1 to RE3 can include a metal material suitable for reflecting light. For example, the first to third reflective electrodes RE1 to RE3 can include at least one of and / or an alloy of two or more materials selected from the group consisting of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti), but the present disclosure is not necessarily limited thereto.

[0138] The connection electrode can be disposed under each of the first to third reflective electrodes RE1 to RE3. The connection electrode can improve an electrical connection characteristic between the corresponding reflective electrode and a circuit element of the pixel circuit layer PCL. The connection electrode can have a multi-layer structure. The multi-layer structure can include titanium (Ti), titanium nitride (TiN), and / or tantalum nitride (TaN), etc., but the present disclosure is not necessarily limited thereto. For example, the corresponding reflective electrode can be positioned between the multi-layers of the connection electrode.

[0139] The buffer pattern BFP can be disposed under at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP can include an inorganic material such as silicon carbonitride, but the present disclosure is not necessarily limited thereto. By disposing the buffer pattern BFP, a height of the corresponding reflective electrode in the third direction DR3 can be adjusted. For example, the buffer pattern BFP can be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0140] The first to third reflective electrodes RE1 to RE3 can function as a full mirror, and the cathode CE can function as a half mirror. Light emitted from the emission layer of the emission structure EMS can be amplified at least in part by reciprocating between the corresponding reflective electrode and the cathode CE, and the amplified light can be output through the cathode CE. In this way, the distance between the reflective electrode and the cathode CE can be understood as a resonance distance of light emitted from the corresponding emission layer of the emission structure EMS.

[0141] The first sub-pixel SP1 can have a shorter resonance distance than the other sub-pixels SP due to the buffer pattern BFP. The resonance distance adjusted in this way can effectively and efficiently amplify light in a specific wavelength range (e.g., red). Accordingly, the first sub-pixel SP1 can effectively and efficiently output light in the corresponding wavelength range.

[0142] In Figure 6 , the buffer pattern BFP is shown as being provided to the first sub-pixel SP1 and not provided to the second sub-pixel SP2 or the third sub-pixel SP3, but the present disclosure is not necessarily limited thereto. The buffer pattern BFP can also be provided to at least one of the second sub-pixel SP2 and the third sub-pixel SP3 in order to adjust a resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first to third sub-pixels SP1 to SP3 can correspond to red light, green light, and blue light, respectively; the distance between the first reflective electrode RE1 and the cathode CE can be shorter than the distance between the second reflective electrode RE2 and the cathode CE, and the distance between the second reflective electrode RE2 and the cathode CE can be shorter than the distance between the third reflective electrode RE3 and the cathode CE.

[0143] To flatten steps between the first to third reflective electrodes RE1 to RE3, a planarization layer PLNL can be disposed on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL can have a planar surface while covering the first to third reflective electrodes RE1 to RE3 and the via layer VIAL in its entirety. In one or more embodiments, the planarization layer PLNL can not be provided.

[0144] On the planarization layer PLNL, the first to third anodes AE1 to AE3 can be disposed to be respectively superimposed with the first to third reflective electrodes RE1 to RE3. The first to third anodes AE1 to AE3 can have similar shapes to the first to third emission areas EMA1 to EMA3 in the first to third sub-pixels SP1 to SP3 when viewed in the third direction DR3. The first to third anodes AE1 to AE3 can be respectively connected to the first to third reflective electrodes RE1 to RE3. The first anode AE1 can be connected to the first reflective electrode RE1 through a first via VIA1 that penetrates the planarization layer PLNL. The second anode AE2 can be connected to the second reflective electrode RE2 through a second via VIA2 that penetrates the planarization layer PLNL. The third anode AE3 can be connected to the third reflective electrode RE3 through a third via VIA3 that penetrates the planarization layer PLNL. Figure 5

[0145] The first to third anodes AE1 to AE3 can include an electrically conductive material. For example, the first to third anodes AE1 to AE3 can include at least one of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and / or indium tin zinc oxide (ITZO). However, the present disclosure is not necessarily limited thereto. For example, the first to third anodes AE1 to AE3 can include titanium nitride.

[0146] An insulating layer can also be provided to adjust a height of one or more of the first to third anodes AE1 to AE3. The insulating layer can be disposed between one or more of the first to third anodes AE1 to AE3 and the corresponding reflective electrode. In this case, the planarization layer PLNL and / or the buffer pattern BFP can not be provided. For example, the first to third sub-pixels SP1 to SP3 can respectively correspond to red, green, and blue; a distance between the first anode AE1 and the cathode CE can be shorter than a distance between the second anode AE2 and the cathode CE, and the distance between the second anode AE2 and the cathode CE can be shorter than a distance between the third anode AE3 and the cathode CE.

[0147] ​A pixel-defining layer (PDL) can be disposed on portions of the first anode AE1 to the third anode AE3 and on the planarization layer PLNL. The PDL may include openings (OPs) that expose portions of the first anode AE1 to the third anode AE3. The openings (OPs) of the PDL can define the emission regions of the first sub-pixels SP1 to the third sub-pixels SP3. In this way, the PDL can define the first emission regions EMA1 to the third emission regions EMA3, while also being disposed within the non-emission region NEA.

[0148] The pixel-defining layer (PDL) may include multiple inorganic insulating layers. Each of the multiple inorganic insulating layers may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following. For example, the pixel defining layer PDL may include a first inorganic insulating layer to a third inorganic insulating layer stacked sequentially, the first inorganic insulating layer to the third inorganic insulating layer may respectively include silicon nitride, silicon oxide and silicon nitride. The first inorganic insulating layer to the third inorganic insulating layer may have a stepped profile in the region adjacent to the opening OP. However, this disclosure is not limited thereto. For example, the pixel defining layer PDL may include an organic insulating layer.

[0149] A separator SPR can be set in the boundary region BDA between adjacent sub-pixels SP. The separator SPR can cause discontinuities in the boundary region BDA within the emission structure EMS. For example, the emission structure EMS can be cut or bent in the boundary region BDA due to the separator SPR.

[0150] Separator spacers (SPRs) can be disposed within or on the pixel-defining layer (PDL). The PDL may include one or more trenches TRCH1 and TRCH2 as separator spacers (SPRs) within the boundary region (BDA). Figure 6 As shown, one or more trenches TRCH1 and TRCH2 can penetrate the pixel defining layer PDL and partially penetrate the planarization layer PLNL. However, this disclosure is not limited to this. For example, one or more trenches TRCH1 and TRCH2 can penetrate the pixel defining layer PDL and the planarization layer PLNL, and can partially penetrate the via layer VIAL. For example, one or more trenches TRCH1 and TRCH2 can at least partially penetrate the planarization layer PLNL and / or the via layer VIAL, and portions of the pixel defining layer PDL can be disposed in one or more trenches TRCH1 and TRCH2.

[0151] exist Figure 6In the embodiment, two trenches TRCH1 and TRCH2 are shown to be provided in the boundary area BDA. However, the present disclosure is not necessarily limited thereto. For example, the pixel defining layer PDL can include one trench in the boundary area BDA. For example, the pixel defining layer PDL can include three or more trenches in the boundary area BDA.

[0152] Due to the first trench TRCH1 and the second trench TRCH2, discontinuous portions such as the first void VD1 and the second void VD2 can be formed in the boundary area BDA of the emission structure EMS. Some of the plurality of layers stacked in the emission structure EMS can be cut or bent due to the first void VD1 and the second void VD2. For example, at least one charge generation layer included in the emission structure EMS can be disconnected in the first void VD1 and the second void VD2. In this way, due to the first trench TRCH1 and the second trench TRCH2, portions of the emission structure EMS included in the first sub-pixel SP1 to the third sub-pixel SP3 can be at least partially separated.

[0153] In Figure 6 In the embodiment, the first void VD1 and the second void VD2 are shown to be formed in the boundary area BDA of the emission structure EMS, but the present disclosure is not necessarily limited thereto. For example, a concave valley can be formed in the boundary area BDA of the emission structure EMS. Depending on the shape of the first trench TRCH1 and the second trench TRCH2, the discontinuous portions formed in the emission structure EMS can be modified in one or more suitable ways.

[0154] The emission structure EMS can be formed by a process such as vacuum deposition and / or inkjet printing, etc. In one or more embodiments, substantially the same material as the emission structure EMS can be positioned on the bottom surface of the first trench TRCH1 and the second trench TRCH2 (in) adjacent to the via layer VIAL.

[0155] The partition SPR can be provided in one or more suitable variations such that the emission structure EMS can have discontinuous portions in the boundary area BDA.

[0156] The emission structure EMS can be arranged on the anode AE exposed by the opening OP of the pixel defining layer PDL. The emission structure EMS can be arranged to fill the opening OP of the pixel defining layer PDL as a whole across the first sub-pixel SP1 to the third sub-pixel SP3. As described above, due to the partition SPR, the emission structure EMS can be at least partially cut or bent at the boundary area BDA. Therefore, if the display panel DP is operated (see, for example, FIG. 1A) Figure 3 (e.g., when the display panel DP is operated (see, for example, FIG. 1A) Figure 3), the current flowing from each of the first to third sub-pixels SP1 to SP3 to its adjacent sub-pixel SP through the layer included in the emission structure EMS can be reduced. Accordingly, the first to third light emitting elements LD1 to LD3 can operate with relatively high reliability.

[0157] The cathode CE can be disposed on the emission structure EMS. The cathode CE can be commonly provided to the first to third sub-pixels SP1 to SP3. The cathode CE can function as a half mirror that partially transmits and partially reflects light emitted from the emission structure EMS.

[0158] The first anode AE1, a portion of the emission structure EMS overlapping the first anode AE1, and a portion of the cathode CE overlapping the first anode AE1 can constitute the first light emitting element LD1. The second anode AE2, a portion of the emission structure EMS overlapping the second anode AE2, and a portion of the cathode CE overlapping the second anode AE2 can constitute the second light emitting element LD2. The third anode AE3, a portion of the emission structure EMS overlapping the third anode AE3, and a portion of the cathode CE overlapping the third anode AE3 can constitute the third light emitting element LD3.

[0159] The step coverage of the cathode CE can be deteriorated due to the first and second trenches TRCH1 and TRCH2 provided in the boundary area BDA, such that the cathode CE can be deposited unevenly (e.g., the coverage of the cathode CE can be deteriorated at the first and second trenches TRCH1 and TRCH2 due to the steps). In other words, the cathode CE can have a partially uneven surface in the boundary area BDA. For example, the portion of the cathode CE overlapping the first and second trenches TRCH1 and TRCH2 (or, the first and second voids VD1 and VD2) can have a relatively thin thickness, and have a valley shape with a steep slope. In this case, the connectivity of the cathode CE can be deteriorated, and the cathode CE can be disconnected in a serious case.

[0160] The auxiliary electrode AXE can be partially disposed on the cathode CE. For example, the auxiliary electrode AXE can be disposed on a portion of the cathode CE which overlaps the boundary area BDA. The auxiliary electrode AXE can have a flat surface while covering the portion of the cathode CE which overlaps the boundary area BDA. Since the auxiliary electrode AXE is disposed on a portion of the cathode CE which has weak connectivity, the connectivity can be supplemented. Thus, the operation reliability of the first to third light emitting elements LD1 to LD3 can be increased. In addition, since the auxiliary electrode AXE is disposed on a portion of the cathode CE which overlaps the non-emission area NEA, it can not affect the luminance. The auxiliary electrode AXE can include a conductive material. For example, the auxiliary electrode AXE can include indium zinc oxide, aluminum, or silver, but the present disclosure is not necessarily limited thereto. In other words, the cathode CE can have an uneven surface in the boundary area BDA due to the first and second trenches TRCH1 and TRCH2, resulting in a potential connectivity problem, or even a disconnection in a serious case. To solve this problem, the auxiliary electrode AXE can be disposed on the cathode CE in the boundary area BDA to supplement the connectivity and improve the operation reliability of the light emitting elements LD1 to LD3. Since the auxiliary electrode AXE overlaps the non-emission area NEA, the auxiliary electrode AXE made of a conductive material such as indium zinc oxide, aluminum, or silver does not affect the luminance.

[0161] The auxiliary electrode AXE can not be disposed on a portion of the cathode CE which overlaps the first to third non-boundary areas NBA1 to NBA3 adjacent to the boundary area BDA. The first non-boundary area NBA1 can be defined as an area including the first emission area EMA1 and a portion of the non-emission area NEA around the first emission area EMA1. The second non-boundary area NBA2 can be defined as an area including the second emission area EMA2 and a portion of the non-emission area NEA around the second emission area EMA2. The third non-boundary area NBA3 can be defined as an area including the third emission area EMA3 and a portion of the non-emission area NEA around the third emission area EMA3. In one or more embodiments, because the auxiliary electrode AXE is not disposed on the cathode CE which overlaps the first to third emission areas EMA1 to EMA3, high optical properties can be maintained. If the auxiliary electrode AXE is disposed on the cathode CE which overlaps the first to third emission areas EMA1 to EMA3, the thickness can increase and the transmittance of light emitted from the first to third emission areas EMA1 to EMA3 can decrease. For example, the luminance can decrease, such that the optical properties can be deteriorated. In other words, the auxiliary electrode AXE is not placed on the cathode CE in the non-boundary areas NBA1 to NBA3 adjacent to the boundary area BDA. These non-boundary areas NBA1 to NBA3 include the emission areas EMA1 to EMA3 and portions of the non-emission area NEA around the emission areas EMA1 to EMA3. By not placing the auxiliary electrode AXE on the cathode CE in these emission areas EMA1 to EMA3, high optical properties are maintained. If the auxiliary electrode AXE is placed there, it would increase the thickness and decrease the light transmittance, resulting in decreased luminance and deteriorated optical properties.

[0162] The thickness t2 of the conductive layer (i.e., the cathode CE and the auxiliary electrode AXE) which overlaps the boundary area BDA can be greater than the thickness t1 of the conductive layer (i.e., the cathode CE) which overlaps the first to third non-boundary areas NBA1 to NBA3.

[0163] According to one or more embodiments, the auxiliary electrode AXE can be made of the same material as the cathode CE. In such embodiments, the auxiliary electrode AXE can be referred to as the cathode CE. Under these assumptions, the thickness t2 of the cathode CE which overlaps the boundary area BDA can be greater than the thickness t1 of the cathode CE which overlaps the first to third non-boundary areas NBA1 to NBA3. By forming the thickness (i.e., t2) of the portion of the cathode CE having weak connectivity to be thick and the thickness (i.e., t1) of the portion of the cathode CE which can cause luminance to decrease to be thin, the connectivity of the cathode CE can be increased while maintaining high optical properties.

[0164] A packaging layer TFE can be disposed on the cathode CE and the auxiliary electrode AXE. The packaging layer TFE can prevent or reduce the possibility of oxygen and / or moisture permeating into the light emitting element layer LDL.

[0165] Figure 7 is a top view of a deposition mask according to one or more embodiments of the present disclosure. Figure 8 is a perspective view illustrating an example in which the deposition mask according to one or more embodiments of the present disclosure is applied. In Figure 8 , for the sake of clarity and conciseness, the auxiliary electrode AXE deposited on the first pixel PXL1 among the first pixel PXL1 and the second pixel PXL2 in Figure 4 is schematically illustrated. The auxiliary electrode AXE deposited at the remaining pixels PXL can be constructed in a similar manner.

[0166] Referring to Figure 7 and Figure 8 , the deposition mask MK can be a material used in a deposition process of the auxiliary electrode AXE described in Figure 6 . For example, the deposition mask MK can be a fine metal mask (FMM) made of a metal material or a fine silicon mask (FSM) made of a silicon (Si) material. The deposition mask MK can include a frame portion FP, first to third masking portions MP1 to MP3, a support portion SPT, and an opening HP.

[0167] The frame portion (or frame) FP can serve as a skeleton of the deposition mask MK and can be composed of the above-described metal material or silicon material.

[0168] The first to third masking portions MP1 to MP3 can function to protect areas in which the auxiliary electrode AXE should not be deposited. The first masking portion MP1 can have a shape corresponding to the first non-boundary area NBA1 of the first pixel PXL1. The second masking portion MP2 can have a shape corresponding to the second non-boundary area NBA2 of the first pixel PXL1. The third masking portion MP3 can have a shape corresponding to the third non-boundary area NBA3 of the first pixel PXL1. For example, the first to third masking portions MP1 to MP3 can prevent or reduce the possibility of the auxiliary electrode AXE being deposited on the cathode CE overlaid with the first to third non-boundary areas NBA1 to NBA3. The structure of the first to third masking portions MP1 to MP3 can vary according to the structure of the first to third sub-pixels SP1 to SP3 (see, for example, Figure 5

[0169] ​The support portions SPT can be used to fix the first to third masking portions MP1 to MP3 to the frame portion FP. Also, the support portions SPT can be used to connect the first to third masking portions MP1 to MP3 to each other. For example, the support portions SPT can be disposed at the upper side, the lower side, the left side, and the right side of each of the first to third masking portions MP1 to MP3. However, the disclosure is not necessarily limited thereto, and the number or arrangement of the support portions SPT can vary.

[0170] The support portions SPT can block deposition of the auxiliary electrode AXE like the first to third masking portions MP1 to MP3. For example, the auxiliary electrode AXE can not be deposited on the cathode CE overlapped with the support portions SPT. Since the auxiliary electrode AXE is an auxiliary layer for supplementing the connectivity of the cathode CE, the first pixel PXL1 can function to normally emit light even if some of the auxiliary electrode AXE is missing.

[0171] The openings HP can be positioned between the frame portion FP, the first to third masking portions MP1 to MP3, and the support portions SPT. The openings HP can be used to allow deposition of the auxiliary electrode AXE. For example, the openings HP can allow the auxiliary electrode AXE to be deposited on the cathode CE overlapped with the boundary area BDA of the first pixel PXL1. In Figure 8 In the middle, the shadow area of the first pixel PXL1 can indicate an area in which the auxiliary electrode AXE is deposited. For example, the deposition material can pass through the openings HP and be deposited on the cathode CE overlapped with the boundary area BDA of the first pixel PXL1 to form the auxiliary electrode AXE.

[0172] Figure 9 is a cross-sectional view of an emission structure according to one or more embodiments of the disclosure.

[0173] Referring to Figure 9 , the emission structure EMS can have a series structure in which the first and second emission portions EU1 and EU2 are stacked. In one or more embodiments, the emission structure EMS can be formed in substantially the same manner in each of the first to third light emitting elements LD1 to LD3 in Figure 6 .

[0174] Each of the first emission part EU1 and the second emission part EU2 can include at least one emission layer that emits light according to an applied current. The first emission part EU1 can include a first emission layer EML1, a first electron transport part ETU1, and a first hole transport part HTU1. The first emission layer EML1 can be disposed between the first electron transport part ETU1 and the first hole transport part HTU1. The second emission part EU2 can include a second emission layer EML2, a second electron transport part ETU2, and a second hole transport part HTU2. The second emission layer EML2 can be disposed between the second electron transport part ETU2 and the second hole transport part HTU2.

[0175] Each of the first hole transport part HTU1 and the second hole transport part HTU2 can include at least one of a hole injection layer and a hole transport layer, and if necessary or desired, a hole buffer layer and / or an electron blocking layer, etc. The first hole transport part HTU1 and the second hole transport part HTU2 can have the same or different configurations.

[0176] Each of the first electron transport part ETU1 and the second electron transport part ETU2 can include at least one of an electron injection layer and an electron transport layer, and if necessary or desired, an electron buffer layer and / or a hole blocking layer, etc. The first electron transport part ETU1 and the second electron transport part ETU2 can have the same or different configurations.

[0177] A connection layer, which can be provided in the form of a charge generation layer CGL, can be disposed between the first emission part EU1 and the second emission part EU2 to connect them to each other. The charge generation layer CGL can have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer can include a p-type dopant such as HAT-CN, TCNQ, and / or NDP-9, etc., and the n-dopant layer can include an alkali metal, an alkaline earth metal, a lanthanide metal, and / or a combination (e.g., any suitable combination) thereof. However, the present disclosure is not necessarily limited thereto.

[0178] The first emission layer EML1 and the second emission layer EML2 can emit different colors of light. The light emitted from the first emission layer EML1 and the second emission layer EML2 can be mixed and recognized as white light. For example, the first emission layer EML1 can emit blue light, and the second emission layer EML2 can emit yellow light. The second emission layer EML2 can include a structure in which a first sub-emission layer formed to emit red light and a second sub-emission layer formed to emit green light are stacked. The red light and the green light can be mixed to produce yellow light. In this case, an intermediate layer can also be disposed between the first sub-emission layer and the second sub-emission layer, the intermediate layer being formed to perform a function of transporting holes and / or a function of blocking electron transport. However, the present disclosure is not necessarily limited thereto. For example, the first emission layer EML1 and the second emission layer EML2 can emit the same color of light.

[0179] Figure 10 is a cross-sectional view of an emission structure according to one or more embodiments of the present disclosure.

[0180] Referring to Figure 10 , the emission structure EMS' can have a series structure in which the first to third emission parts EU1' to EU3' are stacked. In one or more embodiments, the emission structure EMS' can be formed in each of the first to third light emitting elements LD1 to LD3 in the same basic manner as in Figure 6

[0181] Each of the first to third emission parts EU1' to EU3' can include an emission layer that emits light according to an applied current. The first emission part EU1' can include a first emission layer EML1', a first electron transport part ETU1', and a first hole transport part HTU1'. The first emission layer EML1' can be disposed between the first electron transport part ETU1' and the first hole transport part HTU1'. The second emission part EU2' can include a second emission layer EML2', a second electron transport part ETU2', and a second hole transport part HTU2'. The second emission layer EML2' can be disposed between the second electron transport part ETU2' and the second hole transport part HTU2'. The third emission part EU3' can include a third emission layer EML3', a third electron transport part ETU3', and a third hole transport part HTU3'. The third emission layer EML3' can be disposed between the third electron transport part ETU3' and the third hole transport part HTU3'.

[0182] ​Each of the first to third hole transport portions HTU1' to HTU3' can include at least one of a hole injection layer and a hole transport layer, and if necessary or desired, a hole buffer layer and / or an electron blocking layer, etc. The first to third hole transport portions HTU1' to HTU3' can have the same or different configurations.

[0183] Each of the first to third electron transport portions ETU1' to ETU3' can include at least one of an electron injection layer and an electron transport layer, and if necessary or desired, an electron buffer layer and / or a hole blocking layer, etc. The first to third electron transport portions ETU1' to ETU3' can have the same or different configurations.

[0184] The first charge generation layer CGL1' can be disposed between the first and second emission portions EU1' and EU2'. The second charge generation layer CGL2' can be disposed between the second and third emission portions EU2' and EU3'.

[0185] The first to third emission layers EML1' to EML3' can emit different colors of light. The light emitted from each of the first to third emission layers EML1' to EML3' can be mixed and recognized as white light. For example, the first emission layer EML1' can emit blue light, the second emission layer EML2' can emit green light, and the third emission layer EML3' can emit red light. However, the present disclosure is not necessarily limited thereto. For example, two or more of the first to third emission layers EML1' to EML3' can emit the same color of light.

[0186] Unlike as shown in FIG. 1, Figure 9 and Figure 10 Unlike as shown in FIG. 1, Figure 6 The emission structure EMS can include one emission portion in each of the first to third light emitting elements LD1 to LD3. In such an embodiment, the emission portions respectively included in the first to third light emitting elements LD1 to LD3 can be configured to emit different colors of light. For example, the emission portion of the first light emitting element LD1 can emit red light, the emission portion of the second light emitting element LD2 can emit green light, and the emission portion of the third light emitting element LD3 can emit blue light. In such an embodiment, unlike as shown in FIG. 1, Figure 6 Unlike as shown in FIG. 1, the emission portions of the first to third sub-pixels SP1 to SP3 are separated from each other, and each of them can be disposed within the opening OP of the pixel defining layer PDL.

[0187] Figure 11 is a top view of a first pixel according to one or more embodiments of the present disclosure.

[0188] Referring to Figure 11 , the first pixel PXL1' can include the first to third sub-pixels SP1' to SP3'.

[0189] The first sub-pixel SP1' can include a first emission area EMA1' and a non-emission area NEA' around the first emission area EMA1'. The second sub-pixel SP2' can include a second emission area EMA2' and a non-emission area NEA' around the second emission area EMA2'. The third sub-pixel SP3' can include a third emission area EMA3' and a non-emission area NEA' around the third emission area EMA3'.

[0190] The first sub-pixel SP1' and the second sub-pixel SP2' can be arranged in the second direction DR2. The third sub-pixel SP3' can be arranged in the first direction DR1 with respect to the first sub-pixel SP1' and the second sub-pixel SP2'.

[0191] The second sub-pixel SP2' can have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' can have a larger area than the second sub-pixel SP2'. Accordingly, the second emission area EMA2' can have a larger area than the first emission area EMA1', and the third emission area EMA3' can have a larger area than the second emission area EMA2'. However, the present disclosure is not necessarily limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' can have substantially the same area, and the third sub-pixel SP3' can have a larger area than each of the first sub-pixel SP1' and the second sub-pixel SP2'. In this way, the areas of the first to third sub-pixels SP1' to SP3' can vary in one or more suitable ways according to embodiments.

[0192] Figure 12 is a top view of a first pixel according to one or more embodiments of the present disclosure.

[0193] Referring to Figure 12 , the first sub-pixel SP1'' can include a first emission area EMA1'' and a non-emission area NEA'' around the first emission area EMA1''. The second sub-pixel SP2'' can include a second emission area EMA2'' and a non-emission area NEA'' around the second emission area EMA2''. The third sub-pixel SP3'' can include a third emission area EMA3'' and a non-emission area NEA'' around the third emission area EMA3''.

[0194] The first to third sub-pixels SP1'' to SP3'' can have a polygonal shape when viewed in the third direction DR3. For example, the shape of the first to third sub-pixels SP1'' to SP3'' can be a hexagon as shown in Figure 12

[0195] The first to third emission areas EMA1'' to EMA3'' can have a circular shape when viewed in the third direction DR3. However, the disclosure is not necessarily limited thereto. For example, each of the first to third emission areas EMA1'' to EMA3'' can have a polygonal shape.

[0196] The first and third sub-pixels SP1'' and SP3'' can be arranged in the first direction DR1. The second sub-pixel SP2'' can be arranged in a direction inclined at an acute angle with respect to the second direction DR2 (or, in a diagonal direction) with respect to the first sub-pixel SP1''.

[0197] Figure 5 Figure 11 Figure 12 The arrangement of the sub-pixels shown in

[0198] Figure 13 is a cross-sectional view taken along the line I-I' in Figure 5 . With regard to Figure 13 , a description of content overlapping with that of Figure 6 may be simplified or omitted.

[0199] Referring to Figure 13 , the cathode CE overlapping the first and second trench regions TRA1 and TRA2 can have a gentle slope. The gentle slope can be characterized by a gradual and continuous transition from a higher point to a lower point without a sudden change in height to produce a more uniform surface. Further, the first trench region TRA1 can indicate a region in which the first trench TRCH1 is formed, and the second trench region TRA2 can indicate a region in which the second trench TRCH2 is formed. Although the connection is supplemented by forming the auxiliary electrode AXE on the portion of the cathode CE having weak connection in Figure 6 , the connection can be supplemented by forming the auxiliary electrode AXE on the portion of the cathode CE having weak connection in Figure 13 ​​​The connection can be supplemented by changing the shape of the portion of the cathode CE having weak connection. In this case, the thickness t2 of the cathode CE superimposed with the first trench region TRA1 and the second trench region TRA2 can be smaller than the thickness t1 of the remaining portion of the cathode CE. This is because the cathode CE superimposed with the first trench region TRA1 and the second trench region TRA2 is irradiated with a laser L (see, for example Figure 19 ) and melted. In other words, the cathode CE superimposed with the first trench region TRA1 and the second trench region TRA2 has a gentle slope. The first trench region TRA1 corresponds to a region in which the first trench TRCH1 is formed, and the second trench region TRA2 corresponds to a region in which the second trench TRCH2 is formed. Unlike the case where the auxiliary electrode AXE is added to improve the connection Figure 6 , Figure 13 The connection is improved by reshaping the cathode CE. Therefore, due to the laser irradiation and melting in these regions, the thickness t2 of the cathode CE in the trench regions TRA1 and TRA2 is smaller than the thickness t1 of the remaining portion of the cathode CE.

[0200] Figures 14 to 19 is a cross-sectional view illustrating a manufacturing process of a display device according to one or more embodiments of the disclosure. In Figures 14 to 19 , the substrate SUB, the pixel circuit layer PCL, the via layer VIAL, and / or the planarization layer PLNL, etc. can be manufactured according to a suitable, generally utilized, and / or generally available manufacturing process.

[0201] Referring to Figure 14 , the first to third anodes AE1 to AE3 can be patterned on the planarization layer PLNL. The first to third anodes AE1 to AE3 can be patterned at positions corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third anodes AE1 to AE3 can be patterned to penetrate the planarization layer PLNL and be connected to the first to third reflective electrodes RE1 to RE3, respectively.

[0202] Referring to Figure 15 , the pixel definition layer PDL can be patterned on the planarization layer PLNL and the first to third anodes AE1 to AE3. The pixel definition layer PDL can be partially patterned on the first to third anodes AE1 to AE3 to have openings OP. Thereby, portions of the first to third anodes AE1 to AE3 corresponding to the openings OP can be exposed.

[0203] Referring to Figure 16The first trench TRCH1 and the second trench TRCH2 can be patterned at locations that are superimposed with the boundary area BDA. The first trench TRCH1 and the second trench TRCH2 can be patterned to be spaced apart and / or separated (e.g., spaced or separated) from each other in the boundary area BDA, and to penetrate portions of the pixel defining layer PDL and the planarization layer PLNL.

[0204] Referring to Figure 17 The emission structure EMS can be patterned on the first to third anodes AE1-3 and the pixel defining layer PDL. Due to the first trench TRCH1 and the second trench TRCH2, first and second voids VD1-2 can be formed in the process of patterning the emission structure EMS. The first and second voids VD1-2 can cause formation of discontinuous portions in the emission structure EMS. In addition, portions of the emission structure EMS that are superimposed with the first trench TRCH1 and the second trench TRCH2 can be deposited unevenly to have a valley shape due to reduced step coverage (e.g., reduced coverage due to a step).

[0205] Referring to Figure 18 The cathode CE can be patterned on the emission structure EMS. As described in Figure 6 the portions of the cathode CE that are superimposed with the first trench TRCH1 and the second trench TRCH2 can be deposited unevenly to have a shape of a steeply inclined valley due to reduced step coverage (e.g., reduced coverage due to a step).

[0206] Referring to Figure 19The cathode CE can be partially irradiated with a laser L. For example, the laser L can irradiate a portion of the cathode CE having weak connectivity (i.e., a portion of the cathode CE overlaid with the first trench region TRA1 and the second trench region TRA2). In this case, the portion of the cathode CE overlaid with the first trench region TRA1 and the second trench region TRA2 can be melted and its shape can be changed. For example, the portion of the cathode CE irradiated with the laser L can be melted to fill in a steep valley, and then the portion of the cathode CE overlaid with the first trench region TRA1 and the second trench region TRA2 can have a gentler slope. Thus, the connectivity of the cathode CE can be increased, and the risk of disconnection can be reduced. The laser L can be a laser used in a laser lift-off (LLO) process, but the present disclosure is not necessarily limited thereto. In other words, the cathode CE can be partially irradiated with a laser L. For example, the laser L can be aimed at a portion of the cathode CE having weak connectivity (specifically, a region overlaid with the first trench region TRA1 and the second trench region TRA2). In this case, the target portion of the cathode CE can be melted and reshaped. For example, the laser L can melt the cathode CE to fill it in a steep valley, thereby creating a smoother, gentler slope in the region overlaid with the first trench region TRA1 and the second trench region TRA2. Such a gentle slope enhances the connectivity of the cathode CE and reduces the risk of disconnection. The gentle slope can be characterized by a gradual transition and a continuous transition from a higher point to a lower point without a sudden change in height to produce a more uniform surface. After ensuring the connectivity of the cathode CE, an encapsulation layer TFE can be formed on the cathode CE (see, e.g., Figure 13 ).

[0207] Figure 20 is a block diagram of a display system according to one or more embodiments of the present disclosure.

[0208] Referring to Figure 20 , the display system 1000 can include a processor 1100 and one or more display devices 1210 and 1220.

[0209] The processor 1100 can perform one or more suitable tasks and calculations. The processor 1100 can include an application processor, a graphic processor, a microprocessor, and / or a central processing unit (CPU), etc. The processor 1100 can be connected to and control other components of the display system 1000 through a bus system.

[0210] In Figure 20 , the display system 1000 is shown to include a first display device 1210 and a second display device 1220. The processor 1100 can be connected to the first display device 1210 through a first channel CH1 and to the second display device 1220 through a second channel CH2.

[0211] Through the first channel CH1, the processor 1100 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display apparatus 1210. The first display apparatus 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display apparatus 1210 can be configured similarly to the display apparatus 100 described with reference to Figure 1 In such an embodiment, the first image data IMG1 and the first control signal CTRL1 can be provided as input image data IMG and a control signal CTRL in Figure 1

[0212] Through the second channel CH2, the processor 1100 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display apparatus 1220. The second display apparatus 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display apparatus 1220 can be configured similarly to the display apparatus 100 described with reference to Figure 1 In such an embodiment, the second image data IMG2 and the second control signal CTRL2 can be provided as input image data IMG and a control signal CTRL in Figure 1

[0213] The display system 1000 can include a computing system (such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation device, and / or an ultra-mobile personal computer (UMPC)) that provides a video display function. In addition, the display system 1000 can include at least one of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0214] Figure 21 is a perspective view showing an example of a display system to which an application Figure 20 of one or more embodiments according to the present disclosure is applied.

[0215] The display system 1000 described with reference to Figure 21 , Figure 20 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0216] ​​The head-mounted display device 2000 can include a head-mounted band 2100 and a display device storage case 2200. The head-mounted band 2100 can be connected to the display device storage case 2200. The head-mounted band 2100 can include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the head of a user. The horizontal band can be formed around (e.g., encircle) the side of the head of the user, and the vertical band can be formed around (e.g., encircle) the top of the head of the user. However, the present disclosure is not necessarily limited thereto. For example, the head-mounted band 2100 can be implemented in the form of a glasses frame and / or a helmet, etc.

[0217] The display device storage case 2200 can store the first display device 1210 and the second display device 1220 of Figure 20 The display device storage case 2200 can further store the processor 1100 of Figure 20

[0218] Figure 22 is a diagram illustrating a head-mounted display device worn by a user according to one or more embodiments of the present disclosure. Figure 21

[0219] Referring to Figure 22 , the first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 can be disposed in the head-mounted display device 2000. The head-mounted display device 2000 can further include one or more lenses LLNS and RLNS.

[0220] Within the display device storage case 2200, the right-eye lens RLNS can be disposed between the first display panel DP1 and the right eye of the user. Within the display device storage case 2200, the left-eye lens LLNS can be disposed between the second display panel DP2 and the left eye of the user.

[0221] An image output from the first display panel DP1 can be displayed to the right eye of the user through the right-eye lens RLNS. The right-eye lens RLNS can refract light from the first display panel DP1 toward the right eye of the user. The right-eye lens RLNS can perform an optical function to adjust a viewing distance between the first display panel DP1 and the right eye of the user.

[0222] An image output from the second display panel DP2 can be displayed to the left eye of the user through the left-eye lens LLNS. The left-eye lens LLNS can refract light from the second display panel DP2 toward the left eye of the user. The left-eye lens LLNS can perform an optical function to adjust a viewing distance between the second display panel DP2 and the left eye of the user.

[0223] ​​Each of the right-eye lens RLNS and the left-eye lens LLNS can include an optical lens having a cross-section in the shape of a thin pancake, e.g., a convex shape. Each of the right-eye lens RLNS and the left-eye lens LLNS can include a multi-channel lens including sub-regions having different optical properties. In such embodiments, each display panel can output images corresponding to the sub-regions of the multi-channel lens, respectively, and the output images can pass through the corresponding sub-regions and be displayed to the user.

[0224] Various embodiments of the present disclosure provide a display device that can maintain high optical properties while ensuring cathode connectivity, a method of manufacturing a display device, and a deposition mask.

[0225] However, aspects and features of the present disclosure are not limited to the above-described aspects and features, and one or more suitable other aspects and features within the spirit and scope of the present disclosure will be understood by one of ordinary skill in the art.

[0226] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0227] Also, in describing embodiments of the present disclosure, the use of “may” indicates “one or more embodiments of the present disclosure.”

[0228] As used herein, the terms “substantially,” “approximately,” and similar terms are used as approximation terms and not as degree terms, and are intended to account for variations in measurement values or calculated values that would be recognized by one of ordinary skill in the art. “Substantially” as used herein includes the recited value and means that, considering the measurement being discussed and the error associated with the measurement of the specific quantity (i.e., the limitations of the measurement system), the value is within an acceptable range of deviation from the specific value as determined by one of ordinary skill in the art. For example, “substantially” can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the recited value.

[0229] The display apparatus, electronic device, apparatus for manufacturing a display apparatus, or any other related apparatus or component according to embodiments of the disclosure described herein can be implemented using any suitable hardware, firmware (for example, application specific integrated circuits), software, or combinations thereof. For example, various components of the apparatus can be formed on one integrated circuit (IC) chip or on separate IC chips. Also, various components of the apparatus can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, various components of the apparatus can be processes or threads running on one or more processors in one or more computing apparatuses, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in memory which can be implemented using any suitable memory (for example, random access memory (RAM)). The computer program instructions can also be stored in any non-transitory computer readable media (for example, CD-ROM, flash drive, etc.). Also, those skilled in the relevant art will recognize that the functionality of various computing apparatuses can be combined or integrated into a single computing apparatus, or the functionality of a particular computing apparatus can be distributed across one or more other computing apparatuses without departing from the scope of embodiments of the disclosure.

[0230] It will be understood that the description of features or aspects within each embodiment should generally be taken to apply to other similar features or aspects in other embodiments unless otherwise described. Accordingly, it will be apparent to those ordinary skilled in the art that features, attributes and / or elements described in conjunction with a particular embodiment can be used alone or in combination with features, attributes and / or elements described in conjunction with other embodiments, unless otherwise indicated. It will be understood that the foregoing is a description of various example embodiments and that it is not to be interpreted in a limiting sense. Various modifications to the disclosed embodiments and other example embodiments, as well as features and / or elements thereof, will be apparent to those skilled in the art and are intended to be included within the spirit and scope of the disclosure as defined by the appended claims and their equivalents.

Claims

1. A display device, the display device comprising: A pixel includes one or more sub-pixels, each sub-pixel having an emitting region to emit light, and the pixel having a non-emitting region surrounding the emitting region of the sub-pixel; A pixel defining layer is superimposed on the non-emitting region and defines a trench in the boundary region between adjacent sub-pixels of the sub-pixel, the trench penetrating the pixel defining layer; The emission structure is located on a portion of the trench and the pixel defining layer; Cathode, on the emitting structure; as well as An auxiliary electrode is located on the portion of the cathode.

2. The display device according to claim 1, wherein, The auxiliary electrode is located on the portion of the cathode that overlaps with the boundary region.

3. The display device according to claim 2, wherein: The cathode is superimposed on a non-boundary region adjacent to the boundary region; and The auxiliary electrode is not superimposed on the non-boundary region.

4. The display device according to claim 1, wherein, The auxiliary electrode comprises a conductive material.

5. The display device according to claim 4, wherein, The auxiliary electrode includes indium zinc oxide, aluminum, or silver.

6. The display device according to claim 1, wherein the display device further comprises an encapsulation layer covering the cathode and the auxiliary electrode.

7. The display device according to claim 1, wherein, The launching structure includes: The first transmitting section includes a first hole transport section, a first transmitting layer, and a first electron transport section; The second transmitting section includes a second hole transport section, a second transmitting layer, and a second electron transport section; and A charge generation layer is located between the first emitting portion and the second emitting portion.

8. A display device, the display device comprising: A pixel includes one or more sub-pixels, each sub-pixel having an emitting region to emit light, and the pixel having a non-emitting region surrounding the emitting region of the sub-pixel; A pixel defining layer is superimposed on the non-emitting region and defines a trench in the boundary region between adjacent sub-pixels of the sub-pixel, the trench penetrating the pixel defining layer; The emission structure is located on a portion of the trench and the pixel defining layer; as well as Cathode, on the emission structure, Wherein, the thickness of the portion of the cathode overlapping with the boundary region is greater than the thickness of the portion of the cathode overlapping with the non-boundary region adjacent to the boundary region.

9. A display device, the display device comprising: A pixel includes one or more sub-pixels, each sub-pixel having an emitting region to emit light, and the pixel having a non-emitting region surrounding the emitting region of the sub-pixel; A pixel defining layer is superimposed on the non-emitting region and defines a trench in the boundary region between adjacent sub-pixels of the sub-pixel, the trench penetrating the pixel defining layer; The emission structure is located on a portion of the trench and the pixel defining layer; as well as Cathode, on the emission structure, The portion of the cathode that overlaps with the trench has a gentle slope.

10. A deposition mask, the deposition mask comprising: frame; The concealed portions are spaced apart from each other within the frame; as well as A support portion for securing the shielding portion within the frame; The deposition mask defines an opening between the frame, the masking portion, and the support portion.

11. The deposition mask according to claim 10, wherein, The structure of the masking portion varies depending on the structure of the sub-pixels to be deposited.

12. The deposition mask according to claim 11, wherein, The masked portion corresponds to the non-boundary region of the sub-pixel.

13. The deposition mask according to claim 12, wherein, The opening corresponds to the boundary region of the sub-pixel.

14. The deposition mask according to claim 13, wherein, The opening allows deposited material to pass through, so that the deposited material is deposited on the cathode superimposed with the boundary region.

15. A method for manufacturing a display device, the method comprising the following steps: An anode is formed on the planarization layer; A pixel defining layer is formed on a portion of the anode and the planarization layer, the pixel defining layer defining a sub-pixel at a portion of the anode where the pixel defining layer is not positioned; A trench penetrating the pixel defining layer is formed in the boundary region between adjacent sub-pixels of the sub-pixel; An emission structure is formed on portions of the trench and the pixel defining layer; A cathode is formed on the emission structure; as well as The laser is directed onto the portion of the cathode that overlaps with the trench.

16. The method according to claim 15, wherein, During the step of irradiating the laser, the portion of the cathode that overlaps with the trench is melted to form a gentle slope.

17. The method according to claim 16, wherein, The thickness of the portion of the cathode that overlaps with the trench is less than the thickness of the remaining portion that does not overlap with the trench.

18. The method of claim 15, further comprising forming an encapsulation layer on the cathode.

Images