Opto-coupling structure and method of manufacturing the same

Abstract

The application relates to an optoelectronic coupling structure and a manufacturing method thereof. The optoelectronic coupling structure comprises a substrate, an electronic integrated chip and a first chip located on the substrate, a plurality of first chips are arranged at intervals around the periphery of the electronic integrated chip, a rewiring layer is located on the electronic integrated chip and the first chip, a plurality of second chips are located on the rewiring layer and arranged at intervals along the extension direction of the boundary of the electronic integrated chip, a plurality of photonic integrated chips are located on the rewiring layer and arranged at intervals around a second region, wherein the projection of the photonic integrated chip at least partially overlaps the projection of the first chip, and the projection of the photonic integrated chip at least partially overlaps the projection of the electronic integrated chip; the photonic integrated chip is electrically interconnected with the electronic integrated chip through the rewiring layer. In this way, the signal integrity of high-speed signals in the transmission process of the optoelectronic coupling structure can be improved, the transmission loss can be reduced, the packaging area can be reduced, and the integration degree of the packaging structure can be improved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to optocoupler structures and their manufacturing methods. Background Technology

[0002] In related technologies, optoelectronic packaging structures suffer from long transmission lines, making it difficult to guarantee signal integrity during high-speed signal transmission and significantly increasing transmission loss. Furthermore, the physical separation between the optical engine (e.g., optical chip, driver, transimpedance amplifier, etc.) and the electrical chip in optoelectronic packaging structures results in a large package area and low integration density. Therefore, achieving efficient integration and packaging of optical and electrical chips has become a pressing technical problem. Summary of the Invention

[0003] Therefore, it is necessary to provide an optoelectronic coupling structure to address the problems of signal integrity not being guaranteed, transmission loss being significantly increased, large packaging area being occupied, and low integration density in optoelectronic packaging structures.

[0004] An optocoupler structure includes: a substrate; at least one electronic integrated chip and a plurality of first chips, the electronic integrated chip and the first chips being located on the substrate, the plurality of first chips being spaced apart around the periphery of the electronic integrated chip; wherein the projection of the electronic integrated chip onto the plane of the substrate is located in a first region; a redistribution layer being located on the electronic integrated chip and the first chips; a plurality of second chips being located on the redistribution layer and spaced apart along the boundary extension direction of the electronic integrated chip; wherein the projection of the plurality of second chips onto the plane of the substrate is located in a second region, the second region being located within the first region; a plurality of photonic integrated chips being located on the redistribution layer and spaced apart around the second region; wherein the projection of the photonic integrated chip onto the plane of the substrate at least partially overlaps the projection of the first chips onto the plane of the substrate, and the projection of the photonic integrated chip onto the plane of the substrate at least partially overlaps the projection of the electronic integrated chip onto the plane of the substrate; the photonic integrated chip is electrically interconnected with the electronic integrated chip through the redistribution layer.

[0005] In one embodiment, both the first chip and the photonic integrated chip extend along a direction perpendicular to the boundary of the electronic integrated chip, and the projection of the first chip onto the plane of the substrate lies within the projection of the photonic integrated chip onto the plane of the substrate. This shortens the interconnection path between the photonic integrated chip and the first chip, thereby reducing the photoelectric conversion distance between the photonic integrated chip and the electronic integrated chip, and improving packaging integration and signal transmission efficiency.

[0006] In one embodiment, the electronic integrated chip and the first chip, located on the same layer, are electrically interconnected through the redistribution layer; the photonic integrated chip and the second chip, also located on the same layer, are electrically interconnected through the redistribution layer. This further shortens the signal transmission distance between the photonic integrated chip and the electronic integrated chip, improves the signal integrity of high-speed signals during transmission in the optocoupler structure, reduces transmission loss, reduces the package footprint, and increases the integration density of the package structure.

[0007] In one embodiment, the optocoupler structure further includes: a packaging module and a molded through-hole; the electronic integrated chip and the first chip are located in the packaging module; the molded through-hole is located in the packaging module and is situated around the electronic integrated chip and the first chip. The manufacturing cost of using molded through-holes is significantly lower than that of through-silicon vias (TSVs), which is beneficial for mass production and reduces packaging costs.

[0008] In one embodiment, the first chip is a transimpedance amplifier chip and the second chip is a driver chip; or, the first chip is a driver chip and the second chip is a transimpedance amplifier chip.

[0009] Based on this, this application also provides a method for manufacturing an optocoupler structure, the method comprising: providing a first substrate on which a redistribution layer is formed; flip-chip bonding at least one electronic integrated chip and a plurality of first chips onto the redistribution layer; wherein the plurality of first chips are spaced apart around the periphery of the electronic integrated chip, and the projection of the electronic integrated chip onto the plane of the redistribution layer is located in a first region; bonding a second substrate to the surface of the electronic integrated chip and the first chips away from the first substrate, and debonding the first substrate to expose the surface of the redistribution layer; flip-chip bonding a plurality of second chips and a plurality of photonic integrated chips onto the redistribution layer; wherein the plurality of second chips are spaced apart along the extension direction of the boundary of the electronic integrated chip, and the projection of the plurality of second chips onto the plane of the redistribution layer is located in a second region. The first region is located within the second region; a plurality of photonic integrated chips are arranged at intervals around the second region, the projections of the photonic integrated chips on the plane of the redistribution layer at least partially overlap with the projections of the first chip on the plane of the redistribution layer, and the projections of the photonic integrated chips on the plane of the redistribution layer at least partially overlap with the projections of the electronic integrated chips on the plane of the redistribution layer; the photonic integrated chips are electrically interconnected with the electronic integrated chips through the redistribution layer; a third carrier is bonded to the surfaces of the second chip and the photonic integrated chips away from the second carrier, and the second carrier is debonded to expose the surfaces of the electronic integrated chips and the first chip; a substrate is bonded to the surfaces of the electronic integrated chips and the first chip away from the third carrier, and the third carrier is debonded to form the optocoupler structure.

[0010] In one embodiment, both the first chip and the photonic integrated chip extend along a direction perpendicular to the boundary of the electronic integrated chip, and the projection of the first chip onto the plane of the substrate lies within the projection of the photonic integrated chip onto the plane of the substrate. This shortens the interconnection path between the photonic integrated chip and the first chip, thereby reducing the photoelectric conversion distance between the photonic integrated chip and the electronic integrated chip, and improving packaging integration and signal transmission efficiency.

[0011] In one embodiment, the electronic integrated chip and the first chip, located on the same layer, are electrically interconnected through the redistribution layer; the photonic integrated chip and the second chip, also located on the same layer, are electrically interconnected through the redistribution layer. This further shortens the signal transmission distance between the photonic integrated chip and the electronic integrated chip, improves the signal integrity of high-speed signals during transmission in the optocoupler structure, reduces transmission loss, reduces the package footprint, and increases the integration density of the package structure.

[0012] In one embodiment, before flip-bonding at least one of the electronic integrated chips and a plurality of the first chips onto the redistribution layer, the method further includes: forming a molded via on the redistribution layer, the molded via being located in the edge region of the redistribution layer; after flip-bonding at least one of the electronic integrated chips and a plurality of the first chips onto the redistribution layer, the method further includes: forming an encapsulation layer on the redistribution layer, the encapsulation layer encapsulating the electronic integrated chip and the first chips to form an encapsulation module. The manufacturing cost of using molded vias is much lower than that of through-silicon vias (TSVs), which is beneficial for mass production and reduces packaging costs.

[0013] In one embodiment, the first chip is a transimpedance amplifier chip and the second chip is a driver chip; or, the first chip is a driver chip and the second chip is a transimpedance amplifier chip.

[0014] The optocoupler structure and its manufacturing method provided in this application can break the physical boundary between the optical engine and the electronic integrated chip, and form a three-dimensional optocoupler tightly co-packaged structure in a tightly integrated manner. This shortens the high-speed transmission trace distance of the optocoupler conversion signal and the electro-optic conversion signal, resulting in an optocoupler structure with a shorter optocoupler conversion distance. This can improve the signal integrity of the high-speed signal in the optocoupler structure during transmission, reduce transmission loss, reduce the package area occupied, and improve the integration of the package structure. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a cross-sectional schematic diagram of the optocoupler structure provided in the embodiments of this application;

[0017] Figure 2 This is a top view of the optocoupler structure provided in the embodiments of this application;

[0018] Figure 3 A schematic flowchart illustrating the manufacturing method of the optocoupler structure provided in the embodiments of this application;

[0019] Figure 4 A cross-sectional structural schematic diagram of the fabrication process for forming a redistribution layer provided in an embodiment of this application;

[0020] Figure 5 A cross-sectional structural schematic diagram of the preparation process for forming a molded through hole provided in an embodiment of this application;

[0021] Figure 6 A cross-sectional structural schematic diagram of the fabrication process for forming an electronic integrated chip and a first chip, provided in an embodiment of this application;

[0022] Figure 7 A cross-sectional structural schematic diagram of the fabrication process for forming the encapsulation module provided in an embodiment of this application;

[0023] Figure 8 A cross-sectional structural schematic diagram of the fabrication process of the bonding second carrier plate provided in the embodiments of this application;

[0024] Figure 9 A cross-sectional structural schematic diagram of the fabrication process for forming the second chip and the photonic integrated chip provided in the embodiments of this application;

[0025] Figure 10 A cross-sectional structural schematic diagram of the fabrication process of the bonding third carrier provided in the embodiments of this application;

[0026] Figure 11 This is a cross-sectional structural schematic diagram of the fabrication process of the bonding substrate provided in the embodiments of this application.

[0027] In the diagram: 10, substrate; 21, electronic integrated chip; 22, first chip; 23, photonic integrated chip; 24, second chip; 30, redistribution layer; 41, first solder ball; 42, second solder ball; 43, third solder ball; 50, packaging module; 51, molded through-hole; 60, fiber array; 101, first carrier board; 102, second carrier board; 103, third carrier board. Detailed Implementation

[0028] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional scope of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0030] In this invention, numerical ranges are involved. Unless otherwise specified, the numerical ranges are considered continuous and include the minimum and maximum values ​​of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values ​​of the range. Additionally, when multiple ranges are provided to describe features or characteristics, the ranges may be merged. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are included.

[0031] This application provides an optocoupler structure. Figure 1 This is a cross-sectional schematic diagram of the optocoupler structure provided in the embodiments of this application; Figure 2 This is a top view schematic diagram of the optocoupler structure provided in an embodiment of this application. Please refer to... Figure 1 and Figure 2 The optocoupler structure includes:

[0032] substrate 10;

[0033] At least one electronic integrated chip 21 and a plurality of first chips 22 are located on a substrate 10, and the plurality of first chips 22 are arranged at intervals around the electronic integrated chip 21; wherein, the projection of the electronic integrated chip 21 onto the plane of the substrate 10 is located in a first region A.

[0034] Redundancy layer 30 is located on electronic integrated chip 21 and first chip 22;

[0035] Multiple second chips 24 are located on the redistribution layer 30 and are spaced apart along the extension direction of the electronic integrated chip 21 boundary; wherein the projection of the multiple second chips 24 on the plane of the substrate 10 is located in the second region B, and the second region B is located within the first region A.

[0036] Multiple photonic integrated chips 23 are located on the redistribution layer 30 and are spaced apart around the second region B; wherein the projection of the photonic integrated chip 23 onto the plane of the substrate 10 at least partially overlaps with the projection of the first chip 22 onto the plane of the substrate 10, and the projection of the photonic integrated chip 23 onto the plane of the substrate 10 at least partially overlaps with the projection of the electronic integrated chip 21 onto the plane of the substrate 10; the photonic integrated chip 23 is electrically interconnected with the electronic integrated chip 21 through the redistribution layer 30.

[0037] Understandably, the optocoupler structure provided in this application can break the physical boundary between the optical engine and the electronic integrated chip 21, forming a three-dimensional optocoupler tightly co-packaged structure in a tightly integrated manner. This shortens the high-speed transmission trace distance of the optocoupler conversion signal and the electro-optical conversion signal, resulting in an optocoupler structure with a shorter optocoupler conversion distance. This can improve the signal integrity of the high-speed signal in the optocoupler structure during transmission, reduce transmission loss, reduce the package area occupied, and improve the integration of the package structure.

[0038] Here, substrate 10 may include rigid substrate and flexible substrate. Substrate 10 can be connected to a printed circuit board (PCB) for power supply and communication. In this embodiment, substrate 10 can be an organic substrate. Organic substrates can achieve fine wiring, meeting the requirements of high-performance chips for size and signal transmission efficiency. Furthermore, organic substrates have low dielectric constant and loss factor, making them suitable for high-frequency signal transmission and helping to reduce signal delay and transmission loss.

[0039] In some embodiments, the electronic integrated chip 21 can be an application-specific integrated circuit (ASIC) chip; the photonic integrated chip 23 can be called a photonic integrated circuit (PIC) chip.

[0040] In some embodiments, please refer to Figure 1 The first chip 22 and the second chip 24 can be part of an optical engine. Specifically, the first chip 22 can be a trans-impedance amplifier (TIA) chip, and the second chip 24 can be a driver chip; or, the first chip 22 can be a driver chip, and the second chip 24 can be a trans-impedance amplifier chip. In this embodiment, the first chip 22 is a trans-impedance amplifier chip, and the second chip 24 is a driver chip.

[0041] In some embodiments, the electronic integrated chip 21 and the first chip 22 can be placed on the substrate 10, with the electronic integrated chip 21 and the first chip 22 located on the same layer, and the top surface of the electronic integrated chip 21 being flush with the top surface of the first chip 22. The electronic integrated chip 21 and the first chip 22 can be electrically connected to the substrate 10 via a first solder ball 41, which may include a flip-chip bump (C4 bump).

[0042] In some embodiments, please refer to Figure 2, a plurality of first chips 22 are arranged at intervals around the periphery of the electronic integrated chip 21, which can also be said that the plurality of first chips 22 are arranged at intervals along the extension direction of the boundary of the electronic integrated chip 21; specifically, the projection of the electronic integrated chip 21 on the plane where the substrate 10 is located is located in the first region A, and the plurality of first chips 22 are arranged at intervals around the first region A.

[0043] In some specific embodiments, please refer to Figure 2 , the first ends of the plurality of first chips 22 are close to the boundary of the electronic integrated chip 21, and the plurality of first chips 22 extend along a direction perpendicular to the extension direction of the boundary of the electronic integrated chip 21. The second ends of the plurality of first chips 22 are far from the boundary of the electronic integrated chip 21. The direction from the first end to the second end of the first chip 22 is the length direction of the first chip 22 (the direction perpendicular to the extension direction of the boundary of the electronic integrated chip 21). In this way, more first chips 22 can be arranged around the electronic integrated chip 21 as much as possible. While optimizing the layout density of the plurality of first chips 22, the interconnection path between the first chip 22 and the electronic integrated chip 21 is shortened, thereby shortening the optoelectronic conversion distance between the photon integrated chip 23 and the electronic integrated chip 21, and improving the packaging integration degree and signal transmission efficiency.

[0044] In the embodiments of the present application, please refer to Figure 2 , the shape of the electronic integrated chip 21 is rectangular (the shape of the first region A is rectangular). The four sides of the rectangle can be the four sub-boundaries of the electronic integrated chip 21. The number of the first chips 22 near different sides of the rectangle can be the same, and the plurality of first chips 22 near the same side of the rectangle are arranged at equal intervals. Of course, in some other embodiments, the shape of the electronic integrated chip 21 can be circular or other shapes. The number of the first chips 22 near the plurality of sub-boundaries of the electronic integrated chip 21 can be the same, and the plurality of first chips 22 near the same sub-boundary of the electronic integrated chip 21 are arranged at equal intervals. The arrangement manner of the first chips 22 can be specifically set according to the shape of the electronic integrated chip 21 to ensure that the first chips 22 have the optimal layout density. The present application does not make specific limitations on this.

[0045] In some embodiments, please refer to Figure 2 , the projections of the plurality of second chips 24 on the plane where the substrate 10 is located are in a "hui" shape; the projections of the plurality of second chips 24 on the plane where the substrate 10 is located are located in the projection of the electronic integrated chip 21 on the plane where the substrate 10 is located. In the embodiments of the present application, the projections of the plurality of second chips 24 on the plane where the substrate 10 is located are located in the second region B, and the shape of the second region B is the same as the shape of the first region A; the second chips 24 and the photon integrated chip 23 are located on the same layer, and the top surface of the second chip 24 is flush with the top surface of the photon integrated chip 23.

[0046] In some embodiments, please refer to Figure 2 Multiple photonic integrated chips 23 are spaced apart around the second region B, or in other words, multiple photonic integrated chips 23 are spaced apart along the extension direction of the boundary of the second region B, which is beneficial for the mounting and coupling of the fiber array 60 (FA). The first end of the multiple photonic integrated chips 23 is close to the boundary of the second region B, and the multiple photonic integrated chips 23 extend in a direction perpendicular to the extension direction of the boundary of the second region B. The second end of the multiple photonic integrated chips 23 is far away from the boundary of the second region B. The direction from the first end to the second end of the photonic integrated chip 23 is the length direction of the photonic integrated chip 23 (the direction perpendicular to the extension direction of the boundary of the photonic integrated chip 23).

[0047] In some specific embodiments, the projection of the photonic integrated chip 23 onto the plane of the substrate 10 at least partially overlaps with the projection of the first chip 22 onto the plane of the substrate 10, and the projection of the photonic integrated chip 23 onto the plane of the substrate 10 at least partially overlaps with the projection of the electronic integrated chip 21 onto the plane of the substrate 10; or, the photonic integrated chip 23 at least partially covers the electronic integrated chip 21, and the photonic integrated chip 23 at least partially covers the first chip 22.

[0048] It is understood that in the above embodiments, the photonic integrated chip 23 can adopt the same arrangement as the first chip 22. As many photonic integrated chips 23 as possible can be set up, the layout density of multiple photonic integrated chips 23 can be optimized, the interconnection path between the photonic integrated chip 23 and the first chip 22 and the second chip 24 can be shortened, and the photoelectric conversion distance between the photonic integrated chip 23 and the electronic integrated chip 21 can be shortened, thereby improving the packaging integration and signal transmission efficiency.

[0049] In some embodiments, the photonic integrated chip 23 is located on the electronic integrated chip 21 and extends to the first chip 22; the photonic integrated chip 23 and the electronic integrated chip 21 are assembled together in a stacked manner, so that the interconnection between the photonic integrated chip 23 and the electronic integrated chip 21 is shorter and the performance is better, which can further reduce the package size and improve the package integration.

[0050] In some embodiments, please refer to Figure 2 Both the first chip and the photonic integrated chip 23 extend in a direction perpendicular to the boundary of the electronic integrated chip 21. The projection of the first chip 22 onto the plane of the substrate 10 lies within the projection of the photonic integrated chip 23 onto the plane of the substrate 10. This minimizes the interconnection path between the photonic integrated chip 23 and the first chip 22, thereby shortening the photoelectric conversion distance between the photonic integrated chip 23 and the electronic integrated chip 21, and improving packaging integration and signal transmission efficiency.

[0051] In some embodiments, please refer to Figure 1 The redistribution layer 30 (RDL) may include an interlayer dielectric layer consisting of a metal interconnect layer and an isolation layer between the metal interconnect layers. The redistribution layer 30 can be used for electrical connections between the photonic integrated chip 23 and the electronic integrated chip 21, as well as other devices. The specific structure of the redistribution layer 30 can be customized according to actual packaging requirements.

[0052] In some specific embodiments, please refer to Figure 1 The photonic integrated chip 23 is electrically interconnected with the electronic integrated chip 21 through the redistribution layer 30, achieving vertical electrical interconnection. The electronic integrated chip 21 and the first chip 22, located on the same layer, can be electrically interconnected through the redistribution layer 30. Similarly, the photonic integrated chip 23 and the second chip 24, also located on the same layer, can be electrically interconnected through the redistribution layer 30. The electronic integrated chip 21, the first chip 22, the photonic integrated chip 23, and the second chip 24 are all interconnected with the redistribution layer 30 using flip-chip bonding. This further shortens the signal transmission distance between the photonic integrated chip 23 and the electronic integrated chip 21, improves the signal integrity of high-speed signals during transmission in the optocoupler structure, reduces transmission loss, reduces the package footprint, and increases the integration density of the package structure.

[0053] In the embodiments of this application, please refer to Figure 1 The photoelectric conversion path C is: fiber array 60 → photonic integrated chip 23 → first chip 22 (transimpedance amplifier) ​​→ electronic integrated chip 21; the electro-optical conversion path D is: electronic integrated chip 21 → second chip 24 (driver chip) → photonic integrated chip 23 → fiber array 60.

[0054] In some embodiments, please refer to Figure 1 The optocoupler structure also includes: a packaging module 50 and a molded through-hole 51 (TMV); the electronic integrated chip 21 and the first chip 22 are located in the packaging module 50; the molded through-hole 51 is located in the packaging module 50 and is located around the electronic integrated chip 21 and the first chip 22.

[0055] It should be noted that the redistribution layer 30 may include an edge region and a central region. Here, the central region is the area where the electronic integrated chip 21 and the first chip 22 are located, and the edge region is the area outside the central region (the area on the redistribution layer 30 that is not covered by the electronic integrated chip 21 and the first chip 22). In this embodiment, the molded via 51 is located around the electronic integrated chip 21 and the first chip 22, or the molded via 51 is located in the edge region of the redistribution layer 30.

[0056] In some specific embodiments, the molded through-hole 51 penetrates the packaging module 50, and the redistribution layer 30 is electrically connected to the substrate 10 through the molded through-hole 51 and a plurality of first solder balls 41.

[0057] It is understandable that the first chip 22 and the electronic integrated chip 21 are co-packaged in the packaging module 50. The first chip 22 and the electronic integrated chip 21 are tightly integrated to achieve optoelectronic co-packaging, which can improve the signal integrity of high-speed signals in the optocoupler structure during transmission, reduce transmission loss, reduce the packaging area occupied, and improve the integration of the packaging structure. The molded through-hole 51 can replace the TSV (through silicon via) in the three-dimensional packaging of the prior art. The manufacturing cost of the molded through-hole 51 is much lower than that of the through silicon via, which is conducive to mass production and reduces packaging costs.

[0058] In some embodiments, please refer to Figure 1 The packaging module 50 also includes a plurality of second solder balls 42, which are located on top of the first chip 22 and the electronic integrated chip 21. The redistribution layer 30 can be electrically connected to the first chip 22 and the electronic integrated chip 21 through the second solder balls 42. The second solder balls 42 may include micro bumps.

[0059] In some embodiments, please refer to Figure 1 The optocoupler structure also includes multiple third solder balls 43, which are located on top of the redistribution layer 30. The redistribution layer 30 can be electrically connected to the second chip 24 and the photonic integrated chip 23 via the third solder balls 43. The third solder balls 43 may include microbumps. It should be noted that the size of the first solder ball 41 (C4 bump) is larger than the size of the microbumps used by the second solder ball 42 and the third solder ball 43. Microbumps are commonly used for interconnection between chips, while C4 bumps are commonly used for interconnection between chips and the substrate 10.

[0060] Based on this, embodiments of this application also provide a method for manufacturing an optocoupler structure. Figure 3 A schematic flowchart illustrating the manufacturing method of the optocoupler structure provided in this application embodiment is shown in the figure. The manufacturing method of the optocoupler structure includes:

[0061] Step S101: Provide a first carrier board, on which a redistribution layer is formed;

[0062] Step S102: At least one electronic integrated chip and a plurality of first chips are flip-bonded on the redistribution layer; wherein, the plurality of first chips are arranged at intervals around the periphery of the electronic integrated chip, and the projection of the electronic integrated chip on the plane of the redistribution layer is located in the first region;

[0063] Step S103: Bond the second substrate to the surface of the electronic integrated chip and the first chip away from the first substrate, and debond the first substrate to expose the surface of the redistribution layer;

[0064] Step S104: A plurality of second chips and a plurality of photonic integrated chips are flip-bonded onto a redistribution layer; wherein, the plurality of second chips are spaced apart along the extension direction of the electronic integrated chip boundary, and the projections of the plurality of second chips on the plane of the redistribution layer are located in a second region, which is located within a first region; the plurality of photonic integrated chips are spaced apart around the second region, and the projections of the photonic integrated chips on the plane of the redistribution layer at least partially overlap with the projections of the first chips on the plane of the redistribution layer, and the projections of the photonic integrated chips on the plane of the redistribution layer at least partially overlap with the projections of the electronic integrated chips on the plane of the redistribution layer; the photonic integrated chips are electrically interconnected with the electronic integrated chips through the redistribution layer;

[0065] Step S105: Bond a third carrier to the surface of the second chip and the photonic integrated chip away from the second carrier, and debond the second carrier to expose the surfaces of the electronic integrated chip and the first chip.

[0066] Step S106: Bond substrates to the surfaces of the electronic integrated chip and the first chip away from the third carrier, and debond the third carrier to form an optocoupler structure.

[0067] It should be understood that although the steps in the above flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Moreover, at least some of the steps in the above flowchart may include multiple steps or stages, and these steps or stages are not necessarily completed at the same time, nor are they necessarily performed sequentially.

[0068] Figure 4 A cross-sectional structural schematic diagram of the fabrication process for forming a redistribution layer provided in an embodiment of this application; Figure 5 A cross-sectional structural schematic diagram of the preparation process for forming a molded through hole provided in an embodiment of this application; Figure 6 A cross-sectional structural schematic diagram of the fabrication process for forming an electronic integrated chip and a first chip, provided in an embodiment of this application; Figure 7 A cross-sectional structural schematic diagram of the fabrication process for forming the encapsulation module provided in an embodiment of this application; Figure 8 A cross-sectional structural schematic diagram of the fabrication process of the bonding second carrier plate provided in the embodiments of this application; Figure 9 A cross-sectional structural schematic diagram of the fabrication process for forming the second chip and the photonic integrated chip provided in the embodiments of this application; Figure 10 A cross-sectional structural schematic diagram of the fabrication process of the bonding third carrier provided in the embodiments of this application; Figure 11 This is a cross-sectional structural schematic diagram of the fabrication process of the bonding substrate provided in the embodiments of this application.

[0069] Below, in conjunction with Figures 4 to 11The manufacturing method of the optocoupler structure provided in the embodiments of this application and its beneficial effects are further described in detail.

[0070] First, please refer to Figure 4 In step S101, a first carrier board 101 is provided, and a redistribution layer 30 is formed on the first carrier board 101.

[0071] In some embodiments, the first carrier 101 and the subsequent second and third carriers are all temporary carriers. The carriers can be made of materials such as silicon, glass, ceramic, sapphire or metal. Temporary carriers can provide mechanical support, protection and process compatibility for structures such as chips.

[0072] In some embodiments, the redistribution layer 30 may include an interlayer dielectric layer between a metal interconnect layer and an isolation metal interconnect layer; the material of the interlayer dielectric layer may include silicon dioxide (SiO2), and the material of the metal interconnect layer may include copper (Cu). The structure of the redistribution layer 30 can be customized according to actual packaging requirements, and multilayer redistribution layer traces can be fabricated according to wiring requirements.

[0073] Then, please refer to Figure 6 In step S102, at least one electronic integrated chip 21 and a plurality of first chips 22 are flip-bonded onto the redistribution layer 30; wherein, the plurality of first chips 22 are spaced apart around the electronic integrated chip 21, and the projection of the electronic integrated chip 21 onto the plane of the redistribution layer 30 is located in the first region A (e.g., Figure 2 (As shown).

[0074] In some embodiments, the first ends of the plurality of first chips 22 are close to the boundary of the electronic integrated chip 21, and the plurality of first chips 22 extend in a direction perpendicular to the extension direction of the boundary of the electronic integrated chip 21, and the second ends of the plurality of first chips 22 are far away from the boundary of the electronic integrated chip 21.

[0075] In some embodiments, please refer to Figure 5 Before flip-bonding at least one electronic integrated chip 21 and a plurality of first chips 22 onto the redistribution layer 30, the method may further include: forming a molded via 51 on the redistribution layer 30, the molded via 51 being located in the edge region of the redistribution layer 30.

[0076] It should be noted that the redistribution layer 30 may include an edge region and a central region. Here, the central region can be the area where the subsequently formed electronic integrated chip and the first chip are located, and the edge region is the area outside the central region on the redistribution layer.

[0077] In some embodiments, please refer to Figure 5Before flip-bonding at least one electronic integrated chip 21 and a plurality of first chips 22 onto the redistribution layer 30, the method may further include: forming a second solder ball 42 on the redistribution layer 30, the second solder ball 42 being located in the central region of the redistribution layer 30. In some specific embodiments, the molded via 51 can be fabricated by processes such as photolithography, etching, and deposition; the second solder ball 42 can prepare for the subsequent bonding of the electronic integrated chip and the first chips.

[0078] In some embodiments, please refer to Figure 7 After flip-bonding at least one electronic integrated chip 21 and multiple first chips 22 onto the redistribution layer 30, the method further includes: forming an encapsulation layer on the redistribution layer 30, the encapsulation layer encapsulating the electronic integrated chip 21 and the first chips 22 to form an encapsulation module 50. Here, the first chips 22 and the electronic integrated chip 21 are co-encapsulated in the encapsulation module 50, and the first chips 22 and the electronic integrated chip 21 are tightly bonded together to achieve optoelectronic co-encapsulation.

[0079] Forming an encapsulation layer on the redistribution layer 30 may specifically include: using a molding material to encapsulate and fix the electronic integrated chip 21 and the first chip 22; and using a chemical mechanical polishing (CMP) process to smooth the surface of the molding material.

[0080] Next, please refer to Figure 8 In step S103, the second carrier 102 is bonded to the surfaces of the electronic integrated chip 21 and the first chip 22 that are away from the first carrier 101, and the first carrier 101 is debonded to expose the surface of the redistribution layer 30.

[0081] In some embodiments, please refer to Figure 8 After unbonding the first substrate 101 and exposing the surface of the redistribution layer 30, the method may further include forming a third solder ball 43 on the surface of the redistribution layer 30 away from the second substrate 102. The third solder ball 43 can prepare for the subsequent bonding of the photonic integrated chip 23 and the second chip 24.

[0082] Next, please refer to Figure 9 In step S104, multiple second chips 24 and multiple photonic integrated chips 23 are flip-bonded onto the redistribution layer 30; wherein, the multiple second chips 24 are spaced apart along the extension direction of the electronic integrated chip 21 boundary, and the projection of the multiple second chips 24 onto the plane of the redistribution layer 30 is located in the second region B (e.g., Figure 2As shown), the second region B is located within the first region A; multiple photonic integrated chips 23 are arranged at intervals around the second region B, and the projection of the photonic integrated chip 23 on the plane where the redistribution layer 30 is located at least partially overlaps with the projection of the first chip 22 on the plane where the redistribution layer 30 is located, and the projection of the photonic integrated chip 23 on the plane where the redistribution layer 30 is located at least partially overlaps with the projection of the electronic integrated chip 21 on the plane where the redistribution layer 30 is located; the photonic integrated chip 23 is electrically interconnected with the electronic integrated chip 21 through the redistribution layer 30.

[0083] In some embodiments, both the first chip 22 and the photonic integrated chip 23 extend along a direction perpendicular to the boundary of the electronic integrated chip 21, and the projection of the first chip 22 onto the plane of the redistribution layer 30 lies within the projection of the photonic integrated chip 23 onto the plane of the redistribution layer 30. This minimizes the interconnection path between the photonic integrated chip 23 and the first chip 22, thereby shortening the photoelectric conversion distance between the photonic integrated chip 23 and the electronic integrated chip 21, and improving packaging integration and signal transmission efficiency.

[0084] In some embodiments, the first chip 22 is a transimpedance amplifier chip and the second chip 24 is a driver chip; or, the first chip 22 is a driver chip and the second chip 24 is a transimpedance amplifier chip.

[0085] In some specific embodiments, the electronic integrated chip 21 and the first chip 22 located on the same layer are electrically interconnected through the redistribution layer 30; the photonic integrated chip 23 and the second chip 24 located on the same layer are electrically interconnected through the redistribution layer 30.

[0086] It is understandable that the transmission of high-speed signals between different chips can be achieved through the redistribution layer 30. The redistribution layer 30 can shorten the interconnection distance between chips, reduce the package size, and thus shorten the transmission distance between chips, which is conducive to high-speed signal high-quality transmission and reduces transmission loss.

[0087] Next, please refer to Figure 10 In step S105, a third carrier 103 is bonded to the surfaces of the second chip 24 and the photonic integrated chip 23 away from the second carrier 102, and the second carrier 102 is debonded to expose the surfaces of the electronic integrated chip 21 and the first chip 22.

[0088] In some embodiments, please refer to Figure 10 After unbonding the second substrate 102 and exposing the surfaces of the electronic integrated chip 21 and the first chip 22, the method may further include forming a first solder ball 41 on the exposed surfaces of the electronic integrated chip 21 and the first chip 22, the first solder ball 41 being prepared for subsequent bonding of the substrate.

[0089] Finally, please refer to Figure 11In step S106, the substrate 10 is bonded to the surface of the electronic integrated chip 21 and the first chip 22 away from the third carrier 103, and the third carrier 103 is debonded to form an optocoupler structure.

[0090] In some embodiments, please refer to Figure 11 After bonding the substrate 10 to the surfaces of the electronic integrated chip 21 and the first chip 22 away from the third carrier 103 and debonding the third carrier 103, the method may further include: coupling and mounting the fiber array 60 at the end of the photonic integrated chip 23 away from the second chip 24; and bonding the substrate 10 to the printed circuit board through the first solder ball 41 to perform power supply operation.

[0091] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0092] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for manufacturing an optocoupler structure, characterized in that, The manufacturing method of the optocoupler structure includes: A first carrier board is provided, on which a redistribution layer is formed; At least one electronic integrated chip and a plurality of first chips are flip-chip bonded on the redistribution layer; wherein, the plurality of first chips are arranged at intervals around the periphery of the electronic integrated chip, and the projection of the electronic integrated chip on the plane of the redistribution layer is located in a first region; A second substrate is bonded to the surface of the electronic integrated chip and the first chip away from the first substrate, and the first substrate is debonded to expose the surface of the redistribution layer. Multiple second chips and multiple photonic integrated chips are flip-chip bonded onto the redistribution layer; wherein, the multiple second chips are spaced apart along the extension direction of the electronic integrated chip boundary, and the projections of the multiple second chips on the plane of the redistribution layer are located in a second region, which is located within the first region; the multiple photonic integrated chips are spaced apart around the second region, and the projections of the photonic integrated chips on the plane of the redistribution layer at least partially overlap with the projections of the first chips on the plane of the redistribution layer, and the projections of the photonic integrated chips on the plane of the redistribution layer at least partially overlap with the projections of the electronic integrated chips on the plane of the redistribution layer; the photonic integrated chips are electrically interconnected with the electronic integrated chips through the redistribution layer; A third carrier is bonded to the surface of the second chip and the photonic integrated chip away from the second carrier, and the second carrier is debonded to expose the surfaces of the electronic integrated chip and the first chip; A substrate is bonded to the surface of the electronic integrated chip and the first chip away from the third carrier, and the third carrier is debonded to form the optocoupler structure.

2. The method for manufacturing the optocoupler structure according to claim 1, characterized in that, Both the first chip and the photonic integrated chip extend in a direction perpendicular to the boundary of the electronic integrated chip, and the projection of the first chip onto the plane of the substrate is located within the projection of the photonic integrated chip onto the plane of the substrate.

3. The method for manufacturing the optocoupler structure according to claim 1 or claim 2, characterized in that, The electronic integrated chip and the first chip, which are located on the same layer, are electrically interconnected through the redistribution layer; the photonic integrated chip and the second chip, which are located on the same layer, are electrically interconnected through the redistribution layer.

4. The method for manufacturing the optocoupler structure according to claim 3, characterized in that, Before flip-bonding at least one of the electronic integrated chips and a plurality of the first chips onto the redistribution layer, the method further includes: forming a molded via on the redistribution layer, the molded via being located in the edge region of the redistribution layer; After flip-bonding at least one of the electronic integrated chips and a plurality of the first chips onto the redistribution layer, the method further includes: forming an encapsulation layer on the redistribution layer, the encapsulation layer encapsulating the electronic integrated chip and the first chips to form an encapsulation module.

5. The method for manufacturing the optocoupler structure according to claim 3, characterized in that, The first chip is a transimpedance amplifier chip, and the second chip is a driver chip; or, the first chip is a driver chip, and the second chip is a transimpedance amplifier chip.

6. An optocoupler structure, characterized in that, The optocoupler structure includes: substrate; At least one electronic integrated chip and a plurality of first chips are located on the substrate, and the plurality of first chips are arranged at intervals around the periphery of the electronic integrated chip; wherein the projection of the electronic integrated chip on the plane of the substrate is located in a first region; A redistribution layer is located on the electronic integrated chip and the first chip; Multiple second chips are located on the redistribution layer and are spaced apart along the extension direction of the electronic integrated chip boundary; wherein the projection of the multiple second chips on the plane of the substrate is located in a second region, and the second region is located within the first region; Multiple photonic integrated chips are located on the redistribution layer and spaced apart around the second region; wherein the projection of the photonic integrated chip onto the plane of the substrate at least partially overlaps with the projection of the first chip onto the plane of the substrate, and the projection of the photonic integrated chip onto the plane of the substrate at least partially overlaps with the projection of the electronic integrated chip onto the plane of the substrate; the photonic integrated chip is electrically interconnected with the electronic integrated chip through the redistribution layer; The optocoupler structure is prepared using the manufacturing method described in any one of claims 1-5.

7. The optocoupler structure according to claim 6, characterized in that, Both the first chip and the photonic integrated chip extend in a direction perpendicular to the boundary of the electronic integrated chip, and the projection of the first chip onto the plane of the substrate is located within the projection of the photonic integrated chip onto the plane of the substrate.

8. The optocoupler structure according to claim 6 or claim 7, characterized in that, The electronic integrated chip and the first chip, which are located on the same layer, are electrically interconnected through the redistribution layer; the photonic integrated chip and the second chip, which are located on the same layer, are electrically interconnected through the redistribution layer.

9. The optocoupler structure according to claim 8, characterized in that, The optocoupler structure further includes: The package module and the molded through-hole; the electronic integrated chip and the first chip are located in the package module; the molded through-hole is located in the package module and is located on the periphery of the electronic integrated chip and the first chip.

10. The optocoupler structure according to claim 8, characterized in that, The first chip is a transimpedance amplifier chip, and the second chip is a driver chip; or, the first chip is a driver chip, and the second chip is a transimpedance amplifier chip.

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