Electrostatic discharge (ESD) protection clamp technology

Abstract

Device (100), comprising: a semiconductor area (104) with an electrical device (120); and a rear end region (102) arranged on the semiconductor region (104), wherein the rear end region (102) comprises the following: a first connection; a second terminal; and a metal-insulator transition material, IMT material, (112) which is electrically coupled between the first terminal and the second terminal, wherein the IMT material (112) is defined as a plurality of strips (110-1, 110-2, 110-3) having a width or height approximately equal to a grain size of the IMT material (112).

Description

TECHNICAL AREA

[0001] This description refers to electrostatic discharge (ESD) protection clamp technology. BACKGROUND

[0002] An electrostatic discharge (ESD) generated during the manufacturing and assembly of a device can cause an enormous voltage spike through contacts on a chip. Such an ESD can cause permanent damage to the device. Some ESD solutions can occupy a considerable amount of space within the device (e.g., more than 20% of the silicon area), which can be undesirable. Therefore, there is a need for systems, processes, and devices to address the drawbacks of existing technology and provide other new and innovative features.

[0003] US Patent 2011 / 0006830 A1 discloses a metal-insulator junction device and, in particular, a circuit with the device which is capable of controlling a high current at low temperature heat, since high temperature heat is generated in a transistor when a high current flows through the transistor.

[0004] KR 1020160092336 A discloses an electronic device with a power MOS component, more precisely an electronic device with a temperature-variable resistor component that can prevent overheating of a power MOS component.

[0005] US patent 2009 / 0208639 A1 discloses a method for producing a thin film with an abrupt metal-insulator transition characteristic, in particular a method for producing a V2O3 thin film with an abrupt characteristic. SUMMARY

[0006] The invention is described in the independent claims. Preferred embodiments are described in the dependent claims.

[0007] According to a first aspect, we describe a device comprising a semiconductor region with an electrical device; and a rear end region arranged on the semiconductor region, the rear end region comprising: a first terminal; a second terminal; and a metal-insulator junction material, IMT material, electrically coupled between the first terminal and the second terminal, the IMT material being defined as a plurality of strips having a width or height approximately equal to a grain size of the IMT material.

[0008] According to a second aspect, we describe a device comprising a first terminal; a second terminal; and an electrostatic discharge (ESD) device electrically coupled between the first terminal and the second terminal, the ESD device comprising: a metal-insulator transition material (IMT material), the IMT material being defined as a plurality of strips having a width or height approximately equal to a grain size of the IMT material; and a heat distribution material coupled to the IMT material.

[0009] According to a third aspect, we describe a device comprising a first terminal; a second terminal; and a first electrostatic discharge device, ESD device, electrically coupled between the first terminal and the second terminal, wherein the first ESD device comprises a first metal-insulator transition material, IMT material, and is contained in a first layer of a rear end region of a semiconductor device; and a second electrostatic discharge device, ESD device, comprising a second IMT material, wherein the first ESD device is in a second layer of the rear end region of the semiconductor device, the first layer being different from the second layer, and wherein the first and second IMT materials are defined as a plurality of strips having a width or height approximately equal to a grain size of the IMT material. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic circuit diagram representing a system that includes an ESD device and an electronic device. Fig. Figure 1B is a diagram showing a side cross-sectional view of the ESD device used in the Fig. The system shown in 1A is included. Fig. 2, Fig. 3 to Fig. 4 represent variations of the in Fig. 1B represents the system shown. Fig. 5 represents another variation of the in Fig. Figure 1B shows the system, which includes a heat distributor. Fig. Figure 6 is a schematic circuit diagram showing a system with multiple ESD components. Fig. Figure 7 is a lateral cross-sectional view of at least one implementation form of a system. Fig. Figure 8 is a top view of at least one implementation form of a system. Fig. Figure 9 is a graphic illustrating the operation of at least one of the ESD device implementations described here. Fig. Figure 10 is a diagram showing a top view of a variation of the ESD device 110 according to the invention, which is located in Fig. 1B is shown. Fig. Figure 11 is a graph that shows the mean time to failure of an IMT material as a function of width / grain size. DETAILED DESCRIPTION

[0010] An electrostatic discharge (ESD) generated during the manufacture, assembly, or use of a system containing an electronic device (e.g., a semiconductor component, a chip, or an electronic circuit) can cause a voltage spike between terminals (e.g., one or more power supply terminals, a ground terminal) of the electronic circuit. The ESD devices (which may also be called ESD clamps) described herein can be used to prevent these types of ESD events, which can undesirably damage the electronic device. The ESD devices can be configured to reduce the risk or prevent ESD events from destroying or disabling an electronic device.In other words, ESD devices can be configured to provide ESD protection for an electronic device within a system. ESD devices can be relatively small (e.g., less than 20% of the silicon on a chip), which can be desirable. Such relatively small ESD devices can reduce production costs and lead to an overall reduction in the cost of a device.

[0011] The ESD devices described here may include a material with a metal-insulator junction (IMT) (also referred to as IMT material). The use of an IMT material may result in the ESD device (and its protection) being located in a rear end region (e.g., the rear end of a conductor region, a rear end section) of a system rather than a front end region (e.g., the front end of a conductor region, a semiconductor region) of the system. By placing the ESD device in the rear end region, the space (e.g., the chip space) of the semiconductor region is not utilized for ESD protection. Specifically, ESD devices may include a two-terminal device made of an insulator-metal junction (IMT) material (e.g., VO₂, niobium dioxide (NbO₂)). The IMT material may be created during the chip fabrication of the rear end region (e.g., metal plane).In some implementations, the IMT material within the ESD device can be configured to switch to a conductive (e.g., metallic) material when the voltage between a pair of terminals (e.g., two contacts) exceeds a target operating voltage (e.g., a target operating voltage), either positively or negatively, in response to an ESD event. The material can be configured to revert to an insulating material once the ESD event has ended.

[0012] Fig. Figure 1A is a schematic circuit diagram showing a system 100 with an ESD device 110 and an electronic device 120. As shown in Fig. As shown in Figure 1, the ESD device 110 is arranged between a VDD terminal (e.g., a first terminal) and a VSS terminal (e.g., a second terminal). The ESD device 110 can define a conductive path parallel to the electronic device 120 to protect the electronic device 120 from an ESD event.

[0013] Specifically, the ESD device 110 can dissipate power from the electronic device 120 during an ESD event. The electronic device 120 can include, for example, a metal oxide semiconductor field-effect transistor (MOSFET) device (e.g., a vertical MOSFET, a horizontal or lateral MOSFET device), a bipolar junction transistor (BJT) device, a diode, a resistor, a junction field-effect transistor (JFET) device, an application-specific integrated circuit (ASIC), and so on.

[0014] In response to a voltage between the VDD and VSS terminals exceeding a threshold voltage, the ESD Device 110 can be configured to transition from an insulating to a conductive state. If the voltage between the VDD and VSS terminals is less than the threshold voltage, the ESD Device 110 can be configured to transition from the conductive to the insulating state. In some implementations, the insulating state can be a relatively insulating state, and the conductive state can be a relatively conductive state. The default state of the ESD Device 110 can be an insulating state.

[0015] The ESD device 110 includes a material with a metal-insulator junction (IMT). The IMT material allows the ESD device 110 to switch between an insulating and a conductive state. The IMT material within the ESD device 110 can be configured to switch to a conductive (e.g., metallic) state when the voltage between the VDD terminal and the VSS terminal exceeds an ESD threshold voltage of the electronic device 120 in response to an ESD event, either positively or negatively. The IMT material can be configured to return to an insulating state within the ESD device 110 once the ESD event has ended (and the voltage falls below the ESD threshold voltage).

[0016] In some implementations, the ESD threshold voltage may lie outside a target operating voltage range of the electronic device 120. In some implementations, the ESD threshold voltage may be greater than an upper target operating voltage of the electronic device 120.

[0017] The IMT material can be located in a rear end region (e.g., a rear trace region, a rear end section) of System 100 instead of a front end region (e.g., a front end of a trace region, a semiconductor region) of System 100. Accordingly, the use of an IMT material may result in the ESD device 110 being located in a rear end region of System 100 rather than a front end region. By placing the ESD device 110 in the rear end region, the semiconductor region (e.g., the chip space) is not used for ESD protection. In some implementations, enclosing an ESD device in the rear end region can free up considerable space in a semiconductor region within a semiconductor chip. This additional space can provide increased functionality in a semiconductor chip through additional circuitry or other features.This enables a significant reduction in manufacturing costs by allowing more, smaller chips per wafer. In some implementations, enclosing an ESD device 110 in the rear end region and relatively close to the actual event origin (the terminals exposed to an external device) can improve the response time and overall ESD protection of the ESD device 110. As noted above, the ESD devices 110 can be or include a two-terminal device made of a metal-insulator junction (IMT) material (e.g., VO2, NbO2).

[0018] Fig. Figure 1B is a diagram showing a side cross-sectional view of the ESD device 110, which is located in the Fig. System 100 is included in 1A. Fig. Figure 1B represents an exemplary physical implementation of the circuit representation of the in Fig. 1A shows system 100. As in Fig. As shown in Figure 1B, the system 100 includes an ESD device 110, which is electrically coupled between a VDD port and a VSS port. Specifically, the ESD device 110 is electrically and physically coupled to the VDD port, and the ESD device 110 is electrically and physically coupled to the VSS port.

[0019] The ESD device 110, the VSS connector, and the VDD connector are arranged in a rear end region 102 of the system 100. The rear end region 102 can, for example, include metal layers, insulating layers, vias, or so forth. The rear end region 102 can be formed on (e.g., arranged on) a semiconductor area 104.

[0020] As in Fig. Figure 1B shows the ESD device 110 contained within an insulator 101 (e.g., a dielectric (e.g., a low-k dielectric), an oxide) between the VSS terminal and the VDD terminal. The ESD device 110 is positioned between a first section of the insulator 101 and a second section of the insulator 101.

[0021] The electronic component 120 is formed in the semiconductor region 104 (e.g., arranged therein). The semiconductor region 104 can include a semiconductor substrate (e.g., a silicon substrate, a gallium nitride substrate) or an epitaxial layer formed on (e.g., arranged on) a semiconductor substrate.

[0022] Although not explicitly in Fig. As shown in Figure 1, the ESD device 110 encloses an IMT material. The IMT material within the ESD device 110 transitions to a conductive (e.g., metallic) state when the voltage between the VDD terminal and the VSS terminal exceeds an ESD threshold voltage, and the IMT material reverts to an insulating state when the voltage falls below the ESD threshold voltage. The voltage at which the IMT material changes its state from a conductive state to an insulating state can be termed a trigger voltage. Accordingly, the ESD device 110 can be configured such that the trigger voltage of the ESD device 110 is above the ESD threshold voltage and / or outside a target operating voltage range of the electronic device 120.

[0023] The ESD device 110 (or part thereof) can be contained in a metal layer (e.g., metal layer 1 (M1), metal layer 2 (M2)) or within a via layer. Fig. 2 illustrates a variation of the in Fig. System 100 shown in Figure 1B. In this example implementation, the ESD device 110 is contained in a metal layer 103, which includes metal sections M1-A (associated with VDD) and M1-B (associated with VSS). A via layer 105 includes the vias V1-A (associated with VDD) and V1-B (associated with VSS).

[0024] Fig. Figure 3 illustrates another variation of the in Fig. 1B of the system 100 shown. In this exemplary implementation form, the ESD device 110 is contained in the via layer 105.

[0025] Fig. 4 represents yet another variation of the one in Fig. Figure 1B shows the system 100. In this exemplary implementation, a first section of the ESD device 110 is contained in the metal layer 103, and a second section of the ESD device 110 is contained in the via layer 105.

[0026] Fig. 5 represents yet another variation of the in Fig. 1B shows system 100, which includes a heat distributor. As in Fig. As shown in Figure 5, the ESD device 110 includes a heat distributor 111 and an IMT material 112. The heat distributor 111 is coupled to the IMT material 112 of the ESD device 110.

[0027] In some implementations, since Joule heating can play a relatively large role in the introduction of the IMT material 112, the trip voltage of the IMT material 112 can be further increased by surrounding the material with materials of high thermal conductivity, such as the heat spreader 111. In some implementations, the trip voltage or the reliability of the ESD device 110 can be increased using the heat spreader 111. The heat spreader 111 can be configured to thermally dissipate heat from the IMT material 112 of the ESD device 110. The heat spreader 111 can be made of a material with relatively high thermal conductivity. The heat spreader 111 can be located adjacent to the IMT material 112.

[0028] In some implementations, the heat distributor 111 can be or enclose an electrical insulator such as aluminum oxide (Al₂O₃) or silicon nitride (Si₃N₄). In some implementations, the heat distributor 111 can be or enclose a material other than silicon dioxide (SiO₂). In some implementations, the heat distributor 111 can be coupled to, adjacent to, or enclose a metal layer (not shown).

[0029] In some implementations, the heat spreader 111 can also increase the reliability of the ESD device 110 during ESD events. Since many failure mechanisms can be greatly accelerated by higher temperatures, the heat spreader 111 can dissipate heat from the IMT material 112. In some implementations, the heat spreader 111 can enable better dissipation of the enormous power generated during an ESD event. In some implementations, the IMT material 112 and the heat spreader 111 can be coupled with a clean interface exhibiting low thermal resistance between the heat spreader 111 and the IMT material 112. The heat spreader 111 can be made of a relatively electrically insulating material (e.g., an insulator such as an oxide) and a thermally conductive material (e.g., a thermally conductive metallic material).

[0030] In some implementations, since Joule heating can play a relatively large role in the introduction of the IMT material 112, the trigger voltage of the ESD device 110 can be further increased by increasing the resistivity of the IMT material 112 in the insulating state. In some implementations, the resistivity of the IMT material 112 in the insulating state can be increased by growth conditions or post-growth treatments.

[0031] IMT material 112 can be produced using a variety of processes. For example, IMT material 112 can be deposited using pulsed laser deposition, sputtering, molecular beam epitaxy, vanadium oxidation, atomic layer deposition, or similar techniques. In some conversion processes, the electrical properties of IMT material 112 (e.g., vanadium dioxide (VV2)) can be sensitive to film stoichiometry, strain, defect concentration, or grain structure. In some conversion processes, one or more of these properties can be modified (e.g., tuned) by adjusting the substrate type, deposition temperature, oxygen pressure, or by post-deposition annealing. In some conversion processes, the resistance of IMT material 112 in the insulating state (e.g., phase) can also be determined by similar factors and can be adjusted by modifying the strain, increasing the oxygen content, or other factors.The growth temperature can be increased by changing it. In some reaction regimes, deposition can be carried out, for example, using a VO₂ target or reactively with a vanadium (V) target using oxygen in the presence of oxygen in any case, to obtain a target VO₂ stoichiometry. In some reaction regimes, deposition or annealing after deposition can be carried out at an increased substrate temperature between, for example, 300 °C and 600 °C, in order to, for example, adjust the stoichiometry or to achieve relatively large crystal grains.

[0032] In the Fig. In the embodiment shown in Figure 5, the heat spreader 111 is arranged above the IMT material 112 (in a vertical stack). In other words, the IMT material 112 is located between the heat spreader 111 and the semiconductor area 104 (and the electronic device 120). Although not shown, in some embodiments a heat spreader may be located below the IMT material 112. In other words, the heat spreader may be located between the IMT material 112 and the semiconductor area 104 (and the electronic device 120).

[0033] In some implementations, an ESD device (such as the ESD Device 110) can include one or more IMT material layers and one or more heat distribution layers in a vertical stack. For example, an ESD device can include two heat distribution layers and two IMT material layers nested in a vertical stack.

[0034] In some implementations, the release voltage of the ESD device 110 can be determined by its length L1. In other implementations, the release voltage of the IMT material 112 can scale linearly with the length. The length L1 can be set for a specific ESD device 110 (and contact combination or pair) such that the release voltage of the ESD device 110 is greater than, for example, the operating voltage or ESD voltage of the ESD device 110. The principles relating to length and release voltage can be applied to any of the implementations described herein. The release voltage of the ESD device 110 can be defined based on the height H1 of the IMT material 112 within the ESD device 110.

[0035] Fig. Figure 6 is a schematic circuit diagram showing a System 600 with multiple ESD devices. The diagram in Fig. System 600, shown in section 6, is a variation of the one shown in [reference missing]. Fig. System 100 is shown in Figure 1A. System 600 includes ESD devices A1 to A3 and an electronic device 620. One or more of the ESD devices A1 to A3 may include an IMT material. One or more of the ESD devices A1 to A3 may be contained in a rear end region of System 600.

[0036] As in Fig. Figure 6 shows ESD device A1 arranged between a VDD port (e.g., a first port) and a VSS port (e.g., a second port). ESD device A2 is arranged between the VDD port and an IN port (e.g., a third port). ESD device A3 is arranged between the VSS port and the IN port. In some implementations, one or more of the ESD devices A1 to A3 can be assigned to one or more sections of the electronic device 620.

[0037] ESD devices A1 to A3 define conductor tracks parallel to the electronic device 620 between different nodes of the system 600 to protect the electronic device 620 from various types of ESD events. Specifically, ESD device A1 can dissipate power from the electronic device 620 during an ESD event between the VDD and VSS terminals. ESD device A2 can dissipate power from the electronic device 620 during an ESD event between the VDD and IN terminals, and ESD device A3 can dissipate power from the electronic device 620 during an ESD event between the VSS and IN terminals.

[0038] ESD devices A1 to A3 can have different trigger voltages. For example, ESD device A1 can have a trigger voltage higher than that of ESD device A2 or ESD device A3. ESD device A2 can have a trigger voltage higher than, equal to, or lower than that of ESD device A3. The trigger voltages of ESD devices A1 to A3 can be defined by the length of an IMT material contained within the devices (where a greater length defines a higher trigger voltage).

[0039] Fig. Figure 7 is a side cross-sectional view of at least one implementation of a system 700. The system 700 has a rear end region 702 with the ESD devices B1 to B3 and a semiconductor region 704 with an electronic device 720. In this implementation, the rear end region 720 includes the insulating layers 701, the metal layers 703-1 to 703-4, and the via layers 705-1 to 705-4. The size (e.g., thickness, height, volume) of the metal layers 703 can increase from the lower metal layer 703-1 to the upper metal layer 703-4. The system 700 includes the terminals T1 and T2 (which are externally accessible via the metal layer 703-4) as well as other intermediate node points within the rear end region 702.

[0040] As in Fig. As shown in Figure 7, the ESD device B1 is located within the 705-4 via layer between terminals T1 and T2. ESD devices B2 and B3 are located within the 705-4 via layer and are electrically coupled to terminals T1 and T2, respectively. As shown in Figure 7, the ESD device B1 is located within the 705-4 via layer between terminals T1 and T2. Fig. As shown in Figure 7, ESD devices B1 to B3 enclose an IMT material arranged between heat spreaders (one on the top and one on the bottom). In this configuration, the length of each ESD device B1 to B3 is different, so the trip voltages of each ESD device B1 to B3 are different.

[0041] Fig. Figure 8 is a top view (or plan view) of at least one implementation form of a System 800. As in Fig. As shown in Figure 8, the system encloses ESD devices C1 to C3 within a layer of metal 803. ESD devices C2 and C3 have a rectangular profile or shape when viewed from above. ESD device C1 has a non-rectangular profile or shape. The ESD devices described here can have a variety of profiles or shapes (e.g., curved, irregular) when viewed from above.

[0042] Fig. Figure 9 is a graphic illustrating the operation of at least one of the ESD device implementation forms (e.g., the one in Fig. Figure 1A of the ESD device 110 illustrates the processes described herein. In some transformation modes, materials such as VO2 or NbO2 undergo a reversible transition from insulator to metal at a critical temperature or voltage, with a change in resistance spanning several orders of magnitude. In some transformation modes, the IMT trigger voltage (V) can be IMT) greater than the operating voltage of the electronic components (e.g., circuits) on a semiconductor chip (V op ), so that the IMT material can be used to protect against an ESD event. In some implementations, the IMT material is insulating and conductive (e.g., metallic) in response to any voltage across the IMT material greater than |V IMT | is either positive or negative. After the ESD event is complete, the IMT material returns to its insulating state. This behavior is described in Fig. 9 shown.

[0043] The implementation methods described herein can be contrasted with examples of current ESD protection used between contacts that include, for example, diodes, various configurations of NMOS devices, or a silicon-controlled rectifier fabricated using BJTs. The implementation methods described herein may differ from designs that become metallic and carry high currents when an ESD event occurs. The implementation methods described herein may also differ from designs with major components located in a front-end area (e.g., front-end-of-line processing).

[0044] In some implementations, incorporating IMT material within a back-end-of-line (BEOL) ESD device can lead to a significant saving of chip area by replacing conventional front-end-of-line (FEOL) ESD devices. In some implementations, the IMT material can be deposited or structured as a thin film in one of the last layers (e.g., within the rear-end region, metal layers) on a semiconductor chip. In some implementations, in addition to saving space, the implementations described herein have the advantage of limiting the high currents and heating during ESD events to upper levels at a distance from the more sensitive gate oxides and thin metal conductors, thereby improving reliability. In some implementations, conductors of IMT material can be arranged between the various contact combinations in the upper metal layers (e.g., across Metal 2 (M2)).In some implementations, additional protection can be incorporated by adding IMT material at lower metal levels (e.g., below metal 3 (M3)).

[0045] Fig. Figure 10 is a diagram showing a top view of a variation of the ESD device 110 according to the invention, which is located in Fig. Figure 1B shows a top view of the ESD device 110 according to the invention, as described in Figure 11. Fig. As shown in 10, the following is derived from the in Fig. Consider the direction Q shown in 1B. As in Fig. As shown in Figure 10, the ESD device 110 includes several parallel strips 110-1 to 110-3. Each of the strips can include one or more IMT material layers and one or more heat distribution layers (not shown). In some implementations, electromigration in the ESD device 110 during an ESD event can be reduced by using multiple parallel strips. In some implementations, electromigration (especially the movement of oxygen-depleted areas along grain boundaries oriented parallel to the current path) can be a failure mechanism and can be reduced by improving material purity or by controlling geometry and grain size / orientation.

[0046] As a specific example, in some implementation forms, electromigration within the ESD device 110 during an ESD event can be reduced if a width W1 (or height (not shown)) of at least one of the several parallel strips is approximately equal to or smaller than a grain size of the IMT material. Although in Fig. Not shown in Figure 10, electromigration within an ESD device (e.g., ESD device 110) during an ESD event can be reduced in some implementation forms if a width (or height) of the ESD device (excluding parallel stripes) is approximately equal to or smaller than a grain size of the IMT material.

[0047] In some implementations, reliability can be improved if the IMT material is divided into relatively small strips (e.g., strips with a small cross-sectional area) with a width or height approximately equal to the grain size. In some implementations, a larger grain size can be achieved (e.g., by annealing the IMT material to create a annealed IMT material). In some implementations, a single crystal can also be used as the IMT material. In some implementations, annealing with an ESD device (to anneal the IMT material to a annealed IMT material) can limit the number of grain boundaries available for electromigration and can add surface area for heat distribution. Fig.Figure 11 is a graph that shows the mean time to failure of an IMT material as a function of width / grain size. An ESD device (e.g., ESD Device 110) may incorporate an IMT material designed to reduce (e.g., minimize) the mean time to failure.

[0048] It is understood that in the foregoing description, when an element, such as a layer, region, substrate, or component, is described as being on, connected, electrically connected, coupled to, or electrically coupled to another element, it may be placed, connected, or coupled directly on top of the other element, or one or more intervening elements may be present. Conversely, when an element is described as being directly on, directly connected to, or directly coupled to another element or layer, no intervening elements or layers are present. Although the terms directly on, directly connected to, or directly coupled may not be used in the detailed description, elements shown as being directly on, directly connected, or directly coupled may be identified as such.The claims of the application may be amended, if necessary, to indicate exemplary relationships described in the patent specification or shown in the figures.

[0049] As used in this patent specification, a singular form may include a plural form unless a specific case is definitively indicated with respect to the context. Spatial expressions (e.g., above, superior, below, beneath, under, and so forth) are intended to include various orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative expressions "above" and "below" may each include vertically above and vertically below, respectively. In some implementations, the term "adjacent" may include "laterally adjacent to" or "horizontally adjacent to".

[0050] Implementation methods for the various techniques described herein can be found in digital electronic circuits or in computer hardware, firmware, software, or combinations thereof. Process steps can also be executed by a dedicated logic circuit, such as an FPGA (Field Programmable Gate Array) or an ASIC (Application-Specific Integrated Circuit), and a device can be implemented in this form.

[0051] Implementation forms can be implemented in a computer system that includes a back-end component, such as a data server; a middleware component, such as an application server; a front-end component, such as a client computer with a graphical user interface or a web browser through which a user can interact with an implementation form; or any combination of such back-end, middleware, or front-end components. Components can be interconnected by any form or medium of digital data communication, such as a communication network. Examples of communication networks include a local area network (LAN) and a wide area network (WAN), such as the internet.

[0052] Some implementation forms can be realized using various semiconductor processing and packaging techniques. Some embodiments can be implemented using different types of semiconductor processing techniques in conjunction with semiconductor substrates, including, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and so forth.

[0053] Each section of the device and / or method described in this document can be combined in any combination, except for mutually exclusive combinations. The patent claims described in this document may include various combinations or subcombinations of the functions, components, or features of the various described embodiments.

Claims

[1] Device (100), comprising: a semiconductor area (104) with an electrical device (120); and a rear end region (102) arranged on the semiconductor region (104), wherein the rear end region (102) comprises the following: a first connection; a second terminal; and a metal-insulator transition material, IMT material, (112) which is electrically coupled between the first terminal and the second terminal, wherein the IMT material (112) is defined as a plurality of strips (110-1, 110-2, 110-3) having a width or height approximately equal to a grain size of the IMT material (112). [2] Device (100) according to claim 1, wherein the IMT material (112) is contained in an electrostatic discharge, ESD, device (110) which is electrically coupled between the first terminal and the second terminal. [3] Device (100) according to claim 1, wherein: the IMT material (112) VO2 or NbO2; and the IMT material (112) is a tempered IMT material. [4] Device (100) according to claim 1, wherein the IMT material (112) has a trigger voltage which is greater than a target operating voltage of the electrical device. [5] Device (100) according to claim 1, wherein the IMT material (112) is produced during the semiconductor processing of the rear end region (102), the device (100) further comprising: a heat distributor (111) that is coupled to the IMT material (112) and is contained in the rear end area. [6] Device (100), comprising: a first connection; a second connection; and an electrostatic discharge (ESD) device (110) electrically coupled between the first terminal and the second terminal, the ESD device (110) comprising: a metal-insulator transition material, IMT material, (112) wherein the IMT material (112) is defined as a plurality of strips having a width or height approximately equal to a grain size of the IMT material (112); and a heat distribution material (111) coupled with the IMT material (112). [7] Device (100) according to claim 6, wherein the heat distributor (111) is a first heat distributor, wherein the ESD device (110) includes a second heat distributor. [8] Device (100) according to claim 6, comprising: a semiconductor area (104) with an electrical device (120); and a rear end area (102) arranged on the semiconductor area (104), wherein the rear end area (102) comprises the ESD device (110), wherein the heat distributor (111) includes an electrically insulating material and a thermally conductive material. [9] Device (100), comprising: a first connection; a second connection; and a first electrostatic discharge device, ESD device, (110) which is electrically coupled between the first terminal and the second terminal, wherein the first ESD device (110) comprises a first metal-insulator transition material, IMT material, (111) and is contained in a first layer of a rear end region (102) of a semiconductor device (120); and a second electrostatic discharge device, ESD device, comprising a second, IMT, material, wherein the first ESD device is in a second layer of the rear end region (104) of the semiconductor device (120), wherein the first layer is different from the second layer, where the first and second IMT material are defined as a plurality of strips with a width or height approximately equal to the grain size of the IMT material. [10] Device (100) according to claim 9, wherein the first layer is a first metal layer and the second layer is an insulating layer or a second metal layer, wherein the device (100) further comprises a heat distributor (111) coupled to the first IMT material.

Images