Updating device, updating method and storage device for storage device configuration parameters

Abstract

The application discloses an updating device, an updating method and a storage device for storage device configuration parameters. The updating device delays an access enable signal from a control logic, inputs a delay signal of the access enable signal into an access enable signal port of the storage device, and makes the storage device enter a non-enabled state relative to the access enable signal when the access enable signal represents a non-enabled state. At least one updating enable signal is outputted when the storage device is in the non-enabled state and the access enable signal represents a non-enabled state, so that a time window of an updating operation of the storage device configuration parameters starts from the access enable signal representing a non-enabled state and ends when the storage device is in the non-enabled state. The delay time of the delay signal is determined according to the number of clock cycles required by the updating operation of the storage device configuration parameters. The application improves the flexibility of the configuration parameter updating.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated chip, in particular, to an updating device of storage device configuration parameter, an updating method and a storage device. BACKGROUND

[0002] The storage device has become an indispensable basic device in electronic equipment. The storage device itself needs some basic configuration parameters.

[0003] Generally, the updating of the configuration parameters of the storage device is usually performed by software or firmware during the idle state of the IP (intellectual property) core, and the updating operation of the configuration parameters cannot be performed during the non-idle state of the IP core, which leads to the difficulty of updating the configuration parameters of the storage device flexibly to adapt to the system operation. SUMMARY

[0004] Embodiments of the present application provide an updating device of storage device configuration parameter to improve the flexibility of the updating of the configuration parameters of the storage device.

[0005] Embodiments of the present application provide an updating device of storage device configuration parameter, which is used for,

[0006] delaying an access enable signal from a control logic for enabling the access of the storage device, and inputting a delay signal of the obtained access enable signal to an access enable signal port of the storage device, wherein the delay signal enables the storage device to enter a non-enabled state relative to the access enable signal when the access enable signal represents a non-enabled situation,

[0007] outputting at least one updating enable signal for enabling the updating operation of the configuration parameters of the storage device when the storage device is in the non-enabled state and the access enable signal represents the non-enabled situation, so that the time window of the updating operation of the configuration parameters of the storage device at least starts from the access enable signal representing the non-enabled state and lasts until the storage device is in the non-enabled state,

[0008] wherein,

[0009] the delay duration of the delay signal is determined according to the number of clock cycles required by the updating operation of the configuration parameters of the storage device.

[0010] As a possible implementation, the updating device comprises:

[0011] The delay logic module is configured to delay the access enable signal by a set number of beats to obtain a delay signal, and perform an OR logic operation on the delay signal and the access enable signal, and output the operation result of the OR logic operation as an update enable signal to the configuration parameter controller of the storage device.

[0012] The number of beats is determined according to a number of clock cycles required for the update operation of the configuration parameter of the storage device, and one clock cycle is one beat.

[0013] As a possible implementation, the delay logic module includes one or more first synchronous control flip-flops connected in sequence, and an OR gate.

[0014] The first synchronous control flip-flop is configured to receive the access enable signal.

[0015] The first synchronous control flip-flop is configured to receive the access enable signal.

[0016] The signal output by the last first synchronous control flip-flop in the first synchronous control flip-flops is the delay signal.

[0017] The delay signal and the access enable signal are input to the OR gate to perform an OR logic operation.

[0018] The first synchronous control flip-flops are configured to receive the same clock signal.

[0019] The number of first synchronous control flip-flops is determined according to the set number of beats.

[0020] As a possible implementation, the clock signal is also input to a clock signal port of the storage device.

[0021] The output signals of the first synchronous control flip-flops are input to the OR gate.

[0022] The update device further includes:

[0023] The delay module is configured to delay at least one of the access operation signal and the access data signal from the control logic by the delay time of the delay signal, and input the delayed signal to a corresponding port of the storage device.

[0024] As a possible implementation, the delay module includes:

[0025] The delay circuit includes one or more second synchronous control flip-flops connected in sequence, and is configured to delay one of the access signals from the control logic for accessing the storage device.

[0026] The second synchronous control flip-flops are configured to receive the same clock signal.

[0027] One of the access signals is input to a first second synchronous control flip-flop in the delay circuit,

[0028] The output of a last second synchronous control flip-flop in the delay circuit is input to a corresponding port of the storage device as a delay signal of one of the access signals,

[0029] The number of the second synchronous control flip-flops is the same as that of the first synchronous control flip-flops,

[0030] Each second synchronous control flip-flop respectively inputs the same clock signal as that of each first synchronous control flip-flop.

[0031] As a possible implementation, the access signals include a read operation signal, a write operation signal, a read data signal, and a write data signal;

[0032] The delay module includes a plurality of delay circuits, wherein each delay circuit is used to delay one of the access signals, and the number of the delay circuits is the same as that of the access signals required to be delayed.

[0033] As a possible implementation, the storage device is a static random access memory in a system on chip,

[0034] As a possible implementation, the access enable signal, the access signals, and the clock signal come from the control logic of an IP core in the system on chip,

[0035] As a possible implementation, the update enable signal is input to a configuration parameter controller of the static random access memory, and the configuration parameter controller updates the configuration parameter of the static random access memory according to the update enable signal and the configuration parameter stored in the configuration parameter controller,

[0036] As a possible implementation, the configuration parameter at least includes read margin information.

[0037] The second aspect of the embodiments of the present application provides a storage device, which includes an update device of any of the above-mentioned configuration parameters of the storage device.

[0038] The third aspect of the embodiments of the present application provides an update method of a configuration parameter of a storage device, which includes:

[0039] In the case that the access enable signal for enabling the control of accessing the storage device from the control logic represents a non-enabled state, the access enable signal is delayed to obtain a delay signal of the access enable signal, and the delay signal is input to the access enable signal port of the storage device, wherein the delay signal makes the storage device enter the non-enabled state in a delayed manner relative to the access enable signal,

[0040] In the case that the storage device is in the non-enabled state during the period and the access enable signal represents a non-enabled state, an update enable signal for enabling an update operation of the storage device configuration parameter is generated, so that the time window of the update operation of the storage device configuration parameter starts from the time when the access enable signal represents a non-enabled state and lasts until the storage device is in the non-enabled state.

[0041] In the case that the storage device is in the non-enabled state during the period and the access enable signal represents a non-enabled state, an update enable signal for enabling an update operation of the storage device configuration parameter is generated, so that the time window of the update operation of the storage device configuration parameter starts from the time when the access enable signal represents a non-enabled state and lasts until the storage device is in the non-enabled state.

[0042] The delay time of the delay signal is determined according to the number of clock cycles required by the update operation of the storage device configuration parameter.

[0043] As a possible implementation, the method further comprises:

[0044] The at least one access signal from the control logic for accessing the storage device is input to the access signal port of the storage device after being delayed.

[0045] The delay time of the at least one access signal is the same as the delay time of the delay signal of the access enable signal.

[0046] The update device for the storage device configuration parameter provided by the embodiments of the present application outputs an update enable signal in the case that the storage device is in the non-enabled state during the period and the access enable signal represents a non-enabled state, and inputs the access enable signal from the control logic to the access enable signal port of the storage device after being delayed, so that the time window of the update operation of the storage device configuration parameter starts from the time when the access enable signal represents a non-enabled state and lasts until the storage device is in the non-enabled state. In this way, the update operation of the storage device configuration parameter can be performed in the non-access state of the storage device even if the IP core is in a non-idle state, which is beneficial to utilizing the gap of the non-access state of the storage device, and improves the flexibility, real-time performance and dynamic performance of the update of the storage device configuration parameter. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 It is a schematic diagram of the update device for the storage device configuration parameter of the embodiments of the present application.

[0048] Figure 2 It is a port signal schematic diagram of the SRAM of the embodiments of the present application.

[0049] Figure 3 It is a write operation timing schematic diagram of the SRAM port of the embodiments of the present application.

[0050] Figure 4 It is a read-write operation timing schematic diagram of the SRAM port of the embodiments of the present application.

[0051] Figure 5A schematic diagram of an update device for updating the read margin of the SRAM of the embodiment.

[0052] Figure 6 A schematic diagram of the delay logic module of the embodiment.

[0053] Figure 7 A schematic diagram of the delay logic module of the embodiment. Figure 6 A schematic diagram of the timing of the signals in the delay logic module of the embodiment.

[0054] Figure 8 Another schematic diagram of the update device of the embodiment.

[0055] Figure 9 A schematic diagram of the delay module of the embodiment.

[0056] Figure 10 A schematic diagram of the flow of the method for updating the configuration parameters of the storage device of the embodiment. DETAILED DESCRIPTION

[0057] In order to make the purposes, technical means and advantages of the present application more clear, the present application is further described in detail below with reference to the drawings.

[0058] The update device for updating the configuration parameters of the storage device provided by the embodiment of the present application creates a time window for the update operation of the configuration parameters of the storage device by delaying the input of the access enable signal from the control logic for enabling the access to the storage device to the access enable signal port of the storage device, so that the update operation of the configuration parameters of the storage device can be performed in the non-access state of the storage device even in the case that the IP core is not idle.

[0059] Referring to Figure 1 as shown, Figure 1 A schematic diagram of the update device for updating the configuration parameters of the storage device of the embodiment of the present application. The update device delays the access enable signal from the control logic for enabling the access to the storage device to obtain a delay signal of the access enable signal, and inputs the delay signal to the access enable signal port of the storage device, wherein the delay signal makes the storage device enter the non-enabled state relative to the access enable signal in the case that the access enable signal represents the non-enabled state,

[0060] During the period that the storage device is in the non-enabled state and the access enable signal represents the non-enabled state, at least one update enable signal for enabling the update operation of the configuration parameters of the storage device is output to the storage device, so that the time window for the update operation of the configuration parameters of the storage device starts at least from the access enable signal representing the non-enabled state and lasts until the storage device is in the non-enabled state,

[0061] wherein,

[0062] The delay duration of the delay signal is determined according to the number of clock cycles required by the update operation of the configuration parameter of the storage device. As an example, the delay duration is greater than or equal to the duration corresponding to the number of clock cycles required by the update operation.

[0063] As an example, to avoid the timing disorder of the access operation signal and the access data signal of the storage device, the update device further comprises a delay module configured to delay at least one of the access operation signal and the access data signal from the control logic by the delay duration of the delay signal and then input the delayed signal to the corresponding port of the storage device.

[0064] It should be understood that the control logic can be from a processor, an IP core, etc., and embodiments of the present application do not limit this; the configuration parameter includes, but is not limited to, a read margin, a write margin, and other configuration parameters that require the storage device to be in a non-access state for parameter update. The specific configuration parameter depends on the configuration parameter required by the storage device, and embodiments of the present application do not limit this; the access enable signal includes, but is not limited to, a read-write enable signal, a read enable signal, a write enable signal, or any combination thereof, and other signals that enable the storage device to meet the requirements of the configuration parameter update operation. The specific port signal of the storage device depends on the storage device, and embodiments of the present application do not limit this; the storage device can be an SRAM, a RAM, etc.

[0065] Depending on different designs, in some embodiments, the implementation of the related functions of the update device can be a hardware circuit. In other embodiments, the implementation of the related functions of the update device can be a combination of more than one of hardware, firmware, and software (i.e., a program).

[0066] In hardware form, the functionality of the updating device can be implemented by various logics of integrated circuits. For example, the functionality of the updating device can be implemented by various logics of one or more hardware controllers, microcontrollers, hardware processors, microprocessors, application-specific integrated circuits, digital signal processors, field programmable gate arrays, central processing units, or other processing logic. The functionality of the updating device can be implemented by various logics of integrated circuits in a hardware description language (e.g., Verilog HDL or VHDL) or other suitable programming languages.

[0067] In software form or firmware form, the functionality of the updating device can be implemented as programming codes. For example, the programming codes can be implemented by using a general programming language (e.g., C, C++ or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a "non-transitory machine-readable storage medium". In some embodiments, the non-transitory machine-readable storage medium includes, for example, semiconductor memories and / or storage devices. An electronic device (e.g., a CPU, a hardware controller, a microcontroller, a hardware processor or a microprocessor) can read and execute the programming codes from the non-transitory machine-readable storage medium, thereby implementing the functionality of the updating device.

[0068] The updating device for configuration parameters of the storage device provided by the embodiment of the present application outputs an updating enable signal when the storage device is in the non-enabled state and the access enable signal is in the non-enabled state, so as to form a time window starting from the access enable signal being in the non-enabled state and ending when the storage device is in the non-enabled state, so that the storage device performs the updating operation of the configuration parameters in the time window, and the configuration parameters of the storage device are updated in the gap of the non-idle IP core and the idle storage device, and the real-time performance and flexibility of the updating of the configuration parameters of the storage device are improved.

[0069] To facilitate understanding of the embodiment of the present application, the read margin updating of a static random access memory (SRAM) in an IP core of a system on chip (SoC) chip is taken as an example for illustration, and it should be understood that the embodiment of the present application is not limited to the SoC chip, nor to the SRAM in the IP core, nor to the read margin parameter itself, and is applicable to other chips, other storage devices and other configuration parameters.

[0070] The read margin is a key indicator for measuring the ability of the SRAM to resist unintentional state flip during the read operation, and its core is to quantify the stability of the SRAM in the data read process and serve as an important basis for design and process optimization, to ensure the reliable read / write of data while achieving a balance between stability, power consumption, area and performance.

[0071] The change of the power supply voltage of the SoC will directly affect the read margin, and then determine whether the SRAM can work stably. Simply speaking, the higher the power supply voltage of the SoC, the larger the value of the read margin, and the more stable the read / write operation of the SRAM; on the contrary, the power supply voltage of the SoC is reduced, and the value of the read margin will be sharply reduced, and the risk of read / write operation failure will significantly increase.

[0072] Low-power design has become an indispensable part of SoC design. When the SoC has a large amount of processing tasks, the clock frequency of the SoC is relatively high, and the power supply voltage of the SoC needs to be set relatively large. At this time, the value of the read margin needs to be set relatively large, so that the speed of the SRAM will be relatively fast, and the power consumption of the chip will also be relatively large. When the SoC has a small amount of tasks, the speed requirement of the SRAM is not so high, and the power consumption can be reduced by reducing the power supply voltage of the SoC. The SRAM requires the value of the read margin to be changed before the power supply voltage of the SoC is reduced. Since the power supply voltage of the SoC is dynamically changed according to the size of the task amount, the value of the read margin of the SRAM also needs to be dynamically changed.

[0073] SRAM itself restricts the value of Read Margin from being changed during read and write operations. Applicant has found that in order to protect the SRAM from being accessed when the software or firmware is updating the value of Read Margin, the value of Read Margin is usually updated by the skilled person during the period when the IP core in the SoC is idle, that is, only when the IP core is completely idle, the value of Read Margin is updated.

[0074] Referring to Figure 2 illustrated, Figure 2 is a schematic diagram of port signals of the SRAM of the embodiment. The port signals of the SRAM include: a clock signal clk, a read and write enable signal Me, a read and write operation signal We, a Read Margin signal for configuring the value of Read Margin to the SRAM, a write data signal W_data for writing data to the SRAM, and a read data signal R_data for reading data from the SRAM.

[0075] As an example, the clock signal clk, the read and write enable signal Me, the read and write operation signal We, the write data signal W_data, and the read data signal R_data come from the control logic of the IP core; the Read Margin signal comes from the Read Margin controller.

[0076] As an example, the read and write enable signal Me is 1 when there is a read and write operation to access the SRAM, and the read and write enable signal Me is 0 when there is no operation to access the SRAM; when the read and write enable signal Me is 0, the value of the read and write operation signal We is meaningless because there is no operation to access the SRAM at this time, and when the read and write enable signal Me is 1, the read and write operation signal We is 1 to indicate a write operation, and the read and write operation signal We is 0 to indicate a read operation.

[0077] Referring to Figure 3 illustrated, Figure 3 is a schematic diagram of the write operation timing of the port of the SRAM of the embodiment. In the clock cycle when the read and write enable signal Me and the read and write operation signal We are pulled high at the same time, the value in the write data signal W_data is written into the SRAM.

[0078] Referring to Figure 4 illustrated, Figure 4 is a schematic diagram of the read and write operation timing of the port of the SRAM of the embodiment. In the clock cycle when the read and write enable signal Me is pulled high, the signal of the read and write operation signal We is 0, so it is a read operation, and in the next clock cycle adjacent to the clock cycle when the read and write enable signal Me is pulled high, the value in the read data signal R_data is the data read from the SRAM.

[0079] It should be understood that the read / write timings of different SRAMs may vary, but they generally conform to the timings described above. All require a read / write enable signal We, a write data signal W_data or a read data signal R_data, and a delay of several clock cycles between the read / write operation signal Me. This embodiment does not impose any limitations on this.

[0080] Since SRAM requires that no read or write operations access the SRAM within a certain number of clock cycles before and after updating the Read Margin, for ease of description, in this embodiment, the duration of the required number of clock cycles before and after the Read Margin update is denoted as Rtime. Different SRAMs have different requirements for the number of clock cycles, and therefore different Rtimes. In this embodiment, a control signal is applied to the SRAM port pin to ensure that no operation accesses the SRAM within a certain number of time cycles before and after updating the Read Margin.

[0081] Since the read / write enable signal We directly indicates whether there is an operation accessing the SRAM, the SRAM Read Margin value can be updated within the duration of any operation that does not access the SRAM for longer than Rtime.

[0082] See Figure 5 As shown, Figure 5 This is a schematic diagram of an update device for updating the SRAM Read Margin in this embodiment. In the diagram, the read / write enable signal Me from the control logic of the IP core is input to the delay logic module as an access enable signal. A clock signal is also input to the delay logic module. The delay logic module delays the read / write enable signal Me and outputs a delayed signal to the SRAM's read / write enable signal Me port. When the read / write enable signal Me is disabled and the SRAM is in an inaccessible state (i.e., disabled), the delay logic module outputs an update enable signal to the Read Margin controller to enable the Read Margin controller to perform a Read Margin update operation. This enables the Read Margin controller to input the current Read Margin to the SRAM, thereby updating the SRAM's Read Margin. The Read Margin controller internally stores the value of the Read Margin to be updated. This value is externally configured, and the specific configuration method is not limited in this embodiment. The Read Margin controller records the externally updated Read Margin value and updates the SRAM's Read Margin value when the update enable signal becomes 0.

[0083] See Figure 6 As shown, Figure 6A schematic diagram of a delay logic module for the embodiment. The delay logic module comprises: an OR gate, and a plurality of digital circuit flip-flops (DEF) with synchronous control function connected in sequence, for example, D-type flip-flops, referred to as first synchronous control flip-flops (first DEFs) for the convenience of writing; a read / write enable signal Me from the control logic of the IP core is input to the first DEF at the head of the first DEF connected in sequence, and a signal output by the last first DEF of the first DEF connected in sequence (the Me3 signal in the figure) is input to the read / write enable signal Me port of the SRAM as a delay signal; the signals output by the first DEF (the Me1- Me3 signals in the figure) and the read / write enable signal Me (the Me0 signal in the figure) from the control logic of the IP core are input to the OR gate respectively, and the OR gate performs OR logic operation on the input read / write enable signal Me and the signals output by the first DEF, and outputs the logic operation result as an update enable signal; the clock signal from the control logic of the IP core is input to each first DEF as the clock signal of the DEF. The number of the first DEF connected in sequence is determined according to the required Rtime, for example, the number of the first DEF in the figure is 3.

[0084] Referring to Figure 7 as shown, Figure 7 for Figure 6 A schematic diagram of the timing of each signal in the example delay logic module. When the Me0 signal is 0, the Me1 signal is delayed by one clock cycle relative to the Me0 signal, i.e. by 1 beat, the Me2 signal is delayed by one clock cycle relative to the Me1 signal and by two clock cycles relative to the Me0 signal, i.e. by 2 beats, and the Me3 signal is delayed by one clock cycle relative to the Me2 signal and by three clock cycles relative to the Me0 signal, i.e. by 3 beats relative to the Me0 signal. Wherein, one beat corresponds to one clock cycle. When the OR logic operation value of the Me0- Me3 signal is 0, the update enable signal Me_a outputs a 0 value signal to enable the update operation of the read margin, so that the clock cycle from when the Me0 signal is 0 to when the Me_a signal is 0 is the clock cycle without access operation before the update operation, and the clock cycle during which the Me0 signal is maintained as 0 is the clock cycle of the update operation itself and after the update operation. As an example, Figure 7 In the example, the Me0 signal is maintained as 0 for 4 clock cycles, so that the SRAM is also maintained in the non-access state for 4 clock cycles. The time window for the update operation is formed from when the Me0 signal is 0 to when the SRAM is in the non-access state, in which time window the IP core can be in the non-idle state while the SRAM is in the idle state, so that even if the IP core can be in the non-idle state, the update operation can be performed by taking advantage of the gap during which the SRAM is in the idle state, which is conducive to the dynamic update of the read margin of the SRAM.

[0085] In the embodiment, the Me0 signal and the Me3 signal are subjected to OR logical operation, which is beneficial to improve the anti-interference capability of the update enable signal and the robustness of the update operation. As a variant, only the Me0 signal and the Me3 signal can be subjected to OR logical operation.

[0086] Referring to Figure 8 illustrated, Figure 8 is another schematic diagram of the update device in the embodiment. In order to avoid the timing disorder of the read-write operation signal We, the write data signal W_data and the read data signal R_data of the SRAM, the update device further includes a delay module. The read-write operation signal We, the write data signal W_data and the read data signal R_data from the control logic of the IP core are input into the delay module, and the delay module outputs the input signals to the corresponding ports of the SRAM after delaying the input signals for the same number of clock cycles as the delay signals output by the delay logic module.

[0087] Referring to Figure 9 illustrated, Figure 9 is a schematic diagram of the delay module in the embodiment. The delay module includes a delay circuit composed of one or more second DEF connected in sequence. The delay circuit is used to delay any access signal for accessing the SRAM from the control logic of the IP core. The access signal is input into the first second DEF in the delay circuit. The output signal of the last second DEF in the delay circuit is input into the access signal port of the SRAM as the delay signal of the access signal. The clock signal from the control logic of the IP core is input into each second DEF as the clock signal of the DEF.

[0088] In the embodiment, the read-write operation signal We, the write data signal W_data and the read data signal R_data from the control logic of the IP core are input into the corresponding delay circuits composed of the corresponding second DEF connected in sequence respectively. In each delay circuit, the number of second DEFs is the same as that of first DEFs.

[0089] It should be understood that the DEF for delaying in the embodiment can also be implemented by using a counter.

[0090] Referring to Figure 10 illustrated, Figure 10 is a flowchart of the method for updating the configuration parameters of the storage device in the embodiment. The method includes:

[0091] Step 1001, in the case that the access enable signal from the control logic for enabling the access of the storage device is in the non-enabled state, delay the access enable signal to obtain a delay signal of the access enable signal, and input the delay signal to the access enable signal port of the storage device, wherein the delay signal makes the storage device enter the non-enabled state in delay relative to the access enable signal,

[0092] Step 1002, in the case that the storage device is in the non-enabled state and the access enable signal is in the non-enabled state, generate at least one update enable signal for enabling the update operation of the storage device configuration parameter, so that the time window of the update operation of the storage device configuration parameter at least starts from the access enable signal being in the non-enabled state and ends when the storage device is in the non-enabled state,

[0093] Wherein,

[0094] The delay time of the delay signal is determined according to the number of clock cycles required by the update operation of the storage device configuration parameter.

[0095] The method further comprises:

[0096] 1003, delay any signal from the control logic for accessing the storage device and input it to the corresponding port of the storage device.

[0097] It should be understood that step 1003 can be executed synchronously with step 1001, or asynchronously. When executed synchronously, the delay time of the delay in step 1003 is the same as the delay time of the access enable signal. When executed asynchronously, the delay time of the delay in step 1003 is determined according to the delay time of the access enable signal and the timing of step 1003, so that the delay time of at least one of the access signals is the same as the delay time of the delay signal of the access enable signal, thereby avoiding timing confusion.

[0098] For the device / network side equipment / storage medium embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant part can be referred to the part of the method embodiment.

[0099] In this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0100] The application has been described herein in relation to particular embodiments, and any modifications and / or improvements, etc., made to the preferred embodiments are intended to fall within the scope of the application.

Claims

1. A device for updating configuration parameters of a storage device, characterized in that, The updating device is used for, The read / write enable signal from the control logic of the IP core used to access the storage device is delayed. This delayed read / write enable signal is then input to the access enable signal port of the storage device, creating a time window for updating the storage device's configuration parameters. Here, the read / write enable signal indicates whether an access operation is occurring, and the delayed signal causes the read / write enable signal to be delayed before entering the storage device's access enable signal port. When the storage device is in an inaccessible state and the read / write enable signal indicates no access operation, at least one update enable signal is output to enable the update operation of the storage device configuration parameters. in, The time window begins at least when the read / write enable signal output by the IP core indicates no access operation, and continues until the no-access state of the storage device ends. During the specified time window, the IP core is in a non-idle state while the storage device is in an inaccessible idle state. The storage device is used for update operations during its idle state. The delay duration of the delay signal is determined based on the number of clock cycles required before the update operation. The read / write enable signal indicates that there is no access operation. The duration of the read / write enable signal is determined based on the update operation itself and the number of clock cycles required after the update operation.

2. The updating device as described in claim 1, characterized in that, The updating device includes: The delay logic module is used to delay the read / write enable signal according to the set number of ticks to obtain a delayed signal. The delayed signal and the read / write enable signal are then subjected to an OR logic operation. The result of the OR logic operation is output as an update enable signal to the configuration parameter controller of the storage device. The number of ticks is determined based on the number of clock cycles required for updating the storage device configuration parameters, with one clock cycle being one tick.

3. The updating device as described in claim 2, characterized in that, The delay logic module includes: a first synchronization control flip-flop, and an OR gate. in, Multiple first synchronization control triggers are connected in sequence. The read / write enable signal is input to the first synchronous control flip-flop in the series of sequentially connected first synchronous control flip-flops. The signal output of the last of the first synchronous control triggers connected in sequence is used as the delay signal. At least the delay signal and the read / write enable signal should be input to the OR gate to perform OR logic operations. Each of the first synchronous control triggers receives the same clock signal. The number of the first synchronous control triggers is determined according to the set number of beats.

4. The updating device as described in claim 3, characterized in that, The clock signal is also input to the clock signal port of the storage device. The output signals of each of the sequentially connected first synchronous control triggers are respectively input to an OR gate; The updating device further includes: The delay module is used to input at least one of the access operation signal and access data signal from the control logic to the corresponding port of the storage device after delaying it according to the delay duration of the delay signal.

5. The updating device as described in claim 4, characterized in that, The delay module includes: A delay circuit consisting of one or more second synchronous control flip-flops connected in sequence is used to delay one of the access signals from the control logic for accessing the memory device. in, One of the access signals is input to the first second synchronous control trigger in the delay circuit. The output of the second-to-last synchronous control trigger in the delay circuit is used as a delayed signal of one of the access signals and input to the corresponding port of the storage device. The number of second synchronization control triggers is the same as the number of first synchronization control triggers. Each of the second synchronous control triggers receives the same clock signal, and the clock signal is the same as that of each of the first synchronous control triggers.

6. The updating device as described in claim 5, characterized in that, The access signals include: read operation signal, write operation signal, read data signal, and write data signal; The delay module includes: a multi-channel delay circuit, wherein each delay circuit is used to delay one of the access signals, and the number of delay circuits is the same as the number of access signals to be delayed.

7. The updating device as described in claim 6, characterized in that, The storage device is a static random access memory (SRAM) within a system-on-a-chip (SoC). The read / write enable signal, access signal, and clock signal originate from the control logic of the IP core within the system-on-a-chip (SoC). The update enable signal is input to the configuration parameter controller of the static random access memory (SRAM). The configuration parameter controller updates the configuration parameters of the SRAM according to the configuration parameters stored in the configuration parameter controller based on the update enable signal. The configuration parameters include at least read tolerance information.

8. A storage device, characterized in that, The storage device includes an update device for the storage device configuration parameters as described in any one of claims 1 to 7.

9. A method for updating configuration parameters of a storage device, characterized in that, The method includes: The read / write enable signal from the control logic of the IP core for accessing the storage device is delayed to obtain a delayed read / write enable signal, which is then input to the access enable signal port of the storage device. This creates a time window for updating the storage device configuration parameters. The read / write enable signal indicates an access operation, or indicates no access operation. The delayed signal causes the read / write enable signal to be delayed before entering the access enable signal port of the storage device. When the storage device is in an inaccessible state and the read / write enable signal indicates no access operation, at least one update enable signal is generated to enable an update operation for the storage device configuration parameters. in, The time window begins at least from the start of the IP and output read / write enable signals indicating no access operation, and continues until the storage device is in an inaccessible state. During the specified time window, the IP core is in a non-idle state while the storage device is in an inaccessible idle state. The storage device is used for update operations during its idle state. The delay duration of the delay signal is determined based on the number of clock cycles required before the update operation. The read / write enable signal indicates that there is no access operation. The duration of the read / write enable signal is determined based on the update operation itself and the number of clock cycles required after the update operation.

10. The updating method as described in claim 9, characterized in that, The method further includes: At least one of the access signals from the control logic used to access the storage device is delayed and then input to the corresponding port of the storage device access signal. The delay duration of at least one of the access signals is the same as the delay duration of the read / write enable signal.

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