A True Random Number Generator and Method Based on Physical Phase Transition

Abstract

This invention discloses a true random number generator and method based on physical phase transition. In this true random number generator, a differential entropy source unit generates two output signals with a random time difference based on the first-order physical phase transition process of the material. A time-to-digital converter is connected to the output of the differential entropy source unit, quantizing the random time difference between the first and second output signals into a multi-bit random number. A control unit is connected in one path to the differential entropy source unit to provide an excitation signal to induce the physical phase transition of the material; the other path is connected to the time-to-digital converter via a self-calibration circuit to provide a clock signal for calibration. This invention utilizes the first-order physical phase transition of vanadium dioxide as an entropy source, fundamentally improving entropy quality and robustness, physically offsetting common-mode drift, and outputting unbiased random bits.

Description

Technical Field

[0001] This invention relates to the field of information security and confidential communication technology, and specifically to a true random number generator and method based on physical phase transition. Background Technology

[0002] With the advent of the era of intelligent interconnection, the real-time convergence and transmission of massive amounts of data faces increasingly severe security challenges. Data streams are highly vulnerable to attacks, theft, or tampering, posing serious security risks. The core of ensuring secure data transmission lies in high-quality random keys. The performance of a true random number generator directly determines the confidentiality and reliability of the key, serving as the fundamental guarantee for the entire information security system.

[0003] However, existing hardware true random number generators have several inherent drawbacks. Their entropy sources typically rely on second-order physical effects of standard CMOS circuits (such as timing jitter or metastability), making their randomness susceptible to variations in process, voltage, and temperature (PVT), resulting in insufficient robustness. Their raw bitstream output often exhibits statistical bias, requiring complex digital post-processing circuitry to eliminate bias and introducing additional power consumption and delay overhead. During on-chip system integration, multiple entropy sources are prone to noise coupling and frequency locking through the substrate, severely weakening randomness. Furthermore, the entropy capture efficiency of certain circuit architectures is low, leading to wasted entropy resources. In addition, existing solutions mostly employ passive digital feedback systems for compensation, failing to fundamentally solve the instability problem of entropy sources, and generally lack physical immunity to environmental drift, active defense mechanisms against external physical attacks, and self-diagnostic and self-repair capabilities to cope with long-term device aging and failure.

[0004] In view of this, there is an urgent need in this field for a new true random number generator technology solution with a more reliable physical basis for entropy sources, high entropy capture efficiency, and environmental immunity and intelligent management capabilities. Summary of the Invention

[0005] To address the aforementioned problems, this invention provides a true random number generator that possesses physical-level environmental drift immunity, efficient and lossless entropy capture, and self-calibration and self-repair capabilities. The core idea of ​​this invention is to utilize a symmetrical entropy source device based on a first-order physical phase transition to generate pulse pairs with random time differences, and then use a self-calibrating time-to-digital conversion unit to efficiently and accurately quantize these random time differences into multi-bit digital random numbers.

[0006] The present invention provides a true random number generator based on differential phase transition entropy source and self-calibration time quantization, comprising: a differential entropy source unit, a time-to-digital conversion unit, a control unit, and a self-calibration circuit.

[0007] The differential entropy source unit is used to generate two output signals with a random time difference based on the first-order physical phase transition process of the material; the time-to-digital conversion unit is connected to the output of the differential entropy source unit and is used to convert the first output signal C... out1 Second output signal C out2 The random time difference between the two is quantized into a multi-bit random number; the control unit is connected to the differential entropy source unit in one way to provide it with an excitation signal to induce a physical phase transition of the material; the control unit is also connected to the time-to-digital converter unit through a self-calibration circuit to provide it with a clock signal for calibration, thereby suppressing the influence of PVT variation.

[0008] The differential entropy source unit includes a pair of structurally symmetrical entropy source branches. Each entropy source branch includes an entropy source device, a resistor, and a comparator. In the entropy source branch, one end of the first entropy source device E1 and one end of the second entropy source device E2 are connected to one end of resistor R1 and one end of resistor R2, respectively, to form a voltage divider circuit. The other ends of entropy source devices E1 and E2 are connected to the power supply VCC, and the other ends of resistors R1 and R2 are both connected to the common terminal GND. Preferably, to ensure the symmetry of the two branches, the resistance values ​​of the first resistor R1 and the second resistor R2 are equal. The connection point between the entropy source device and the resistor serves as the output node E. out1 E out2 The non-inverting inputs of comparators C1 and C2 are connected to the non-inverting inputs, and the inverting inputs of comparators C1 and C2 are connected to a common reference voltage V. ref The output terminals C of the comparators C1 and C2 out1 C out2 This is the output signal of the differential entropy source unit.

[0009] The entropy source device is a stacked structure consisting of a platinum (Pt) heating layer, a vanadium dioxide (VO2) functional layer, and an aluminum nitride (AlN) heat dissipation layer. The platinum (Pt) heating layer, the vanadium dioxide (VO2) functional layer, and the aluminum nitride (AlN) heat dissipation layer have the same area. During operation, the control unit applies an adjustable-slope excitation signal to the platinum heating layers of the first and second entropy source devices E1 and E2, inducing an insulator-metal phase transition in the VO2 functional layer, thereby generating heat at the first and second output nodes E1 and E2. out1 E out2 A voltage signal with a random time difference is generated between them.

[0010] In this embodiment of the invention, the data input terminal of the D flip-flop array is connected to the output of each stage of the slow delay line, and its clock input terminal is connected to the output of each stage of the fast delay line, which is used to capture the position where the fast line signal catches up with the slow line signal, thereby quantizing the analog time difference into digital code.

[0011] The true random number generator provided by the present invention also includes a self-calibration circuit, which includes a delay-locked loop (DLL) for generating stable control voltages Vp and Vn that are resistant to PVT variations.

[0012] Based on the above-mentioned true random number generator, the present invention also provides a corresponding true random number generation method, the method comprising the following steps:

[0013] The control unit provides an excitation signal to the differential entropy source unit to induce a physical phase transition in the material; on the other hand, it is connected to the time-to-digital converter unit through a self-calibration circuit to provide a clock signal for calibration.

[0014] The time-to-digital conversion unit is calibrated by a self-calibration circuit: the total delay of the slow delay line is locked to an integer multiple of the period of the external reference clock by the delay-locked loop (DLL) in the self-calibration circuit to determine the stable control voltages Vp1 and Vn1 applied to the slow delay line, and after applying bias voltages to Vp1 and Vn1, control voltages Vp2 and Vn2 applied to the fast delay line are generated.

[0015] The control unit applies an excitation signal to the differential entropy source unit;

[0016] The differential entropy source unit responds to the excitation signal and generates first and second output signals C with random time differences. out1 C out2 ;

[0017] The arbitrator in the time-to-digital conversion unit determines the arrival order of the first and second output signals, and routes the first and second output signals to the slow delay line and the fast delay line respectively by controlling the analog switch;

[0018] The first and second output signals propagate in the slow delay line and the fast delay line, respectively, and are sampled and compared by the D flip-flop array;

[0019] The D flip-flop array quantizes the random time difference into a multi-bit digital code, which is latched into the capture register and output as the final random number.

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] High-quality entropy source with physical immunity: Utilizing the VO2 first-order physical phase transition as the entropy source, the entropy quality and robustness are fundamentally improved. The differential symmetric architecture can physically offset the common-mode drift introduced by PVT changes and naturally output unbiased random bits. Efficient and lossless entropy capture: Employing a vernier delay line (TDC) structure, the random time difference of each phase transition event is completely converted into multi-bit digital random numbers, ensuring a stable and efficient entropy capture rate. Innovative tunability and adaptability: On-demand tuning of entropy intensity is achieved through slope-adjustable excitation signals; combined with a DLL-based self-calibration circuit, a precise scale for time quantization is provided to resist environmental changes. High system-level reliability: Through redundant design of the entropy source array and online health diagnostics, system-level self-healing capability is achieved, solving the long-term reliability pain point of new material devices. High integration and design convenience: VO2 devices can be integrated into the back-end metal layer (BEOL) of the chip, naturally isolated from the underlying silicon substrate, eliminating the crosstalk lock-in problem of traditional CMOS entropy sources.

[0022] The above and other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0023] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0024] Figure 1 This is a system structure block diagram of the true random number generator of the present invention;

[0025] Figure 2 This is a schematic diagram of the differential entropy source circuit in an embodiment of the present invention;

[0026] Figure 3 This is a structural diagram of the time-to-digital conversion unit (TDC) in an embodiment of the present invention;

[0027] Figure 4 This is a circuit diagram of the adjustable delay unit in an embodiment of the present invention;

[0028] Figure 5 This is a block diagram of the self-calibration circuit in an example of the present invention;

[0029] Figure 6 This is a timing diagram of the entropy intensity being tuned on demand in an embodiment of the present invention;

[0030] Figure 7 This is a diagram of an entropy source array structure with self-healing capability in an embodiment of the present invention;

[0031] Figure 8This is a schematic diagram illustrating the principle of physical attack detection in an embodiment of the present invention;

[0032] Figure 9 This is a cross-sectional schematic diagram of a single entropy source device in an embodiment of the present invention. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this invention clearer, specific embodiments of the invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0034] It should be noted that in the description of this invention, the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0035] As described in the background section, traditional true random number generators based on CMOS circuits have poor robustness due to the susceptibility of their entropy source to changes in PVT; they are prone to crosstalk lockout when integrated on-chip; and they also suffer from problems such as low entropy capture efficiency and bias in the output bit stream.

[0036] To address the aforementioned problems, this invention proposes a true random number generator based on a first-order physical phase transition. This invention utilizes the inherent quantum and thermodynamic uncertainties exhibited by vanadium dioxide (VO2) during the insulator-metal phase transition, transforming this microscopic uncertainty into a macroscopic, random time difference between two pulse signals through a fully differential symmetric architecture. Subsequently, a self-calibrating vernier delay line time-to-digital converter (TDC) losslessly quantizes this random time difference into multi-bit random numbers. This invention ensures high quality and interference resistance of the entropy source from a physical perspective, and combined with efficient quantization circuitry and intelligent system management, achieves high-performance, high-reliability true random number generation.

[0037] Figure 1This is a system block diagram of a preferred embodiment of the true random number generator of the present invention. The true random number generator includes: a control unit, a differential entropy source unit, a time-to-digital converter unit, and a self-calibration circuit. In this embodiment, the control unit can be a microcontroller (MCU), which is responsible for generating excitation signals and controlling the overall system operation. The differential entropy source unit generates a pair of digital pulse signals with a random time difference under excitation. The time-to-digital converter unit receives the pulse pair and accurately quantizes its time difference into a multi-bit random number. The self-calibration circuit is used to ensure the quantization accuracy of the time-to-digital converter unit.

[0038] In this embodiment, the core of random number generation is the differential entropy source unit, and its specific circuit schematic is as follows: Figure 2 As shown. This unit adopts a fully differential symmetric architecture, where the same excitation signal from the control unit is simultaneously applied to two symmetric entropy source devices E1 and E2, as shown. Figure 9 As shown, the device consists of a platinum (Pt) heating element, a vanadium dioxide (VO2) functional layer, and an aluminum nitride (AlN) heat dissipation layer. When the excitation signal passes through the Pt heating element, the resulting Joule heating causes the temperature of the VO2 functional layer to rise and undergo a phase transition. The abrupt change in resistance causes the output node E to... out1 and E out2 A voltage step is generated. Each voltage step signal is then passed through corresponding comparators C1 and C2, and shaped into a clear first output signal and a clear second output signal C. out1 and C out2 .

[0039] The physical principle of the entropy source lies in the fact that the insulator-metal phase transition of VO2 is a first-order phase transition process, and its domain nucleation and growth at the microscopic level have inherent, unpredictable quantum and thermodynamic uncertainties. This results in two symmetrical entropy source devices receiving the exact same excitation, but the precise timing of their phase transitions is completely random and asynchronous. The differential symmetry architecture transforms this microscopic randomness into a macroscopic, measurable random time difference between the two output pulses, while simultaneously suppressing common-mode drift introduced by PVT variations at the physical level.

[0040] The time-to-digital conversion unit is specifically a vernier delay-line time-to-digital converter (TDC), which includes: an arbitrator, an analog switch, a slow delay line and a fast delay line, a D flip-flop array, and a capture register; the signal propagation delay of the fast delay line is less than that of the slow delay line; the two inputs of the arbitrator are connected to the outputs of two differential entropy source units, and the output of the arbitrator is connected to the control terminal of the analog switch; the two data inputs of the analog switch are also connected to the outputs of the two differential entropy source units, and the two data outputs of the analog switch are respectively connected to the inputs of the slow delay line and the fast delay line; Both the slow delay line and the fast delay line consist of several series-connected adjustable delay units; the D flip-flop array contains several D flip-flops; the output of each adjustable delay unit in the fast delay line is connected to the input of the corresponding D flip-flop, and the output of each adjustable delay unit in the slow delay line is connected to the clock terminal of the corresponding D flip-flop. The outputs of all D flip-flops are connected to the input of the capture register via a bus. The capture register catches up with the slow delay line signal, quantizes the analog time difference into a digital code, and outputs the generated random number; the output of the last adjustable delay unit in the fast delay line is grounded.

[0041] In this embodiment of the invention, the arbitrator is used to determine the first and second output signals C. out1 C out2 The order of arrival is determined, and the state of the analog switch is controlled according to the order of arrival. The analog switch sends the first arriving signal to the slow delay line and the later arriving signal to the fast delay line.

[0042] In this embodiment of the invention, the adjustable delay unit is specifically a voltage-controlled delay NOT gate, whose delay time is precisely controlled by independent control voltages Vp and Vn.

[0043] The random time difference generated by the differential entropy source unit is precisely quantized by the time-to-digital conversion unit, and its structure is as follows: Figure 3 As shown. The first output signal C from the comparator. out1 Second output signal C out2 As input signals A respectively In1 and A In2 The signal enters an arbitrator. The arbitrator determines the order of pulse arrival and generates a control signal CTL, which is sent to the analog switch. Simultaneously, the first output signal C... out1 Second output signal C out2 Also used as data input S In1 and S In2 The signal is sent to the analog switch. The analog switch, according to the CTL's instructions, outputs the signal through its terminal S. out1 and S out2The first-arriving pulse is routed to the slow delay line, and the second-arriving pulse is routed to the fast delay line. Both the slow and fast delay lines consist of a series of interconnected adjustable delay units (IL1 to IL). N ;IF1 to IF N It consists of [structure / component]. The specific circuitry for each adjustable delay unit is as follows: Figure 4 As shown, it includes two PMOS transistors M p1 and M p2 Two NMOS transistors M n3 and M n4 PMOS transistor M p1 The source is connected to the power supply VCC, and the gate is used to receive the control voltage V. p The drain is connected to the PMOS transistor M. p2 The source of the PMOS transistor; p2 The drain of the NMOS transistor M n3 The drain is connected to the output node V. out NMOS transistor M n4 The source is grounded, and the gate is used to receive the control voltage V. n Its drain is connected to the NMOS transistor M. n3 The source of the NMOS transistor M; n3 The gate of the PMOS transistor M p2 The gates are connected together to the input signal V. In By independently adjusting the control voltage V p and control voltage V n This allows for precise control of the unit's transmission delay time.

[0044] The core of the adjustable delay unit is a PMOS transistor M P2 and NMOS transistor M N3 The CMOS inverter is constructed with a pull-up current source consisting of a PMOS transistor M. P1 To achieve this, the pull-down current source is an NMOS transistor M. N4 Achieved by independently adjusting the control voltage V. p and V n The size of the voltage allows for precise limitation of the charging and discharging current, thus enabling flexible control of its output V. out The transmission delay time. Following this, an array of D flip-flops (D1 to D2) NThe data input terminal is connected to the output nodes of each stage of the slow delay line, and the clock input terminal is connected to the output nodes of each stage of the fast delay line. When the fast line pulse catches up with the slow line pulse, the output of the D flip-flop array forms a thermometer code such as "111...100...0", and the position of its "1-0" flip point precisely corresponds to the initial random time difference. This digital code is finally sent to the capture register for latching and output through the bus Q[N:1].

[0045] In this embodiment of the invention, the data input terminal of the D flip-flop array is connected to the output of each stage of the slow delay line, and its clock input terminal is connected to the output of each stage of the fast delay line, which is used to capture the position where the fast line signal catches up with the slow line signal, thereby quantizing the analog time difference into digital code.

[0046] To ensure the accuracy of time quantization, this invention also includes a self-calibration circuit, the block diagram of which is shown below. Figure 5 As shown, the self-calibration circuit is implemented as follows: the clock signal from the control unit is split into two paths. One path is input to the first input terminal of the phase detector PD, and the other path is input to the second input terminal of the phase detector PD after passing through a slow delay line. The phase detector PD compares the phase difference between the two input signals, generates an error signal, and generates a control voltage V through the loop filter LF. p and V n And by controlling the voltage V p and V n Dynamically adjust all adjustable delay units on the slow delay line until the total delay of the slow delay line is locked to an integer multiple of the clock signal period, determined by V. p and V n After applying the bias voltage, the control voltage for all delay units on the fast delay line is obtained.

[0047] In this embodiment, the circuit is implemented using a delay-locked loop (DLL). In calibration mode, a stable external reference clock from the control unit is fed to the phase detector (PD) and the complete slow delay line. The phase detector (PD) compares the phase difference between the two signals, generates an error signal, and uses a loop filter (LF) to generate and dynamically adjust the control voltage V applied to all adjustable delay units on the slow line. p and V n This continues until the total delay of the slow delay line is precisely locked to an integer multiple of the reference clock cycle. The control voltages for all delay units on the fast delay line are obtained by applying bias voltages to Vp and Vn.

[0048] In this embodiment, the control unit can also implement a variety of advanced management functions. For example, refer to Figure 6The timing diagram shown demonstrates that the control unit can actively tune the distribution range of the time difference Δt between output pulse pairs by adjusting the slope of the excitation signal, thus achieving a flexible trade-off between entropy intensity and throughput. For example, refer to... Figure 7 The structural diagram shown illustrates that the differential entropy source unit can be implemented as an array containing N entropy source devices. The control unit can perform online health diagnostics through monitoring lines and automatically switch from a faulty unit to a backup unit by controlling a multiplexer. Furthermore, refer to... Figure 8 The schematic diagram shows that the control unit can also monitor physical characteristics of the entropy source, such as the "average phase transition time," and compare them with the preset normal operating range. When the parameters exceed the normal operating range, it can be determined that a physical attack has occurred.

[0049] In a specific embodiment, the control unit may be a 32-bit microcontroller with PWM (Pulse Width Modulation) peripherals and DAC (Digital-to-Analog Converter); the peak voltage of the excitation signal applied to the Pt heating element may be adjusted between 1V and 3V, and the slope may be programmed within the range of 0.1V / μs to 10V / μs; the delay time of the adjustable delay unit in the slow delay line and the fast delay line may be calibrated within the range of 30ps to 100ps, with a delay difference of approximately 5-10ps; the external reference clock frequency used by the self-calibration circuit may be 100MHz; the D flip-flop may be a high-speed edge-triggered D flip-flop from the standard cell library, and the capture register may be composed of a set of parallel D latches.

[0050] In one embodiment of the present invention, the electrical connection between the control unit and the entropy source device is achieved through a metal interconnect layer inside the chip. Specifically, the control unit, as a standard CMOS circuit, is fabricated in the front-end process layer (FEOL) of the silicon substrate. Metal traces leading from the DAC pins of the MCU are connected to a platinum heating layer integrated on the chip surface through a back-end process layer (BEOL) via multilayer metal wiring and interlayer vias in the standard CMOS process, thereby accurately applying the excitation signal generated by the MCU to the entropy source device.

[0051] This invention also provides a true random number generation method, which includes: first, calibrating the delay line in the time-to-digital conversion unit using a self-calibration circuit to establish a stable timing reference; then, applying an excitation signal to a differential entropy source unit by a control unit, wherein the differential entropy source unit, in response to the excitation signal, generates first and second output signals C with random time differences. out1 C out2 Finally, the time-to-digital conversion unit precisely quantizes the random time difference into a multi-bit digital code, which is then latched by the capture register and output as a random number.

[0052] This method combines a high-quality physical entropy source from the first-order physical phase transition of vanadium dioxide (VO2) with the efficient and lossless entropy capture mechanism of a vernier delay line time-to-digital converter (TDC). By precisely mapping microscopic quantum and thermodynamic uncertainties to macroscopically measurable multi-bit digital random numbers, it achieves highly reliable and high-performance true random number generation.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A physical phase change based true random number generator, characterized in that, The application relates to a differential entropy source unit, a time-to-digital conversion unit, a control unit and a self-calibration circuit. The differential entropy source unit generates two output signals with random time difference based on a first-order physical phase change process of a material; The differential entropy source unit comprises an entropy source device which is a stacked structure composed of a platinum Pt heating layer, a vanadium dioxide VO2 functional layer and an aluminum nitride AlN heat dissipation layer; The time-to-digital conversion unit is connected to the output of the differential entropy source unit and quantizes the random time difference between the first output signal and the second output signal into a multi-bit digital random number; The control unit is connected to the differential entropy source unit and provides an excitation signal to the differential entropy source unit to induce the physical phase change of the material; The other end is connected to the time-to-digital conversion unit through the self-calibration circuit and provides a clock signal to the time-to-digital conversion unit for calibration; The time-to-digital conversion unit comprises an arbitrator, an analog switch, a slow delay line and a fast delay line, a D flip-flop array and a capture register; The signal propagation delay of the fast delay line is smaller than that of the slow delay line; two input ends of the arbitrator are connected to the output ends of the two differential entropy source units, and an output end of the arbitrator is connected to a control end of the analog switch; two data input ends of the analog switch are also connected to the output ends of the two differential entropy source units, and two data output ends of the analog switch are connected to the input ends of the slow delay line and the fast delay line respectively; the slow delay line and the fast delay line are both composed of a plurality of series-connected adjustable delay units; the D flip-flop array has a plurality of D flip-flops; the output end of each adjustable delay unit in the fast delay line is connected to the input end of a corresponding D flip-flop, the output end of each adjustable delay unit in the slow delay line is connected to the clock end of a corresponding D flip-flop, the output ends of all the D flip-flops are connected to the input end of the capture register through a bus, the capture register captures the position where the fast delay line signal catches up with the slow delay line signal, quantizes the analog time difference into a digital code, and the output end of the capture register outputs the generated random number; the output end of the last adjustable delay unit in the fast delay line is grounded; The differential entropy source unit comprises a pair of structure-symmetrical entropy source branches; in the entropy source branch, one end of a first entropy source device E1 and one end of a second entropy source device E2 are connected to one end of a resistor R1 and one end of a resistor R2 respectively to form a voltage divider circuit, the other ends of the entropy source devices E1 and E2 are connected to a power supply VCC, and the other ends of the resistors R1 and R2 are both connected to a common end GND; The self-calibration circuit is specifically implemented as: a clock signal from a control unit is divided into two paths, one path is input to a first input terminal of a phase detector PD, and the other path is input to a second input terminal of the phase detector PD after passing through a slow delay line; the phase detector PD compares the phase difference of the two input signals, generates an error signal, and generates a control voltage V p and V n through a loop filter LF p and V n The control voltage V p and V n is added to a bias voltage to obtain the control voltage of all delay units on the fast delay line.

2. The physical phase change based true random number generator of claim 1, wherein, The resistance values of the first resistor R1 and the second resistor R2 are equal; The arbitrator is used for judging the arrival sequence of the first output signal and the second output signal and controlling the state of the analog switch according to the arrival sequence; the analog switch sends the signal arriving first into the slow delay line and sends the signal arriving later into the fast delay line. The connection point between the entropy source device and the resistor serves as an output node E out1 , E out2 , connected to the non-inverting input of comparators C1, C2, the inverting input of which is connected to a uniform reference voltage V ref ; the outputs C out1 , C out2 of the comparators C1, C2 are the output signals of the differential entropy source unit.

3. The physical phase change based true random number generator of claim 2, wherein, The platinum (Pt) heating layer, vanadium dioxide (VO2) functional layer and aluminum nitride (AlN) heat dissipation layer in the entropy source device have the same area, and when working, a control unit applies a slope-adjustable excitation signal to the platinum heating layers of the first and second entropy source devices E1 and E2, so as to cause the vanadium dioxide functional layer to undergo insulator-metal phase transition and generate voltage signals with random time difference between the first and second output nodes E out1 、 E out2 .

4. The physical phase change based true random number generator of claim 3, wherein, The application further discloses a method for generating a random number, comprising the following steps:

5. The physical phase change based true random number generator of claim 4, wherein, The adjustable delay unit is specifically a voltage-controlled delay NOT gate, comprising two PMOS transistors M p1 and M p2 , two NMOS transistors M n3 and M n4 ; the source of the PMOS transistor M p1 is connected to a power supply VCC, the gate is used for receiving a control voltage V p , and the drain is connected to the source of the PMOS transistor M p2 ; the drain of the PMOS transistor M p2 and the drain of the NMOS transistor M n3 are connected to an output node V out ; the source of the NMOS transistor M n4 is grounded, the gate is used for receiving a control voltage V n , and the drain is connected to the source of the NMOS transistor M n3 ; and the gate of the NMOS transistor M n3 and the gate of the PMOS transistor M p2 are commonly connected to an input signal V In .

6. A physical phase change based true random number generation method for implementing the true random number generator of any one of claims 1 to 5, characterized in that, S1, the control unit provides an excitation signal to the differential entropy source unit to induce the physical phase change of the material; The other end is connected to the time-to-digital conversion unit through the self-calibration circuit and provides a clock signal to the time-to-digital conversion unit for calibration; ​ S2, the self-calibration circuit locks the total delay of the slow delay line on an integer multiple of the clock signal period, determines the stable control voltage applied to the slow delay line, and generates the control voltage applied to the fast delay line after applying a bias voltage to the stable control voltage; S3, the differential entropy source unit generates first and second output signals with random time difference in response to the excitation signal; S4, the arbiter in the time-to-digital conversion unit judges the arrival order of the first and second output signals, and inputs the first and second output signals into the slow delay line and the fast delay line respectively by controlling the analog switch; S5, the first and second output signals propagate in the slow delay line and the fast delay line respectively, and are sampled and compared by the D flip-flop array; S6, the D flip-flop array quantizes the random time difference into a multi-bit digital code, which is latched into the capture register and output as the final random number.

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