A PCIe cache coherency system implemented on a switch

Abstract

This invention discloses a PCIe cache coherence system implemented on a switch, comprising: a switch having multiple ports for connecting to devices; a port access table, each port having its own port access table, the port access table being used to record events where the device corresponding to the port establishes cached data, and the entries in the port access table including a BDF number, a physical address, and a status flag; and a coherence proxy unit configured to modify the data in all port access tables; when a device performs a write operation on external data or cached data, the coherence proxy unit creates new entries in the port access table of the device storing the cached data and the port access table of the device from which the cached data originates, and modifies entries in other port access tables that have different BDF numbers but the same physical address as the new entries until the cache is invalidated.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more particularly to a PCIe cache coherency system implemented on a switch. Background Technology

[0002] With the rapid development of artificial intelligence, deep learning, high-performance computing, and big data processing technologies, the demand for data transmission has exploded. In high-bandwidth, low-latency data exchange scenarios, traditional PCIe architecture faces numerous severe challenges, including insufficient bandwidth, latency, and lengthy data transmission paths. To address these issues, some solutions attempt to optimize data transmission through shared memory. However, in multi-device data exchange scenarios, such as in large-scale parallel systems like deep learning training, graphics rendering, and high-performance scientific computing, shared memory-based data transmission can lead to cache inconsistency problems. This cache inconsistency issue becomes particularly pronounced when multiple devices need to read and write shared data simultaneously.

[0003] In computer systems, the PCIe bus is an important internal interconnect standard used to connect components such as the CPU, memory, and peripherals. However, existing technologies have the following main drawbacks in maintaining cache coherency:

[0004] 1. In cache coherency processing among multiple XPUs, the current PCIe protocol usually adopts the method of controlling memory attributes. This method requires moving data from memory to the XPU for computation every time data is retrieved, which causes a lot of latency and cannot meet the needs of training large models with trillions of parameters.

[0005] 2. Existing cache consistency designs can lead to cache inconsistency issues in multi-device data exchange scenarios, such as in large-scale parallel systems like deep learning training, graphics rendering, and high-performance scientific computing, due to shared memory-based data transmission methods. This is especially true when multiple devices need to read and write shared data simultaneously, where the cache consistency problem becomes even more prominent.

[0006] 3. Existing cache consistency handling methods often require software to actively maintain cache consistency, such as refreshing the cache or invalidating the cache. This approach increases system complexity and latency, and cannot meet the requirements of efficient data transmission.

[0007] 4. Traditional PCIe architecture lacks effective hardware support for handling cache coherency between the CPU and multiple XPUs, making it difficult to meet the requirements of high bandwidth and low latency in large-scale parallel computing scenarios;

[0008] 5. Existing cache coherence designs lack flexibility and efficiency when dealing with complex memory access patterns, making it difficult to adapt to diverse computing needs and affecting the overall system performance and scalability.

[0009] Therefore, a more efficient PCIe cache coherency design is urgently needed to address the latency issues in existing technologies and improve the speed of training large AI models using the PCIe protocol. Simultaneously, this design also needs to effectively manage cache coherency among multiple XPUs to ensure data consistency and availability, thereby meeting the ever-increasing computing demands.

[0010] The above background information is provided only to assist in understanding the inventive concept and technical solution of this invention. It does not necessarily belong to the prior art of this application, nor does it necessarily provide technical teaching. In the absence of clear evidence that the above information was disclosed before the filing date of this application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0011] The purpose of this invention is to provide a PCIe cache coherency system implemented on a switch.

[0012] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0013] A PCIe cache coherency system implemented on a switch, comprising:

[0014] A switch having multiple ports for connecting to devices;

[0015] A port access table is set for each port. The port access table is used to record events in which the device corresponding to the port establishes cached data. The table entries include BDF number, physical address and status flag, wherein the BDF number is used to point to the device storing cached data, the physical address is used to point to the device from which the cached data originates, and the status flag is used to indicate the cache validity of the cached data.

[0016] A consistency proxy unit is configured to modify the data in the tables of all said port access tables;

[0017] When the device performs a write operation on external data or cached data, the consistency proxy unit creates new entries in both the port access table of the device storing the cached data and the port access table of the device from which the cached data originates, and modifies entries in other port access tables that have different BDF numbers but the same physical address as the new entries until the cache is invalidated.

[0018] In some embodiments, the device storing the cached data and the device from which the cached data originates may refer to the same device or different devices.

[0019] In some embodiments, when an event occurs that cached data is created in the port access table, the consistency proxy unit writes the BDF number of the device storing the cached data and the physical address of the device from which the cached data originates into the port access table and marks it as cache valid.

[0020] In some embodiments, when the first device performs read / write operations on the external data, the PCIe cache coherency system implemented on the switch is configured to perform the following steps:

[0021] The first device sends a virtual address translation request to the switch;

[0022] After receiving the conversion request, the consistency proxy unit converts the virtual address into a physical address and sends it back to the first device. At the same time, the consistency proxy unit records the event of establishing cached data between the first device and the second device in the port access table of the first device and the port access table of the second device, respectively.

[0023] After receiving the physical address, the first device sends a data packet containing the physical address to the switch;

[0024] When the data packet is a read operation data packet, the switch forwards the data packet to the second device according to the physical address. When the data packet is a write operation data packet, the switch checks whether there is a matching entry in all port access tables that has the same physical address as the data packet but a different BDF number. If the matching entry exists, the consistency proxy unit sends a cache invalidation signal to the matching entry. After receiving the cache invalidation confirmation signal, the switch forwards the data packet to the second device. If the matching entry does not exist, the switch directly forwards the data packet to the second device.

[0025] In some embodiments, it is configured such that when an event of creating cached data in the port access table is performed, it is necessary to determine whether there is a free entry in the port access table. If there is a free entry, the event of creating cached data in the port access table is performed directly. If there is no free entry, the entry in the port access table is evicted according to the eviction algorithm before the event of creating cached data is performed.

[0026] In some embodiments, the elimination algorithm is a first-in-first-out algorithm or a least-used algorithm.

[0027] In some embodiments, before eliminating an item in the port access table, the consistency proxy unit sends a cache invalidation signal to a matching item whose BDF number and physical address are the same as the item to be eliminated, and deletes the item to be eliminated after receiving a cache invalidation confirmation signal.

[0028] In some embodiments, if no confirmation signal of cache invalidation is received, the switch sends an interrupt signal to the host.

[0029] In some embodiments, it is configured to perform the following steps when the first device performs read / write operations on the cached data:

[0030] The first device sends a virtual address translation request to its internal mapping module;

[0031] The mapping module converts the virtual address into a physical address and then sends it back to the first device.

[0032] The first device determines whether the cached data originates from the first device or the second device;

[0033] When the cached data originates from the first device, and the first device performs a read operation on the cached data, the first device accesses the cached data.

[0034] In some embodiments, when the cached data originates from the first device and the first device performs a write operation on the cached data, the consistency proxy unit records the event of establishing cached data within the first device in the port access table of the first device. The switch detects whether there is a matching entry in all port access tables that has the same physical address as the cached data but a different BDF number. If the matching entry exists, the consistency proxy unit sends a cache invalidation signal to the matching entry, and the first device accesses the cached data. If the matching entry does not exist, the consistency proxy unit does not take any action, and the first device accesses the cached data.

[0035] In some embodiments, it is configured to perform the following steps when the first device performs read / write operations on cached data:

[0036] The first device sends a virtual address translation request to its internal mapping module;

[0037] The mapping module converts the virtual address into a physical address and then sends it back to the first device.

[0038] The first device determines whether the cached data originates from the first device or the second device;

[0039] When the cached data originates from the second device, the first device queries its device access table to check whether the entry with the same physical address returned by the mapping module is cached invalid.

[0040] When the physical address cache expires, the first device sends a data packet containing the physical address to the switch, and the switch forwards the data packet to the second device based on the physical address.

[0041] In some embodiments, when the physical address cache is valid and the first device performs a read operation on the cached data, the first device accesses the cached data;

[0042] When the physical address cache is valid and the first device performs a write operation on the cached data, the consistency proxy unit records the event of establishing cached data between the first device and the second device in the port access table of the first device and the port access table of the second device, respectively. The switch checks whether there is a matching entry in all port access tables that has the same physical address as the cached data but a different BDF number. If the matching entry exists, the consistency proxy unit sends a cache invalidation signal to the matching entry, and the first device accesses the cached data. If the matching entry does not exist, the consistency proxy unit does not take any action, and the first device accesses the cached data.

[0043] In some embodiments, each of the devices is provided with a device access table, which is used to record events in which cached data is established between the device corresponding to the device access table and other devices.

[0044] In some embodiments, the port access table and the device access table corresponding to the same device are always kept synchronized.

[0045] In some embodiments, the entries in the device access table include the device's BDF number, physical address, and status flag, wherein the BDF number is used to point to the device storing cached data, the physical address is used to point to the device from which the cached data originates, and the status flag is used to indicate the cache validity of the cached data.

[0046] The beneficial effects of the technical solution provided by this invention are as follows:

[0047] a. By adding a port access table corresponding to the device on the port of the switch, the port access table is used to record the event of the device establishing cache data corresponding to the port access table, thus realizing hardware-level cache consistency management. It eliminates the need to move data from memory to the device for calculation every time data is retrieved, which significantly reduces the latency caused by software-managed consistency management in large-scale calculations and improves data transmission efficiency.

[0048] b. When a device performs a write operation on external data or cached data, a new entry is created in the port access table of the device storing the cached data and the port access table of the device from which the cached data originates. The entries in other port access tables that have different BDF numbers but the same physical address as the new entry are modified until the cache expires. This achieves automatic cache synchronization between multiple devices, avoids cache inconsistency problems, and ensures the consistency of data owned by all devices.

[0049] c. By implementing the port access table in hardware, the need for software to actively maintain cache consistency in traditional methods is eliminated. The operation is automated, with the switch hardware responsible for consistency management. The CPU does not need to run software to maintain consistency, which reduces CPU load, reduces system complexity, reduces latency, and improves system stability and reliability.

[0050] d. This invention is applicable to computing nodes consisting of a CPU, multiple XPUs, and a switch. It is particularly suitable for large-scale parallel systems such as deep learning training, graphics rendering, and high-performance scientific computing, and can meet the needs of training large models with trillions of parameters. Specifically, in AI application scenarios such as deep learning and training language models, a large amount of data is transferred between devices. Since an interrupt must be sent to the CPU to maintain consistency after each transfer, and the CPU continues to run the program after processing the interrupt, this patent can reduce the CPU load and the latency of interrupt processing, thereby improving the efficiency of deep learning and training language models.

[0051] e. Compared to the traditional PCIe architecture, this invention provides a more flexible memory access mechanism through the addition of a port access table, which can better adapt to diverse computing needs and improve system performance and scalability. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 A schematic diagram of a first device performing a write operation on external data in a PCIe cache coherence system implemented on a switch, as provided in an exemplary embodiment of the present invention. Figure 1 ;

[0054] Figure 2A schematic diagram of a first device performing a write operation on external data in a PCIe cache coherence system implemented on a switch, as provided in an exemplary embodiment of the present invention. Figure 2 ;

[0055] Figure 3 A flowchart illustrating a PCIe cache coherence method implemented on a switch, as provided in an exemplary embodiment of the present invention. Figure 1 At this time, the first device performs read and write operations on external data;

[0056] Figure 4 A flowchart illustrating a PCIe cache coherence method implemented on a switch, as provided in an exemplary embodiment of the present invention. Figure 1 At this point, the first device performs read and write operations on the cached data. Detailed Implementation

[0057] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0059] like Figure 1-4 As shown, in some embodiments of the present invention, a PCIe cache coherency system implemented on a switch is provided.

[0060] Specifically, in some embodiments, the PCIe cache coherence system implemented on a switch according to the present invention includes:

[0061] A switch has multiple ports for connecting to devices;

[0062] A port access table is set up for each port. The port access table is used to record events in which the device corresponding to the port establishes cached data. The entries of the port access table include BDF (bus, device, function) number, physical address, and status flag. The BDF number is used to point to the device storing the cached data, the physical address is used to point to the device from which the cached data originates, and the status flag is used to indicate the cache validity of the cached data. The device storing the cached data and the device from which the cached data originates can point to the same device or different devices. When they point to different devices, the first device represents the device storing the cached data, and the second device represents the device from which the cached data originates.

[0063] The Coherence Agent unit is configured to modify the data in all port access tables. When an event that creates cached data in the port access table occurs, the Coherence Agent unit writes the BDF number of the device storing the cached data and the physical address of the device from which the cached data originates into the port access table and marks it as cache valid.

[0064] Each device has its own device access table. This table records events where the device corresponding to it establishes cached data with other devices. The port access table and the device access table for the same device are always synchronized. Each entry in the device access table includes the device's BDF number, physical address, and status flag. The BDF number points to the device storing the cached data, the physical address points to the device from which the cached data originated, and the status flag indicates the validity of the cached data. By setting up the device access table, devices can verify the validity of cached data without going through a switch.

[0065] When a device performs a write operation on external data or cached data, the consistency agent unit creates new entries in the port access table of the device storing the cached data and the port access table of the device from which the cached data originates, and modifies the entries in other port access tables that have different BDF numbers but the same physical address as the new entries until the cache is invalidated.

[0066] like Figure 1-3 As shown, when the first device performs read / write operations on external data, the PCIe cache coherency system implemented on the switch is configured to include the following steps:

[0067] The first device sends a virtual address translation request to the switch;

[0068] After receiving the conversion request, the consistency proxy unit converts the virtual address to a physical address and sends it back to the first device. At the same time, the consistency proxy unit records the event of establishing cached data between the first device and the second device in the port access table of the first device and the port access table of the second device, respectively. By setting the mapping between virtual address and physical address, the first device verifies the legality of its actions before reading and writing external data, thus avoiding security risks.

[0069] After receiving the physical address, the first device sends a data packet containing the physical address to the switch;

[0070] When the data packet is a read operation data packet, since it does not involve modification of external data, the switch forwards the data packet to the second device based on the physical address. When the data packet is a write operation data packet, the switch checks whether there is a matching entry in all port access tables that has the same physical address as the data packet but a different BDF number. If a matching entry exists, the consistency proxy unit sends a cache invalidation signal to the matching entry. After receiving the cache invalidation confirmation signal, the switch forwards the data packet to the second device to ensure the integrity and consistency of data transmission. If no cache invalidation confirmation signal is received, the switch sends an interrupt signal to the host. If no matching entry exists, the data packet is directly forwarded to the second device.

[0071] In some embodiments, when an event for creating cached data in the port access table is performed, it is necessary to determine whether there is a free entry in the port access table. If there is a free entry, the event for creating cached data in the port access table is created directly. If there is no free entry, the entry in the port access table is evicted according to the eviction algorithm before the event for creating cached data is created. The eviction algorithm is either the first-in-first-out algorithm or the least-used (LRU) algorithm.

[0072] Before eliminating an entry in the port access table, the consistency agent unit sends a cache invalidation signal to a matching entry that has the same BDF number and physical address as the entry to be eliminated, and deletes the entry to be eliminated after receiving the cache invalidation confirmation signal.

[0073] like Figure 4 As shown, when the first device performs read / write operations on cached data, the following steps are executed:

[0074] The first device sends a virtual address translation request to its internal mapping module;

[0075] The mapping module converts the virtual address to a physical address and sends it back to the first device. By setting the mapping between the virtual address and the physical address, the first device verifies the legality of its actions before reading and writing cached data, thus avoiding security risks.

[0076] The first device determines whether the cached data originates from the first device or the second device;

[0077] When the cached data originates from the first device, and the first device performs a read operation on the cached data, the first device accesses the cached data because it does not involve modifying the cached data.

[0078] When the cached data originates from the first device, and the first device performs a write operation on the cached data, the consistency proxy unit records the event of establishing cached data within the first device in the port access table of the first device. The switch checks whether there is a matching entry in all port access tables that has the same physical address as the cached data but a different BDF number. If a matching entry exists, the consistency proxy unit sends a cache invalidation signal to the matching entry, and the first device accesses the cached data. If no matching entry exists, the consistency proxy unit does not take any action, and the first device accesses the cached data.

[0079] When cached data originates from a second device, the first device queries its device access table to check if the entry with the same physical address returned by the mapping module is cached invalid.

[0080] When the physical address cache expires, the first device sends a data packet containing the physical address to the switch. The switch forwards the data packet to the second device based on the physical address. Due to the configuration characteristics of the port access table, when the cached data comes from the first device, the entry in the device access table of the first device that is the same as the physical address returned by the mapping module must be cached and valid. Therefore, there is no need to further verify whether the cache has expired.

[0081] When the physical address cache is valid and the first device performs a read operation on the cached data, the first device accesses the cached data since it does not involve modifying the cached data.

[0082] When the physical address cache is valid and the first device performs a write operation on the cached data, the consistency proxy unit records the event of establishing cached data between the first device and the second device in the port access table of the first device and the port access table of the second device, respectively. The switch checks whether there is a matching entry in all port access tables that has the same physical address as the cached data but a different BDF number. If a matching entry exists, the consistency proxy unit sends a cache invalidation signal to the matching entry, and the first device accesses the cached data. If no matching entry exists, the consistency proxy unit does not take any action, and the first device accesses the cached data.

[0083] By setting the steps for the first device to write cached data, it is ensured that the first device can directly modify the cached data, achieving fast response processing, while maintaining the consistency of the same data across devices.

[0084] In summary, this invention solves the problems of significant latency and cache inconsistency caused by PCIe cache consistency design in the prior art.

[0085] The above description is only a specific embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A PCIe cache coherency system implemented on a switch, characterized in that, include: A switch having multiple ports for connecting to devices; A port access table is set for each port. The port access table is used to record events in which the device corresponding to the port establishes cached data. The table entries include BDF number, physical address and status flag, wherein the BDF number is used to point to the device storing cached data, the physical address is used to point to the device from which the cached data originates, and the status flag is used to indicate the cache validity of the cached data. A consistency proxy unit is configured to modify the data in the tables of all said port access tables; When the device performs a write operation on external data or cached data, the consistency proxy unit creates new entries in both the port access table of the device storing the cached data and the port access table of the device from which the cached data originates, and modifies entries in other port access tables that have different BDF numbers but the same physical address as the new entries until the cache is invalidated.

2. The PCIe cache coherency system implemented on a switch according to claim 1, characterized in that, The device storing the cached data and the device from which the cached data originates can refer to the same device or different devices.

3. The PCIe cache coherency system implemented on a switch according to claim 1, characterized in that, When an event occurs that cached data is created in the port access table, the consistency proxy unit writes the BDF number of the device storing the cached data and the physical address of the device from which the cached data originates into the port access table and marks it as cache valid.

4. The PCIe cache coherency system implemented on a switch according to claim 1, characterized in that, When the first device performs read / write operations on the external data, the PCIe cache coherency system implemented on the switch is configured to perform the following steps: The first device sends a virtual address translation request to the switch; After receiving the conversion request, the consistency proxy unit converts the virtual address into a physical address and sends it back to the first device. At the same time, the consistency proxy unit records the event of establishing cached data between the first device and the second device in the port access table of the first device and the port access table of the second device, respectively. After receiving the physical address, the first device sends a data packet containing the physical address to the switch; When the data packet is a read operation data packet, the switch forwards the data packet to the second device according to the physical address. When the data packet is a write operation data packet, the switch checks whether there is a matching entry in all port access tables that has the same physical address as the data packet but a different BDF number. If the matching entry exists, the consistency proxy unit sends a cache invalidation signal to the matching entry. After receiving the cache invalidation confirmation signal, the switch forwards the data packet to the second device. If the matching entry does not exist, the switch directly forwards the data packet to the second device.

5. The PCIe cache coherency system implemented on a switch according to claim 1, characterized in that, It is configured such that when an event of creating cached data in the port access table occurs, it needs to determine whether there is a free entry in the port access table. If there is a free entry, the event of creating cached data in the port access table is created directly. If there is no free entry, the entry in the port access table is evicted according to the eviction algorithm before the event of creating cached data is created.

6. The PCIe cache coherency system implemented on a switch according to claim 5, characterized in that: The elimination algorithm is either a first-in-first-out (FIFO) algorithm or a least-used algorithm.

7. The PCIe cache coherency system implemented on a switch according to claim 5, characterized in that: Before eliminating an entry in the port access table, the consistency proxy unit sends a cache invalidation signal to a matching entry whose BDF number and physical address are the same as the entry to be eliminated, and deletes the entry to be eliminated after receiving the cache invalidation confirmation signal.

8. The PCIe cache coherency system implemented on a switch according to claim 5 or 7, characterized in that: If no confirmation signal for cache invalidation is received, the switch sends an interrupt signal to the host.

9. The PCIe cache coherency system implemented on a switch according to claim 1, characterized in that: It is configured to perform the following steps when the first device performs read or write operations on the cached data: The first device sends a virtual address translation request to its internal mapping module; The mapping module converts the virtual address into a physical address and then sends it back to the first device. The first device determines whether the cached data originates from the first device or the second device; When the cached data originates from the first device, and the first device performs a read operation on the cached data, the first device accesses the cached data.

10. The PCIe cache coherency system implemented on a switch according to claim 9, characterized in that: When the cached data originates from the first device, and the first device performs a write operation on the cached data, the consistency proxy unit records the event of establishing cached data within the first device in the port access table of the first device. The switch checks whether there is a matching entry in all port access tables that has the same physical address as the cached data but a different BDF number. If the matching entry exists, the consistency proxy unit sends a cache invalidation signal to the matching entry, and the first device accesses the cached data. If the matching entry does not exist, the consistency proxy unit does not take any action, and the first device accesses the cached data.

11. The PCIe cache coherency system implemented on a switch according to claim 1, characterized in that: It is configured to perform the following steps when the first device performs read or write operations on cached data: The first device sends a virtual address translation request to its internal mapping module; The mapping module converts the virtual address into a physical address and then sends it back to the first device. The first device determines whether the cached data originates from the first device or the second device; When the cached data originates from the second device, the first device queries its device access table to check whether the entry with the same physical address returned by the mapping module is cached invalid. When the physical address cache expires, the first device sends a data packet containing the physical address to the switch, and the switch forwards the data packet to the second device based on the physical address.

12. The PCIe cache coherency system implemented on a switch according to claim 11, characterized in that: When the physical address cache is valid and the first device performs a read operation on the cached data, the first device accesses the cached data; When the physical address cache is valid and the first device performs a write operation on the cached data, the consistency proxy unit records the event of establishing cached data between the first device and the second device in the port access table of the first device and the port access table of the second device, respectively. The switch checks whether there is a matching entry in all port access tables that has the same physical address as the cached data but a different BDF number. If the matching entry exists, the consistency proxy unit sends a cache invalidation signal to the matching entry, and the first device accesses the cached data. If the matching entry does not exist, the consistency proxy unit does not take any action, and the first device accesses the cached data.

13. The PCIe cache coherency system implemented on a switch according to claim 1, characterized in that: Each of the devices is provided with a device access table, which is used to record events in which cached data is established between the device corresponding to the device access table and other devices.

14. The PCIe cache coherency system implemented on a switch according to claim 13, characterized in that: The port access table and the device access table corresponding to the same device are always kept synchronized.

15. The PCIe cache coherency system implemented on a switch according to claim 13, characterized in that: The entries in the device access table include the device's BDF number, physical address, and status flag. The BDF number points to the device storing the cached data, the physical address points to the device from which the cached data originates, and the status flag indicates the cache validity of the cached data.

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