Chip data plane verification method and device, and electronic equipment

Abstract

The application provides a chip data plane verification method and device and electronic equipment, and relates to the technical field of chip verification. Context information of a sending queue and a receiving queue corresponding to a to-be-verified network card chip is used to divide a target verification area from a system memory, the target verification area is converted into a virtual memory address to establish a corresponding queue channel, and finally the data plane path is verified through the channel. The blocking problem of the data plane verification caused by the incomplete debugging of the control plane in the prior art is completely eliminated, parallel verification of the control plane and the data plane is realized, and the overall chip verification period is significantly shortened.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a method, apparatus and electronic device for verifying chip data plane. Background Technology

[0002] In existing technologies, network interface card (NIC) drivers and NIC chips exchange control messages via the control plane's mailbox and CMDQ channels, and transmit data packet sending and receiving messages via the data plane's SQ / RQ channels. The data plane requires SQ / RQ CTX configuration via the CMDQ channel before data packet sending and receiving can commence.

[0003] During the chip verification phase, when the control plane is not fully debugged and cannot be used normally, a method is needed to verify the data plane path independently of the control plane, so that the control plane path and the data plane path can be verified in parallel, thus shortening the chip verification cycle. Summary of the Invention

[0004] The purpose of this invention is to provide a method, apparatus, and electronic device for verifying the data plane of a chip, which overcomes the problem of data plane verification being blocked when the control plane is not fully debugged in the prior art, realizes parallel verification of the control plane and the data plane, and significantly shortens the overall chip verification cycle.

[0005] In a first aspect, embodiments of the present invention provide a method for verifying the data plane of a chip. The method includes: obtaining context information of a pre-configured transmit queue and receive queue in a network interface card (NIC) chip to be verified; the context includes the physical memory start address, memory size, and descriptor format corresponding to the transmit queue and receive queue; dividing a target verification region from the currently configured system memory based on the physical memory start address and memory size of the context information; in response to NIC driver initialization, converting the target verification region into a virtual memory address to establish a transmit queue channel and a receive queue channel corresponding to the NIC chip to be verified; and performing data plane path verification on the NIC chip to be verified through the transmit queue channel and the receive queue channel.

[0006] In conjunction with the first aspect, this embodiment of the invention also provides a first implementation of the first aspect, wherein the step of dividing the target verification region from the currently configured system memory based on the physical memory start address and memory size of the context information includes: obtaining the currently configured exclusive physical memory region information from the memory management module of the operating system kernel; the exclusive physical memory region information includes the physical start address range, overall memory size, and remaining available space size of the corresponding physical memory region; reading the context information of the pre-configured send queue and receive queue from the network card chip to be verified, and extracting the physical memory start address and memory size corresponding to the send queue and the physical memory start address and memory size corresponding to the receive queue; verifying whether the physical memory start address is within the start address range of the exclusive physical memory region, and whether the memory size is within the remaining available space range of the exclusive physical memory region; if the physical memory start address is within the start address range of the exclusive physical memory region, and the memory size is within the remaining available space range of the exclusive physical memory region, then the verification is successful; determining the target verification regions corresponding to the send queue and the receive queue respectively in the exclusive physical memory region with the physical memory start address as the starting position and the memory size as the length.

[0007] In conjunction with the first aspect, the present invention also provides a second implementation of the first aspect, wherein the above method further includes: obtaining the system address space partition of the operating system, determining a contiguous memory region from the system address space partition; generating boot parameters based on the starting address and address length of the contiguous memory region; and updating the boot configuration of the operating system based on the boot parameters to reserve the contiguous memory region and generate an exclusive physical memory region.

[0008] In conjunction with the first aspect, this embodiment of the invention also provides a third implementation of the first aspect, wherein the step of obtaining the system address space partition of the operating system and determining a contiguous memory region from the system address space partition includes: calling the memory information query interface provided by the operating system kernel to obtain the overall layout information of the system address space; the layout information includes the start address, end address, and attributes of each memory segment in the system address space, and the attributes of the memory segment include allocated attributes, reserved attributes, or free status attributes; traversing the layout information of the system address space and filtering out all memory segments with free attributes; analyzing the filtered free memory segments to determine contiguous memory segments, and determining the contiguous memory segments as the target contiguous memory region.

[0009] In conjunction with the first aspect, this embodiment of the invention also provides a fourth implementation of the first aspect, wherein the step of updating the operating system's boot configuration based on boot parameters to reserve a contiguous memory region and generate an exclusive physical memory region includes: locating the operating system's boot configuration file; adding boot parameters to the configuration line of the kernel boot entry in the boot configuration file; restarting the operating system so that the operating system parses the boot parameters during the boot process and identifies the contiguous memory region that needs to be reserved; and marking the identified contiguous memory region as reserved so that it does not participate in the operating system's regular memory allocation, thereby generating an exclusive physical memory region.

[0010] In conjunction with the first aspect, this invention also provides a fifth implementation of the first aspect, wherein the step of converting the target verification region into a virtual memory address in response to network card driver initialization, so as to establish a transmit queue channel and a receive queue channel corresponding to the network card chip to be verified, includes: in response to network card driver initialization, calling the memory mapping interface provided by the operating system kernel, and passing the physical memory start address and memory size of the target verification region to the memory mapping interface; allocating independent continuous virtual address ranges for the physical memory regions of the transmit queue and the receive queue in the kernel virtual address space of the operating system through the memory mapping interface, forming virtual memory addresses corresponding to the transmit queue and the receive queue respectively; establishing a mapping relationship between the continuous virtual address ranges and the corresponding target verification region, forming transmit queue channels and receive queue channels corresponding to the transmit queue and the receive queue of the network card chip to be verified respectively.

[0011] Secondly, embodiments of the present invention provide a method for verifying the data plane of a chip. The method includes: responding to a power-on operation on a network interface card (NIC) chip and entering a chip startup phase; during the startup phase of the NIC chip, obtaining context information corresponding to the transmit queue channel and receive queue channel of the NIC chip through on-chip firmware; the context information includes the physical memory start address, physical memory size, and descriptor format corresponding to each of the transmit queue channel and receive queue channel, and the physical memory size in the context information is consistent with the memory size of the target verification area divided on the host side; the target verification area is determined by the method of any of the above embodiments; configuring the context information to the hardware module of the NIC chip, so as to establish a transmit queue channel and a receive queue channel with the host side by accessing the target verification area corresponding to the host side, thereby performing data plane path verification of the NIC chip.

[0012] Thirdly, embodiments of the present invention provide a chip data plane verification apparatus, the apparatus comprising: a data acquisition module, configured to acquire context information of a pre-configured transmit queue and receive queue in the network interface card (NIC) chip to be verified; the context includes the physical memory start address, memory size, and descriptor format corresponding to the transmit queue and receive queue; a region determination module, configured to divide a target verification region from the currently configured system memory based on the physical memory start address and memory size of the context information; a channel establishment module, configured to convert the target verification region into a virtual memory address in response to NIC driver initialization, so as to establish a transmit queue channel and a receive queue channel corresponding to the NIC chip to be verified; and an execution module, configured to perform data plane path verification on the NIC chip to be verified through the transmit queue channel and the receive queue channel.

[0013] Fourthly, embodiments of the present invention provide a chip data plane verification device, the device comprising: a startup module, configured to respond to a power-on operation on a network interface card (NIC) chip and enter a chip startup phase; an information acquisition module, configured to acquire context information corresponding to the transmit queue channel and receive queue channel of the NIC chip through on-chip firmware during the startup phase of the NIC chip; the context information includes the physical memory start address, physical memory size, and descriptor format corresponding to each of the transmit queue channel and receive queue channel, and the physical memory size in the context information is consistent with the memory size of the target verification area divided on the host side; the target verification area is determined by the method of any of the above embodiments; and a configuration module, configured to configure the context information to the hardware module of the NIC chip, so as to establish a transmit queue channel and a receive queue channel with the host side by accessing the target verification area corresponding to the host side, thereby performing data plane path verification of the NIC chip.

[0014] Fifthly, embodiments of the present invention provide an electronic device, which includes a processor and a memory. The memory stores machine-executable instructions that can be executed by the processor, and the processor executes the machine-executable instructions to implement the chip data plane verification method of any of the above embodiments.

[0015] The embodiments of this invention bring the following beneficial effects: These embodiments provide a method, apparatus, and electronic device for verifying the data plane of a chip. Based on the context information of the transmit and receive queues corresponding to the network interface card (NIC) chip to be verified, a target verification region is divided from system memory. This target verification region is then converted into virtual memory addresses to establish corresponding queue channels, and finally, the data plane path is verified through these channels. This completely eliminates the blocking problem of data plane verification due to incomplete control plane debugging in existing technologies, enabling parallel verification of the control plane and data plane, significantly shortening the overall chip verification cycle. Simultaneously, by dividing the target verification region based on reserved memory, physical memory address attributes (such as alignment requirements and contiguous size) can be flexibly specified, unaffected by dynamic memory allocation by the operating system, ensuring the stability and convenience of data plane verification. Furthermore, only simple modifications to the driver software and chip are required, without affecting other modules of the NIC or the existing data path verification process.

[0016] Other features and advantages of the invention will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the module distribution involved in network interface card chip data path verification provided in an embodiment of the present invention;

[0020] Figure 2 A flowchart illustrating a chip data plane verification method provided in an embodiment of the present invention;

[0021] Figure 3 A flowchart of another chip data plane verification method provided in an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of a verification principle provided in an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of a chip data plane verification device provided in an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0027] The data exchange channels between the network interface card (NIC) chip and the host are divided into two categories: control plane and data plane. 1. Control plane channels include mailbox and CMDQ, used for transmitting control messages between the driver and the NIC. a. Mailbox channel: Implemented based on PCIe BAR space registers, the driver sends control commands to the NIC by writing to the registers; this is a low-speed control channel suitable for transmitting short messages. b. CMDQ channel: Exists in a memory area on the host side; the driver and NIC interact via DMA to control message content; this is a high-speed control channel suitable for transmitting large amounts of data. 2. Data plane channels include SQ and RQ, used for transmitting information needed for sending and receiving data packets between the driver and the NIC. a. SQ: Send queue, exists in a memory area on the host side; the driver and NIC interact via DMA to send packet attribute information; this is a high-speed data sending channel. b. RQ: Receive queue, exists in a memory area on the host side; the driver and NIC interact via DMA to receive packet attribute information; this is a high-speed data receiving channel. The module distribution involved in NIC chip data path verification is as follows: Figure 1 As shown.

[0028] The establishment of the SQ / RQ channel required for network card data transmission and reception relies on the normal operation of the CMDQ channel, which in turn depends on the normal operation of the mailbox channel. CMDQ involves numerous chip hardware modules, making its implementation relatively complex and requiring a lengthy verification cycle. Therefore, a method is needed to verify the SQ / RQ channel without relying on CMDQ, thereby shortening the overall chip verification time.

[0029] This invention provides a method, apparatus, and electronic device for verifying the data plane of a chip, which overcomes the problem of data plane verification being blocked when the control plane is not fully debugged in the prior art, and realizes parallel verification of the control plane and data plane, significantly shortening the overall chip verification cycle.

[0030] To facilitate understanding, a chip data plane verification method provided in an embodiment of the present invention will be described first. Figure 2 A flowchart of an embodiment of the present invention is shown, with reference to Figure 2 The method includes the following steps:

[0031] Step S102: Obtain the context information of the pre-configured transmit queue and receive queue in the network card chip to be verified.

[0032] After the network interface card (NIC) chip to be verified is powered on, the host side accesses the chip's hardware configuration interface (such as the PCIe BAR space register) to read the context information (CTX) of the transmit queue (SQ) and receive queue (RQ) pre-stored in the chip. The context information includes the physical memory start address, memory size, and descriptor format corresponding to the SQ, as well as the physical memory start address, memory size, and descriptor format corresponding to the RQ. Among them, the descriptor format defines the data structure of the transmit queue element (SQE) of the SQ and the complete queue element (CQE) of the RQ, including the number of bits in the address field, the position of the length field, and the status bit identifier.

[0033] Step S104: Based on the physical memory start address and memory size of the context information, divide the target verification area from the currently configured system memory.

[0034] In existing technologies, the SQ / RQ configuration of a chip needs to be issued through the control plane (mailbox / CMDQ). If the control plane is not fully debugged, it will block data plane verification. This invention divides the target verification region corresponding to the aforementioned context information from the currently configured system memory, without requiring the control plane to participate in address configuration, thus enabling the determination of memory regions without a control plane.

[0035] Step S106: In response to the network card driver initialization, the target verification area is converted into a virtual memory address to establish a transmit queue channel and a receive queue channel corresponding to the network card chip to be verified.

[0036] Step S108: Perform data plane path verification on the network interface card chip to be verified through the transmit queue channel and the receive queue channel.

[0037] The target verification region is the corresponding physical memory region on the host side, while the network card driver runs in the operating system kernel's virtual address space. This embodiment of the invention establishes a virtual address-physical address mapping by responding to driver initialization address translation. This allows the driver to indirectly access physical memory through virtual addresses, while the chip can directly access the same physical memory via DMA, providing a unified interface for data interaction and resolving the incompatibility issue between their address spaces. Compared to existing technologies, this embodiment of the invention can directly translate the target verification region address through a kernel memory mapping interface (such as ioremap) during the driver initialization phase, without requiring any configuration from the control plane. After mapping, the driver and chip can achieve data transmission and reception based on the virtual address-physical address mapping, directly establishing a transmit / receive channel independent of the control plane, achieving the goal of parallel verification of the control plane and data plane.

[0038] During address translation, independent, contiguous virtual address ranges are allocated to the physical memory regions of SQ and RQ, and the two virtual address ranges do not overlap. Simultaneously, this target verification region is the exclusive memory for the current verification and does not participate in the system's regular memory allocation. This design of independent virtual addresses and exclusive physical memory avoids mutual interference between SQ and RQ data interactions and prevents data loss or tampering caused by other system processes occupying memory, ensuring the independence and security of channel data transmission.

[0039] In summary, this invention, based on the context information of the transmit and receive queues corresponding to the network interface card (NIC) chip to be verified, divides the target verification region from system memory, then converts the target verification region into virtual memory addresses to establish corresponding queue channels, and finally verifies the data plane path through the channels. This completely eliminates the blocking problem of data plane verification caused by the control plane not being fully debugged in existing technologies, enabling parallel verification of the control plane and data plane, significantly shortening the overall chip verification cycle. Furthermore, by dividing the target verification region based on reserved memory, physical memory address attributes (such as alignment requirements and contiguous size) can be flexibly specified, unaffected by dynamic memory allocation by the operating system, ensuring the stability and convenience of data plane verification. Moreover, only simple modifications to the driver software and chip are required, without affecting other modules of the NIC or the existing data path verification process.

[0040] Furthermore, based on the above embodiments, this invention also provides another method for verifying the chip data plane. Figure 3 A flowchart of an embodiment of the present invention is shown, with reference to Figure 3 The method includes the following steps:

[0041] Step S202: Obtain the context information of the pre-configured transmit queue and receive queue in the network card chip to be verified.

[0042] Step S204: Based on the physical memory start address and memory size of the context information, divide the target verification region from the currently configured system memory.

[0043] During the operation of the host operating system, the currently configured memory information is read by calling the interface provided by the operating system kernel memory management module (such as parsing the contents of the / proc / iomem file in Linux, or calling the kernel-mode memory query function). In this embodiment of the invention, a dedicated physical memory region is pre-configured, and the information of this dedicated physical memory region includes the physical starting address range of the corresponding physical memory region, the total memory size, and the remaining available space.

[0044] In practical implementation, the system address space partitioning of the operating system can be obtained, and a contiguous memory region can be determined from the system address space partitioning; based on the starting address and address length of the contiguous memory region, boot parameters can be generated; based on the boot parameters, the boot configuration of the operating system can be updated to reserve the contiguous memory region and generate an exclusive physical memory region.

[0045] Furthermore, the aforementioned target contiguous memory region is determined based on the attributes of memory segments, such as allocated (occupied by system processes or hardware), reserved (reserved by the system for specific hardware functions), or free (unoccupied and available for allocation). The overall layout information of the system address space can be obtained by calling the memory information query interface provided by the operating system kernel. This layout information includes the start and end addresses of each memory segment in the system address space, as well as the attributes of the memory segments, including allocated, reserved, or free attributes. The layout information of the system address space is traversed to filter out all memory segments with free attributes. These filtered free memory segments are then analyzed to determine contiguous memory segments, which are then identified as the target contiguous memory region.

[0046] This invention revolves around pre-planning and system reservation, locking in a dedicated memory region during the operating system startup phase. Specifically, on the host side, tools provided by the operating system (such as the `sudo cat / proc / iomem` command in Linux) are used to examine the system address space partitioning. From the results, a contiguous System RAM memory region is selected, ensuring that its address space is contiguous and unoccupied by other processes, satisfying the memory continuity requirements of the send queue (SQ) and receive queue (RQ). Further, the physical starting address and memory size of the selected contiguous memory region are extracted, and boot parameters are generated according to the format supported by the operating system. Further, the operating system's boot configuration file (such as ` / etc / default / grub` in Linux) is modified, adding the generated boot parameters to the kernel boot entries. After executing commands such as `update-grub` to update the configuration, the system is restarted. This allows the operating system to recognize and mark this region as reserved during startup, preventing it from participating in regular memory allocation, ultimately generating an exclusive physical memory region. In this embodiment of the invention, the currently dedicated physical memory region does not participate in the operating system's dynamic memory allocation (such as kmalloc, vmalloc), which prevents other processes from occupying or tampering with the memory in this region. This ensures that the descriptor buffer (storing SQE) and transmit data buffer of SQ, as well as the descriptor buffer (storing CQE) and receive data buffer of RQ, are independent and secure, preventing problems such as packet overwriting and descriptor loss during the verification process. This region provides dedicated memory space for the interaction between the network card chip to be verified and the host driver. The chip can directly access the physical memory in this region through DMA, and the driver can access this region through virtual address mapping. Both can achieve data packet transmission and reception without relying on the control plane (mailbox / CMDQ) to issue memory configuration.

[0047] Furthermore, in this embodiment of the invention, address range and space size verification are performed based on the context information of the sending queue and receiving queue. It is determined that the physical memory starting addresses of both the SQ and RQ are within the physical starting address range of the exclusive physical memory region, and the sum of the memory sizes of the SQ and RQ is less than or equal to the remaining available space size of the exclusive physical memory region. If the verification passes, a corresponding verification sub-region is defined. The addresses of the SQ verification sub-region and the RQ verification sub-region do not overlap, and together they constitute the target verification region required for the data plane verification of the network interface card chip to be verified, providing an independent memory carrier for subsequent address mapping and data interaction.

[0048] Step S206: In response to the network card driver initialization, the memory mapping interface provided by the operating system kernel is called, and the physical memory start address and memory size of the target verification region are passed to the memory mapping interface.

[0049] Step S208: Through the memory mapping interface, independent and continuous virtual address ranges are allocated in the kernel virtual address space of the operating system for the send queue and the receive queue respectively, forming virtual memory addresses corresponding to the send queue and the receive queue respectively.

[0050] After the network card driver corresponding to the network card chip to be verified is loaded by the operating system, the driver enters the initialization phase. At this time, in response to the initialization process, the memory mapping interface provided by the operating system kernel (such as the ioremap function in Linux) is called. Two core parameters are passed to this memory mapping interface: one is the physical memory start address and memory size corresponding to the send queue (SQ) in the target verification region; the other is the physical memory start address and memory size corresponding to the receive queue (RQ) in the target verification region. Among them, the target verification region is a physical memory region dedicated to SQ and RQ, which is divided from the above-mentioned exclusive physical memory region, and its address and size parameters have been verified and matched. After receiving the parameters, the operating system kernel's memory mapping interface performs address allocation in the virtual address space: allocating two non-overlapping continuous virtual address ranges for the physical memory regions of SQ and RQ respectively. During the allocation process, the kernel ensures the continuity and integrity of the virtual address range to meet the address continuity requirements when the driver accesses physical memory through virtual addresses. After the allocation is completed, the kernel forms the virtual memory address (starting address + address range) corresponding to SQ and the virtual memory address (starting address + address range) corresponding to RQ, and returns these two sets of virtual address information to the network card driver.

[0051] Step S210: Establish a mapping relationship between continuous virtual address ranges and corresponding target verification areas, forming the transmit queue channel and receive queue channel corresponding to the transmit queue and receive queue of the network card chip to be verified, respectively.

[0052] After allocating virtual address ranges, the memory mapping interface further establishes a one-to-one mapping relationship between SQ virtual address ranges and SQ physical memory regions, and between RQ virtual address ranges and RQ physical memory regions. This mapping relationship is recorded in the operating system kernel's page table to ensure that the driver can accurately translate virtual addresses into corresponding physical addresses. After the mapping relationship is established, the network card driver can read and write SQ physical memory through SQ virtual addresses (e.g., writing to SQE, reading transmission status), and the network card chip to be verified can access SQ / RQ physical memory through DMA technology (e.g., reading SQE, writing to CQE, and receiving packets). At this point, the driver-physical memory-chip transmit queue channel (based on SQ mapping) and receive queue channel (based on RQ mapping) are formally formed, and the channel establishment is completely independent of the control plane. In summary, Figure 4 A schematic diagram illustrating the verification principle of an embodiment of the present invention is shown.

[0053] Step S212: Perform data plane path verification on the network interface card chip to be verified through the transmit queue channel and the receive queue channel.

[0054] In the specific implementation, for the verification of the sending queue channel: The host side starts a packet sending and receiving test application, generates a data packet to be verified, and sends the packet to the network card driver corresponding to the network card chip to be verified via the TCP / IP protocol stack; After parsing the data packet to be verified, the network card driver constructs a sending queue element (SQE) according to the pre-configured sending queue (SQ) descriptor format (including address field, length field, status bits, etc.). The SQE contains the virtual address of the data packet to be verified in the SQ target verification area (an SQ sub-area divided in the exclusive physical memory area) and the packet length. The network card driver writes the constructed SQE into the descriptor buffer of the SQ target verification area through the virtual memory address corresponding to the sending queue channel, and at the same time writes the data packet to be verified into the data buffer of the SQ target verification area; The network card chip to be verified reads the SQE in the descriptor buffer of the SQ target verification area through DMA technology, parses out the physical address of the data packet to be verified, and then obtains the data packet to be verified from the data buffer of the SQ target verification area. After the network card chip to be verified performs hardware processing on the acquired data packet to be verified (such as adding an Ethernet frame header), it sends the data packet through its own network port. The network card driver monitors the status bits (such as "send complete flag") of the SQ descriptor through the virtual memory address corresponding to the send queue channel. If the status bits show that the packet has been read normally by the chip and there are no sending errors, it is determined that the send queue channel verification is successful.

[0055] For receive queue channel verification: The network interface card (NIC) chip to be verified receives externally input verification data packets through the network port. After parsing the verification data packets, the chip constructs a complete queue element (CQE) according to the pre-configured receive queue (RQ) descriptor format. The CQE contains the virtual address of the verification data packet in the RQ target verification region (an RQ sub-region divided within the exclusive physical memory region), the packet length, and the reception status (e.g., "data complete"). The NIC chip to be verified uses DMA technology to write the received verification data packets into the data buffer of the RQ target verification region, and simultaneously writes the constructed CQE into the descriptor buffer of the RQ target verification region. The NIC driver polls the descriptor buffer of the RQ target verification region through the virtual memory address corresponding to the receive queue channel, reads the CQE, parses out the virtual address and data length of the verification data packets, and then retrieves the verification data packets from the data buffer of the RQ target verification region. The network interface card (NIC) driver uploads the acquired verification data packets to the packet transceiver test application via the TCP / IP protocol stack. The packet transceiver test application compares the sent verification data packets with the received verification data packets. If the content is consistent, there are no packet losses or errors, and the NIC driver detects that the "receive completion flag" of the RQ descriptor is normal, then the receive queue channel verification is considered successful. Specifically, if both the send and receive queue channels pass verification, it indicates that the data plane path (including SQ / RQ channels, DMA interaction, and network interface transceiver) of the NIC chip under verification is working normally, and the data plane path verification is considered successful. If any channel verification fails (e.g., packet loss, descriptor parsing error, abnormal status bits), then an anomaly is found in the data plane path, and the hardware logic or driver configuration of the NIC chip under verification needs to be located.

[0056] Corresponding to the above Figure 2 This invention also provides a chip data plane verification device. Figure 5 A schematic diagram of an embodiment of the present invention is shown, with reference to... Figure 5 The device includes: a data acquisition module 100, used to acquire context information of pre-configured transmit and receive queues in the network interface card (NIC) chip to be verified; the context includes the physical memory start address, memory size, and descriptor format corresponding to the transmit and receive queues; a region determination module 200, used to divide the target verification region from the currently configured system memory based on the physical memory start address and memory size of the context information; a channel establishment module 300, used to convert the target verification region into a virtual memory address in response to NIC driver initialization, so as to establish transmit queue channels and receive queue channels corresponding to the NIC chip to be verified; and an execution module 400, used to perform data plane path verification on the NIC chip to be verified through the transmit queue channels and receive queue channels. The chip data plane verification device provided in this embodiment of the invention has the same implementation principle and technical effects as described above. Figure 2 ,3 The method embodiments shown are the same. For the sake of brevity, any parts not mentioned in the device embodiment section can be referred to the corresponding content in the foregoing method embodiments.

[0057] Furthermore, this embodiment of the invention also provides a verification method for the data plane of a chip, which is described in detail for a verification method corresponding to a network interface card (NIC) chip. Corresponding to the above embodiment, the method includes the following steps:

[0058] Step S10: Respond to the power-on operation for the network card chip and enter the chip startup stage.

[0059] When the network interface card (NIC) chip to be verified receives the power-on operation signal, it automatically triggers the initialization process and enters the chip startup stage. This stage is a preparatory step for data plane verification and does not rely on the startup instructions of the host-side control plane (such as mailbox, CMDQ), ensuring that the verification process can be started independently.

[0060] Step S20: During the startup phase of the network interface card (NIC) chip, the context information corresponding to the transmit queue channel and receive queue channel of the NIC chip is obtained through the on-chip firmware.

[0061] The context information includes the starting address, size, and descriptor format of the physical memory corresponding to each of the send queue channel and the receive queue channel, and the physical memory size in the context information is consistent with the memory size of the target verification region allocated on the host side. The target verification region is determined by the method of any of the above embodiments, and will not be described in detail here.

[0062] Step S30: Configure the context information to the hardware module of the network card chip so as to establish a transmit queue channel and a receive queue channel with the host side by accessing the corresponding target verification area on the host side, thereby performing data plane path verification of the network card chip.

[0063] After acquiring the context information, the on-chip firmware sends this information to the network interface card (NIC) chip's hardware modules (including SQ control logic, RQ control logic, and DMA controller) via the chip's internal hardware configuration interface (such as the register write path), completing the hardware module's parameter initialization. Based on the configured physical memory start address and size, the hardware module can precisely access the corresponding target verification area (SQ sub-area, RQ sub-area) on the host side through DMA technology, thereby establishing a bidirectional data interaction link between the chip and host memory. That is, a send queue channel (chip-host memory-driver) for packet transmission and a receive queue channel (driver-host memory-chip) for packet reception.

[0064] After the send queue channel and receive queue channel are established, data plane path verification can be carried out based on these two channels: the send queue channel enables the chip to read and send verification messages from the host side via the network port, and the receive queue channel enables the chip to receive and upload external verification messages from the host side. Finally, the integrity and correctness of the message transmission and reception are verified (such as no packet loss, no packet errors, and normal status bits) to determine whether the data plane path of the network card chip is normal. The entire verification process does not depend on the configuration or interaction commands of the control plane, realizing parallel verification of the control plane and the data plane.

[0065] Furthermore, the chip data plane verification method provided in this embodiment of the invention has the same implementation principle and technical effects as described above. Figure 2 , 3 The method embodiments shown are the same. For the sake of brevity, any parts of this method embodiment not mentioned can be referred to the corresponding content in the foregoing method embodiments.

[0066] Correspondingly, this embodiment of the invention also provides a chip data plane verification device, which includes: a startup module, used to respond to a power-on operation for the network interface card (NIC) chip and enter the chip startup phase; an information acquisition module, used to acquire context information corresponding to the transmit queue channel and receive queue channel of the NIC chip through the on-chip firmware during the startup phase of the NIC chip; the context information includes the physical memory start address, physical memory size and descriptor format corresponding to each of the transmit queue channel and receive queue channel, and the physical memory size in the context information is consistent with the memory size of the target verification area divided on the host side; the target verification area is determined by the method of any of the above embodiments; and a configuration module, used to configure the context information to the hardware module of the NIC chip so as to establish the transmit queue channel and receive queue channel with the host side by accessing the target verification area corresponding to the host side, thereby performing data plane path verification of the NIC chip.

[0067] Furthermore, the chip data plane verification device provided in this embodiment of the invention has the same implementation principle and technical effects as described above. Figure 2 , 3 The method embodiments shown are the same. For the sake of brevity, any parts not mentioned in the device embodiments can be referred to the corresponding content in the foregoing method embodiments.

[0068] This invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the above-described... Figures 2 to 3 The steps of any of the methods shown. Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the above-described steps. Figures 2 to 3The steps of any of the methods shown. Embodiments of the present invention also provide a structural schematic diagram of an electronic device, such as... Figure 6 The diagram shown is a structural schematic of the electronic device, which includes a processor 61 and a memory 60. The memory 60 stores computer-executable instructions that can be executed by the processor 61. The processor 61 executes the computer-executable instructions to implement the above-mentioned... Figures 2 to 3 Any of the methods shown.

[0069] exist Figure 6 In the illustrated embodiment, the electronic device further includes a bus 62 and a communication interface 63, wherein the processor 61, the communication interface 63, and the memory 60 are connected via the bus 62. The memory 60 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk drive. Communication between this system network element and at least one other network element is achieved through at least one communication interface 63 (which can be wired or wireless), using the Internet, wide area network, local area network, metropolitan area network, etc. Bus 62 can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, or an AMBA (Advanced Microcontroller Bus Architecture) bus. AMBA defines three types of buses: APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), and AXI (Advanced deXtensible Interface). Bus 62 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6The diagram uses only a single double-headed arrow, but this does not imply a single bus or a single type of bus. Processor 61 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed through integrated logic circuits in the hardware of processor 61 or through software instructions. Processor 61 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory, and the processor 61 reads information from the memory and, in conjunction with its hardware, completes the aforementioned tasks. Figures 2 to 3 Any of the methods shown.

[0070] The present invention provides a computer program product for a chip data plane verification method, apparatus, and electronic device, including a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. Specific implementations can be found in the method embodiments and will not be repeated here. Those skilled in the art will understand that, for convenience and brevity, the specific working process of the system described above can be referred to the corresponding process in the preceding method embodiments, and will not be repeated here. Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0071] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Finally, it should be noted that the above embodiments are merely specific implementations of the invention, used to illustrate the technical solutions of the invention, and not to limit it. The scope of protection of the invention is not limited thereto. Although the invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in this invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this invention, and should all be covered within the scope of protection of this invention. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A method for verifying the data plane of a chip, characterized in that, The method includes: Obtain the context information of the pre-configured transmit and receive queues in the network interface card chip to be verified; the context includes the physical memory start address, memory size, and descriptor format corresponding to the transmit and receive queues; Based on the physical memory start address and memory size of the context information, the target verification region is divided from the currently configured system memory; In response to the network card driver initialization, the target verification area is converted into a virtual memory address to establish a transmit queue channel and a receive queue channel corresponding to the network card chip to be verified. The data plane path of the network interface card chip to be verified is performed through the transmit queue channel and the receive queue channel.

2. The method according to claim 1, characterized in that, The steps of dividing the target verification region from the currently configured system memory based on the physical memory start address and the memory size of the context information include: Obtain the currently configured exclusive physical memory region information from the operating system kernel's memory management module; the exclusive physical memory region information includes the physical starting address range of the corresponding physical memory region, the total memory size, and the remaining available space size; Read the pre-configured context information of the send queue and receive queue from the network card chip to be verified, and extract the physical memory start address and memory size corresponding to the send queue, as well as the physical memory start address and memory size corresponding to the receive queue; Verify whether the physical memory start address is within the start address range of the exclusive physical memory region, and whether the memory size is within the remaining available space range of the exclusive physical memory region; If the starting address of the physical memory is within the starting address range of the exclusive physical memory region, and the memory size is within the remaining available space of the exclusive physical memory region, then the verification is successful. Starting from the physical memory start address and using the memory size as the length, target verification regions corresponding to the sending queue and the receiving queue are determined in the exclusive physical memory region.

3. The method according to claim 2, characterized in that, The method further includes: Obtain the system address space partition of the operating system, and determine a contiguous memory region from the system address space partition; Based on the starting address and address length of the contiguous memory region, boot parameters are generated; Based on the boot parameters, the boot configuration of the operating system is updated to reserve the contiguous memory region and generate an exclusive physical memory region.

4. The method according to claim 3, characterized in that, The steps of obtaining the system address space partition of the operating system and determining a contiguous memory region from the system address space partition include: The memory information query interface provided by the operating system kernel is invoked to obtain the overall layout information of the system address space; the layout information includes the start address, end address and attributes of each memory segment in the system address space, and the attributes of the memory segment include allocated attributes, reserved attributes or free status attributes; Traverse the layout information of the system address space and filter out all memory segments with free attributes; The selected free memory segments are analyzed to identify contiguous memory segments, which are then identified as the target contiguous memory region.

5. The method according to claim 3, characterized in that, The step of updating the operating system's boot configuration based on the boot parameters to reserve the contiguous memory region and generate an exclusive physical memory region includes: Locate the boot configuration file of the operating system, and add the boot parameters to the configuration line of the kernel boot entry in the boot configuration file; Reboot the operating system so that it can parse the boot parameters during the startup process and identify the contiguous memory region that needs to be reserved. The identified contiguous memory regions are marked as reserved to avoid participating in the operating system's regular memory allocation, thereby generating exclusive physical memory regions.

6. The method according to claim 1, characterized in that, The steps of responding to network card driver initialization and converting the target verification region into a virtual memory address to establish a transmit queue channel and a receive queue channel corresponding to the network card chip to be verified include: In response to the network card driver initialization, the memory mapping interface provided by the operating system kernel is called, and the physical memory start address and memory size of the target verification region are passed to the memory mapping interface; Through the memory mapping interface, independent and continuous virtual address ranges are allocated in the kernel virtual address space of the operating system for the physical memory regions of the sending queue and the receiving queue, respectively, forming virtual memory addresses corresponding to the sending queue and the receiving queue. Establish a mapping relationship between the continuous virtual address range and the corresponding target verification area to form the transmission queue channel and the reception queue corresponding to the transmission queue and the reception queue of the network card chip to be verified, respectively.

7. A method for verifying the data plane of a chip, characterized in that, The method includes: In response to the power-on operation of the network interface card (NIC) chip, the chip enters the startup phase; During the startup phase of the network interface card (NIC) chip, context information corresponding to the transmit queue channel and receive queue channel of the NIC chip is obtained through the on-chip firmware; the context information includes the physical memory start address, physical memory size and descriptor format corresponding to each of the transmit queue channel and receive queue channel, and the physical memory size in the context information is consistent with the memory size of the target verification area divided on the host side; the target verification area is determined by the method described in any one of claims 1-6; The context information is configured to the hardware module of the network interface card (NIC) chip to establish a transmit queue channel and a receive queue channel with the host side by accessing the target verification area on the host side, thereby performing data plane path verification of the NIC chip.

8. A verification device for the data plane of a chip, characterized in that, The device includes: The data acquisition module is used to acquire the context information of the pre-configured transmit queue and receive queue in the network interface card chip to be verified; the context includes the physical memory start address, memory size and descriptor format corresponding to the transmit queue and receive queue; The region determination module is used to divide the target verification region from the currently configured system memory based on the physical memory start address and the memory size of the context information; The channel establishment module is used to respond to the network card driver initialization, convert the target verification area into a virtual memory address, and establish a transmit queue channel and a receive queue channel corresponding to the network card chip to be verified. The execution module is used to perform data plane path verification on the network interface card chip to be verified through the transmit queue channel and the receive queue channel.

9. A verification device for the data plane of a chip, characterized in that, The device includes: The startup module is used to respond to the power-on operation of the network card chip and enter the chip startup stage; An information acquisition module is used to acquire context information corresponding to the transmit queue channel and receive queue channel of the network interface card (NIC) chip through on-chip firmware during the startup phase of the NIC chip; the context information includes the physical memory start address, physical memory size and descriptor format corresponding to each of the transmit queue channel and receive queue channel, and the physical memory size in the context information is consistent with the memory size of the target verification area divided on the host side; the target verification area is determined by the method described in any one of claims 1-6; The configuration module is used to configure the context information to the hardware module of the network card chip, so as to establish a transmit queue channel and a receive queue channel with the host side by accessing the target verification area corresponding to the host side, thereby performing data plane path verification of the network card chip.

10. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing machine-executable instructions that can be executed by the processor, the processor executing the machine-executable instructions to implement the chip data plane verification method according to any one of claims 1 to 7.

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