Buffer tree generation method based on graph attention network, electronic equipment and storage medium

Abstract

The invention discloses a buffer tree generation method based on a graph attention network, an electronic device and a storage medium, and the method comprises the steps: converting a buffer insertion problem in a layout stage of a digital integrated circuit into a sequence generation problem of a buffer tree, and carrying out the learning and prediction of the coding and decoding processes of a to-be-optimized sequence based on the graph attention network. And finally, optimizing the constraint as a physical design tool. According to the buffer tree generation method based on the graph attention network, the electronic equipment and the storage medium provided by the invention, the problems of overlarge buffer insertion solution space and overlong iteration time can be effectively solved, so that a designer or a tool is guided to carry out optimization, the iteration of the design is reduced, the time cost of chip design is reduced, and the efficiency of chip design is improved. The method is of great significance in accelerating the design process of a digital integrated circuit.

Description

TECHNICAL FIELD

[0001] The application relates to a buffer tree generation method based on a graph attention network, an electronic device and a storage medium, and belongs to the technical field of electronic design automation. BACKGROUND

[0002] With the continuous development of integrated circuit design and the continuous progress of process, the complexity and integration degree are further improved, which poses a challenge to the layout method in the current digital chip physical design. In the physical design stage, the EDA (Electronic Design Automation) tool needs to layout millions or even hundreds of millions of gate-level units, and through multiple iterations of optimization, the power consumption, performance and area (PPA) are optimized. The current rule-driven layout method has the problems of low solution space exploration efficiency and long timing convergence period, and the layout optimization method based on machine learning can learn from the prior circuit layout, and optimize and guide according to the prediction result, which has been widely studied in recent years.

[0003] However, the existing layout optimization method based on machine learning does not fully consider the influence of cross-stage timing and netlist information change, which hinders its application in the physical design process, and machine learning still faces great challenges in timing prediction and optimization method. In the layout optimization stage, buffer insertion is a key interconnection line optimization technology in the timing convergence process. With the development of Moore's law, the proportion of interconnection line delay is getting higher and higher. Since the buffer unit can break the interconnection line in the layout stage, reduce the parasitic parameters, increase the driving strength of the target unit, and improve the timing characteristics, the buffer insertion algorithm and method are widely studied. The typical process of the buffer insertion optimization algorithm is based on the initial layout result, the minimum Steiner tree (SMT) is constructed according to the interconnection line RC model and the netlist, then the Steiner tree is segmented to generate the buffer tree position, finally the Ginneken-Lillis type algorithm is used to determine the buffer tree layout, and the buffer is dynamically adjusted according to the wiring topology and delay model until the timing convergence is achieved. Since the joint solution space of the buffer insertion is huge, the simulated annealing and approximate processing method are used for solving, and the running time is too long.

[0004] Therefore, the person skilled in the art needs to solve the problems of large solution space of buffer tree generation in the layout stage and long optimization iteration time. SUMMARY

[0005] Objective: In order to overcome the deficiencies in the prior art, the application provides a buffer tree generation method based on a graph attention network, an electronic device and a storage medium, which can effectively solve the problems of too large buffer tree generation solution space and too long iteration time, thereby guiding designers or tools to optimize, reducing design iterations and reducing the time cost of chip design, which is of great significance for accelerating the digital integrated circuit design process.

[0006] Technical scheme: To solve the above technical problems, the technical scheme adopted by the application is:

[0007] In a first aspect, a buffer tree generation method based on a graph attention network includes the following steps:

[0008] The circuit netlist is converted into a graph data structure with line nets as graph nodes and the connection relationship between line nets as graph edges.

[0009] According to the graph data structure, an adjacency matrix is obtained, and according to the adjacency matrix, a feature matrix is obtained.

[0010] The feature matrix is input into a physical design tool, and the obtained optimization result is used as a label to be learned.

[0011] The adjacency matrix, the feature matrix and the label to be learned are used as a sample data set.

[0012] The sample data set is used to train a buffer insertion model to obtain a trained buffer insertion model.

[0013] The input netlist of the circuit to be optimized and the extracted features are input into the trained buffer insertion model to obtain a buffer prediction value.

[0014] The buffer prediction value is encoded and decoded according to the width of each fanout tree and a preset insertion order to obtain a sequence matrix of buffer size and position.

[0015] Optionally, it also includes: using the sequence matrix of buffer size and position as optimization guide information to generate an optimization constraint script that can be recognized by a physical design tool, and finally inputting into the physical design tool for detailed layout.

[0016] Optionally, the feature matrix obtained according to the adjacency matrix specifically includes:

[0017] According to the adjacency matrix, the extracted features of the center network itself and the extracted features of the neighbor network of the center network are obtained, and the extracted features of the center network itself and the extracted features of the neighbor network of the center network are used as the feature matrix.

[0018] Optionally, the buffer insertion model includes an embedding layer, a GNN layer and a fully connected layer.

[0019] The GNN layer includes a plurality of GAT layers connected in series.

[0020] Optionally, the GNN layer includes three GAT layers connected in series.

[0021] Optionally, the extracted features include timing margin, pin rise transition time, pin fall transition time, pin worst transition time, worst delay in each timing arc of the cell, worst delay in the timing arc of the line network, fan-in and fan-out number, total area of the cell, total capacitance of the pin, total resistance of the pin, coordinate values of the cell in the x-axis and y-axis, and maximum Manhattan distance between the cell and the driving cell.

[0022] Optionally, the encoding and decoding of the buffer prediction value according to the width of each fan-out tree and the preset insertion order obtain a sequence matrix of buffer size and position, and specifically include

[0023] The buffer tree is encoded into an FxS matrix according to the width of each fan-out tree and the preset insertion order, where F is the number of load cells, and S is the maximum buffer order.

[0024] The FxS matrix is restored into a buffer tree, and redundant buffers with similar positions are deleted to obtain a sequence matrix of buffer size and position.

[0025] Optionally, the deleting of the redundant buffers with similar positions specifically includes

[0026] All adjacent buffer pairs in the same driving level in the buffer tree are traversed.

[0027] The minimum physical distance D_min determined by the process library file is used as a threshold.

[0028] The Manhattan distance between adjacent buffers is calculated, and when a pair of adjacent buffers not only have the same type but also have a Manhattan distance less than the threshold, one of the buffers is determined as a redundant cell and is marked.

[0029] The number of all unmarked buffers in each layer is counted, and when the number of effective buffers exceeds half of the total number of buffers in the layer, all buffers marked as redundant cells in the layer are removed from the buffer tree topology to obtain an optimized sequence matrix of buffer size and position.

[0030] In a second aspect, a computer readable storage medium has a computer program stored thereon, and the computer program is executed by a processor to implement the buffer tree generation method based on the graph attention network according to any one of the first aspect.

[0031] In a third aspect, a computer device includes

[0032] a memory for storing instructions.

[0033] a processor for executing the instructions to cause the computer device to perform operations of the method for buffer tree generation based on graph attention networks according to any one of the first aspect.

[0034] Beneficial effects: the method for buffer tree generation based on graph attention networks, the electronic device and the storage medium provided by the application convert the buffer insertion problem in the digital integrated circuit layout stage into the sequence generation problem of the buffer tree, and learn and predict the encoding and decoding process of the to-be-optimized sequence based on the graph attention network (GAT), finally serve as the optimization constraint of the embedded physical design tool. The application can effectively solve the problems of too large buffer insertion solution space and too long iteration time, thereby guiding the designer or the tool to optimize, reducing the iteration of the design, reducing the time cost of the chip design, and having important significance for accelerating the digital integrated circuit design process. BRIEF DESCRIPTION OF DRAWINGS

[0035] Figure 1 FIG. 1 is a flowchart of the method for buffer tree generation based on graph attention networks according to the application.

[0036] Figure 2 FIG. 2 is a schematic diagram of the process of converting the circuit netlist into a graph data structure, wherein, Figure 2 (a) in the figure is a first circuit to be converted, Figure 2 (b) in the figure is a graph representation structure of the first circuit taking the unit as a node, Figure 2 (c) in the figure is an adjacency matrix of the first circuit taking the unit as a node, Figure 2 (d) in the figure is a second circuit to be converted, Figure 2 (e) in the figure is a graph representation method of the second circuit taking the line net as a node, Figure 2 (f) in the figure is an adjacency matrix of the second circuit taking the line net as a node.

[0037] Figure 3 FIG. 3 is a schematic diagram of the encoding and decoding process of the buffer insertion model. Wherein, Figure 3 (a) in the figure is an example circuit in which the buffer has been inserted, Figure 3 (b) in the figure is the buffer array converted from the example circuit, Figure 3 (c) in the figure is the buffer size matrix abstracted from the buffer array, Figure 3 (d) in the figure is the circuit decoded from the buffer size array.

[0038] Figure 4 FIG. 4 is a schematic diagram of the implementation process of the GAT (graph attention neural network) layer, wherein, Figure 4 (a) in the figure is a schematic diagram of the attention coefficient calculation structure,Figure 4 Fig. 6 is a schematic diagram of a feature-weighted aggregation structure. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by a person skilled in the art without creative work fall within the protection scope of the present application.

[0040] The present application will be further described below with reference to specific embodiments.

[0041] Embodiment 1

[0042] This embodiment introduces a buffer tree generation method based on a graph attention network. The buffer insertion problem in the layout stage of a digital integrated circuit is converted into a sequence generation problem of a buffer tree, and the encoding and decoding processes of the to-be-optimized sequence are learned and predicted based on a graph attention network. As shown in Figure 1 The method comprises the following steps:

[0043] Step S1: Obtain a circuit netlist, and convert the mutual connection between line nets in the circuit netlist into a graph data structure. As shown in Figure 2 (a)- Figure 2 According to the graph data structure, an adjacency matrix is obtained, the features of the center network itself and the features of the neighbor network of the center network are obtained according to the adjacency matrix, the features of the center network itself and the features of the neighbor network of the center network are taken as a feature matrix, and a series of feature values of the circuit are extracted from a technology file (Technology File, TF) in a process design kit (Process Design Kits, PDK) and a circuit netlist, a circuit layout and a timing report file generated in a target circuit design process, as initial information input into a buffer insertion model.

[0044] The extracted feature values need to fully include overall circuit information. The features of a sub-circuit can be divided into timing-related features and physical information-related features.

[0045] The timing features include but are not limited to rising and falling timing margins, rising and falling transition times, worst transition time, and cell worst delay; the physical features include functional type, driving strength, fan-in and fan-out, cell area, input and output total capacitance, and input and output total resistance.

[0046] The circuit optimization result given by the physical design tool is taken as a label to be learned, and the adjacency matrix, the feature matrix and the label to be learned are taken as a sample data set.

[0047] The label to be learned maps the driving strength of the cell after layout optimization, i.e., the gate size, into a label value, and the label value of the buffer prediction task includes a buffer type and a position label, wherein the position label is an x / y-axis coordinate.

[0048] Step S2: The sample data set is divided into training set data and test set data, the training set data is used for buffer insertion model training to obtain a trained buffer insertion model, the test set data is used to verify the prediction accuracy and efficiency of the trained buffer insertion model, and the trained buffer insertion model is adjusted according to the verification result to obtain an adjusted buffer insertion model.

[0049] The buffer insertion model includes an embedding layer, a GNN layer and a full connection layer.

[0050] The input of the full connection layer includes the embedding vector of the current stage and the embedding vector of the previous stage.

[0051] Step S3: The input netlist of the circuit to be optimized and the extracted features are input into the trained buffer insertion model or the adjusted buffer insertion model to obtain a buffer prediction value, the buffer prediction value is encoded and decoded according to the width of each fanout tree and a preset insertion stage number to obtain a sequence matrix of buffer size and position.

[0052] Step S4: The sequence matrix of buffer size and position is taken as optimization guide information to generate an optimization constraint script that can be recognized by the physical design tool, and finally sent to the physical design tool for detailed layout.

[0053] Further, in the step S1, the application takes the pin timing slack of the circuit before layout optimization as the initial feature, and the timing slack is the most important indicator of circuit performance, which can reflect the degree of violation of the local circuit before layout optimization. The higher the degree of violation, the more likely the local circuit is to be optimized and adjusted. In the standard cell delay calculation of static timing analysis, the transition time of the input pin and the output load are usually interpolated to calculate the cell delay, and the cell delay has a nonlinear relationship with the transition time. Selecting the rising and falling of the pin and the worst transition time feature can reflect the timing characteristics. According to the timing report, the worst delay of each timing arc of the cell and the worst delay of the wire timing arc are extracted as features. The clock period of the circuit, which is one of the most important features of the circuit, directly affects the performance of the circuit. The higher the clock frequency, the faster the data processing and propagation speed of the target circuit. Secondly, in the standard cell library, there are standard cells with different functions that together form a digital chip capable of processing complex information, and each type of function has multiple drive strengths. Strong drive strength often has higher load capacity and better timing characteristics, but at the cost of increased area and power consumption. The variety of cell types and drive strengths has a great impact on circuit performance, so the application extracts the cell function type and drive strength of the initial netlist, where the function type of the cell is represented by one-hot encoding. The number of fan-in and fan-out is selected as the initial feature, which reflects the number of driving cells and the load capacity of the cell. The total area of the cell and the total capacitance and total resistance of the pin are also selected as features. Finally, the x and y coordinates of the cell and the maximum Manhattan distance between the target cell and its driving cells are selected as features. The former reflects the position of each standard cell after global layout, including shape, density, and congestion information; the latter contains the distance between the pins of the network, and a longer distance usually means larger resistance and capacitance parasitic parameters and larger line delay.

[0054] Further, in the step S2, the label of the buffer prediction task includes the buffer type and the position label, where the position label is the x / y axis coordinate. As shown in Figure 3 , the type label generation process of the circuit after layout optimization is explained, Figure 3 In (a) of the layout optimization process before the circuit, it includes a NAND gate A as a driving cell, and three other cells B, C, and D as loads. The buffers introduced in the logic synthesis and layout process are removed in advance, and only standard cells and timing cells with logical functions are retained. This is because the idealized routing model such as the wire load model and the inaccurate estimated parasitic parameters at the early stage of design will cause inaccurate timing estimation, thereby increasing the calculation overhead and the number of iterations. Figure 3The middle (b) is a sub-circuit after layout optimization, in order to achieve the balance of PPA and timing convergence, five buffers are inserted to form a maximum three-level buffer tree, wherein 8X, 4X and 1X represent the driving strength of the buffer respectively. Figure 3 The middle (c) and (d) are the generation process of the label corresponding to the wire net from unit A to unit B. According to the driving strength of the buffer, the vector from unit A to unit B is constructed in this example, and the label value of A to B is constructed. The vector value of A to C is constructed in this example, and the label value of A to C is obtained. [ 8 , 8 , 0 ] The vector value of A to D is constructed in this example, and the label value of A to D is obtained. [ 8 , 1 , 0 ] The label value of A to D is constructed in this example, and the label value of A to D is obtained. [[ 8 , 4 , 1 ],[ 8 , 8 , 0 ],[ 8 , 1 , 0 ]] The three-dimensional label matrix of A to D is finally generated for a single wire net. The buffer position label generation process after layout optimization is similar to the type label generation process, and the multi-dimensional label matrix of each buffer x and y axis coordinate is finally generated for a single wire net.

[0055] In order to achieve better timing optimization effect and experimental persuasion, four different sizes of buffers (buffer) and four different sizes of inverters (inverter) are selected as the optimization unit of the buffer insertion process in this example, each size and type corresponds to the value in the label vector, that is, a classification result predicted by the model. At this time, this paper obtains the graph representation method, feature information and label feature value corresponding to each wire net, which can be used for buffer insertion model.

[0056] Further, the buffer insertion model is composed of embedding layer, GNN layer and full connection layer, in order to realize dynamic weight distribution mechanism and high-order expression ability, GAT layer is adopted for network design.

[0057] Among them, the embedding layer adopts linear projection matrix to standardize the features through vector space dimension reduction technology, generates initial feature embedding vector with node information, and serves as the benchmark input of graph message passing mechanism. The purpose is to realize the parameterized alignment of feature distribution, through data scale normalization and sparsity control, not only to provide stable tensor structure for subsequent neighborhood aggregation operation, but also to improve model convergence efficiency and suppress gradient anomaly phenomenon.

[0058] The abstract embedding vector containing all node information obtained by embedding layer is sent into the multi-layer GAT for learning. Assuming that the number of GAT model layers is M, a node prediction will depend on the features in its local M-hop neighborhood structure. Setting more network layers has stronger expression ability, extracts more meaningful high-level features, but too many layers will cause increased computational complexity, gradient disappearance problem and overfitting risk. Considering the above factors, the graph neural network module in this paper uses three GAT layers, which can aggregate information up to 3-hop neighbors and fully learn the deep relationship between nodes. Each layer of GNN in this paper is composed of the same basic module, the graph attention layer (GAT).

[0059] As shown in Figure 4 (a) and (b), a set of input node features is given, where , is the number of nodes. This part represents the number of standard cells, is the feature dimension. This layer generates a new feature set through self-attention mechanism. First, the input features are shared linearly transformed, parameterized as weight matrix , which transforms the nodes into . The attention mechanism is used to calculate the importance of node to node , which is represented by the following formula:

[0060]

[0061] where is a single-layer feedforward neural network. When only considering the first-order neighbors of node , the attention coefficient is normalized by the function:

[0062]

[0063] After multiple rounds of training, the unit size prediction solution can be obtained, and the classification result represents the candidate driving strength of each unit in the layout optimization process. Since the driving strength of each unit in the standard cell library is different, if the prediction result is in the cell library, select the prediction type as the optimization result; if the prediction result is not in the cell library, select the smaller unit size closest to the driving strength as the optimization result.

[0064] where, for the classification task of predicting buffer type, the softmax function is used as the full connection layer, and the cross entropy is still used as the loss function, for the regression task of predicting buffer position, the MLP is used as the full connection layer, and the mean squared error (MSE) is used as the loss function.

[0065] Further, the encoding represents a matrixing buffer tree encoding of the actual buffer tree, and the decoding is a reconstruction of the buffer tree structure from the predicted matrixing result, and the potential buffer insertion scheme is generated in the early design stage.

[0066] In Figure 3 In (a), the circuit is an example of a buffer tree inserted in the layout optimization process, such as Figure 3 In (b), the buffer tree is encoded as an FxS matrix, where F is the number of loaded cells, and S is the maximum number of buffer stages, and in this example, F and S are both 3. Each column in the matrix corresponds to a buffer stage, s1 is the first stage buffer inserted after cell A, s2 is the second stage buffer, and so on. The element value represents the type of buffer inserted at that level, and if there is no buffer at a certain level, it is replaced with {0X}. For example, Figure 3 In (c), the buffer tree is replaced with a matrixing method to obtain a buffer tree encoding matrix that includes information about each level. Through the cascading prediction strategy described above, the matrix result of the potential buffer type and coordinate position added in the optimization of each wire net can be obtained. In the decoding process, the final predicted matrix needs to be converted into the actual buffer tree, as shown in Figure 3 In (d), according to the matrix, the buffer type and position of each level and each wire net can be obtained.

[0067] The decoding process of the buffer is represented as restoring the buffer size or position matrix into the circuit netlist, and deleting the redundant buffers with similar positions. The steps of this optimization algorithm for redundant buffer trees are as follows: the flow of the optimization algorithm for redundant buffers mainly includes two stages: redundancy marking and heuristic pruning.

[0068] In the redundancy marking stage, the algorithm first traverses all adjacent buffer pairs in the same stage of the buffer tree. It calculates the Manhattan distance between adjacent buffers according to the minimum physical distance D_min determined by the technology file as the threshold. When a pair of adjacent buffers not only have the same type, but also have a Manhattan distance less than D_min, the algorithm determines that one of the buffers is a redundant cell, and sets its type attribute to an invalid value (such as 0) as a marker to be deleted.

[0069] Subsequently, in the heuristic pruning phase, the algorithm evaluates the removal decision of the marked buffer layer by layer. To prevent over-removal that may destroy the original fan-out structure of the buffer tree, the algorithm adopts a heuristic rule: it counts the number of all unmarked "valid" buffers in the layer. Only when the number of valid buffers exceeds half of the total number of buffers in the layer, the algorithm finally confirms to perform the deletion operation and formally removes all buffers marked as redundant in the layer from the buffer tree topology.

[0070] Through this "mark-prune" two-stage process, the algorithm can accurately locate and remove redundant buffers, and effectively optimize the buffer tree layout.

[0071] Embodiment 2:

[0072] The embodiment introduces a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, a buffer tree generation method based on a graph attention network is realized.

[0073] Embodiment 3:

[0074] A computer device comprises:

[0075] A memory for storing instructions.

[0076] A processor for executing the instructions to cause the computer device to perform the operations of a buffer tree generation method based on a graph attention network as described in any one of embodiments 1.

[0077] Embodiment 4:

[0078] In order to show the influence of the buffer tree insertion optimization process on the overall physical design, the results after routing are further evaluated. Reasonable layout results can reduce routing complexity and improve routing iteration efficiency and reliability. The optimization framework proposed in this paper can accelerate timing convergence in the early stage of layout design and minimize design rule violations after circuit layout. Compared with the default process after routing, the test set circuit in the optimization process proposed in this paper, in terms of timing, the worst negative slack (WNS), total negative slack (TNS), and violation endpoint number (#VP) indicators are optimized by an average of 12.73%, 4.56%, and 17.06%, respectively. In terms of circuit characteristics, the average wire length is reduced by 0.56%, while the leakage power is only increased by 0.36%, and the overall running time of the circuit physical design is reduced by an average of 2.56%. The overall running time is the time for the tool to perform layout and routing in a single round. In multiple rounds of optimization, it is expected to reduce the number of design iterations, speed up the design process, and reflect the application characteristics of the optimization process.

[0079] Those skilled in the art will appreciate that embodiments of the present application can be readily used as software, hardware, or a combination of software and hardware. In a software embodiment, the methods can be tangibly embodied in a machine-readable storage medium having stored thereon instructions that can be used to program a processing system to perform the methods. The machine-readable storage medium can be magnetic (e.g., magnetic disks), optical (e.g., optical discs), electrical (e.g., electrical ROM, EEPROM, etc.), magneto-optical (e.g., magneto-optical discs), semiconductor (e.g., solid state memory), etc. The instructions may, in some embodiments, be stored in the memory 110 and implemented entirely in software such that the instructions are executed by the processor(s) 112 to implement the functions described herein.

[0080] The present application is described in reference to the flowchart and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processing system or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0081] These computer program instructions can also be stored in a computer- readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instructions which implement the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks. Figure 1 one or more functions specified in the flowchart and / or block diagram block or blocks.

[0083] The above description is only preferred embodiments of the present application. It is obvious that those skilled in the art can make several improvements and refinements without departing from the principles of the present application, and these improvements and refinements should be considered as falling within the scope of the present application.

Claims

1. A method for buffer tree generation based on graph attention network, characterized in that: The method comprises the following steps: Converting the circuit netlist into a graph data structure with the net as the graph node and the connection relationship between the nets as the graph edge; Obtaining an adjacency matrix according to the graph data structure, and obtaining a feature matrix according to the adjacency matrix; Inputting the feature matrix into a layout tool, and taking the obtained optimization result as a label to be learned; Taking the adjacency matrix, the feature matrix and the label to be learned as a sample data set; Training a buffer insertion model by using the sample data set, and obtaining a trained buffer insertion model; Inputting the input netlist of the circuit to be optimized and the extracted features into the trained buffer insertion model to obtain a buffer prediction value; Encoding and decoding the buffer prediction value according to the width of each fan-out tree and a preset insertion level to obtain a sequence matrix of buffer sizes and positions.

2. The buffer tree generation method based on the graph attention network according to claim 1, characterized in that: Further comprising: Taking the sequence matrix of buffer sizes and positions as optimization guide information, and generating an optimization constraint script recognized by a physical design tool.

3. The buffer tree generation method based on graph attention network according to claim 1 or 2, characterized in that: The feature matrix is obtained according to the adjacency matrix, and specifically comprises: According to the adjacency matrix, the extraction features of the center network itself and the extraction features of the neighbor network of the center network are obtained, and the extraction features of the center network itself and the extraction features of the neighbor network of the center network are taken as the feature matrix.

4. The buffer tree generation method based on the graph attention network according to claim 1 or 2, characterized in that: The buffer insertion model comprises an embedding layer, a GNN layer and a fully connected layer. The GNN layer comprises a plurality of GAT layers connected in series.

5. The buffer tree generation method based on graph attention network according to claim 4, characterized in that: The GNN layer comprises three GAT layers connected in series.

6. The buffer tree generation method based on graph attention network according to claim 1 or 2, characterized in that: The extracted features comprise timing margin, pin rising transition time, pin falling transition time, pin worst transition time, worst delay in each timing arc of the unit, worst delay in the net timing arc, fan-in and fan-out number, total area of the unit, total capacitance of the pin, total resistance of the pin, coordinate values of the unit on the x-axis and the y-axis, and the maximum Manhattan distance between the unit and the driving unit.

7. The buffer tree generation method based on graph attention network according to claim 1 or 2, characterized in that: The sequence matrix of buffer sizes and positions is obtained by encoding and decoding the buffer prediction value according to the width of each fan-out tree and the preset insertion level, and specifically comprises The buffer tree is encoded into an F×S matrix according to the width of each fan-out tree and the preset insertion level, wherein F is the number of load units and S is the maximum buffer level; The F×S matrix is restored into a buffer tree, and redundant buffers with similar positions are deleted to obtain the sequence matrix of buffer sizes and positions.

8. The buffer tree generation method based on graph attention network according to claim 7, characterized in that: The redundant buffers with similar positions are deleted, and specifically comprise: All adjacent buffer pairs in the same driving level in the buffer tree are traversed; The minimum physical distance D_min determined by the process library file is taken as a threshold value; The Manhattan distance between adjacent buffers is calculated, and when a pair of adjacent buffers are not only completely the same in type, but also have a Manhattan distance less than the threshold value, one of the buffers is determined as a redundant unit and is marked; The number of all unmarked buffers in each layer is counted, and when the number of valid buffers exceeds half of the total number of buffers in the layer, all buffers marked as redundant units in the layer are removed from the buffer tree topology to obtain the sequence matrix of optimized buffer sizes and positions.

9. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and the computer program is executed by a processor to implement the method of claim 1 to 8.

10. A computer device, comprising: The computer program product comprises: a memory for storing instructions; a processor for executing the instructions, so that the computer device performs the operations of the method of claim 1 to 8.

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