Analysis methods, devices, electronic equipment, and storage media at the top level of digital-to-analog chips

Abstract

This application provides a method, apparatus, electronic device, and storage medium for analyzing the top layer of a digital-to-analog chip. The method includes: determining first parameter information of metal line segments connected to a third-party module in the top layer of the digital-to-analog chip based on a chip layout data file of the top layer; determining antenna risk values ​​of connection nodes between the top layer of the digital-to-analog chip and the third-party module based on the first parameter information; when the antenna risk value is higher than a preset risk threshold, converting the chip layout data file into a first diagram structure and determining second parameter information between the third-party modules based on the first diagram structure; and analyzing antenna effects occurring at connection nodes between the top layer of the digital-to-analog chip and the third-party module based on the second parameter information. This application can perform analysis of the top layer of a digital-to-analog chip without using GDSII for antenna effect analysis.

Description

Technical Field

[0001] This application belongs to the technical field of analog-digital chip analysis, specifically relating to a method, apparatus, electronic device, and storage medium for analyzing the top layer of an analog-digital chip. Background Technology

[0002] At the top layer of a digital-to-analog chip, with limited wiring resources (using four metal layers or less), especially when it contains third-party IP (Intellectual Property) modules (containing only metal layers and no GDSII (Graphic Data System II, a chip layout data file format used in electronic design automation; mainly used to store and exchange chip physical design information), antenna effects are prone to occur after IP merging at the foundry.

[0003] Among related technologies, solutions to eliminate the antenna effect include: jumper wire method and adding diode to ground method. These two methods, when not using third-party IP modules and when area is not a concern, can be iterated several times to ensure that the antenna effect violation problem of the chip can be solved when GDSII is provided to the foundry.

[0004] However, in special cases where the chip top layer uses only four or fewer metal wiring layers and contains third-party IP (containing only metal layers and no GDSII module specifically for antenna effects), the traditional method may result in antenna effects being cleaned up before IP merge, but antenna violations may be found after IP merge. This requires iterative back and forth and takes a long time, which is not conducive to the development and launch time of chip products. Summary of the Invention

[0005] In view of the above problems, a method, apparatus, electronic device, and storage medium for top-level analysis of analog-digital chips are proposed to overcome or at least partially solve the above problems, including:

[0006] A method for analyzing the top layer of a digital-to-analog chip, the method comprising:

[0007] Based on the chip layout data file of the top layer of the digital-analog chip, determine the first parameter information of the metal line segments that are connected to the third-party module at the top layer of the digital-analog chip;

[0008] Based on the first parameter information, determine the antenna risk value of the connection node between the digital-analog chip and the third-party module in the top layer of the digital-analog chip;

[0009] When the antenna risk value is higher than a preset risk threshold, the chip layout data file is converted into a first diagram structure, and the second parameter information between the third-party modules is determined based on the first diagram structure.

[0010] Based on the second parameter information, an analysis is performed on the antenna effect occurring at the connection node between the digital-analog chip and the third-party module in the top layer.

[0011] Optionally, the first parameter information includes the length, width, number of vias, and connection status of the metal line segment; determining the antenna risk value of the connection node with the third-party module in the top layer of the digital-analog chip based on the first parameter information includes:

[0012] Determine the weighting coefficients;

[0013] The antenna risk value is determined based on the weighting coefficient, as well as the length information, width information, number of through holes, and connection status.

[0014] Optionally, determining the weighting coefficients includes:

[0015] Determine the number of metal layers in the top layer of the digital-to-analog chip;

[0016] The weighting coefficient is determined based on the number of metal layers.

[0017] Optionally, the weighting coefficients include: a first weighting coefficient for length information, a second weighting coefficient for width information, a third weighting coefficient for the number of through holes, and a fourth weighting coefficient for connection status;

[0018] The sum of the first weighting coefficient, the second weighting coefficient, and the third weighting coefficient is zero.

[0019] Optionally, the method further includes:

[0020] When the antenna risk value is not higher than the preset risk threshold, it is determined that there is no antenna effect in the connection node between the digital-analog chip top layer and the third-party module.

[0021] Optionally, the step of analyzing the antenna effect at the connection node between the digital-analog chip and the third-party module in the top layer of the digital-analog chip based on the second parameter information includes:

[0022] The second parameter information is input into a preset prediction model to obtain the first probability that the connection node between the digital-analog chip and the third-party module will have an antenna effect.

[0023] The prediction model is obtained by training on the parameter information between third-party modules corresponding to multiple digital-analog chips, as well as the probability of antenna effect occurring at the connection nodes in each digital-analog chip.

[0024] Optionally, the second parameter information includes at least one of the following:

[0025] Pin area between third-party modules, distance between third-party modules, width of connection between third-party modules, and length of connection between third-party modules.

[0026] Optionally, the method further includes:

[0027] When the first probability exceeds the probability threshold, the digital-to-analog chip is jumpered.

[0028] The chip layout data file after jumper processing is converted into a second diagram structure, and the third parameter information between the third-party modules is determined based on the second diagram structure.

[0029] Based on the third parameter information, a second probability of antenna effect occurring in the connection node between the digital-analog chip and the third-party module after jumper processing is determined.

[0030] Optionally, the method further includes:

[0031] When the second probability exceeds the probability threshold, a diode is added to the analog-digital chip;

[0032] The chip layout data file with added diodes is converted into a third diagram structure, and the fourth parameter information between the third-party modules is determined based on the third diagram structure.

[0033] Based on the fourth parameter information, the third probability of antenna effect occurring at the connection node between the digital-to-analog chip and the third-party module after the addition of the diode is determined.

[0034] This application also provides an analysis device for the top layer of a digital-to-analog chip, the device comprising:

[0035] The first determining module is used to determine the first parameter information of the metal line segments that are connected to the third-party module on the top layer of the digital-analog chip, based on the chip layout data file of the top layer of the digital-analog chip.

[0036] The second determining module is used to determine the antenna risk value of the connection node with the third-party module in the top layer of the digital-analog chip based on the first parameter information.

[0037] The third determining module is used to convert the chip layout data file into a first diagram structure when the antenna risk value is higher than a preset risk threshold, and to determine the second parameter information between the third-party modules based on the first diagram structure.

[0038] The analysis module is used to analyze the antenna effect occurring at the connection node between the digital-analog chip and the third-party module in the top layer of the digital-analog chip, based on the second parameter information.

[0039] Optionally, the first parameter information includes the length, width, number of through holes, and connection status of the metal wire segment; the second determining module is used to determine a weighting coefficient; and to determine the antenna risk value based on the weighting coefficient, the length, width, number of through holes, and connection status.

[0040] Optionally, the second determining module is used to determine the number of metal layers in the top layer of the digital-to-analog chip; and to determine the weighting coefficient based on the number of metal layers.

[0041] Optionally, the weighting coefficients include: a first weighting coefficient for length information, a second weighting coefficient for width information, a third weighting coefficient for the number of through holes, and a fourth weighting coefficient for connection status;

[0042] The sum of the first weighting coefficient, the second weighting coefficient, and the third weighting coefficient is zero.

[0043] Optionally, the analysis module is used to determine that there is no antenna effect in the connection node between the digital-analog chip top layer and the third-party module when the antenna risk value is not higher than the preset risk threshold.

[0044] Optionally, the analysis module is used to input the second parameter information into a preset prediction model to obtain a first probability that the connection node between the digital-analog chip and the third-party module in the top layer of the digital-analog chip will have an antenna effect; wherein, the prediction model is trained by the parameter information between the third-party modules corresponding to multiple digital-analog chips and the probability that the connection node in each digital-analog chip will have an antenna effect.

[0045] Optionally, the second parameter information includes at least one of the following:

[0046] Pin area between third-party modules, distance between third-party modules, width of connection between third-party modules, and length of connection between third-party modules.

[0047] Optionally, the analysis module is further configured to perform jumper processing on the analog-digital chip when the first probability exceeds a probability threshold; convert the chip layout data file after jumper processing into a second graph structure, and determine the third parameter information between the third-party modules based on the second graph structure; and determine the second probability of antenna effect occurring at the connection node between the analog-digital chip and the third-party module after jumper processing based on the third parameter information.

[0048] Optionally, the analysis module is further configured to: add a diode to the analog-digital chip when the second probability exceeds the probability threshold; convert the chip layout data file after adding the diode into a third diagram structure; determine the fourth parameter information between the third-party modules based on the third diagram structure; and determine the third probability of antenna effect occurring at the connection node between the analog-digital chip and the third-party module after adding the diode based on the fourth parameter information.

[0049] This application also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the above-described analysis method for the top layer of a digital-to-analog chip.

[0050] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described analysis method for the top layer of a digital-to-analog chip.

[0051] This application has the following advantages:

[0052] In this application, based on the chip layout data file of the top layer of the digital-analog chip, first parameter information of the metal line segments that are connected to the third-party module in the top layer of the digital-analog chip is determined; based on the first parameter information, the antenna risk value of the connection node between the top layer of the digital-analog chip and the third-party module is determined; when the antenna risk value is higher than a preset risk threshold, the chip layout data file is converted into a first diagram structure, and second parameter information between the third-party modules is determined based on the first diagram structure; based on the second parameter information, an analysis is performed on the antenna effect occurring at the connection node between the top layer of the digital-analog chip and the third-party module. Through this application embodiment, the analysis of the top layer of the digital-analog chip can be realized without GDSII for running antenna effect analysis, thereby avoiding the waste of a lot of time in back-and-forth iterations; and the analysis results can be used to effectively eliminate antenna effects after IP merging. Attached Figure Description

[0053] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0054] Figure 1 This is a flowchart illustrating the steps of a top-level analysis method for a digital-to-analog chip according to an embodiment of this application;

[0055] Figure 2 This is a flowchart of another method for analyzing the top layer of a digital-to-analog chip according to an embodiment of this application;

[0056] Figure 3 This is a flowchart of another method for analyzing the top layer of a digital-to-analog chip according to an embodiment of this application;

[0057] Figure 4 This is a schematic diagram of a network structure according to an embodiment of this application;

[0058] Figure 5 This is a flowchart illustrating the steps of a digital-to-analog chip analysis and recovery process according to an embodiment of this application;

[0059] Figure 6 This is a schematic diagram of the structure of an analysis device at the top layer of a digital-analog chip according to an embodiment of this application. Detailed Implementation

[0060] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0061] Before IP merging, third-party IP modules, for confidentiality reasons, do not provide the complete GDSII to downstream factories; they only provide GDSII containing a small amount of metal information. After IP merging at the foundry, all the complete GDSIIs are obtained. At this point, antenna violations may occur when running antenna effect verification. To avoid wasting significant time on iterative iterations and to effectively eliminate antenna effects after IP merging, this application provides a top-level analysis method for digital-to-analog chips. This method allows for top-level analysis of digital-to-analog chips even without a GDSII used for antenna effect verification. For example, refer to... Figure 1 The diagram illustrates a flowchart of the steps in an embodiment of this application for analyzing the top layer of a digital-to-analog chip. Figure 1 As shown, the analysis method for the top layer of this analog-to-digital chip can include the following steps:

[0062] Step 101: Based on the chip layout data file of the top layer of the digital-analog chip, determine the first parameter information of the metal line segments that are connected to the third-party module at the top layer of the digital-analog chip.

[0063] The digital-to-analog chip (DAC) is an integrated circuit that simultaneously processes digital and analog signals. This DAC can be used in computers or computer-aided devices. This application can repair the DAC to avoid antenna effects. The top layer of the DAC is the "top-level architecture" in the DAC design process. The top layer can be used to connect third-party modules. Third-party modules can refer to pre-designed and verified circuit modules with specific functions, such as processor cores and memory controllers. This application does not limit this. For example, a third-party module can be a third-party intellectual property module.

[0064] Chip layout data files can store structured information about the physical layer of analog and digital chips. For example, chip layout data files can be GDSII (Graphic Data System II), which is currently the only universal and mainstream chip layout data exchange format in the semiconductor industry. It is responsible for transmitting the physical design information of analog and digital chips to wafer fabs for the production of photomasks.

[0065] In some embodiments, the chip layout data file of the top layer of the digital-to-analog chip can be obtained first; the chip layout data file does not contain GDSII used to run the antenna effect.

[0066] After obtaining the chip layout data file, the first parameter information of the metal line segments that are connected to the top layer of the digital-analog chip and the third-party module can be extracted from it; for example, the first parameter information may include the length information, width information, etc. of the metal line segments, but this application embodiment does not limit this.

[0067] Step 102: Based on the first parameter information, determine the antenna risk value of the connection node with the third-party module in the top layer of the digital-analog chip.

[0068] In some embodiments, after obtaining the first parameter information, the antenna risk value can be calculated based on the first parameter information to determine the possible new antenna efficiency of the connection node with the third-party module in the top layer of the digital-analog chip.

[0069] Step 103: When the antenna risk value is higher than the preset risk threshold, convert the chip layout data file into the first diagram structure, and determine the second parameter information between the third-party modules based on the first diagram structure.

[0070] After determining the antenna risk value, a preliminary analysis of the digital-analog chip can be performed based on the antenna risk value. For example, the relationship between the antenna risk value and the preset risk threshold can be determined first. The preset risk threshold can be set according to the actual situation. For example, based on the experience of traces with only 4 layers of metal or less, the preset risk threshold can be set to 45.

[0071] In some embodiments, if the antenna risk value is not higher than a preset risk threshold, analysis can be performed on the next metal segment.

[0072] Conversely, if the antenna risk value is higher than the preset risk threshold, it can be determined that the digital-to-analog chip may have an antenna effect; at this time, the digital-to-analog chip can be further analyzed.

[0073] For example, if the antenna risk value is determined to be higher than a preset risk threshold, the chip layout data file can be converted into a first diagram structure. For instance, Cadence's Abstract tool can be used to extract and process the chip layout data file to obtain the first diagram structure. Specifically, the Abstract tool can extract and process the first parameter information of the metal segments that connect the top layer of the analog / digital chip to third-party modules, thus obtaining simplified data, i.e., the first diagram structure.

[0074] The first diagram structure may include metal line segments (including length and width, as edge features) and third-party modules (including the length of pin connection points and through holes, as nodes).

[0075] After obtaining the first graph structure, the first graph structure can be analyzed to obtain the second parameter information between the third-party modules.

[0076] For example, the second parameter information may include at least one of the following:

[0077] Pin area between third-party modules, distance between third-party modules, width of connection between third-party modules, and length of connection between third-party modules.

[0078] Step 104: Based on the second parameter information, analyze the antenna effect occurring at the connection node between the digital-analog chip and the third-party module at the top layer.

[0079] After determining the second parameter information, we can further analyze the antenna effect situation of the connection node based on the second parameter information to further determine whether the connection node may have an antenna effect.

[0080] If it is further determined that the connection node may have an antenna effect, then improvements can be made to the digital-to-analog chip; otherwise, the data of the digital-to-analog chip is submitted to the foundry for merging. This application does not impose any restrictions on this.

[0081] In this embodiment, based on the chip layout data file of the top layer of the digital-analog chip, first parameter information of the metal line segments connected to the third-party module in the top layer of the digital-analog chip is determined; based on the first parameter information, the antenna risk value of the connection node between the top layer of the digital-analog chip and the third-party module is determined; when the antenna risk value is higher than a preset risk threshold, the chip layout data file is converted into a first graph structure, and second parameter information between the third-party modules is determined based on the first graph structure; based on the second parameter information, an analysis is performed on the antenna effect occurring at the connection node between the top layer of the digital-analog chip and the third-party module. Through this embodiment, the analysis of the top layer of the digital-analog chip can be achieved without using GDSII to run antenna effect analysis, thus avoiding the waste of a lot of time through iterative iterations; and the analysis results can be used to effectively eliminate antenna effects after IP merging.

[0082] Reference Figure 2 The flowchart illustrates another method for analyzing the top layer of a digital-to-analog chip according to an embodiment of this application, which may include the following steps:

[0083] Step 201: Based on the chip layout data file of the top layer of the digital-analog chip, determine the first parameter information of the metal line segments that are connected to the third-party module at the top layer of the digital-analog chip.

[0084] In some embodiments, the chip layout data file of the top layer of the digital-to-analog chip can be obtained first; the chip layout data file does not contain GDSII used to run the antenna effect.

[0085] After obtaining the chip layout data file, the first parameter information of the metal line segments that are connected to the top layer of the digital-analog chip and the third-party module can be extracted from it.

[0086] Step 202: The first parameter information includes the length, width, number of through holes, and connection status of the metal wire segment; determine the weighting coefficient.

[0087] In some embodiments, the first parameter information may include the length information of the metal wire segment, the width information of the metal wire segment, the number of through holes in the metal wire segment, and the connection status of the metal wire segment; wherein, the connection status of the metal wire segment can be represented by 1 and 0; 1 indicates that there is a connection relationship, and 0 indicates that there is no connection relationship.

[0088] For example, after obtaining the first parameter information, a feature vector can be assigned to the obtained first parameter information; where L represents the length information of the metal line segment, W represents the width information of the metal line segment, N represents the number of through holes, and IP_connect represents the connection status; IP_connect=1 indicates that there is a connection relationship, and IP_connect=0 indicates that there is no actual connection relationship.

[0089] In some embodiments, weighting coefficients for each piece of information in the first parameter information can also be determined.

[0090] In some embodiments of this application, the weighting coefficients can be determined through the following sub-steps:

[0091] Sub-step 11: Determine the number of metal layers on the top layer of the digital-to-analog chip.

[0092] In some embodiments, the number of metal layers at the top of the digital-analog chip can be determined first; for example, the top metal layer may refer to the global connection responsible for cross-module (such as signal transmission between the digital core and the analog interface, global allocation of power / ground network, transmission line of high-frequency signal, etc.), and this application embodiment does not limit this.

[0093] Sub-step 11: Determine the weighting coefficients based on the number of metal layers.

[0094] After determining the number of metal layers, the corresponding weighting coefficients can be determined based on the number of metal layers to adapt to different digital-to-analog chips for analysis. For example, different numbers of metal layers can correspond to different weighting coefficients, and the specific correspondence can be preset according to the actual situation. This application embodiment does not limit this.

[0095] In some embodiments of this application, the weighting coefficients include: a first weighting coefficient for length information, a second weighting coefficient for width information, a third weighting coefficient for the number of through holes, and a fourth weighting coefficient for the connection status.

[0096] The sum of the first weighting coefficient, the second weighting coefficient, and the third weighting coefficient is zero.

[0097] In some embodiments, the weighting coefficients may include at least a first weighting coefficient for length information, a second weighting coefficient for width information, a third weighting coefficient for the number of vias, and a fourth weighting coefficient for the connection status.

[0098] The sum of the first, second, and third weighting coefficients is zero, which was determined based on both physical laws and project experience.

[0099] The three factors, L, W, and N, are mutually restrictive and balanced. A sum of zero for all three ensures consistency in the formula under different parameter combinations, making the risk threshold more closely reflect real-world projects. However, if the sum of the three factors is not zero, the risk threshold may fail in certain scenarios. For example, some process rules are sensitive to line length L, which can cause the risk threshold to become ineffective, preventing a valid assessment.

[0100] The first weighting coefficient indicates that the length of the metal line has a positive impact on the antenna; the longer the line segment, the more likely the line is to exhibit antenna violation. The second and third weighting coefficients indicate that the width of the metal line and the number of vias have a negative impact on the antenna; the wider the line width and the more vias, the less likely the line is to exhibit antenna violation.

[0101] For example, based on the aforementioned determination of weighting coefficients according to the number of metal layers: if the top layer uses only 4 or fewer metal layers, the first weighting coefficient of the metal line segment is relatively heavy, and can generally be set as the sum of the absolute values ​​of the second and third weighting coefficients. For example, the first weighting coefficient is 0.6, the second weighting coefficient is -0.3, and the third weighting coefficient is -0.3.

[0102] If the top layer uses a large number of metal layers, such as 6 or 7 layers or more, the coefficients can be set as follows: First weight coefficient = 0.4, Second weight coefficient = -0.2, Third weight coefficient = -0.2.

[0103] Step 203: Determine the antenna risk value based on the weighting coefficient, length information, width information, number of through holes, and connection status.

[0104] After determining the weighting coefficients, as well as the length, width, number of through holes, and connection status, the antenna risk value can be determined based on the weighting coefficients, length, width, number of through holes, and connection status.

[0105] For example, the weighting coefficients include a first weighting coefficient α, a second weighting coefficient β, a third weighting coefficient γ, and a fourth weighting coefficient δ; length information L, width information W, number of through holes N, and connection status IP_connect. The antenna risk value R can be calculated using the following formula:

[0106] R=α*L+β*W+γ*N+δ*IP_connect.

[0107] Assume that the top layer of the analog-digital chip is connected to a third-party module, and that the metal line segment has an L of 100u, a W of 1u, an N of 10, and an IP_Connection of 1.

[0108] α=0.5, β=-0.3, α=-0.2, δ=1, then R=50-0.3-2+1=48.7; the preset risk threshold is 45, so it can be determined that R has exceeded the preset risk threshold of 45. It can be preliminarily determined that the metal line segment is a high-risk line that violates the antenna effect and may cause an antenna effect violation after IP merge.

[0109] Step 204: When the antenna risk value is higher than the preset risk threshold, convert the chip layout data file into the first diagram structure, and determine the second parameter information between the third-party modules based on the first diagram structure.

[0110] After determining the antenna risk value, a preliminary analysis of the digital-to-analog chip can be performed based on the antenna risk value; for example, the relationship between the antenna risk value and the preset risk threshold can be determined first.

[0111] In some embodiments, if the antenna risk value is not higher than a preset risk threshold, analysis can be performed on the next metal segment.

[0112] Conversely, if the antenna risk value is higher than the preset risk threshold, it can be determined that the digital-to-analog chip may have an antenna effect; at this time, the digital-to-analog chip can be further analyzed.

[0113] For example, if the antenna risk value is determined to be higher than a preset risk threshold, the chip layout data file can be converted into a first diagram structure.

[0114] After obtaining the first diagram structure, it can be analyzed to obtain second parameter information that determines the relationships between third-party modules. For example, the second parameter information may include one or more of the following: pin area between third-party modules, distance between third-party modules, width of the connection between third-party modules, and length of the connection between third-party modules.

[0115] Step 205: Based on the second parameter information, analyze the antenna effect occurring at the connection node between the digital-analog chip and the third-party module in the top layer.

[0116] After determining the second parameter information, we can further analyze the antenna effect situation of the connection node based on the second parameter information to further determine whether the connection node may have an antenna effect.

[0117] Step 206: When the antenna risk value is not higher than the preset risk threshold, it is determined that there is no antenna effect in the connection node between the digital-analog chip and the third-party module in the top layer.

[0118] In some embodiments, if it is determined that the antenna risk value corresponding to a connection node with a third-party module in the top layer of the digital-analog chip is not higher than a preset risk threshold, it can be directly determined that the metal line segment corresponding to the connection node does not have the risk of antenna effect. At this time, the analysis can be performed on the next metal line segment or the next digital-analog chip. This application embodiment does not limit this.

[0119] In this embodiment, based on the chip layout data file of the top layer of the digital-analog chip, the first parameter information of the metal segments connected to the third-party module is determined. The first parameter information includes the length, width, number of vias, and connection status of the metal segments. A weighting coefficient is determined. Based on the weighting coefficient, and the length, width, number of vias, and connection status, an antenna risk value is determined. When the antenna risk value is higher than a preset risk threshold, the chip layout data file is converted into a first diagram structure, and the second parameter information between the third-party modules is determined based on the first diagram structure. Based on the second parameter information, an antenna effect analysis is performed on the connection nodes between the top layer of the digital-analog chip and the third-party module. When the antenna risk value is not higher than the preset risk threshold, it is determined that there is no antenna effect at the connection nodes between the top layer of the digital-analog chip and the third-party module. Through this embodiment, the analysis of the top layer of the digital-analog chip can be performed without using GDSII to run antenna effect analysis, thus avoiding the waste of a lot of time through iterative iterations. Furthermore, the analysis results can be used to effectively eliminate antenna effects after IP merging.

[0120] Reference Figure 3 The flowchart illustrates another method for analyzing the top layer of a digital-to-analog chip according to an embodiment of this application, which may include the following steps:

[0121] Step 301: Based on the chip layout data file of the top layer of the digital-analog chip, determine the first parameter information of the metal line segments that are connected to the third-party module at the top layer of the digital-analog chip.

[0122] In some embodiments, the chip layout data file of the top layer of the digital-to-analog chip can be obtained first; the chip layout data file does not contain GDSII used to run the antenna effect.

[0123] After obtaining the chip layout data file, the first parameter information of the metal line segments that are connected to the top layer of the digital-analog chip and the third-party module can be extracted from it.

[0124] Step 302: Based on the first parameter information, determine the antenna risk value of the connection node with the third-party module in the top layer of the digital-analog chip.

[0125] In some embodiments, after obtaining the first parameter information, the probability of antenna efficiency issues arising between the connection node of the digital-analog chip and the third-party module in the top layer of the digital-analog chip, i.e., the antenna risk value, can be calculated based on the first parameter information.

[0126] Step 303: When the antenna risk value is higher than the preset risk threshold, convert the chip layout data file into a first diagram structure, and determine the second parameter information between third-party modules based on the first diagram structure.

[0127] After determining the antenna risk value, a preliminary analysis of the digital-to-analog chip can be performed based on the antenna risk value; for example, the relationship between the antenna risk value and the preset risk threshold can be determined first.

[0128] In some embodiments, if the antenna risk value is not higher than a preset risk threshold, analysis can be performed on the next metal segment.

[0129] Conversely, if the antenna risk value is higher than the preset risk threshold, it can be determined that the digital-to-analog chip may have an antenna effect; at this time, the digital-to-analog chip can be further analyzed.

[0130] For example, if the antenna risk value is determined to be higher than a preset risk threshold, the chip layout data file can be converted into a first diagram structure.

[0131] After obtaining the first diagram structure, it can be analyzed to obtain second parameter information that determines the relationships between third-party modules. For example, the second parameter information may include the pin area between third-party modules, the distance between third-party modules, the width of the connection between third-party modules, and the length of the connection between third-party modules.

[0132] Step 304: Input the second parameter information into the preset prediction model to obtain the first probability of antenna effect occurring at the connection node between the digital-analog chip and the third-party module at the top layer.

[0133] The prediction model is trained using parameter information from third-party modules corresponding to multiple digital-analog chips, as well as the probability of antenna effects occurring at connection nodes in each digital-analog chip.

[0134] After obtaining the second parameter information, the vectorized second parameter information can be input into the preset prediction model; the preset prediction model can be trained by the parameter information between the third-party modules corresponding to multiple digital-analog chips, as well as the probability of antenna effect occurring at the connection nodes in each digital-analog chip.

[0135] For example, based on the principle of antenna effect, when analyzing antenna effect, the most important factors are the pin area between third-party modules, the distance between third-party modules, the width of the connection between third-party modules, and the length of the connection between third-party modules. Finally, based on the probability of antenna effect occurring between the pins of two third-party modules, high-risk areas are marked.

[0136] Analysis revealed that the problem is a regression problem, and therefore a deep neural network can be used to solve it.

[0137] First, the network inputs are defined as the pin area between third-party modules, the distance between third-party modules, the width of the connection between third-party modules, and the length of the connection between third-party modules. The output is the probability of the antenna effect occurring at the connection node.

[0138] During the training phase, all routing instances from previous projects (including reliable and unreliable connections) can be used. The pin connections of all non-repeating third-party modules in these instances are abstracted into data such as [pin area between third-party modules, distance between third-party modules, width of the connection between third-party modules, and length of the connection between third-party modules]. The output is either 0 or 1, where 0 indicates normal operation and 1 indicates an antenna effect. The network structure is as follows: Figure 4 As shown:

[0139] The network can include at least FC1, ReLU, FC2, and sigmoid; the inputs can be the pin area between third-party modules, the distance between third-party modules, the width of the connection between third-party modules, and the length of the connection between third-party modules; the output can be the probability of the antenna effect occurring at the connection node.

[0140] After the trained prediction model is input with the second parameter information, it can analyze whether the corresponding connection node will experience antenna effect based on the second parameter information.

[0141] For example, after receiving the second parameter information, the prediction model can iterate through the probability of antenna effect occurring in all connection relationships and obtain the first probability from the data trained on historical projects, that is, the probability of whether the connection node to be predicted will experience antenna effect.

[0142] Step 305: When the first probability exceeds the probability threshold, perform jumper processing on the digital-to-analog chip.

[0143] If the probability exceeds a certain threshold, it can be determined that the connection node may exhibit an antenna effect; otherwise, an antenna effect is unlikely. The probability threshold can be set according to actual conditions, for example, 85%, but this application does not impose such a limitation.

[0144] If the first probability is determined not to exceed the probability threshold, analysis can be performed on the next connection node or another analog-digital chip.

[0145] Conversely, if the initial probability exceeds the probability threshold, the analog-to-digital chip can be processed. For example, jumper processing can be performed on the analog-to-digital chip first. Jumper processing can refer to replanning the wiring path through the top layer metal (usually a higher layer metal, such as Metal3 and above). Essentially, it cuts off the direct connection between the "antenna" and the sensitive gate oxide device, or reduces the effective area of ​​the "antenna", thereby limiting the amount of charge accumulation.

[0146] Step 306: Convert the chip layout data file after jumper processing into a second diagram structure, and determine the third parameter information between third-party modules based on the second diagram structure.

[0147] After performing jumper processing on the top layer of the analog-to-digital chip, the chip layout data file of the analog-to-digital chip after jumper processing can be obtained again; the obtained chip layout data file at this time is the file of the analog-to-digital chip after jumper processing.

[0148] After obtaining the chip layout data file after jumper processing, step 303 can be repeated. For example, after obtaining the chip layout data file after jumper processing, it can be converted to obtain a second graph structure; the first graph structure and the second graph structure are graph structures obtained after conversion for different chip layout data files.

[0149] After obtaining the second diagram structure, the second diagram structure can be analyzed and extracted to obtain the third parameter information between the third-party modules in the digital-to-analog chip after jumper processing; the third parameter information may include the pin area between the third-party modules, the distance between the third-party modules, the width of the connection between the third-party modules, and the length of the connection between the third-party modules in the digital-to-analog chip after jumper processing.

[0150] Step 307: Based on the third parameter information, determine the second probability of antenna effect occurring at the connection node between the digital-to-analog chip and the third-party module after jumper processing.

[0151] After obtaining the third parameter information, the second probability of antenna effect occurring at the connection node between the digital-analog chip and the third-party module after jumper processing can be determined based on the third parameter information; for example, the third parameter information can be input into a preset prediction model to obtain the second probability.

[0152] Step 308: When the second probability exceeds the probability threshold, add a diode to the digital-to-analog chip.

[0153] In some embodiments, if the second probability does not exceed a probability threshold, it can be determined that the currently analyzed connection node in the digital-to-analog chip after jumper processing no longer exhibits antenna effects. In this case, analysis can be performed on another connection node or on another digital-to-analog chip.

[0154] Conversely, if the second probability exceeds the probability threshold, it can be determined that the currently analyzed connection node in the digital-to-analog chip after jumper processing has an antenna effect; in this case, a diode can be added to the digital-to-analog chip after jumper processing.

[0155] Adding a diode is a hardware protection method that eliminates the antenna effect by connecting a diode between the metal line segment (or polysilicon) and the substrate to release the charge accumulated during the plasma etching process. Its core logic is to provide a safe charge discharge path for the "antenna" (metal line / polysilicon) and avoid charge breakdown of the gate oxide layer of sensitive devices.

[0156] Step 309: Convert the chip layout data file after adding diodes into a third diagram structure, and determine the fourth parameter information between third-party modules based on the third diagram structure.

[0157] After adding diodes to the top layer of the analog-to-digital chip, the chip layout data file of the analog-to-digital chip with added diodes can be obtained again; the obtained chip layout data file at this time is the file of the analog-to-digital chip with added diodes.

[0158] After obtaining the chip layout data file with added diodes, step 303 can be repeated. For example, after obtaining the chip layout data file with added diodes, it can be converted to obtain a third diagram structure; the third diagram structure and the second diagram structure are diagram structures obtained after conversion for different chip layout data files.

[0159] After obtaining the third diagram structure, the third diagram structure can be analyzed and extracted to obtain the fourth parameter information between the third-party modules in the digital-to-analog chip after adding diodes; the fourth parameter information may include the pin area between the third-party modules, the distance between the third-party modules, the width of the connection between the third-party modules, and the length of the connection between the third-party modules in the digital-to-analog chip after adding diodes.

[0160] Step 310: Based on the fourth parameter information, determine the third probability of antenna effect occurring at the connection node between the digital-to-analog chip with the third-party module after the diode is added.

[0161] After obtaining the fourth parameter information, the third probability of antenna effect occurring at the connection node between the digital-to-analog chip with the added diode and the third-party module can be determined based on the fourth parameter information; for example, the fourth parameter information can be input into a preset prediction model to obtain the third probability.

[0162] In some embodiments, if the third probability does not exceed a probability threshold, it can be determined that the currently analyzed connection node in the digital-to-analog chip with the added diode no longer exhibits antenna effects. In this case, analysis can be performed on another connection node or on another digital-to-analog chip.

[0163] Conversely, if the third probability exceeds the probability threshold, it can be determined that the currently analyzed connection node in the digital-analog chip after jumper processing has an antenna effect. At this time, the digital-analog chip can continue to be repaired (e.g., jumper processing or adding diodes) until the probability does not exceed the probability threshold.

[0164] In some embodiments, after the probability does not exceed a probability threshold, new GDSII data can be generated, and a verification tool can be used to check the antenna effect of the entire digital-analog chip to ensure that the repaired data does not have antenna effect violations.

[0165] In this embodiment, based on the chip layout data file of the top layer of the analog-digital chip, the first parameter information of the metal line segments connected to the third-party module in the top layer of the analog-digital chip is determined; based on the first parameter information, the antenna risk value of the connection node between the top layer of the analog-digital chip and the third-party module is determined; when the antenna risk value is higher than a preset risk threshold, the chip layout data file is converted into a first diagram structure, and the second parameter information between the third-party modules is determined based on the first diagram structure; the second parameter information is input into a preset prediction model to obtain the first probability of antenna effect occurring at the connection node between the top layer of the analog-digital chip and the third-party module; wherein, the prediction model consists of the parameter information between the third-party modules corresponding to multiple analog-digital chips, and the probability of antenna effect occurring at the connection node in each analog-digital chip. The probability is obtained through training. When the first probability exceeds the probability threshold, jumper processing is performed on the digital-to-analog chip. The chip layout data file after jumper processing is converted into a second graph structure, and the third parameter information between third-party modules is determined based on the second graph structure. Based on the third parameter information, the second probability of antenna effect occurring at the connection nodes between the jumper-processed digital-to-analog chip and the third-party module is determined. When the second probability exceeds the probability threshold, diodes are added to the digital-to-analog chip. The chip layout data file after adding diodes is converted into a third graph structure, and the fourth parameter information between third-party modules is determined based on the third graph structure. Based on the fourth parameter information, the third probability of antenna effect occurring at the connection nodes between the added diodes and the third-party module is determined. Through the embodiments of this application, top-level analysis of the digital-to-analog chip can be achieved without using GDSII to run antenna effect analysis, thereby avoiding the waste of a lot of time through back-and-forth iterations. Moreover, the analysis results can be used to effectively eliminate antenna effect after IP merging.

[0166] Furthermore, for chips with only four or fewer layers of wiring resources at the top, deep neural networks are used to detect the connection relationship between the third intellectual property module (which only has metal layers and lacks poly and ACT layers, and also lacks GDSII data specifically for antenna effect analysis) and the main chip. This avoids the omission of antenna effects due to the lack of poly and ACT layers in the third intellectual property module, resolving potential risk blind spots after traditional IP merging, and repairing antenna effect violations. Moreover, by predicting risk values ​​through deep neural networks and dynamically detecting violation areas after IP merging, combined with jumper optimization and the insertion of diodes to ground, antenna effects at the top layer of the chip after IP merging can be effectively eliminated, improving chip reliability and saving chip manufacturing and development time.

[0167] Reference Figure 5 The following is a flowchart illustrating the steps of a digital-to-analog chip analysis and recovery process according to an embodiment of this application:

[0168] First, the GDSII at the top layer of the analog-digital chip can be obtained; then, the first parameter information of the metal line segment that has a connection relationship with the third-party module can be extracted from it: the length information L, width information W, number of through holes N, and connection status IP_Connect of the metal line segment.

[0169] Next, the antenna risk value R can be calculated based on the first parameter information, and it can be determined whether R is greater than a preset risk threshold. If R is not greater than the preset risk threshold, the antenna effect can be checked directly using a verification tool.

[0170] Conversely, if R is greater than a preset risk threshold, it is initially marked as a high-risk area, and a deep neural network model is used to predict the interconnection (i.e., converting the chip layout data file into a first graph structure, and determining the second parameter information between third-party modules based on the first graph structure; based on the second parameter information, analyzing the antenna effect of the connection nodes between the digital-analog chip and the third-party modules in the top layer). If the output first probability is greater than the probability threshold, it is further marked as a high-risk area, and jumper processing and / or adding diodes are performed to generate a new GDSII. Then, the antenna effect can be checked on the new GDSII using verification tools.

[0171] If the first probability output is not greater than the probability threshold, then the verification tool is used directly to check for antenna effects.

[0172] After checking for antenna effects using verification tools, it can be further determined whether the digital-to-analog chip still has antenna effects. If not, the process ends and the final GDSII is output for subsequent steps, such as sending it to the foundry for merging. Otherwise, the deep neural network model is reused for complex connection prediction.

[0173] When four or fewer metal layers are used at the top layer of a digital-to-analog chip, and there is no dedicated GDSII data for antenna effect analysis, antenna effect violations mainly manifest in the length L, width W, and number of vias N of the metal lines. This process primarily extracts parameters from the metal layers to predict and detect antenna effects, bringing violations before IP merging to the point before the IP merge process, avoiding repeated iterations with the foundry and saving time.

[0174] Example: The analog-to-digital chip contains a third-party module, but only provides GDSII data on the metal layer. A pin of the third-party module has a metal connection to the top layer, assuming L=100u, W=0.6u, N=4, and IP_connectc=1.

[0175] Using traditional methods, antenna violations might not be detected before IP merge, but if violations are found after the foundry merge, it is necessary to go back and modify them, and then merge again, which wastes time.

[0176] Using the method provided in this application: obtain information about the metal line segments, first predict the risk threshold, then convert it into a graph structure for accurate judgment; if the probability of occurrence is too high, it is determined that repair is required.

[0177] After fixing the issue, the precise judgment process is run again until the probability is low enough to classify it as a safe zone. Finally, the data is submitted to the Foundry for merging. If no violations are found, time is saved.

[0178] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of this application.

[0179] Reference Figure 6 The diagram shows a structural schematic of a top-level analysis device for a digital-to-analog chip according to an embodiment of this application, which may include the following modules:

[0180] The first determining module 601 is used to determine the first parameter information of the metal line segments that are connected to the third-party module at the top layer of the digital-analog chip based on the chip layout data file at the top layer of the digital-analog chip.

[0181] The second determining module 602 is used to determine the antenna risk value of the connection node with the third-party module in the top layer of the digital-analog chip based on the first parameter information.

[0182] The third determining module 603 is used to convert the chip layout data file into a first diagram structure when the antenna risk value is higher than a preset risk threshold, and to determine the second parameter information between the third-party modules based on the first diagram structure.

[0183] Analysis module 604 is used to analyze the antenna effect occurring at the connection node between the digital-analog chip and the third-party module in the top layer based on the second parameter information.

[0184] In some embodiments of this application, the first parameter information includes the length information, width information, number of through holes, and connection status of the metal wire segment; the second determining module 602 is used to determine the weighting coefficient; and the antenna risk value is determined based on the weighting coefficient, as well as the length information, width information, number of through holes, and connection status.

[0185] In some embodiments of this application, the second determining module 602 is used to determine the number of metal layers in the top layer of the digital-to-analog chip; and to determine a weighting coefficient based on the number of metal layers.

[0186] In some embodiments of this application, the weighting coefficients include: a first weighting coefficient for length information, a second weighting coefficient for width information, a third weighting coefficient for the number of through holes, and a fourth weighting coefficient for the connection status.

[0187] The sum of the first weighting coefficient, the second weighting coefficient, and the third weighting coefficient is zero.

[0188] In some embodiments of this application, the analysis module 604 is used to determine that there is no antenna effect in the connection node between the digital-analog chip top layer and the third-party module when the antenna risk value is not higher than a preset risk threshold.

[0189] In some embodiments of this application, the analysis module 604 is used to input the second parameter information into a preset prediction model to obtain the first probability that the connection node between the digital-analog chip and the third-party module in the top layer of the digital-analog chip will have an antenna effect; wherein, the prediction model is trained by the parameter information between the third-party modules corresponding to multiple digital-analog chips and the probability that the connection node in each digital-analog chip will have an antenna effect.

[0190] In some embodiments of this application, the second parameter information includes at least one of the following:

[0191] Pin area between third-party modules, distance between third-party modules, width of connection between third-party modules, and length of connection between third-party modules.

[0192] In some embodiments of this application, the analysis module 604 is further configured to perform jumper processing on the digital-analog chip when the first probability exceeds a probability threshold; convert the chip layout data file after jumper processing into a second graph structure, and determine the third parameter information between the third-party modules based on the second graph structure; and determine the second probability of antenna effect occurring at the connection node between the digital-analog chip and the third-party module after jumper processing based on the third parameter information.

[0193] In some embodiments of this application, the analysis module 604 is further configured to add a diode to the analog-digital chip when the second probability exceeds a probability threshold; convert the chip layout data file after adding the diode into a third graph structure, and determine the fourth parameter information between the third-party modules based on the third graph structure; and determine the third probability of antenna effect occurring at the connection node between the analog-digital chip and the third-party module after adding the diode based on the fourth parameter information.

[0194] In this embodiment, based on the chip layout data file of the top layer of the digital-analog chip, first parameter information of the metal line segments connected to the third-party module in the top layer of the digital-analog chip is determined; based on the first parameter information, the antenna risk value of the connection node between the top layer of the digital-analog chip and the third-party module is determined; when the antenna risk value is higher than a preset risk threshold, the chip layout data file is converted into a first graph structure, and second parameter information between the third-party modules is determined based on the first graph structure; based on the second parameter information, an analysis is performed on the antenna effect occurring at the connection node between the top layer of the digital-analog chip and the third-party module. Through this embodiment, the analysis of the top layer of the digital-analog chip can be achieved without using GDSII to run antenna effect analysis, thus avoiding the waste of a lot of time through iterative iterations; and the analysis results can be used to effectively eliminate antenna effects after IP merging.

[0195] This application also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, it implements the above-mentioned analysis method for the top layer of the analog-digital chip.

[0196] This application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it implements the above-described analysis method for the top layer of a digital-to-analog chip.

[0197] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0198] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0199] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0200] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0201] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0202] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0203] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0204] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0205] The above provides a detailed description of the analysis method, apparatus, electronic device, and storage medium for the top layer of a digital-analog chip. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for analyzing the top layer of a digital-to-analog chip, characterized in that, The method comprises: According to the chip layout data file of the top layer of the digital-analog chip, determining the first parameter information of the metal line segment of the top layer of the digital-analog chip having a connection relationship with the third-party module, the first parameter information comprising length information, width information, the number of through holes and connection conditions of the metal line segment; Determine the number of metal layers of the top layer of the digital-analog chip; According to the number of metal layers, determine the weight coefficient; the weight coefficient comprises: the first weight coefficient for length information, the second weight coefficient for width information, the third weight coefficient for the number of through holes, and the fourth weight coefficient for the connection condition; the sum of the first weight coefficient, the second weight coefficient and the third weight coefficient is zero; According to the weight coefficient, and the length information, width information, the number of through holes and connection conditions, determine the antenna risk value; When the antenna risk value is higher than the preset risk threshold, the chip layout data file is converted into a first graph structure, and the second parameter information between the third-party modules is determined according to the first graph structure; the second parameter information comprises at least one of the pin area between the third-party modules, the distance between the third-party modules, the width of the connection line between the third-party modules, and the length of the connection line between the third-party modules; According to the second parameter information, analyze the connection nodes of the top layer of the digital-analog chip with the third-party module that have antenna effect.

2. The method of claim 1, wherein, The method further comprises: When the antenna risk value is not higher than the preset risk threshold, it is determined that the connection nodes of the top layer of the digital-analog chip with the third-party module do not have antenna effect.

3. The method of claim 1, wherein, According to the second parameter information, analyze the connection nodes of the top layer of the digital-analog chip with the third-party module that have antenna effect, comprising: Input the second parameter information into a preset prediction model to obtain the first probability of the connection nodes of the top layer of the digital-analog chip with the third-party module that have antenna effect; Wherein, the prediction model is trained by the parameter information between the third-party modules corresponding to a plurality of digital-analog chips, and the probability of the connection nodes in each digital-analog chip having antenna effect.

4. The method of claim 3, wherein, The method further comprises: When the first probability exceeds the probability threshold, perform jumper processing on the digital-analog chip; Convert the chip layout data file after jumper processing into a second graph structure, and determine the third parameter information between the third-party modules according to the second graph structure; According to the third parameter information, determine the second probability of the connection nodes of the digital-analog chip after jumper processing with the third-party module that have antenna effect.

5. The method of claim 4, wherein, The method further comprises: When the second probability exceeds the probability threshold, add a diode to the digital-analog chip; Convert the chip layout data file after adding a diode into a third graph structure, and determine the fourth parameter information between the third-party modules according to the third graph structure; According to the fourth parameter information, determine the third probability of the connection nodes of the digital-analog chip after adding a diode with the third-party module that have antenna effect.

6. An apparatus for analyzing a top layer of a digital-to-analog chip, the apparatus comprising: The device comprises: The first determining module is configured to determine first parameter information of a metal line segment having a connection relationship between the top layer of the digital-analog chip and a third-party module according to a chip layout data file of the top layer of the digital-analog chip, the first parameter information including length information, width information, via hole quantity, and connection conditions of the metal line segment. The second determining module is configured to determine a metal layer number of the top layer of the digital-analog chip, determine a weight coefficient according to the metal layer number, the weight coefficient including a first weight coefficient for the length information, a second weight coefficient for the width information, a third weight coefficient for the via hole quantity, and a fourth weight coefficient for the connection conditions, a sum of the first weight coefficient, the second weight coefficient, and the third weight coefficient being zero, and determine an antenna risk value according to the weight coefficient and the length information, the width information, the via hole quantity, and the connection conditions. The third determining module is configured to convert the chip layout data file into a first graph structure when the antenna risk value is higher than a preset risk threshold, and determine second parameter information between the third-party modules according to the first graph structure, the second parameter information including at least one of pin area between third-party modules, distance between third-party modules, width of a connection line between third-party modules, and length of the connection line between third-party modules. The analysis module is configured to analyze an antenna effect occurring at a connection node between the top layer of the digital-analog chip and the third-party modules according to the second parameter information.

7. An electronic device, comprising: A computer program is stored on a computer readable storage medium and executable on a processor, and when executed by the processor, implements the analysis method of the top layer of the digital-analog chip according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, A computer program is stored on a computer readable storage medium and executable on a processor, and when executed by the processor, implements the analysis method of the top layer of the digital-analog chip according to any one of claims 1 to 5.

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