Chip surface defect detection method based on complexity self-adaption and edge enhancement
By improving the backbone network and neck structure of the YOLOv12 model to a multi-scale edge-enhanced convolutional module and combining it with data augmentation technology, the problem of insufficient accuracy in wafer defect detection under complex backgrounds was solved, and efficient and accurate identification of minute defects was achieved.
CN121190441APending Publication Date: 2025-12-23ZHEJIANG UNIV OF TECH
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Patent Information
- Application Number
- CN202511364664.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-23
- Publication Date
- 2025-12-23
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Figure CN121190441A_ABST
Abstract
The invention discloses a chip surface defect detection method based on complexity self-adaption and edge enhancement, which comprises the following steps: acquiring a to-be-detected wafer chip, and inputting a trained wafer chip surface defect detection model to obtain the type of a surface defect of the to-be-detected wafer chip; wherein the wafer chip surface defect detection model adopts an improved yolov12 model, that is, a backbone network in the yolov12 model is replaced by an improved backbone network; according to the chip surface defect detection method based on complexity self-adaption and edge enhancement, an existing yov12 model is improved, that is, a backbone network in the yov12 model and a C3K2 structure and an A2C2f structure of the neck are improved, a wafer chip surface defect detection model is obtained, the calculation complexity and the parameter scale are kept low, and meanwhile the chip surface defect detection efficiency is improved. According to the method, the detection precision and the prediction accuracy are remarkably improved, the real-time detection requirement in a resource-constrained environment can be met, and the recognition reliability and the practical application value of tiny defects are improved.
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