A method, apparatus and storage medium for correcting an array image of a light emitting device

Abstract

The application discloses a light emitting device array image correction method and device and a storage medium, which are used for converting irregular light emitting device arrays into array images with fixed repeating periods so as to facilitate defect detection and improve defect detection efficiency. The application comprises the following steps: acquiring a chip array image shot on a target screen, and acquiring coordinate positions of the chips in the target screen and row and column numbers of the chips; constructing a chip coordinate matrix according to the coordinate positions of the chips; calculating row and column spacings between the chips according to the coordinate positions of the chips and preset chip size parameters; constructing theoretical dot array coordinates according to the preset chip size parameters, the row and column numbers of the chips and the row and column spacings between the chips; dividing the chip coordinate matrix into a first area coordinate group; calculating regional transformation matrices according to the theoretical dot array coordinates and the first area coordinate group; and processing the first area coordinate group according to the regional transformation matrices to obtain a corrected image.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image processing, in particular to a light emitting device array image correction method and device and storage medium. BACKGROUND

[0002] In the field of display technology, display technologies such as MiniLED / MicroLED / OLED with light emitting device arrays are gaining more and more favor in the market due to their unique advantages.

[0003] In the generation and manufacturing process of these display technologies, a key and common step is to transplant a large number of light emitting chips onto the corresponding substrate. However, in actual operation, it is difficult to ensure that each chip or pixel point can be transplanted accurately according to the predetermined position, regardless of the technology. This results in a deviation in the spacing between the chips or pixel points, resulting in an irregular arrangement.

[0004] The conventional light-up detection algorithm is based on the early LCD\OLED array generated with the help of a mask with a fixed period. The distance between the pixels in this array is fixed and almost no deviation, so the algorithm only needs to set the appropriate period to effectively highlight the defects. However, when using this conventional light-up detection algorithm to detect irregularly arranged MiniLED / MicroLED / OLED light emitting device arrays, it is not possible to accurately extract defect information according to the fixed spacing. Some otherwise normal chips may be incorrectly identified as defects by the algorithm due to the irregular spacing with the surrounding chips, resulting in over-detection; while some chips with real defects may be missed by the algorithm due to the irregular arrangement of the surrounding chips, resulting in under-detection. This over-detection and under-detection phenomenon has a serious impact on the production and quality control of display screens. Over-detection increases unnecessary detection costs and subsequent processing workload, while under-detection allows defective products to enter the market, reducing product qualification rates and increasing production costs. SUMMARY

[0005] The present application discloses a light emitting device array image correction method, device and storage medium for converting irregular light emitting device arrays into arrays with fixed arrangement rules for defect detection and improving defect detection efficiency.

[0006] The first aspect of the present application discloses a light emitting device array image correction method, comprising:

[0007] Obtaining a chip array image taken of a target screen, and obtaining the coordinate positions of a plurality of chips and the number of rows and columns of the chips in the target screen according to the chip array image;

[0008] constructing a chip coordinate matrix according to coordinate positions of the chips;

[0009] calculating row and column distances between the chips according to the coordinate positions of the chips and preset chip size parameters;

[0010] constructing theoretical lattice coordinates according to the preset chip size parameters, the number of rows and columns of the chips, and the row and column distances between the chips;

[0011] dividing the chip coordinate matrix into a plurality of first area coordinate groups, each of the first area coordinate groups being a set of four coordinates of two adjacent rows and two adjacent columns;

[0012] calculating a plurality of area transformation matrices according to the theoretical lattice coordinates and the plurality of first area coordinate groups;

[0013] processing the first area coordinate groups according to the area transformation matrices to obtain a corrected image.

[0014] Optionally, the step of obtaining the coordinate positions of the chips and the number of rows and columns of the chips in the target screen according to the chip array image specifically comprises:

[0015] Step 1: obtaining the number of rows and columns of the chips in the chip array image;

[0016] Step 2: setting a global threshold value and extracting a chip region according to the global threshold value;

[0017] Step 3: obtaining a connected domain of the chip region and screening out an effective connected domain through eigenvalues of the connected domain;

[0018] Step 4: obtaining coordinate positions of the chips in the effective connected domain and calculating the number of the coordinate positions of the chips.

[0019] Optionally, the step of constructing a chip coordinate matrix according to the coordinate positions of the chips specifically comprises:

[0020] sorting the coordinate positions of the chips according to a preset interval threshold value and the chip array image and then collecting the coordinate positions into a chip coordinate matrix;

[0021] if there is a missing coordinate in the chip coordinate matrix, placing the missing coordinate into a fitting matrix and filling the corresponding position of the missing coordinate in the fitting matrix with a negative number, the missing coordinate being a coordinate position of a chip that is not detected in the chip array image;

[0022] performing coordinate fitting on the fitting matrix to calculate the missing coordinate and then collecting the missing coordinate into the chip coordinate matrix.

[0023] Optionally, after the step four, the correction method further comprises:

[0024] Step five: if the difference between the number of coordinate positions and the product of the number of rows and columns is greater than a preset error value, returning to the step two.

[0025] Optionally, the step of constructing the theoretical dot array coordinates according to the preset chip size parameters, the number of rows and columns of the chips, and the row and column spacing between the chips specifically comprises:

[0026] According to the preset chip size parameters, the number of rows and columns of the chips, and the row and column spacing between the chips, the theoretical resolution of the target screen is calculated;

[0027] According to the theoretical resolution and the preset chip size parameters, the value range of the theoretical dot array coordinates and the first point coordinates are determined;

[0028] According to the first point coordinates and the row and column spacing between the chips, the complete theoretical dot array coordinates are calculated.

[0029] Optionally, the step of calculating the theoretical resolution of the target screen according to the preset chip size parameters, the number of rows and columns of the chips, and the row and column spacing between the chips specifically comprises:

[0030] According to the following formula 1, the theoretical resolution of the target screen is calculated:

[0031] Formula 1;

[0032] Wherein, Z is the theoretical resolution, W represents the number of pixels of width, H represents the number of pixels of height, Mr_X is the length of the chip, Mr_Y is the width of the chip, Dist_R is the row spacing between the chips, Dist_C is the column spacing between the chips, Num_R is the number of chips per row, and Num_C is the number of chips per column.

[0033] Optionally, the step of processing the first region coordinate group according to the region transformation matrix to obtain a corrected image specifically comprises:

[0034] According to a preset compensation value, the first region coordinate group is updated to a second region coordinate group;

[0035] According to the region transformation matrix, the second region coordinate group is corrected to obtain a first corrected region image;

[0036] According to the first region coordinate group, the first corrected region image is cut to obtain a second corrected region image;

[0037] The second correction area image is sorted and merged according to the theoretical dot array coordinates to obtain a complete correction image.

[0038] Optionally, after the step of processing the first area coordinate group according to the area transformation matrix to obtain a correction image, the correction method further comprises:

[0039] According to the chip size parameter, the gap between the chips in the correction image is eliminated, and a second theoretical coordinate matrix and a first no-gap correction image are generated.

[0040] According to the second theoretical coordinate matrix, the chip gray value of the coordinate position of the chip in the first no-gap correction image is extracted.

[0041] A zero gray image is set, and the chip gray value is filled into the corresponding position of the zero gray image to generate a final second no-gap correction image, and the zero gray image is an image with the same size as the first no-gap correction image and a gray value of 0.

[0042] The second aspect of the present application provides a correction device for an array image of a light emitting device, comprising:

[0043] An acquisition unit is configured to acquire a chip array image captured by a target screen, and acquire coordinate positions of a plurality of chips and the number of rows and columns of the chips in the target screen according to the chip array image.

[0044] A first construction unit is configured to construct a chip coordinate matrix according to the coordinate positions of the plurality of chips.

[0045] A first calculation unit is configured to calculate the row and column spacing between the chips according to the coordinate positions of the plurality of chips and a preset chip size parameter.

[0046] A second construction unit is configured to construct theoretical dot array coordinates according to the preset chip size parameter, the number of rows and columns of the chips, and the row and column spacing between the chips.

[0047] A partition unit is configured to divide the chip coordinate matrix into a plurality of first area coordinate groups, and each first area coordinate group is a set of four coordinates of two adjacent rows and two adjacent columns.

[0048] A second calculation unit is configured to calculate a plurality of area transformation matrices according to the theoretical dot array coordinates and the plurality of first area coordinate groups.

[0049] A processing unit is configured to process the first area coordinate group according to the area transformation matrix to obtain a correction image.

[0050] The third aspect of the present application provides a computer readable storage medium, and the computer readable storage medium has a program stored thereon, and the program performs the method of the first aspect and any optional method of the first aspect when executed on a computer.

[0051] From the above technical solutions, the embodiments of the present application have the following advantages:

[0052] By acquiring the photographed chip array image and extracting the chip coordinate positions and the number of rows and columns, the actual distribution of the chips on the target screen can be accurately mastered, thereby providing accurate basic data for subsequent correction work. The obtained coordinate positions are combined to construct a chip coordinate matrix, thereby improving the efficiency and standardization of data processing. The positional relationship of the chips is quantified by calculating the row and column spacings between the chips, thereby providing key spacing parameters for subsequent construction of theoretical dot array coordinates and correction. The theoretical dot array coordinates are calculated according to the preset chip size parameters, the number of rows and columns of the chips, and the row and column spacings between the chips, and the theoretical dot array coordinates represent the positional distribution of the chips in an ideal state, thereby providing an explicit reference standard for correction of actual chip coordinates. The theoretical dot array coordinates provide an important reference standard for subsequent correction of actual irregularly arranged chips.

[0053] The chip coordinate matrix is divided into a first region coordinate group of a plurality of adjacent two rows and two columns of four coordinate sets, and the irregular arrangement of the chips can have a certain regularity or relatively stable deviation mode in a local range. This regional division mode takes into account the local characteristics of the chip arrangement. A plurality of regional transformation matrices are calculated according to the theoretical dot array coordinates and the first region coordinate group. Since the arrangement deviations of the chips in different regions can be different, the regional calculation of the transformation matrices can more accurately capture the coordinate transformation relationship of each region, thereby improving the correction accuracy. At the same time, this mode also enhances the adaptability of the correction method to different irregular arrangement conditions.

[0054] The first region coordinate group is processed according to the calculated regional transformation matrices, which can adjust the actual chip coordinates to positions closer to the theoretical dot array coordinates, thereby realizing accurate correction of the image. The corrected image makes the chips present a more regular arrangement state, which is more consistent with the fixed spacing array mode adapted to the conventional point light inspection algorithm. The conventional point light inspection algorithm can be used to more accurately extract defect information according to the fixed spacing, thereby effectively reducing over-inspection and missed inspection phenomena, improving the accuracy of display screen defect detection, and thereby improving the product qualification rate and reducing production costs. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on these drawings.

[0056] Figure 1 An embodiment schematic diagram of the method for correcting the light emitting device array image in the present application;

[0057] Figure 2 An embodiment schematic diagram of the method for obtaining the coordinate position of the chip and constructing the chip coordinate matrix in the present application;

[0058] Figure 3 An embodiment schematic diagram of the method for calculating the theoretical dot array coordinate in the present application;

[0059] Figure 4 An embodiment schematic diagram of the method for obtaining the corrected image in the present application;

[0060] Figure 5 An embodiment schematic diagram of the method for eliminating the gap between the chips in the corrected image in the present application;

[0061] Figure 6 An embodiment structural schematic diagram of the correcting device for the light emitting device array image in the present application;

[0062] Figure 7 An embodiment schematic diagram of the missed detection phenomenon caused by the abnormal display array arrangement in the present application;

[0063] Figure 8 An embodiment schematic diagram of the chip array image and the local chip array image of the target screen in the present application;

[0064] Figure 9 An embodiment schematic diagram of the method for obtaining the chip coordinate matrix in the present application;

[0065] Figure 10 An embodiment schematic diagram of the theoretical dot array coordinate and the first region coordinate group in the present application;

[0066] Figure 11 An embodiment schematic diagram of the first corrected region image before and after the correction in the present application;

[0067] Figure 12 An embodiment schematic diagram of the local corrected image and the schematic diagram of the corrected image in the present application;

[0068] Figure 13 An embodiment schematic diagram of the local second gapless corrected image and the schematic diagram of the second gapless corrected image in the present application. DETAILED DESCRIPTION

[0069] In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, circuits, and

[0070] It will be understood that the terms "comprises" and / or "comprising," when used in this specification, include the presence of one or more features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0071] It will be understood that the term "and / or," when used in this specification, includes the possibility of both there being a combination of features, integers, steps, operations, elements, and / or components and there being only one of either feature, integer, step, operation, element, component, or group thereof.

[0072] As used in this specification and claims, the terms "if" and "when" can each be interpreted to mean "upon determination" or "in response to a determination" or "upon detection" or "in response to a detection," depending on the context. Similarly, the phrase "if determined" or "if detected" can be interpreted to mean "upon determination" or "in response to a determination" or "upon detection" or "in response to a detection," depending on the context.

[0073] In addition, the terms "first," "second," "third," etc. are used herein only to distinguish one element from another, and do not imply a relative importance or a given order.

[0074] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," and the like in various places throughout this specification are not necessarily all referring to the same embodiment, unless otherwise specified. The terms "comprise," "comprising," "including," "containing," "have," "having," and the like are meant to be open-ended and non-limiting.

[0075] In the field of display technology, MiniLED / MicroLED / OLED display technologies with light-emitting device arrays are gaining more and more favor in the market due to their unique advantages.

[0076] In the generation and manufacturing process of these display technologies, a key and common step is to transplant a large number of light-emitting chips onto the corresponding substrate. However, in actual operation, it is difficult to ensure that each chip or pixel point can be transplanted accurately according to the predetermined position, regardless of the technology. This results in a deviation in the spacing between the chips or pixel points, resulting in an irregular arrangement.

[0077] The conventional lighting detection algorithm is based on the early LCD\OLED array generated with the help of a mask with a fixed period. The distance between pixels in such an array is fixed and almost no deviation, so the algorithm only needs to set the appropriate period to effectively highlight the defects. However, when using this conventional lighting detection algorithm to detect irregularly arranged MiniLED / MicroLED / OLED light-emitting device arrays, it is not possible to accurately extract defect information according to the fixed spacing. Some otherwise normal chips may be incorrectly identified as defects by the algorithm due to the spacing with the surrounding chips not conforming to the fixed pattern, resulting in over-detection; while some chips with real defects may be missed due to the irregular arrangement of the surrounding chips, resulting in under-detection. As shown in Figure 7 Figure 7 is a schematic diagram of under-detection caused by abnormal display array arrangement during detection; Figure 7 (a) in FIG. 1 is a phenomenon of under-detection caused by searching a regular area from the top left corner of the array during lighting detection; Figure 7 (b) in FIG. 1 is a phenomenon of under-detection caused by searching a regular area from the bottom right corner of the array during lighting detection, which tests the complete chip arrangement, and is in sharp contrast to Figure 7 (a) in FIG. 1. This over-detection and under-detection phenomenon has a serious impact on the production and quality control of display screens. Over-detection increases unnecessary detection costs and subsequent processing workload, while under-detection allows defective products to flow into the market, reducing product qualification rates and increasing production costs.

[0078] Therefore, based on this, the present application discloses a light-emitting device array image correction method and device and storage medium, which are used to convert irregular light-emitting device arrays into arrays with fixed repeating periods for defect detection, thereby improving defect detection efficiency.

[0079] ​The technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0080] The method of this application can be applied to servers, devices, terminals, or other devices with logical processing capabilities; therefore, this application does not limit its application. For ease of description, the following description uses a system as the executing entity.

[0081] Please see Figure 1 This application provides an embodiment of a method for correcting an image of a light-emitting device array, comprising the following steps:

[0082] 101. Obtain a chip array diagram of the target screen, and obtain the coordinate positions and row and column numbers of several chips in the target screen based on the chip array diagram.

[0083] By using image acquisition equipment, such as a professional industrial camera, to photograph the target screen, an intuitive image of the chip distribution, i.e., a chip array diagram, can be obtained. Figure 8 As shown, Figure 8 (a) in the image is a chip array diagram of the target screen captured by the camera. Figure 8 (b) in the diagram is a partial array diagram of the chip in the chip array diagram.

[0084] The process involves acquiring a chip array image of the target screen and analyzing it using image processing algorithms (such as edge detection and feature extraction). The position of each chip is accurately identified from the chip array image, allowing the acquisition of the coordinates of several chips on the target screen. By analyzing the chip coordinates, the number of chips in the horizontal and vertical directions is counted. This can be achieved by iterating through the coordinate data according to certain rules (such as horizontal first, then vertical), determining the chip distribution and thus the number of rows and columns.

[0085] 102. Construct a chip coordinate matrix based on the coordinate positions of several chips.

[0086] Based on the coordinates of several chips obtained in step 101, these coordinates are arranged according to certain rules to construct a chip coordinate matrix. This matrix can systematically represent the position information of all chips, facilitating subsequent unified calculations and processing.

[0087] 103. Based on the coordinate positions of several chips and the preset chip size parameters, calculate the row and column spacing between the chips.

[0088] In combination with the preset chip size parameters (including the length and width of the chip in the image, the size, and the number of pixels occupied) and the obtained coordinate positions of several chips, the row and column spacing between the chips is finally obtained by calculating the row and column spacing between multiple groups of chips and taking the average. Specifically, the actual average distance of the chips in the horizontal and vertical directions can be calculated by the difference between the coordinates of adjacent chips and the chip size.

[0089] 104. Constructing theoretical lattice coordinates according to the preset chip size parameters, the number of rows and columns of chips, and the row and column spacing between the chips.

[0090] According to the preset chip size parameters, the number of rows and columns of chips, and the row and column spacing between the chips calculated in step 103, the theoretical lattice coordinates are constructed according to the principle of uniform distribution. The theoretical lattice coordinates represent the position distribution of the chips in the ideal state, providing a reference standard for subsequent comparison and correction with the actual chip coordinates. The specific construction is described in detail in subsequent embodiments and will not be repeated here.

[0091] 105. Dividing the chip coordinate matrix into a plurality of first regional coordinate groups, each first regional coordinate group being a set of four coordinates of two adjacent rows and two adjacent columns.

[0092] In order to more accurately correct the chip coordinates, the chip coordinate matrix constructed in step 102 is divided into regions. The top left corner of the chip coordinate matrix is the starting coordinate, and the four coordinates of two adjacent rows and two adjacent columns are divided into a set in sequence from the starting coordinate, forming a plurality of first regional coordinate groups. This division method can divide the chip coordinates of the entire screen into multiple local regions, and the independent correction matrix calculation for each local region can better adapt to the possible local differences in different regions of the screen and improve the accuracy of correction.

[0093] 106. Calculating a plurality of regional transformation matrices according to the theoretical lattice coordinates and the plurality of first regional coordinate groups.

[0094] According to Figure 10 , the theoretical lattice coordinates and the first regional coordinate groups are shown in Figure 10 , the theoretical lattice coordinates are shown in (a) of Figure 10 , and the first regional coordinate groups are shown in (b) of Figure 10 . Since the chips in the chip array are arranged irregularly, if the transformation matrix is directly calculated from two groups of coordinate matrices, the spacing between the chips cannot be unified to the same value, therefore, the regional transformation matrix is calculated. For each first regional coordinate group, the corresponding coordinates in the theoretical lattice coordinates are compared and analyzed, and the transformation matrix of the region, i.e., the regional transformation matrix, is calculated by the fitting algorithm.

[0095] The area transformation matrix describes the transformation relationship between the actual coordinates and the theoretical coordinates in each local area, and different areas may have different transformation matrices due to manufacturing processes, installation errors and other factors.

[0096] 107. According to the area transformation matrix, the first area coordinate group is processed to obtain a corrected image.

[0097] The first area coordinate group is processed according to the area transformation matrix calculated in step 105. The coordinates in each first area coordinate group are transformed according to the corresponding area transformation matrix, so that the position coordinates of the chips are adjusted to positions close to the theoretical coordinates. After processing all the first area coordinate groups, the coordinates in the entire chip coordinate matrix are corrected, so that the image is regenerated according to the corrected coordinates to obtain a corrected image. The corrected image is a chip array image formed by converting the irregular MiniLED / MicroLED / OLED light emitting device array chip array image.

[0098] In this embodiment, by acquiring the photographed chip array image and extracting the chip coordinate positions and the number of rows and columns, the actual distribution of the chips on the target screen can be accurately mastered, providing accurate basic data for subsequent correction work. The obtained coordinate positions are combined to construct a chip coordinate matrix, improving the efficiency and standardization of data processing. By calculating the row and column spacings between the chips, the positional relationship of the chips is quantized, providing key spacing parameters for subsequent construction of theoretical dot array coordinates and correction. The theoretical dot array coordinates are calculated according to the preset chip size parameters, the number of rows and columns of the chips, and the row and column spacings between the chips. The theoretical dot array coordinates represent the position distribution of the chips in the ideal state, providing a clear reference standard for the correction of actual chip coordinates. The theoretical dot array coordinates provide an important reference standard for subsequent correction of irregularly arranged chips.

[0099] The chip coordinate matrix is divided into a first area coordinate group of several adjacent two-row and two-column four-coordinate sets. The irregular arrangement of the chips may have certain regularity or relatively stable deviation patterns in a local range. This regional division method takes into account the local characteristics of chip arrangement. According to the theoretical dot array coordinates and the first area coordinate group, a plurality of area transformation matrices are calculated. Since the chip arrangement deviations of different areas may be different, the regional calculation of the transformation matrix can more accurately capture the coordinate transformation relationship of each area, improving the accuracy of the correction. At the same time, this method also enhances the adaptability of the correction method to different irregular arrangements.

[0100] According to the calculated area transformation matrix, the first area coordinate group is processed, the actual chip coordinate is adjusted to a position closer to the theoretical lattice coordinate, and the accurate correction of the image is realized. The corrected image makes the chip present a more regular arrangement state, and is more suitable for the fixed pitch array mode adapted by the conventional point light detection algorithm. Using the conventional point light detection algorithm can more accurately extract the defect information according to the fixed pitch, effectively reduces the over-detection and missed detection phenomenon, improves the accuracy of the display screen defect detection, and further improves the product qualification rate and reduces the production cost.

[0101] Please refer to Figure 2 The application provides an embodiment of a method for obtaining the coordinate positions of chips and constructing a chip coordinate matrix, which comprises the following steps:

[0102] 201. Obtain the number of rows and columns of chips in the chip array image.

[0103] 202. Set a global threshold value, and extract the chip region according to the global threshold value.

[0104] 203. Obtain the connected domain of the chip region, and screen out the effective connected domain through the characteristic value of the connected domain.

[0105] 204. Obtain the coordinate positions of the chips in the effective connected domain, and calculate the number of coordinate positions of the chips.

[0106] 205. If the difference between the number of coordinate positions and the product of the number of rows and columns is greater than a preset error value, return to step 202.

[0107] 206. According to the preset interval threshold value and the chip array image, sort the coordinate positions of the chips and then collect them into a chip coordinate matrix.

[0108] 207. If there is a missing coordinate in the chip coordinate matrix, put the missing coordinate into a fitting matrix, and fill the corresponding position of the missing coordinate in the fitting matrix with a negative number. The missing coordinate is a coordinate position of the chip that is not detected in the chip array image.

[0109] 208. Perform coordinate fitting on the fitting matrix, calculate the missing coordinate, and collect the missing coordinate into the chip coordinate matrix.

[0110] After the chip array image is preprocessed, an image edge detection algorithm is used to perform edge detection on the chip array image, so as to highlight the boundary of the chip array. Then, the noise and small edge fluctuations of the image after edge detection are eliminated, so that the boundary of the chip array is clearer. Finally, by analyzing the processed image, the number of rows and columns is obtained by counting the arrangement rule of the chips in the horizontal direction and the vertical direction, and the number of rows and columns of the chips in the target screen is determined.

[0111] A suitable global threshold value is set, which can be determined according to the distribution range of gray levels and the gray level difference between the chip and the background. The pre-processed chip array image is binarized using the global threshold value. Morphological operations are performed on the binarized image to further remove noise and small isolated regions, making the chip region more complete and accurate.

[0112] The binarized image is processed using a connected component analysis algorithm to obtain all connected components. The characteristic values of each connected component, such as area, perimeter, aspect ratio, etc., are calculated. The area can be calculated by counting the number of pixels in the connected component; the perimeter can be calculated by counting the number of pixels on the boundary of the connected component; the aspect ratio can be calculated by the length and width of the minimum bounding rectangle of the connected component.

[0113] Only the connected components that meet the screening conditions are considered as valid connected components, representing possible chip regions. The screening conditions can be set according to the actual characteristics of the chip, such as setting the range of area, the range of aspect ratio, etc. For each valid connected component, the centroid coordinates are calculated as the coordinate position of the chip. The number of chip coordinate positions corresponding to all valid connected components is counted. At the same time, the difference between the number of chip coordinate positions and the product of the number of rows and columns is calculated.

[0114] A preset error value is set, which can be set by human experience. If the calculated difference is greater than the preset error value, it is considered that the detection result may have a large error, and it is necessary to return to step two to re-set the global threshold value and extract the chip region to optimize the detection result.

[0115] The arrangement rule of the chips in the chip array image is analyzed to determine the interval threshold of the chips in the horizontal and vertical directions. The distance between the coordinate positions of adjacent chips can be counted, and the average value is taken as the interval threshold. The coordinate positions of the chips are sorted according to the interval threshold. The sorted chip coordinate positions are collected into a matrix according to the order of the number of rows and columns, which is the chip coordinate matrix. The number of rows and columns of the matrix correspond to the number of rows and columns in the chip array image.

[0116] The chip coordinate matrix is traversed to check whether each position has a corresponding chip coordinate. If a position has no coordinate, it is considered that the position has a missing coordinate. A fitting matrix with the same size as the chip coordinate matrix is created. The positions with missing coordinates in the fitting matrix are filled with negative numbers, which can be represented by -1.

[0117] According to the known chip coordinate positions, the coordinate fitting algorithm is used to fit the variation rule of the chip coordinates in the horizontal and vertical directions. The missing coordinates are calculated using the fitted rule. The calculated missing coordinates are filled into the corresponding missing positions in the chip coordinate matrix. As shown in Figure 9 Figure 9 ​An example of a chip coordinate matrix is obtained.

[0118] In this embodiment, by obtaining the number of rows and columns, the number of rows and columns provides an important reference for subsequent steps of judging whether the chip coordinate is reasonable, constructing the chip coordinate matrix, etc., ensuring the logic and accuracy of the whole process. The setting of the global threshold value can separate the chip region from the complex background, reduce the interference of background noise on chip detection, improve the accuracy of chip region extraction, and lay a foundation for subsequent accurate chip coordinate acquisition. By threshold processing, the image is converted into a binary image, simplifying the structure and features of the image and improving the processing speed.

[0119] Connected component analysis can accurately identify the connected pixel regions in the image, and combined with feature value screening, it can exclude non-chip connected components and improve the accuracy of chip coordinate acquisition. Obtaining the coordinate position of the chip provides key data for subsequent operations. Comparing the number of chip coordinate positions with the number of rows and columns obtained in step one can help to discover abnormal situations in the detection process in time. When there is a large deviation between the coordinate number and the expected value, by returning to step two to reset the global threshold value and extract the chip region, detection errors caused by improper initial threshold setting can be avoided, and the accuracy of the detection result is improved.

[0120] The chip coordinates are sorted in row and column order and summarized into a matrix, so that the chip coordinates have a clear spatial arrangement. By placing the missing coordinates into the fitting matrix and filling them with negative numbers, the positions of the chips not detected in the chip array image can be clearly identified, providing a clear target for subsequent coordinate fitting and supplementation. By calculating the missing coordinates through coordinate fitting and summarizing them into the chip coordinate matrix, the chip coordinate matrix becomes more complete and accurate, providing a guarantee for subsequent comprehensive analysis of the chip.

[0121] Referring to Figure 3 The application provides an embodiment of a method for constructing theoretical dot array coordinates, including the following steps:

[0122] 301. Calculate the theoretical resolution of the target screen according to the preset chip size parameter, the number of rows and columns of the chip, and the row and column spacing between the chips.

[0123] 302. Determine the value range and first point coordinate of the theoretical dot array coordinates according to the theoretical resolution and the preset chip size parameter.

[0124] 303. Calculate the complete theoretical dot array coordinates according to the first point coordinate and the row and column spacing between the chips.

[0125] According to the following formula 1, according to the preset chip size parameter and the number of rows and columns of the chip and the row and column spacing between the chips in the foregoing embodiment, the theoretical resolution of the target screen is calculated:

[0126] Formula 1;

[0127] wherein Z is the theoretical resolution, W represents the number of pixels in width, H represents the number of pixels in height, Mr_X is the length of the chip, Mr_Y is the width of the chip, Dist_R is the row spacing between chips, Dist_C is the column spacing between chips, Num_R is the number of chips per row, and Num_C is the number of chips per column.

[0128] The range of the theoretical dot coordinates is [0, H*Mr_Y-1] for the row coordinate and [0, W*Mr_X-1] for the column coordinate, and the first point coordinate is (Mr_X / 2-1, Mr_Y / 2-1). This is because the resolution represents the number of pixels in the horizontal and vertical directions of the screen, and the coordinates are counted from 0 to resolution-1.

[0129] For each chip in the chip array, the first point coordinate is used to sequentially increase the column spacing Dist_C and the row spacing Dist_R to obtain a number of theoretical dot coordinates corresponding to the row and column number of the chip, thereby forming a complete set of theoretical dot coordinates.

[0130] In this embodiment, the theoretical resolution of the target screen is calculated, and the calculation result of the theoretical resolution provides an important basic parameter for subsequent operations. The range of the theoretical dot coordinates and the first point coordinate are determined to provide a clear boundary for the chip and avoid the calculation of coordinates exceeding the screen range, thereby ensuring the rationality and effectiveness of the calculation. By using the first point coordinate and the row and column spacing, a complete set of theoretical dot coordinates is calculated to construct an accurate theoretical dot model of the chip. The complete set of theoretical dot coordinates can accurately describe the position of each chip in the target screen and provide an accurate basis for the positioning of the chip.

[0131] Referring to Figure 4 The application provides an embodiment of a method for obtaining a corrected image, which comprises the following steps:

[0132] 401. Update the first region coordinate group to a second region coordinate group according to a preset compensation value.

[0133] 402. Correct the second region coordinate group according to a region transformation matrix to obtain a first corrected region image.

[0134] 403. Cut the first corrected region image into a second corrected region image according to the first region coordinate group.

[0135] 404. Arrange the second corrected region image according to the theoretical dot coordinates to obtain a complete corrected image.

[0136] The compensation value Bias is set by human experience, and is set according to the error in the past similar image processing projects. The purpose is to ensure the overlap between adjacent regions. In actual application, the compensation value is set to 10. For each coordinate point {X_per, Y_per} in the first region coordinate group, the corresponding coordinate point {X_per ± Bias, Y_per ± Bias} in the second region coordinate group is updated according to the compensation value. The same batch update is performed on all coordinate points in the first region coordinate group.

[0137] According to the region transformation matrix calculated in the above embodiment, the second region coordinate group is corrected, and the corrected coordinate points are used to perform interpolation processing on the original image to obtain a first corrected region image. As shown in Figure 11 Figure 11 is a schematic diagram of the first corrected region image before and after correction.

[0138] Finally, according to the region boundary and the theoretical coordinates defined in the first region coordinate group, the first corrected region image is cut into a second corrected region image, and the second de-corrected region is the size of the original region image, that is, the size of the region after removing the compensation value. The order of the theoretical point array coordinates is usually determined in advance according to the arrangement rule of the chip array. An empty image container is created, and the size is determined according to the total size of all second corrected region images arranged. Then, according to the order of the theoretical point array coordinates, each second corrected region image is placed in the corresponding position in the container to obtain a complete corrected image. As shown in Figure 12 Figure 12 is a partial schematic diagram of the corrected image and a schematic diagram of the corrected image.

[0139] In this embodiment, the first region coordinate group is updated by the pre-set compensation value, which can correct the errors that may occur in the image acquisition process and provide a more accurate basis for subsequent image correction. The second region coordinate group is corrected according to the region transformation matrix, which can effectively eliminate the geometric distortion in the image, such as rotation and inconsistent scaling, and improve the quality and usability of the image.

[0140] Cutting the first corrected region image into a second corrected image according to the first region coordinate group can remove the irrelevant part of the image and improve the processing efficiency. Arranging the second corrected region image according to the order of the theoretical point array coordinates can construct a complete corrected image.

[0141] Referring to Figure 5 , the application provides an embodiment of a method for eliminating the gap between the chips in the corrected image, which comprises the following steps:

[0142] 501. According to the chip size parameter, the gap between the chips in the corrected image is eliminated, and a second theoretical coordinate matrix and a first gap-free corrected image are generated.​​

[0143] 502、According to the second theoretical coordinate matrix, the chip gray value of the coordinate position of the chip in the first no-gap correction image is extracted.

[0144] 503、A zero gray image is set, and the chip gray value is filled into the corresponding position of the zero gray image to generate the final second no-gap correction image. The zero gray image is an image with the same size as the first no-gap correction image and a gray value of 0.

[0145] The arrangement mode of the chip in the correction image is analyzed to determine the initial theoretical coordinates of each chip under the ideal no-gap condition. The length and width dimensions of each chip are {Mr_X, Mr_Y}, and the gap is eliminated by traversing each pixel point in the range {[X', X'+Mr_X], [Y', Y'+Mr_Y]} to obtain the no-gap theoretical image size with a length and width of {Num_R*Mr_Y, Num_C*Mr_X}.

[0146] In order to eliminate the gap between the chips, the correction image needs to be transformed. Image stitching and deformation methods can be used to calculate the new position of each chip under the no-gap condition according to the chip size parameters and arrangement rules, and then use the image interpolation algorithm to move the chip image to the new position and fill the gap area.

[0147] For each coordinate point in the second theoretical coordinate matrix, its position in the first no-gap correction image is determined. According to the coordinate position, the gray value of the corresponding position is extracted.

[0148] A new image with all gray values of 0 is generated according to the no-gap theoretical image size. Since the theoretical image is suitable for the case where there is no gap between the chips, the new image can be used to detect Mura defects. The corresponding coordinate positions in the first no-gap correction image are filled into the corresponding coordinate positions of the zero gray image to generate the final second no-gap correction image. As shown in Figure 13 , Figure 13 is a local schematic view of the second no-gap correction image and a schematic view of the second no-gap correction image.

[0149] In this embodiment, by eliminating the gap between the chips in the correction image, the chip image is more compact, reducing the interference of the gap on chip feature extraction and analysis, and improving the accuracy of chip detection and recognition. The chip gray value is filled into the zero gray image to generate the second no-gap correction image, so that the image only contains the gray information of the chip, the background is pure black, and the image is more clear and concise, facilitating the observation and analysis of the features of the chip.

[0150] Please refer to Figure 6 , the application provides an embodiment of a correction device for a light emitting device array image, which comprises:

[0151] The acquisition unit 601 is configured to acquire a chip array image of a target screen, and acquire coordinate positions of a plurality of chips in the target screen and a number of rows and columns of the chips according to the chip array image;

[0152] The first construction unit 602 is configured to construct a chip coordinate matrix according to the coordinate positions of the plurality of chips.

[0153] The first calculation unit 603 is configured to calculate a row-column spacing between the plurality of chips according to the coordinate positions of the plurality of chips and a preset chip size parameter.

[0154] The second construction unit 604 is configured to construct a theoretical dot array coordinate according to the preset chip size parameter, the number of rows and columns of the chips, and the row-column spacing between the plurality of chips.

[0155] The partition unit 605 is configured to divide the chip coordinate matrix into a plurality of first regional coordinate groups, each of the first regional coordinate groups being a set of four coordinates of two adjacent rows and two adjacent columns.

[0156] The second calculation unit 606 is configured to calculate a plurality of regional transformation matrices according to the theoretical dot array coordinate and the plurality of first regional coordinate groups.

[0157] The processing unit 607 is configured to process the first regional coordinate groups according to the regional transformation matrices to obtain a corrected image.

[0158] Optionally, after the processing unit 607, the correction device further includes:

[0159] The elimination unit 608 is configured to eliminate the gaps between the chips in the corrected image according to the chip size parameter, and generate a second theoretical coordinate matrix and a first gap-free corrected image.

[0160] The extraction unit 609 is configured to extract chip gray scale values of the coordinate positions of the chips in the first gap-free corrected image according to the second theoretical coordinate matrix.

[0161] The filling unit 610 is configured to set a zero gray scale image, fill the chip gray scale values into corresponding positions of the zero gray scale image, and generate a final second gap-free corrected image, the zero gray scale image being an image with the same size as the first gap-free corrected image and with all gray scale values being 0.

[0162] The specific implementation process is described in detail with reference to the embodiments. Figures 1 to 5 The embodiments are not described herein.

[0163] The application provides a computer readable storage medium, and the computer readable storage medium stores a program. Figure 1 、 Figure 2 、 Figure 3 、 Figure 4and Figure 5 The method in the middle.

[0164] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0165] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0166] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0167] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0168] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A method for correcting an image of a light-emitting device array, characterized in that, include: Obtain a chip array diagram of the target screen captured by the image, and obtain the coordinate positions of several chips in the target screen and the number of rows and columns of the chips based on the chip array diagram; Construct a chip coordinate matrix based on the coordinate positions of several chips; The row and column spacing between the chips is calculated based on the coordinate positions of several chips and preset chip size parameters. Theoretical dot matrix coordinates are constructed based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips; The chip coordinate matrix is ​​divided into several first region coordinate groups, each first region coordinate group being a set of four coordinates in two adjacent rows and two columns. Based on the theoretical lattice coordinates and several sets of coordinates of the first region, several region transformation matrices are calculated by region. Based on the region transformation matrix, the coordinate group of the first region is processed to obtain the corrected image; Based on the chip size parameters, the gaps between the chips in the corrected image are eliminated, and a second theoretical coordinate matrix and a first gapless corrected image are generated; Based on the second theoretical coordinate matrix, extract the chip grayscale value of the chip's coordinate position in the first gapless correction image; Set a zero-grayscale image and fill the corresponding positions of the chip grayscale values ​​into the zero-grayscale image to generate the final second gapless correction image. The zero-grayscale image is an image with the same size as the first gapless correction image and all grayscale values ​​are 0.

2. The correction method according to claim 1, characterized in that, The step of obtaining the coordinate positions and row and column numbers of several chips in the target screen based on the chip array diagram specifically includes: Step 1: Obtain the number of rows and columns of the chips in the chip array diagram; Step 2: Set a global threshold and extract the chip region based on the global threshold; Step 3: Obtain the connected components of the chip region, and filter out the valid connected components by the feature values ​​of the connected components; Step 4: Obtain the coordinate positions of the chips in the effective connected domain, and calculate the number of coordinate positions of the chips.

3. The correction method according to claim 2, characterized in that, The step of constructing a chip coordinate matrix based on the coordinate positions of several chips specifically includes: Based on the preset interval threshold and the chip array diagram, the coordinate positions of the chips are sorted and summarized into a chip coordinate matrix; If there are missing coordinates in the chip coordinate matrix, the missing coordinates are placed in the fitting matrix, and the corresponding positions of the missing coordinates in the fitting matrix are filled with negative numbers. The missing coordinates are the coordinate positions of the chips that were not detected in the chip array diagram. The missing coordinates are calculated by performing coordinate fitting on the fitted matrix and then summarizing the missing coordinates into the chip coordinate matrix.

4. The correction method according to claim 3, characterized in that, Following step four, the correction method further includes: Step 5: If the difference between the product of the number of coordinate positions and the number of rows and columns is greater than a preset error value, then return to Step 2.

5. The correction method according to claim 4, characterized in that, The step of constructing theoretical dot matrix coordinates based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips specifically includes: The theoretical resolution of the target screen is calculated based on the preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips. Based on the theoretical resolution and the preset chip size parameters, determine the range of values ​​for the theoretical dot matrix coordinates and the coordinates of the first point; The complete theoretical matrix coordinates are calculated based on the coordinates of the first point and the row and column spacing between the chips.

6. The correction method according to claim 5, characterized in that, The step of calculating the theoretical resolution of the target screen based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips specifically includes: The theoretical resolution of the target screen is calculated according to the following formula 1: Official 1; Where Z is the theoretical resolution, W represents the number of pixels in width, H represents the number of pixels in height, Mr_X is the length of the chip, Mr_Y is the width of the chip, Dist_R is the row spacing between the chips, Dist_C is the column spacing between the chips, Num_R is the number of chips per row, and Num_C is the number of chips per column.

7. The correction method according to claim 1, characterized in that, The step of processing the first region coordinate group according to the region transformation matrix to obtain the corrected image specifically includes: Based on the preset compensation value, the first region coordinate group is updated to the second region coordinate group; The second region coordinate group is corrected according to the region transformation matrix to obtain the first corrected region image; Based on the first region coordinate set, the first correction region image is segmented to obtain the second correction region image; The second correction region image is sorted and merged according to the theoretical dot matrix coordinates to obtain a complete correction image.

8. A correction device for an image of a light-emitting device array, characterized in that, For performing the correction method as described in any one of claims 1 to 7, comprising: The acquisition unit is used to acquire a chip array diagram of the target screen captured by the image, and to acquire the coordinate positions and the number of rows and columns of several chips in the target screen based on the chip array diagram. The first construction unit is used to construct a chip coordinate matrix based on the coordinate positions of the chips. The first calculation unit is used to calculate the row and column spacing between the chips based on the coordinate positions of the chips and preset chip size parameters. The second construction unit is used to construct theoretical lattice coordinates based on preset chip size parameters, the number of rows and columns of the chip, and the row and column spacing between the chips. A partitioning unit is used to divide the chip coordinate matrix into several first region coordinate groups, wherein the first region coordinate group is a set of four coordinates in two adjacent rows and two columns. The second calculation unit is used to calculate several regional transformation matrices by region based on the theoretical lattice coordinates and several sets of first region coordinates. The processing unit is used to process the first region coordinate group according to the region transformation matrix to obtain the corrected image.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains a program that, when executed on a computer, performs the correction method as described in any one of claims 1 to 7.

Images